Semiconductor device and its manufacturing method

Abstract

This technology is applicable to superjunction structures composed of high aspect ratio columns. [Solution] A method for manufacturing a semiconductor device 1 having a superjunction structure comprises: a first step of patterning an ion implantation mask on second conductivity type semiconductor layers 14A and 14B; and a second step, after the first step, of ion implanting first conductivity type impurities into the second conductivity type semiconductor layer by passing them through openings 54 and 154 of the ion implantation mask to form a first conductivity type column 14a and a second conductivity type column 14b. The first step comprises: a first step of forming mask molding layers 42 and 142 on the second conductivity type semiconductor layer; a second step of forming grooves 52 and 152 extending from the upper surface of the mask molding layer toward the second conductivity type semiconductor layer; a third step of embedding shielding parts 46 and 146 containing metal in the grooves; and a fourth step of removing the mask molding layer between the shielding parts to form an opening.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device having a superjunction structure in which p-type columns and n-type columns are alternately and repeatedly arranged along at least one direction has been proposed. A semiconductor device having a superjunction structure can have characteristics of low on-resistance and high breakdown voltage. Patent Document 1 discloses an example of a semiconductor device having a superjunction structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to further improve the characteristics of low on-resistance and high breakdown voltage, it is desirable to increase the aspect ratio of each of the p-type columns and the n-type columns. The superjunction structure is formed by ion-implanting an impurity of the other conductivity type (for example, a p-type impurity) into a semiconductor layer of one conductivity type (for example, an n-type semiconductor layer). Conventionally, for a mask for ion implantation, a photoresist having an opening corresponding to the ion implantation region is used. In order to shield the impurity of the conductivity type to be ion-implanted and form a column with a high aspect ratio, it is necessary to increase the thickness of the photoresist and narrow the pitch of the openings formed in the photoresist. For this reason, in the photoresist for forming a column with a high aspect ratio, the aspect ratio of the formed openings also becomes high. According to the study by the present inventors, it has been found that when the aspect ratio of the openings formed in the photoresist becomes high, there is a concern about the collapse of the photoresist.

[0005] This specification provides techniques applicable to superjunction structures composed of high aspect ratio columns. [Means for solving the problem]

[0006] This specification discloses a method for manufacturing a semiconductor device (1) having a superjunction structure in which first conductivity type columns (14a) and second conductivity type columns (14b) are alternately and repeatedly arranged along at least one direction. This manufacturing method may comprise a first step of patterning an ion implantation mask on a second conductivity type semiconductor layer (14A, 14B), and a second step, after the first step, ion implanting first conductivity type impurities into the second conductivity type semiconductor layer by passing them through openings (54, 154) of the ion implantation mask to form the first conductivity type columns and the second conductivity type columns. The first step may include: a first step of forming a mask molding layer (42, 142) on the second conductivity type semiconductor layer; a second step of forming grooves (52, 152) extending from the upper surface of the mask molding layer toward the second conductivity type semiconductor layer; a third step of embedding shielding portions (46, 146) containing metal in the grooves; and a fourth step of removing the mask molding layer between the shielding portions to form the opening. The ion implantation mask used in the above manufacturing method has the shielding portions containing metal. The shielding portions containing metal have high shielding properties against the first conductivity type impurities. Therefore, the film thickness of the ion implantation mask can be reduced. As a result, the aspect ratio of the opening formed in the ion implantation mask is reduced, so that the tilting of the ion implantation mask is suppressed. Furthermore, the opening of the ion implantation mask is formed by removing the mask molding layer between the shielding portions that have been previously embedded in the mask molding layer. Therefore, the opening in the ion implantation mask is not formed by directly etching the shielding portion. Alternatively, if the opening is formed by directly etching the shielding portion containing metal, the etching proceeds along the grain boundaries of the shielding portion, which leads to the problem of increased maximum surface roughness on the sides of the opening. In the above manufacturing method, the shielding portion is not directly etched, so the maximum surface roughness of the opening in the ion implantation mask is reduced. As a result, the maximum surface roughness of the interface between the first conductivity type column and the second conductivity type column formed in the second conductivity type semiconductor layer is also reduced. The semiconductor device manufactured by the above manufacturing method can suppress the disruption of the charge balance of the superjunction structure and have high voltage resistance characteristics.

[0007] This specification discloses a semiconductor device (1) having a superjunction structure in which first conductivity type columns (14a) and second conductivity type columns (14b) are arranged alternately in at least one direction. Each of the first conductivity type columns and the second conductivity type columns may be silicon carbide. The pitch of the first conductivity type columns and the second conductivity type columns in the repeating direction may be 0.4 nm or less. The maximum surface roughness of the interface between the first conductivity type columns and the first conductivity type columns may be less than 30 nm. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic cross-sectional view of the main part of the semiconductor device disclosed herein is shown. [Figure 2] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 3] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 4] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 5] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 6] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 7] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 8] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 9] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 10] A schematic cross-sectional view of a key part in one step of the first method for manufacturing a semiconductor device disclosed herein is shown. [Figure 11] Schematically shows a cross-sectional view of a main part in a step of a first manufacturing method of a semiconductor device disclosed in this specification. [Figure 12] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 13] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 14] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 15] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 16] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 17] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 18] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 19] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification. [Figure 20] Schematically shows a cross-sectional view of a main part in a step of a second manufacturing method of a semiconductor device disclosed in this specification.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, a semiconductor device disclosed in this specification will be described with reference to the drawings. For the purpose of clarity of illustration, only one of the repeatedly arranged components may be labeled.

[0010] FIG. 1 schematically shows a cross-sectional view of the main part of the semiconductor device 1. The semiconductor device 1 is a type of power semiconductor device called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10, a drain electrode 22 covering the lower surface of the semiconductor layer 10, a source electrode 24 covering the upper surface of the semiconductor layer 10, and a plurality of trench gates 30 provided in the upper layer portion of the semiconductor layer 10.

[0011] The semiconductor layer 10 is a wide-gap semiconductor. The semiconductor layer 10 is not particularly limited, and for example, may be a 4H silicon carbide layer. Instead of the silicon carbide layer, the semiconductor layer 10 may be, for example, a nitride semiconductor layer, a gallium oxide layer, a diamond layer, or the like. The semiconductor layer 10 is an n + -type drain region 12, a drift region 14, a p-type body region 16, and an n + -type source region 18, and a p + -type body contact region 19.

[0012] The drain region 12 is disposed in the lower layer portion of the semiconductor layer 10 and is provided at a position exposed on the lower surface of the semiconductor layer 10. The drain region 12 is in ohmic contact with the drain electrode 22 covering the lower surface of the semiconductor layer 10. As will be described in the manufacturing method described later, the drain region 12 is composed of an n + -type silicon carbide substrate and an n + -type epitaxial layer grown from its upper surface.

[0013] The drift region 14 is located between the drain region 12 and the body region 16 and has a plurality of p-type columns 14a and a plurality of n-type columns 14b. The p-type columns 14a are examples of first-conductivity columns, and the n-type columns 14b are examples of second-conductivity columns. The p-type columns 14a and n-type columns 14b are arranged to alternately repeat along at least one direction within the cross-section of the semiconductor layer 10, forming a superjunction structure. The plurality of p-type columns 14a and n-type columns 14b may be arranged in a stripe pattern, for example, when viewed from a direction perpendicular to the upper surface of the semiconductor layer 10 (hereinafter referred to as "when viewed from above").

[0014] The p-type column 14a has a height 14H measured along the thickness direction of the semiconductor layer 10, from its bottom surface to its top surface, which is the interface with the body region 16. The p-type column 14a has a width 14W measured between its sides, which are the interface with the n-type column 14b, along the repeating direction of the superjunction structure. The height 14H of the p-type column 14a is not particularly limited, but is, for example, 3.4 μm or more. The width 14W of the p-type column 14a is not particularly limited, but is, for example, 0.4 μm or less. Therefore, the aspect ratio of the p-type column 14a is 8.5 or more. The height and width of the n-type column 14b are similar. Therefore, the pitch of the p-type column 14a and the n-type column 14b in the repeating direction is 0.4 nm or less. A superjunction structure with these dimensions results in a breakdown voltage of 850 V or more for the semiconductor device 1, calculated from the dielectric breakdown field of silicon carbide.

[0015] The body region 16 is located on the drift region 14 and is positioned in the upper part of the semiconductor layer 10. The body region 16 is located between the n-type column 14b and the source region 18 of the drift region 14, separating the n-type column 14b from the source region 18. The concentration of p-type impurities in the body region 16 is adjusted according to a desired gate threshold voltage.

[0016] The source region 18 is located on the body region 16, positioned in the upper part of the semiconductor layer 10, and exposed on the upper surface of the semiconductor layer 10. The source region 18 is in contact with the side surface of the trench gate 30. The source region 18 is in ohmic contact with the source electrode 24 that covers the upper surface of the semiconductor layer 10.

[0017] The body contact region 19 is provided on the body region 16, positioned in the upper part of the semiconductor layer 10, and exposed on the upper surface of the semiconductor layer 10. The body contact region 19 is in ohmic contact with the source electrode 24 that covers the upper surface of the semiconductor layer 10.

[0018] The trench gate 30 is embedded in a trench formed in the upper part of the semiconductor layer 10, and penetrates the source region 18 and the body region 16 to reach the n-type column 14b of the drift region 14. In this example, when the semiconductor layer 10 is viewed from above, the trench gate 30 extends along the longitudinal direction of the p-type column 14a and the n-type column 14b, i.e., in a direction perpendicular to the repeating direction of the superjunction structure. Alternatively, when the semiconductor layer 10 is viewed from above, the trench gate 30 may extend along the repeating direction of the p-type column 14a and the n-type column 14b. The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is formed of polysilicon containing impurities and faces the semiconductor layer 10 via the gate insulating film 34. In particular, the gate electrode 32 faces the portion of the body region 16 that separates the n-type column 14b of the drift region 14 from the source region 18 via the gate insulating film 34. The gate insulating film 34 is made of silicon oxide and covers the inner wall of the trench.

[0019] Next, the operation of the semiconductor device 1 will be explained with reference to Figure 1. When the potential of the drain electrode 22 is positive compared to the potential of the source electrode 24, and the potential of the gate electrode 32 of the trench gate 30 is positive compared to the source electrode 24 and controlled to be higher than a threshold, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 16 in the portion separating the n-type column 14b of the drift region 14 from the source region 18. Electrons supplied from the source region 18 reach the n-type column 14b of the drift region 14 via the channel of the inversion layer. Electrons that reach the n-type column 14b flow through the n-type column 14b to the drain region 12. Since the n-type column 14b has a high concentration of n-type impurities, the semiconductor device 1 can have low on-resistance characteristics.

[0020] When the potential of the gate electrode 32 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel in the inversion layer disappears, and the semiconductor device 1 turns off. The multiple p-type columns 14a and multiple n-type columns 14b constituting the superjunction structure are substantially completely depleted, and a wide area of ​​the drift region 14 is depleted. Furthermore, since the drift region 14 has a superjunction structure, the electric field distribution of the drift region 14 is leveled in the depth direction. As a result, the drift region 14 can bear a large potential difference, and the semiconductor device 1 can have high breakdown voltage characteristics.

[0021] (Method of manufacturing semiconductor devices) The following describes a first and second manufacturing method for semiconductor device 1, with reference to the drawings. The following describes the process of forming a superjunction structure within the manufacturing method of semiconductor device 1. As detailed below, the superjunction structure is formed by vertically connecting p-type columns and n-type columns formed in the lower epitaxial layer and the upper epitaxial layer, respectively. Other processes for manufacturing semiconductor device 1 can utilize known manufacturing techniques as needed.

[0022] (First manufacturing method) The first method for manufacturing the semiconductor device 1 will be described below with reference to Figures 2 to 11. First, as shown in Figure 2, a drain region 12 is prepared. The drain region 12 is n + From the surface of a silicon carbide substrate of type n + An n-type epitaxial layer is formed by crystal growth. Next, using epitaxial growth technology, an n-type lower epitaxial layer 14A is crystal grown from the surface of the drain region 12. The thickness of the lower epitaxial layer 14A is not particularly limited, but may be, for example, 1.8 μm. The lower epitaxial layer 14A constitutes at least a part of the semiconductor layer 10 and is sometimes referred to as an n-type semiconductor layer.

[0023] Next, as shown in Figure 3, a mask-molded layer 42 is formed on the lower epitaxial layer 14A using a deposition technique such as CVD. The mask-molded layer 42 is not particularly limited, but may be an oxide film such as silicon oxide. The thickness of the mask-molded layer 42 is not particularly limited, but may be, for example, 1.1 μm.

[0024] Next, as shown in Figure 4, multiple grooves 52 are formed in the mask-molded layer 42 using etching techniques such as RIE or wet etching. The portion of the mask-molded layer 42 remaining between the grooves 52 is called the mask-molded wall 43. The grooves 52 extend from the upper surface of the mask-molded layer 42 toward the lower epitaxial layer 14A. The grooves 52 do not penetrate the mask-molded layer 42. Therefore, a portion of the mask-molded layer 42 remains on the lower epitaxial layer 14A. The portion of the mask-molded layer 42 remaining on the lower epitaxial layer 14A is called the lift-off film 40. Alternatively, the grooves 52 may penetrate the mask-molded layer 42.

[0025] Next, as shown in Figure 5, a sidewall film 44 is deposited on the inner wall of the groove 52 using a deposition technique such as sputtering. The sidewall film 44 is also deposited on the top surface of the mask-formed wall 43. The sidewall film 44 is a metal-containing film. The sidewall film 44 is not particularly limited, but may be, for example, a metallic nitride film. In this example, the sidewall film 44 is titanium nitride (TiN). In the sputtering method for depositing titanium nitride, titanium (Ti) may be used as the target, nitrogen gas (N2) as the reactive gas, and argon gas (Ar) as the inert gas. Alternatively, the sidewall film 44 may be deposited on the inner wall of the groove 52 using, for example, atomic layer deposition. As will be explained in the second manufacturing method described later, the coverage of the sidewall film 44 deposited using atomic layer deposition is improved. Therefore, the sidewall film 44 can be deposited well even if the pitch of the groove 52 is narrow.

[0026] Next, as shown in Figure 6, the shielding portion 46 is embedded in the groove 52 using a deposition technique such as atomic layer deposition. The shielding portion 46 is also deposited on the top surface of the mask-formed wall 43, completely filling the groove 52. The shielding portion 46 is a film containing metal. The shielding portion 46 is not particularly limited, but may be a single film of metal, for example. In this example, the shielding portion 46 is made of tungsten (W). In the atomic layer deposition method for depositing the tungsten film, there are no particular limitations, but tungsten hexafluoride (WF6), which is a metal precursor gas, and hydrogen (H2), which is a reducing gas, may be used. The material of the shielding portion 46 may also be tungsten silicide (WSi2).

[0027] Next, as shown in Figure 7, the shielding portion 46 formed on the top surface of the mask-molded wall 43 is removed using a planarization technique such as CMP. In this planarization step, the side wall film 44 formed on the top surface of the mask-molded wall 43 is also removed, exposing the mask-molded wall 43.

[0028] Next, as shown in Figure 8, the mask-forming walls 43 between the shielding portions 46 are removed using etching techniques such as RIE or wet etching, forming an opening 54 and patterning the ion implantation mask. In this etching process, only the mask-forming walls 43 are removed, and the lift-off film 40 remaining on the lower epitaxial layer 14A is not removed. Alternatively, the opening 54 may penetrate the lift-off film 40.

[0029] Next, as shown in Figure 9, ion implantation technology is used to implant p-type impurities into the lower epitaxial layer 14A by passing them through the opening 54 of the ion implantation mask. The p-type impurities are not particularly limited, but may be aluminum, for example. The region of the lower epitaxial layer 14A into which the p-type impurities have been introduced becomes a p-type column 14a, and the region sandwiched between the p-type columns 14a becomes an n-type column 14b. As a result, a structure is formed in the lower epitaxial layer 14A in which p-type columns 14a and n-type columns 14b are repeatedly arranged alternately along one direction.

[0030] Next, as shown in Figure 10, the lift-off film 40, sidewall film 44, and shielding portion 46 deposited on the lower epitaxial layer 14A are removed using the lift-off method. Specifically, the lift-off film 40 is etched using an etching solution (e.g., hydrofluoric acid) with a higher etching rate for the lift-off film 40 than for the sidewall film 44 and shielding portion 46, thereby removing the sidewall film 44 and shielding portion 46 laminated on the lift-off film 40.

[0031] Next, as shown in Figure 11, the upper epitaxial layer 14B is crystallized on the lower epitaxial layer 14A using epitaxial growth technology, and then a structure is formed in the upper epitaxial layer 14B in which p-type columns 14a and n-type columns 14b are alternately and repeatedly arranged in one direction. Such an upper epitaxial layer 14B is formed by repeating each of the processes described in Figures 2 to 10. As a result, the p-type columns 14a and n-type columns 14b formed in the lower epitaxial layer 14A and the upper epitaxial layer 14B are connected vertically to form a superjunction structure.

[0032] Subsequently, a body region 16 containing p-type impurities is formed on the upper epitaxial layer 14B using epitaxial growth technology, and a source region 18 and a body contact region 19 are formed in a predetermined region within the body region 16 using ion implantation technology, thereby completing the semiconductor device 1 by forming various electrode structures (trench gate 30, drain electrode 22, and source electrode 24).

[0033] The ion implantation mask used in the above manufacturing method has a shielding portion 46 containing metal. The shielding portion 46 containing metal has high shielding properties against p-type impurities (aluminum in this example). Therefore, even if the thickness of the shielding portion 46 is thin, it is possible to sufficiently shield against p-type impurities and prevent them from being implanted into the non-ion implantation regions of the epitaxial layers 14A and 14B. Because the thickness of the shielding portion 46 is thin, the aspect ratio of the openings 54 formed in the shielding portion 46 is low. As a result, the occurrence of situations such as the shielding portion 46 tilting between the openings 54 is suppressed.

[0034] The opening 54 of the ion implantation mask used in the above manufacturing method is formed by removing the mask molding wall 43 located between the shielding portions 46 that are pre-embedded in the mask molding layer 42. Alternatively, consider the case where the opening 54 is formed by directly etching the tungsten-containing shielding portions 46. For example, if the shielding portions 46 are directly etched using the RIE method, the etching proceeds along the grain boundaries of the shielding portions 46. Because the grain size of tungsten is relatively large, the maximum surface roughness of the side surface of the opening 54 becomes large. On the other hand, in the above manufacturing method, the shielding portions 46 are not directly etched, so the maximum surface roughness of the opening 54 of the ion implantation mask is small. As a result, the maximum surface roughness of the interface between the p-type column 14a and the n-type column 14b formed in the epitaxial layers 14A and 14B is also reduced. The semiconductor device 1 manufactured by the above manufacturing method can suppress the disruption of the charge balance of the superjunction structure and have high voltage resistance characteristics.

[0035] The ion implantation mask used in the above manufacturing method has a sidewall film 44 that covers the side surface of the shielding portion 46. The material of the shielding portion 46 is tungsten, and the material of the sidewall film 44 is titanium nitride. The sidewall film 44 is made of a material with a smaller grain size than the shielding portion 46. By covering the side surface of the shielding portion 46 with the sidewall film 44, the sidewall film 44 with a smaller grain size is exposed on the side surface of the opening 54 of the ion implantation mask. As a result, the maximum surface roughness of the side surface of the opening 54 of the ion implantation mask is kept low. As a result, the maximum surface roughness of the interface between the p-type column 14a and the n-type column 14b formed in the epitaxial layers 14A and 14B is also reduced. The semiconductor device 1 manufactured by the above manufacturing method can have high voltage resistance characteristics because the disruption of the charge balance of the superjunction structure is suppressed.

[0036] The grain size of the tungsten material used for the shielding portion 46 ranges from 17 nm to 30 nm, depending on the crystal orientation. For example, if the shielding portion 46 is directly etched using the RIE method to form the opening of the ion implantation mask, various crystal orientations are exposed on the side surface of the opening 54 of the ion implantation mask, resulting in a maximum surface roughness of 30 nm for the opening 54. It is also considered that the maximum surface roughness of the interface between the p-type column 14a and the n-type column 14b formed using such an ion implantation mask will also be 30 nm. For example, if the pitch in the repeating direction of the p-type column 14a and the n-type column 14b is 0.4 μm or less, a maximum surface roughness of 30 nm at the interface between the p-type column 14a and the n-type column 14b raises concerns about an imbalance in the charge balance of the superjunction structure. On the other hand, in the ion implantation mask manufactured using the above method, the shielding portion 46 is not directly etched, so the maximum surface roughness of the opening 54 of the ion implantation mask is less than 30 nm. Furthermore, since a sidewall film 44 with a small crystal grain size is exposed on the side of the opening 54 of the ion implantation mask, the maximum surface roughness of the opening 54 of the ion implantation mask can be further reduced to less than 25 nm, less than 20 nm, less than 15 nm, or less than 10 nm. Thus, even when the pitch of the p-type column 14a and n-type column 14b in the repeating direction is 0.4 μm or less, the above manufacturing method can suppress the disruption of the charge balance of the superjunction structure and provide high voltage resistance characteristics.

[0037] In the above manufacturing method, when forming grooves 52 in the mask-molded layer 42 and when removing the mask-molded wall 43, a lift-off film 40 is left on the epitaxial layers 14A and 14B. With this method, the lift-off film 40 can function as a protective film. Therefore, damage to the upper surfaces of the epitaxial layers 14A and 14B is suppressed. In addition, the lift-off film 40 remaining on the epitaxial layers 14A and 14B can function as a through-film when ion implanting p-type impurities. Therefore, damage to the upper surfaces of the epitaxial layers 14A and 14B during ion implantation is also suppressed.

[0038] In the ion implantation mask used in the above manufacturing method, a lift-off film 40 remains on the epitaxial layers 14A and 14B. The presence of the lift-off film 40 suppresses metal contamination, preventing metal (tungsten in this example) contained in the shielding portion 46 from penetrating the epitaxial layers 14A and 14B. For example, if metal contained in the shielding portion 46 remains between the lower epitaxial layer 14A and the upper epitaxial layer 14B, there is a concern that the charge balance of the superjunction structure will be disrupted, leading to a decrease in the breakdown voltage of the semiconductor device 1. For this reason, the above manufacturing method is particularly useful when forming a superjunction structure in two stages.

[0039] (Second manufacturing method) The second manufacturing method for semiconductor device 1 will be described below with reference to Figures 12 to 20. The process is the same as the first manufacturing method up to the step shown in Figure 2.

[0040] Next, as shown in Figure 12, a lift-off film 140 is deposited on the lower epitaxial layer 14A using a deposition technique such as sputtering. The lift-off film 140 is not particularly limited, but may be an oxide film such as silicon oxide. The thickness of the lift-off film 140 is not particularly limited, but may be, for example, 20 nm.

[0041] Next, as shown in Figure 13, a diffusion barrier film 141 is deposited on the lift-off film 140 using a deposition technique such as sputtering. The diffusion barrier film 141 is not particularly limited, but may be, for example, a silicon nitride film (SiN). The thickness of the diffusion barrier film 141 is not particularly limited, but may be, for example, 20 nm.

[0042] Next, as shown in Figure 14, a mask-molded layer 142 is formed on the diffusion barrier film 141 using a deposition technique such as CVD. The mask-molded layer 142 is not particularly limited, but may be an oxide film such as silicon oxide. The thickness of the mask-molded layer 142 is not particularly limited, but may be, for example, 1.1 μm.

[0043] Next, as shown in Figure 15, multiple grooves 152 are formed in the mask-molded layer 142 using etching techniques such as RIE or wet etching. The portion of the mask-molded layer 142 remaining between the grooves 152 is called the mask-molded wall 143. The grooves 152 extend from the upper surface of the mask-molded layer 142 toward the diffusion barrier film 141. In this example, the grooves 152 penetrate the mask-molded layer 142 and reach the diffusion barrier film 141. Alternatively, the grooves 152 may not penetrate the mask-molded layer 142, and a portion of the mask-molded layer 42 may remain on the diffusion barrier film 141.

[0044] Next, as shown in Figure 16, a sidewall film 144 is deposited on the inner wall of the groove 152 using a deposition technique such as atomic layer deposition. The sidewall film 144 is also deposited on the top surface of the mask-formed wall 143. The sidewall film 144 is not particularly limited, but may be, for example, a metallic nitride film. In this example, the sidewall film 144 is titanium nitride (TiN). In the atomic layer deposition method for depositing titanium nitride, there are no particular limitations, but titanium tetrachloride (TiCl4) as a metal precursor gas and ammonia (NH4) as a nitrogen precursor gas may be used.

[0045] In the second manufacturing method, the sidewall film 144 is formed using atomic layer deposition. Compared to the first manufacturing method, in which the sidewall film 44 is formed using sputtering, the sidewall film 144 formed using atomic layer deposition is well formed on the inner wall of the groove 152 even if the width of the groove 152 is narrow. Therefore, the pitch of the groove 152 can be narrowed, and consequently, the pitch of the superjunction structure can be narrowed. On the other hand, in atomic layer deposition, metal chloride is used as the metal precursor gas. Therefore, there is a concern that chlorine contained in the metal chloride may diffuse into the lower epitaxial layer 14A. Chlorine diffused into the lower epitaxial layer 14A may cause fluctuations in the gate threshold voltage during cycle operation. In the second manufacturing method, a diffusion barrier film 141 is provided between the groove 152 and the lower epitaxial layer 14A. The diffusion barrier film 141 is made of a material that diffuses less to chlorine than the lift-off film 140. Because such a diffusion barrier film 141 is provided, even if the sidewall film 144 is formed using atomic layer deposition, the diffusion of chlorine contained in the metal chloride into the lower epitaxial layer 14A is suppressed.

[0046] Next, as shown in Figure 17, the shielding portion 146 is embedded in the groove 152 using a deposition technique such as atomic layer deposition. The shielding portion 146 is also deposited on the top surface of the mask-formed wall 143, completely filling the groove 152. The shielding portion 146 is a metal-containing film. The shielding portion 146 is not particularly limited, but may be a single metal film, for example. In this example, the shielding portion 146 is tungsten (W). In atomic layer deposition, although not particularly limited, tungsten hexafluoride (WF6), a metal precursor gas, and hydrogen (H2), a reducing gas, may be used. The material of the shielding portion 146 may also be tungsten silicide (WSi2).

[0047] Next, as shown in Figure 18, the shielding portion 146 formed on the top surface of the mask-molded wall 143 is removed using a planarization technique such as CMP. In this planarization step, the side wall film 144 formed on the top surface of the mask-molded wall 143 is also removed, exposing the mask-molded wall 143.

[0048] Next, as shown in Figure 19, the mask-molded walls 143 between the shielding portions 146 are removed using etching techniques such as RIE or wet etching to form an opening 154 and pattern the ion implantation mask. The diffusion barrier film 141 is exposed at the bottom of the opening 154. Alternatively, a portion of the mask-molded walls 143 may remain.

[0049] Next, as shown in Figure 20, p-type impurities are ion-implanted into the lower epitaxial layer 14A by passing through the opening 154 of the ion implantation mask using ion implantation technology. The p-type impurities are not particularly limited, but may be aluminum, for example. The region of the lower epitaxial layer 14A into which the p-type impurities have been introduced becomes a p-type column 14a, and the region sandwiched between the p-type columns 14a becomes an n-type column 14b. As a result, a structure is formed in the lower epitaxial layer 14A in which p-type columns 14a and n-type columns 14b are alternately and repeatedly arranged along one direction.

[0050] Next, similar to the first manufacturing method, the lift-off method is used to remove the lift-off film 140, diffusion barrier film 141, sidewall film 144, and shielding portion 146 deposited on the lower epitaxial layer 14A. This forms the lower epitaxial layer 14A in the state shown in Figure 10. Furthermore, after growing the upper epitaxial layer 14B on the lower epitaxial layer 14A using epitaxial growth technology, a structure is formed in the upper epitaxial layer 14B in which p-type columns 14a and n-type columns 14b are repeatedly arranged alternately along one direction. This upper epitaxial layer 14B is formed by repeating each of the steps described in Figures 12 to 20. As a result, the p-type columns 14a and n-type columns 14b formed in the lower epitaxial layer 14A and the upper epitaxial layer 14B are connected vertically to form a superjunction structure. Subsequently, the semiconductor device 1 is completed through a process similar to that of the first manufacturing method.

[0051] As described above, the second manufacturing method, by providing a diffusion barrier film 141, can suppress chlorine diffusion when the sidewall film 144 is formed using atomic layer deposition, thereby suppressing fluctuations in the gate threshold voltage during cycle operation. Furthermore, since the second manufacturing method forms the sidewall film 144 using atomic layer deposition, the pitch of the grooves 152 in the mask molding layer 142 can be narrowed due to good coverage, and consequently, the pitch of the superjunction structure can be narrowed. Thus, the second manufacturing method is a useful technique for miniaturizing the superjunction structure.

[0052] The following summarizes the features of the technology disclosed in this specification. Note that each of the technical elements described below is an independent technical element, and exhibits technical usefulness either individually or in various combinations.

[0053] (Aspect 1) A method for manufacturing a semiconductor device (1) having a superjunction structure in which first conductive column (14a) and second conductive column (14b) are repeatedly arranged alternately along at least one direction, The first step involves patterning an ion implantation mask onto a second conductive semiconductor layer (14A, 14B), The process includes, after the first step, a second step of ion implanting a first conductivity type impurity into the second conductivity type semiconductor layer by passing it through the opening (54, 154) of the ion implantation mask to form a first conductivity type column and a second conductivity type column. The first step described above is, The first step involves forming a mask-molded layer (42,142) on the second conductive semiconductor layer, A second step involves forming grooves (52, 152) extending from the upper surface of the mask-molded layer toward the second conductive semiconductor layer, A third step involves embedding a shielding portion (46, 146) containing metal into the groove, A method for manufacturing a semiconductor device, comprising a fourth step of removing the mask molding layer between the shielding portions to form the opening.

[0054] (Aspect 2) The first step described above is, Between the second and third steps, there is further a step of forming a side wall film (44, 144) on the inner wall of the groove. The method for manufacturing a semiconductor device according to embodiment 1, wherein the sidewall film has a smaller crystal grain size than the shielding portion.

[0055] (Aspect 3) The method for manufacturing a semiconductor device according to embodiment 2, wherein the sidewall film is formed using atomic layer deposition.

[0056] (Aspect 4) The method for manufacturing a semiconductor device according to embodiment 2, wherein the sidewall film is titanium nitride.

[0057] (Aspect 5) A method for manufacturing a semiconductor device according to any one of embodiments 1 to 3, wherein in the second and fourth steps of the first step, a portion of the mask molding layer is left on the second conductive semiconductor layer to form a lift-off film (40).

[0058] (Aspect 6) In the first step, the first step is to deposit a lift-off film (140), a diffusion barrier film (141), and the mask molding layer on the second conductive semiconductor layer in this order. The method for manufacturing a semiconductor device according to embodiment 3 or 4, wherein the diffusion barrier film is made of a material that diffuses less to chlorine than the lift-off film.

[0059] (Aspect 7) The method for manufacturing a semiconductor device according to embodiment 6, wherein the diffusion barrier film is silicon nitride.

[0060] (Pattern 8) A method for manufacturing a semiconductor device according to embodiment 5 or 6, further comprising a third step of etching the lift-off film to lift off the ion implantation mask after the second step.

[0061] (Aspect 9) The method further comprises a fourth step of forming a second conductivity type epitaxial layer (14B) on the second conductivity type semiconductor layer after the third step, A method for manufacturing a semiconductor device according to embodiment 8, wherein when the second conductivity type epitaxial layer is the second conductivity type semiconductor layer, the first conductivity type column and the second conductivity type column formed on the second conductivity type semiconductor layer and the second conductivity type epitaxial layer, respectively, are connected to form the superjunction structure by further carrying out the first to third steps.

[0062] (Aspect 10) A method for manufacturing a semiconductor device according to any one of embodiments 1 to 9, wherein the metal contained in the shielding portion contains at least tungsten.

[0063] (Aspect 11) A semiconductor device (1) having a superjunction structure in which first conductive column (14a) and second conductive column (14b) are repeatedly arranged alternately along at least one direction, Each of the first conductive column and the second conductive column is silicon carbide, The pitch of the first conductive column and the second conductive column in the repeating direction is 0.4 μm or less. A semiconductor device in which the maximum surface roughness of the interface between the first conductive column and the second conductive column is less than 30 nm.

[0064] (Aspect 12) The semiconductor device according to embodiment 11, wherein the aspect ratio of each of the first conductive column and the second conductive column is 8.5 or greater.

[0065] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0066] 1: Semiconductor device, 10: Semiconductor layer, 12: Drain region, 14: Drift region, 14a: p-type column, 14b: n-type column, 16: Body region, 18: Source region, 19: Body contact region, 22: Drain electrode, 24: Source electrode, 30: Trench gate, 32: Gate electrode, 34: Gate insulating film

Claims

1. A method for manufacturing a semiconductor device (1) having a superjunction structure in which a first conductive column (14a) and a second conductive column (14b) are repeatedly arranged alternately along at least one direction, The first step involves patterning an ion implantation mask onto a second conductive semiconductor layer (14A, 14B), The process includes, after the first step, a second step of ion implanting a first conductivity type impurity into the second conductivity type semiconductor layer by passing it through the openings (54, 154) of the ion implantation mask to form the first conductivity type column and the second conductivity type column. The first step is, The first step is to form a mask molding layer (42, 142) on the second conductive semiconductor layer, A second step involves forming grooves (52, 152) extending from the upper surface of the mask-molded layer toward the second conductive semiconductor layer, A third step involves embedding a shielding portion (46, 146) containing metal into the groove, A method for manufacturing a semiconductor device, comprising a fourth step of removing the mask molding layer between the shielding portions to form the opening.

2. The first step is, Between the second and third steps, there is further a step of forming a side wall film (44, 144) on the inner wall of the groove. The method for manufacturing a semiconductor device according to claim 1, wherein the sidewall film has a smaller crystal grain size than the shielding portion.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the sidewall film is formed using atomic layer deposition.

4. The method for manufacturing a semiconductor device according to claim 2, wherein the sidewall film is titanium nitride.

5. The method for manufacturing a semiconductor device according to claim 1, wherein in the second and fourth steps of the first step, a portion of the mask molding layer is left on the second conductive semiconductor layer to form a lift-off film (40).

6. In the first step, the first step is to deposit a lift-off film (140), a diffusion barrier film (141), and the mask molding layer on the second conductive semiconductor layer in this order. The method for manufacturing a semiconductor device according to claim 3, wherein the diffusion barrier film is made of a material that diffuses less to chlorine than the lift-off film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the diffusion barrier film is silicon nitride.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, further comprising a third step of etching the lift-off film after the second step to lift off the ion implantation mask.

9. The method further comprises a fourth step of forming a second conductivity type epitaxial layer (14B) on the second conductivity type semiconductor layer after the third step, The method for manufacturing a semiconductor device according to claim 8, wherein when the second conductivity type epitaxial layer is the second conductivity type semiconductor layer, the first conductivity type column and the second conductivity type column formed on the second conductivity type semiconductor layer and the second conductivity type epitaxial layer, respectively, are connected to form the superjunction structure by further carrying out the first to third steps.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the metal included in the shielding portion includes at least tungsten.

11. A semiconductor device (1) having a superjunction structure in which first conductive column (14a) and second conductive column (14b) are repeatedly arranged alternately along at least one direction, Each of the first conductive column and the second conductive column is silicon carbide, The pitch of the first conductive column and the second conductive column in the repeating direction is 0.4 μm or less. A semiconductor device in which the maximum surface roughness of the interface between the first conductive column and the second conductive column is less than 30 nm.

12. The semiconductor device according to claim 11, wherein the aspect ratio of each of the first conductive column and the second conductive column is 8.5 or greater.

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