Multilayer electronic components

Abstract

To provide a stacked electronic component that offers superior reliability and prevents mounting defects. [Solution] A stacked electronic component 100 according to one embodiment of the present invention includes a body 110 that includes a dielectric layer and internal electrodes alternately arranged with the dielectric layer in a first direction, a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first and second surfaces and facing each other in a second direction, a fifth surface 5 and a sixth surface 6 connected to the first, second, third and fourth surfaces and facing each other in a third direction, external electrodes 131, 132 that include connecting portions arranged on the third and fourth surfaces and band portions extending from the connecting portions to a part of the first surface, bump electrodes 141, 142 arranged on the band portions of the external electrodes, and solder layers 151, 152 that include Sn-based solder containing one or more of Sb, Ag and Cu, are arranged between the band portions of the external electrodes and the bump electrodes, and extend to the cross section of the bump electrodes in a second direction and the connecting portion of the external electrodes.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] Multilayer ceramic capacitors (MLCCs), a type of multilayer electronic component, are important chip components used in industries such as communications, computers, consumer electronics, and automobiles due to their advantages of being small yet guaranteeing high capacitance. In particular, they are core passive elements used in various electrical, electronic, and information communication devices such as mobile phones, computers, and digital televisions. Furthermore, as multilayer ceramic capacitors are increasingly used in automobiles and infotainment systems, the demand for high reliability, high strength characteristics, and miniaturization is growing.

[0003] Because the dielectric layers contained in multilayer ceramic capacitors have piezoelectric and electrostrictive properties, when a DC or AC voltage is applied to a multilayer ceramic capacitor, a piezoelectric phenomenon may occur between the internal electrodes, potentially causing vibration.

[0004] Such vibrations are transmitted to the printed circuit board on which the multilayer ceramic capacitor is mounted via the external electrodes of the multilayer ceramic capacitor, generating vibrational noise. This vibrational noise can correspond to an audible frequency range of 20 to 20,000 Hz, which is unpleasant to humans, and such vibrational noise that causes discomfort to humans is called acoustic noise.

[0005] Traditionally, methods to reduce acoustic noise have included making the upper and lower covers of the main unit different in thickness, connecting an interposer containing ceramic material to the bottom of the capacitor, or connecting a metal bump to the bottom of the capacitor.

[0006] In the case of a method for connecting a metal bump to the bottom of a capacitor, a known method is to connect the external electrode and the metal bump with high-temperature solder, as shown in Patent Document 1, and then fix the substrate and electronic components later with general solder.

[0007] In products with metal bumps (where high-temperature solder is present only between the external electrode and the metal bump), the soldering process is added, causing the Sn plating layer that provides mountability to flow downwards, resulting in a thinner upper layer compared to general products. If the Ni plating layer becomes thin or broken, it can act as a pathway for moisture penetration, potentially reducing reliability. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Korean Published Patent No. 10-2023-0022782 [Overview of the project] [Problems that the invention aims to solve]

[0009] One of the several objectives of the present invention is to provide a highly reliable stacked electronic component.

[0010] One of the several objectives of this invention is to prevent the occurrence of mounting defects.

[0011] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0012] A stacked electronic component according to one embodiment of the present invention includes a body comprising a dielectric layer and internal electrodes alternately arranged with the dielectric layer in a first direction, the body comprising a first and second surface facing the first direction, a third and fourth surface connected to the first and second surfaces and facing the second direction, and a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing the third direction; an external electrode comprising connecting portions arranged on the third and fourth surfaces and a band portion extending from the connecting portions to a part of the first surface; a bump electrode disposed on the band portion of the external electrode; and a solder layer comprising Sn-based solder containing one or more of Sb, Ag, and Cu, disposed between the band portion of the external electrode and the bump electrode, and extending to the cross section of the bump electrode in a second direction and the connecting portion of the external electrode. [Effects of the Invention]

[0013] One of the various effects of the present invention is that the reliability of multilayer electronic components has been improved by controlling the arrangement of the solder layer connecting the bump electrode and the band portion.

[0014] One of the various effects of the present invention is to suppress the occurrence of mounting defects when mounting multilayer electronic components onto a substrate.

[0015] However, the diverse yet beneficial advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0016] [Figure 1] This is a perspective view showing a stacked electronic component according to one embodiment of the present invention. [Figure 2] Figure 1 is a bottom perspective view of the stacked electronic component. [Figure 3] This is a cross-sectional view along the line I-I' in Figure 1. [Figure 4] This is a cross-sectional view along the line II-II' in Figure 1. [Figure 5]It is an exploded perspective view showing the decomposition of the main body of a stacked electronic component according to an embodiment of the present invention. [Figure 6] It is an enlarged view of the K1 region in FIG. 3. [Figure 7] It schematically shows the lower surface of the bump electrode. [Figure 8] It is an enlarged view of the K1 region in FIG. 3 according to another embodiment.

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to an ordinary technician. Therefore, the shapes and sizes of elements in the drawings can be exaggerated for a clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0018] And, in order to clearly explain the present invention in the drawings, parts not related to the explanation are omitted, and the sizes and thicknesses of each configuration shown in the drawings are arbitrarily shown for the convenience of explanation, so the present invention is not necessarily limited to what is shown in the drawings. In addition, for components having the same functions within the scope of the same concept, the same reference numerals are used for explanation. Furthermore, throughout the specification, when a certain part says that a certain component "includes", this means that other components can be further included, rather than excluding other components, unless otherwise stated to the contrary.

[0019] In the drawings, the first direction can be defined as the thickness T direction, the second direction as the length L direction, and the third direction as the width W direction.

[0020] Figure 1 is a perspective view showing a stacked electronic component 100 according to one embodiment of the present invention; Figure 2 is a bottom perspective view of the stacked electronic component according to Figure 1; Figure 3 is a cross-sectional view along the line I-I' in Figure 1; Figure 4 is a cross-sectional view along the line II-II' in Figure 1; Figure 5 is an exploded perspective view showing the body of the stacked electronic component according to one embodiment of the present invention in disassembled form; and Figure 6 is an enlarged view of the K1 region in Figure 3.

[0021] The following describes a stacked electronic component 100 according to one embodiment of the present invention, with reference to Figures 1 to 6.

[0022] A stacked electronic component 100 according to one embodiment of the present invention includes a dielectric layer 111 and internal electrodes 121, 122 arranged alternately with the dielectric layer in a first direction, and a body 110 including a first surface 1 and a second surface 1, 2 facing in the first direction, a third surface 3 and a fourth surface 3, 4 connected to the first and second surfaces and facing in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first, second, third, and fourth surfaces and facing in a third direction, and the third surface and the fourth surface The device may include external electrodes 131, 132 including a connecting portion CP and a band portion BP extending from the connecting portion to a part of the first surface; bump electrodes 141, 142 positioned on the band portion of the external electrodes; and solder layers 151, 152 comprising Sn-based solder containing one or more of Sb, Ag, and Cu, positioned between the band portion of the external electrodes and the bump electrodes, and extending between the cross section of the bump electrodes in a second direction and the connecting portion of the external electrodes.

[0023] The main body 110 has dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0024] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be a hexahedron or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedron-shaped.

[0025] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0026] In one embodiment, the main body 110 includes a first-to-third corner connecting the first and third surfaces, a first-to-fourth corner connecting the first and fourth surfaces, a second-to-third corner connecting the second and third surfaces, and a second-to-fourth corner connecting the second and fourth surfaces. The first-to-third corner and the second-to-third corner have a shape that contracts towards the center of the main body in the first direction as they approach the third surface, and the first-to-fourth corner and the second-to-fourth corner can have a shape that contracts towards the center of the main body in the first direction as they approach the fourth surface.

[0027] Due to the overlap of margin regions on the dielectric layer 111 where internal electrodes 121 and 122 are not placed, a step difference is generated due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a form that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 may have a form that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the main body 110 can be rounded by performing a separate process to round the corners connecting the first face with the third, fourth, fifth, and sixth faces, and / or the corners connecting the second face with the third, fourth, fifth, and sixth faces.

[0028] The above-mentioned corners may include the 1st-3rd corner connecting the 1st and 3rd faces, the 1st-4th corner connecting the 1st and 4th faces, the 2nd-3rd corner connecting the 2nd and 3rd faces, and the 2nd-4th corner connecting the 2nd and 4th faces. The corners may also include the 1st-5th corner connecting the 1st and 5th faces, the 1st-6th corner connecting the 1st and 6th faces, the 2nd-5th corner connecting the 2nd and 5th faces, and the 2nd-6th corner connecting the 2nd and 6th faces. The 1st, 2nd, 3rd, 4th, 5th, and 6th faces of the main body 110 can generally be flat surfaces, and non-flat areas can be considered corners. Hereinafter, the extension of each face may mean a line extending from the flat portion of each face.

[0029] On the other hand, in order to suppress the step caused by the internal electrodes 121 and 122, if the internal electrodes after lamination are cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, and then a single dielectric layer or two or more dielectric layers are laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form margin portions 114 and 115, the portions connecting the first surface with the fifth and sixth surfaces, and the portions connecting the second surface with the fifth and sixth surfaces, may not have a contracted form.

[0030] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0031] According to one embodiment of the present invention, the raw material for forming the dielectric layer 111 is not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate-based materials, lead-composite perovskite-based materials, or strontium titanate-based materials can be used. The barium titanate-based material may include BaTiO3-based ceramic powder, and examples of the ceramic powder include BaTiO3, BaTiO3 in which Ca (calcium), Zr (zirconium), etc. are partially solid-dissolved (BaTiO3). 1-x Ca x)TiO3(0 < x < 1), Ba(Ti 1-y Ca y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1) or Ba(Ti 1-y Zr y )O3(0 < y < 1), etc. can be mentioned.

[0032] Also, for the raw material for forming the dielectric layer 111, various ceramic additives, organic solvents, binders, dispersants, etc. can be added to powders such as barium titanate (BaTiO3) according to the purpose of the present invention.

[0033] The main body 110 includes a first internal electrode 121 and a second internal electrode 122 that are disposed inside the main body 110 and are disposed to face each other with the dielectric layer 111 interposed therebetween, and may include a capacitance forming portion Ac where a capacitance is formed and cover portions 112, 113 formed above and below the capacitance forming portion Ac in a first direction.

[0034] Also, the capacitance forming portion Ac is a portion that contributes to the formation of the capacitance of the capacitor, and can be formed by repeatedly laminating a plurality of first internal electrodes 121 and second internal electrodes 122 with the dielectric layer 111 interposed therebetween.

[0035] The cover portions 112, 113 may include an upper cover portion 112 disposed above the capacitance forming portion Ac in a first direction and a lower cover portion 113 disposed below the capacitance forming portion Ac in a first direction.

[0036] The upper cover portion 112 and the lower cover portion 113 can be formed by laminating a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, and can basically play a role in preventing damage to the internal electrodes due to physical or chemical stress.

[0037] The upper cover portion 112 and the lower cover portion 113 described above do not include internal electrodes and may contain the same material as the dielectric layer 111.

[0038] In other words, the upper cover portion 112 and the lower cover portion 113 can include ceramic materials, for example, barium titanate (BaTiO3) based ceramic materials.

[0039] Furthermore, margin portions 114 and 115 may be arranged on the side surface of the volume-forming portion Ac.

[0040] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the main body 110.

[0041] As shown in Figure 4, the margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the body 110 in the width-thickness (WT) direction.

[0042] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0043] The margin portions 114 and 115 may be formed by applying a conductive paste to the ceramic green sheet, except for the areas where the margin portions are formed, to form internal electrodes.

[0044] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated in the third direction (width direction) on both sides of the capacitance forming portion Ac to form margin portions 114 and 115.

[0045] The internal electrodes 121 and 122 may be stacked alternately with the dielectric layer 111.

[0046] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0047] Referring to Figure 3, the first internal electrode 121 can be separated from the fourth surface 4 and exposed via the third surface 3, and the second internal electrode 122 can be separated from the third surface 3 and exposed via the fourth surface 4. The first external electrode 131 can be placed on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 can be placed on the fourth surface 4 of the main body and connected to the second internal electrode 122.

[0048] In other words, the first internal electrode 121 is not connected to the second external electrode 132, but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131, but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance from the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance from the third surface 3.

[0049] In this case, the first internal electrode 121 and the second internal electrode 122 can be electrically isolated from each other by the dielectric layer 111 placed in between them.

[0050] The main body 110 can be formed by alternately stacking ceramic green sheets printed with the first internal electrode 121 and ceramic green sheets printed with the second internal electrode 122, and then firing them.

[0051] The materials used to form the internal electrodes 121 and 122 are not particularly limited, and any material with excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 may include one or more of the following: nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0052] Furthermore, the internal electrodes 121 and 122 can be formed by printing a conductive paste for internal electrodes containing one or more of the following onto a ceramic green sheet: nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. While screen printing or gravure printing can be used as the printing method for the conductive paste for internal electrodes, the present invention is not limited thereto.

[0053] The external electrodes 131 and 132 may include connection portions CP located on the third and fourth surfaces, and band portions BP extending from the connection portions to a part of the first surface. Referring to Figure 3, the region of the external electrodes 131 and 132 located between the extension line E1 of the first surface and the extension line E2 of the second surface can be called the connection portion CP, and the region located below the extension line E1 of the first surface can be called the band portion BP.

[0054] On the other hand, the band section BP is not limited to being located on the first surface, but may extend from the connection section to one or more of the second, fifth, and sixth surfaces.

[0055] The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132. The first external electrode 131 may be positioned on the third surface and connected to the first internal electrode 121, and the second external electrode 132 may be positioned on the fourth surface and connected to the second internal electrode 122.

[0056] The bump electrodes 141 and 142 can be placed on the band portion BP of the external electrode. The bump electrodes 141 and 142 can reduce or absorb vibrations transmitted from the substrate to the multilayer electronic component, and can suppress acoustic noise.

[0057] The bump electrodes 141 and 142 may include a first bump electrode 141 and a second bump electrode 142. The first bump electrode 141 may be positioned on the band portion of the first external electrode 131 and electrically connected to the first external electrode 131, and the second bump electrode 142 may be positioned on the band portion of the second external electrode 132 and electrically connected to the second external electrode 132.

[0058] The solder layers 151 and 152 can serve to bond the external electrodes 131 and 132 to the bump electrodes 141 and 142. They can also serve to prevent the Sn plating layers 131c, 132c and / or the bump Sn plating layers 141c and 142c from flowing off when the multilayer electronic component is fixed to the substrate using general solder.

[0059] The solder layers 151 and 152 may contain Sn-based solder that includes one or more of Sb, Ag, and Cu. By including one or more of Sb, Ag, and Cu in the Sn-based solder, the melting point can be 200°C or higher, and when a multilayer electronic component is fixed to the substrate using general solder, the solder layers 151 and 152 do not melt and can play a role in maintaining the bond between the external electrodes 131 and 132 and the bump electrodes 141 and 142.

[0060] According to one embodiment of the present invention, the Sn-based solder may be one or more of Sn-Sb solder, Sn-Ag solder, Sn-Cu solder, and Sn-Ag-Cu solder.

[0061] On the other hand, the content of Sb, Ag, and Cu in Sn-based solder is not particularly limited and can be added as appropriate depending on the intended use and environment.

[0062] For example, in the case of Sn-Ag solder, by setting the Sn content to 96.5 wt% and the Ag content to 3.5 wt%, a high-melting-point solder with a melting point of approximately 221°C can be used. Similarly, in the case of Sn-Cu solder, by setting the Sn content to 99.3 wt% and the Cu content to 0.7 wt%, a high-melting-point solder with a melting point of approximately 227°C can be used.

[0063] The solder layers 151 and 152 are positioned between the band portions BP of the external electrodes 131 and 132 and the bump electrodes 141 and 142, and can extend from the cross-section of the bump electrodes 141 and 142 in a second direction to the connection portion CP of the external electrodes 131 and 132. According to one embodiment of the present invention, by extending from the cross-section of the bump electrodes 141 and 142 in a second direction to the connection portion CP of the external electrodes 131 and 132, it is possible to prevent the Sn plating layers 131c, 132c and / or the bump Sn plating layers 141c, 142c from flowing off when fixing the multilayer electronic component to the substrate using general solder. In addition, the external electrodes 131 and 132 and the bump electrodes 141 and 142 can be bonded more firmly, and the hermetic sealing of the multilayer electronic component 100 can be enhanced.

[0064] If the solder layers 151 and 152 are placed only between the band portion BP of the external electrodes 131 and 132 and the bump electrodes 141 and 142, when fixing the multilayer electronic component to the substrate using general solder, it may not be possible to prevent the Sn plating layers 131c and 132c and the bump Sn plating layers 141c and 142c from flowing off, which may result in mounting defects.

[0065] In one embodiment, the ends of the solder layers 151 and 152 placed on the connection portion may be positioned between the extension line E1 of the first surface and the extension line E2 of the second surface. That is, the solder layers 151 and 152 do not need to cover the entire connection portion CP of the external electrodes; even if only a part is covered, the external electrodes 131 and 132 and the bump electrodes 141 and 142 can be firmly bonded while preventing the Sn plating layer from flowing off.

[0066] In one embodiment, when the average size in the first direction from the first surface to the internal electrode disposed closest to the first surface is H1, the average size in the first direction from the extension line of the first surface to the end of the solder layer disposed on the connection portion is H2, and the size of the main body in the first direction is T, H1 < H2 < T / 2 can be satisfied.

[0067] In order to form the solder layer such that H2 is equal to or greater than T / 2, while preventing the Sn plating layer from flowing down with respect to the required amount of solder, there may be insufficient improvement in the effect of firmly bonding the external electrodes 131 and 132 and the bump electrodes 141 and 142.

[0068] By satisfying H1 < H2, while preventing the Sn plating layer from flowing down, the effect of firmly bonding the external electrodes 131 and 132 and the bump electrodes 141 and 142 can be more reliably ensured.

[0069] [[ID=1l]] However, it is not intended to exclude the case where H2 is less than or equal to H1. Even if H2 is less than or equal to H1, while preventing the Sn plating layer from flowing down, the effect of firmly bonding the external electrodes 131 and 132 and the bump electrodes 141 and 142 can be ensured. Therefore, according to one embodiment of the present invention, H1 ≧ H2 can be satisfied.

[0070] H1 and H2 can be values obtained by averaging the values measured in a cross-section (L-T cross-section) obtained by cutting the main body 110 in the first and second directions at the central portion in the third direction. H1 is a value obtained by averaging the values measured at an arbitrary point in the second direction of the distance between the internal electrode disposed closest to the first surface 1 and the first surface 1 in the cross-section, and H2 is a value measured based on the end of the solder layer disposed on the connection portion, and can be a value obtained by averaging the values measured on the first external electrode 131 side and the values measured on the second external electrode 132 side. At this time, the extension line E1 of the first surface used as a reference when measuring H1 and H2 may be the same.

[0071] Furthermore, the size T of the main body 110 in the first direction can similarly be the size of the extension line E1 of the first surface and the extension line E2 of the second surface in the first direction measured in the cross section (LT cross section) obtained by cutting the main body 110 in the first and second directions at the central part of the third direction.

[0072] In one embodiment, the region of the solder layers 151 and 152 that extends to the cross-section of the bump electrode in the second direction may be arranged to cover 50% or more of the cross-section of the bump electrode in the second direction. This makes it possible to more reliably ensure a strong bond between the external electrodes 131 and 132 and the bump electrodes 141 and 142 while preventing the Sn plating layer from flowing off.

[0073] On the other hand, while solder layers 151 and 152 can extend to the lower surface of the bump electrode in the first direction, if solder layers 151 and 152 extend to the lower surface of the bump electrode in the first direction, when fixing the multilayer electronic component to the substrate using general solder, the solder layers 151 and 152 will not easily melt into the general solder, which may make it difficult to secure sufficient bonding force between the multilayer electronic component and the substrate, potentially leading to mounting defects.

[0074] Therefore, in one embodiment, the solder layers 151 and 152 can be arranged to extend to a portion of the lower surface of the bump electrode in the first direction.

[0075] Referring to Figure 7, which schematically shows the lower surface of the bump electrode, more preferably, the area of ​​the lower surface of the bump electrode 141 in the first direction that is covered by the solder layer 151 may be 10 area % or less. This prevents the Sn plating layer from flowing off while firmly bonding the external electrodes 131, 132 and the bump electrodes 141, 142, and reliably ensuring the bonding force between the multilayer electronic component and the substrate.

[0076] In other words, it is preferable to have a minimal solder layer on the underside of the bump electrode in contact with the substrate, and more preferably, no solder layer may be present on the underside.

[0077] The method for controlling the arrangement of solder layers 151 and 152 is not particularly limited. During the heat treatment process to bond the external electrodes 131 and 132 and the bump electrodes 141 and 142 using solder layers 151 and 152, the arrangement of solder layers 151 and 152 can be controlled by adjusting the heat treatment temperature, the material and amount of solder layers to control the degree of diffusion of solder layers 151 and 152. Furthermore, by attaching a high heat-resistant adhesive film to the underside of the bump electrodes 141 and 142 to mask them before heat treatment, it is possible to more reliably prevent the molten solder layers 151 and 152 from penetrating to the underside of the bump electrodes 141 and 142. After heat treatment, the high heat-resistant adhesive film attached to the underside of the bump electrodes 141 and 142 can be removed.

[0078] On the other hand, at least a portion of the Handa Formation may be arranged in an island-like manner.

[0079] Referring to Figure 8, which is an enlarged view of the K1 region in Figure 3 according to another embodiment, the solder layer 151' is not arranged continuously, but rather has interrupted regions and can be arranged in an island-like manner.

[0080] However, in order to firmly bond the external electrodes 131, 132 and the bump electrodes 141, 142, it is preferable that the region of the solder layer 151' that is placed between the band portion of the external electrode and the bump electrode is arranged in layers.

[0081] On the other hand, the external electrodes 131 and 132 may be formed using any material that has electrical conductivity, such as metal, and the specific material may be determined by considering electrical properties, structural stability, etc., and may also have a multilayer structure.

[0082] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b, 132b, 131c, and 132c formed on the electrode layers.

[0083] As a more specific example for the electrode layers 131a and 132a, the electrode layers may be firing electrodes containing conductive metal and glass, or resin-based electrodes containing conductive metal and resin.

[0084] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. In addition, the electrode layers may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0085] While materials with excellent electrical conductivity can be used as the conductive metal in the electrode layers 131a and 132a, they are not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0086] The plating layers 131b, 132b, 131c, and 132c play a role in improving mounting characteristics. The types of plating layers 131b, 132b, 131c, and 132c are not particularly limited and may be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and may be formed in multiple layers.

[0087] In one embodiment, the external electrodes 131 and 132 are connected to the internal electrodes 121 and 122 and may include electrode layers 131a and 132a containing Cu and glass, Ni plating layers 131b and 132b disposed on the electrode layers, and Sn plating layers 131c and 132c disposed on the Ni plating layers.

[0088] The bump electrodes 141 and 142 may be formed using any material that has electrical conductivity, such as metal, and the specific material may be determined by considering electrical properties, structural stability, etc. Furthermore, they may have a multilayer structure.

[0089] For example, the bump electrodes 141 and 142 may include bump core portions 141a and 142a positioned in the center of the bump electrode, and bump plating layers 141b, 142b, 141c, and 142c positioned on the bump core portions.

[0090] In one embodiment, the bump electrodes 141 and 142 may include bump core portions 141a and 142a containing Cu, bump Ni plating layers 141b and 142b disposed on the bump core portions, and bump Sn plating layers 141c and 142c disposed on the bump Ni plating layers.

[0091] In one embodiment, the solder layers 151 and 152 may be arranged in contact with the Sn plating layers 131c and 132c and the bump Sn plating layers 141c and 142c.

[0092] As described above, embodiments of the present invention have been explained in detail, but the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0093] Furthermore, the expression "one embodiment" as used in the present invention does not mean that each embodiment is the same as another, but is provided to emphasize and describe the unique and distinct features of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the features of other embodiments. For example, even if a matter described in a particular embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, as long as there is no description in the other embodiment that contradicts or is contrary to that matter.

[0094] The terms used in this invention are used solely to describe one embodiment and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0095] 100: Stacked Electronic Components 110: Main unit 111: Dielectric layer 112, 113: Cover section 114, 115: Margin section 121, 122: Internal electrode 131, 132: External electrode 131a, 132a: Electrode layer 131b, 132b, 131c, 132c: Plating layer 141, 142: Bump electrodes 141a, 142a: Bump electrode section 141b, 142b, 141c, 142c: Bump plating layer 151, 152: Handa Formation CP: Connection part BP: Band Club

Claims

1. A body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction, and including a first and second surface facing the first direction, a third and fourth surface connected to the first and second surfaces and facing the second direction, and a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing the third direction, External electrodes including connecting portions arranged on the third and fourth surfaces and band portions extending from the connecting portions to a part of the first surface, A bump electrode is positioned on the band portion of the external electrode, A multilayer electronic component comprising a solder layer that includes an Sn-based solder containing one or more of Sb, Ag, and Cu, disposed between the band portion of the external electrode and the bump electrode, and extending between the cross section of the bump electrode in a second direction and the connection portion of the external electrode.

2. The stacked electronic component according to claim 1, wherein the Sn-based solder is one or more of Sn-Sb-based solder, Sn-Ag-based solder, Sn-Cu-based solder, and Sn-Ag-Cu-based solder.

3. The stacked electronic component according to claim 1, wherein the end of the solder layer placed on the connection portion is positioned between the extension line of the first surface and the extension line of the second surface.

4. When H1 is the average size in the first direction from the first surface to the internal electrode closest to the first surface, H2 is the average size in the first direction from the extension of the first surface to the edge of the solder layer placed on the connection portion, and T is the size of the main body in the first direction, A stacked electronic component according to claim 1, satisfying H1 < H2 < T / 2.

5. H1 is the average size in the first direction from the first surface to the internal electrode closest to the first surface. When H2 is the average size in the first direction from the extension line of the first surface to the edge of the solder layer placed on the connection portion, A multilayer electronic component according to claim 1, satisfying H1 ≥ H2.

6. The laminated electronic component according to claim 1, wherein the region of the solder layer extending to the cross-section in the second direction of the bump electrode is arranged to cover 50% or more of the cross-section in the second direction of the bump electrode.

7. The laminated electronic component according to claim 1, wherein the solder layer is arranged to extend to a portion of the lower surface of the bump electrode in the first direction.

8. The stacked electronic component according to claim 7, wherein the area of ​​the lower surface of the bump electrode in the first direction that is covered by the solder layer is 10 area % or less.

9. The stacked electronic component according to claim 1, wherein at least a portion of the solder layers are arranged in an island-like manner.

10. The laminated electronic component according to claim 9, wherein the region of the solder layer that is arranged between the band portion of the external electrode and the bump electrode is arranged in layers.

11. The stacked electronic component according to any one of claims 1 to 10, wherein the external electrode is connected to the internal electrode and includes an electrode layer containing Cu and glass, a Ni plating layer disposed on the electrode layer, and a Sn plating layer disposed on the Ni plating layer.

12. The stacked electronic component according to claim 11, wherein the bump electrode is located in the center of the bump electrode and includes a bump core portion containing Cu, a bump Ni plating layer disposed on the bump core portion, and a bump Sn plating layer disposed on the bump Ni plating layer.

13. The laminated electronic component according to claim 12, wherein the solder layer is arranged to be in contact with the Sn plating layer and the bump Sn plating layer.

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