Nitride semiconductor transistor

Abstract

To provide a nitride semiconductor transistor that can improve distortion characteristics. [Solution] The nitride semiconductor transistor comprises a barrier layer having a first upper surface with nitrogen polarity, a channel layer located above the first upper surface and having a second upper surface with nitrogen polarity and a first polarization in a first direction, and a ferroelectric layer located above the second upper surface and having a second polarization in a second direction opposite to the first direction.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor transistors. [Background technology]

[0002] Conventionally, high electron mobility transistors (HEMTs) with multiple channels have been proposed. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-252034 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In recent years, there has been a growing demand for further improvements in distortion characteristics. Here, distortion characteristics refer to the distortion characteristics of the output amplitude relative to the input amplitude when a transistor is used as an amplifier (amplitude modulation-amplitude modulation: AM-AM characteristics). AM-AM characteristics improve as the flatness of the transconductance increases.

[0005] This disclosure aims to provide a nitride semiconductor transistor capable of improving strain characteristics. [Means for solving the problem]

[0006] The nitride semiconductor transistor of this disclosure comprises a barrier layer having a first upper surface with nitrogen polarity, a channel layer located above the first upper surface and having a second upper surface with nitrogen polarity and having a first polarization in a first direction, and a ferroelectric layer located above the second upper surface and having a second polarization in a second direction opposite to the first direction. [Effects of the Invention]

[0007] According to this disclosure, distortion characteristics can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to an embodiment. [Figure 2] Figure 2 shows an example of the band structure of a nitride semiconductor transistor according to the present invention. [Figure 3] Figure 3 shows the characteristics of a nitride layer semiconductor transistor. [Figure 4] Figure 4 is a cross-sectional view (part 1) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 2) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 3) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 4) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 5) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] [1] A nitride semiconductor transistor according to one aspect of the present disclosure comprises a barrier layer having a first upper surface having nitrogen polarity, a channel layer located on the first upper surface and having a second upper surface having nitrogen polarity and having a first polarization in a first direction, and a ferroelectric layer located on the second upper surface and having a second polarization in a second direction opposite to the first direction.

[0011] The first upper surface of the barrier layer has a nitrogen polarity, the second upper surface of the channel layer has a nitrogen polarity, the channel layer has a first polarization, and the ferroelectric layer has a second polarization opposite to the first polarization. Therefore, the channel layer can include a two-dimensional electron gas near the lower surface and near the second upper surface. Accordingly, the flatness of the mutual conductance can be improved, and the distortion characteristic (AM-AM characteristic) of the output amplitude with respect to the input amplitude can be improved.

[0012] 〔2〕 In 〔1〕, the channel layer has a lower surface opposite to the second upper surface, and the channel layer may include a first two-dimensional electron gas located closer to the lower surface than the second upper surface and a second two-dimensional electron gas located closer to the second upper surface than the lower surface. In this case, mainly, the first two-dimensional electron gas is generated by the spontaneous polarization of the barrier layer, and the second two-dimensional electron gas is generated by the spontaneous polarization of the ferroelectric layer.

[0013] 〔3〕 In 〔1〕 or 〔2〕, the ferroelectric layer may be a nitride layer including aluminum and at least one selected from the group consisting of scandium, boron, and yttrium. In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer.

[0014] 〔4〕 In 〔3〕, the ferroelectric layer is an aluminum scandium nitride layer, and in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms may be 40% or less. In this case, the aluminum scandium nitride layer is likely to have a wurtzite crystal structure.

[0015] 〔5〕 In 〔3〕, the ferroelectric layer is an aluminum yttrium nitride layer, and in the aluminum yttrium nitride layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms may be 80% or less. In this case, the aluminum yttrium nitride layer is likely to have a wurtzite crystal structure. ​​〔6〕In [1] or [2], the ferroelectric layer may be a hafnium oxide layer containing at least one selected from the group consisting of zirconium, yttrium, lanthanum, and silicon. In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer.

[0017] 〔7〕In [6], the ferroelectric layer is a hafnium zirconium oxide layer, and in the hafnium zirconium oxide layer, the ratio of the number of zirconium atoms to the total number of hafnium atoms and zirconium atoms may be 45% or more and 55% or less. In this case, it is easy to obtain a high-concentration two-dimensional electron gas.

[0018] 〔8〕In [6], the ferroelectric layer is a hafnium yttrium oxide layer, and in the hafnium yttrium oxide layer, the ratio of the number of yttrium atoms to the total number of hafnium atoms and yttrium atoms may be 3% or more and 7% or less. In this case, it is easy to obtain a high-concentration two-dimensional electron gas.

[0019] 〔9〕In [6], the ferroelectric layer is a hafnium lanthanum oxide layer, and in the hafnium lanthanum oxide layer, the ratio of the number of lanthanum atoms to the total number of hafnium atoms and lanthanum atoms may be 1% or more and 7% or less. In this case, it is easy to obtain a high-concentration two-dimensional electron gas.

[0020] 〔10〕In [6], the ferroelectric layer is a hafnium silicon oxide layer, and in the hafnium silicon oxide layer, the ratio of the number of silicon atoms to the total number of hafnium atoms and silicon atoms may be 2% or more and 9% or less. In this case, it is easy to obtain a high-concentration two-dimensional electron gas.

[0021] 〔11〕In [1] or [2], the ferroelectric layer may be an oxide layer containing at least one selected from the group consisting of barium, bismuth, lead, and titanium and having a perovskite crystal structure. In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer.

[0022] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In this disclosure, "plan view" means viewing the object from above. In this disclosure, the direction in which the nitride semiconductor layer is located relative to the substrate is defined as "up".

[0023] Embodiments of this disclosure relate to nitride semiconductor transistors. Nitride semiconductor transistors are, for example, gallium nitride-based high electron mobility transistors (HEMTs). Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to an embodiment.

[0024] As shown in Figure 1, the nitride semiconductor transistor 1 according to the embodiment includes a substrate 10, a nitride semiconductor layer 20, a ferroelectric layer 24, an insulating film 30, a regrowth layer 41S, a regrowth layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0025] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is the carbon (C) polar surface.

[0026] The nitride semiconductor layer 20 includes a buffer layer 21, a barrier layer 22, and a channel layer 23. The nitride semiconductor layer 20 may have a nucleation layer between the substrate 10 and the buffer layer 21.

[0027] The buffer layer 21 is located on the substrate 10. The buffer layer 21 has a top surface 21A with nitrogen polarity. The buffer layer 21 is, for example, a gallium nitride (GaN) layer. The thickness of the buffer layer 21 is, for example, 100 nm to 2000 nm.

[0028] The barrier layer 22 is located on the upper surface 21A of the buffer layer 21. The barrier layer 22 has an upper surface 22A with nitrogen polarity. The barrier layer 22 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the barrier layer 22 is smaller than that of the channel layer 23. The band gap of the barrier layer 22 is larger than that of the channel layer 23. The thickness of the barrier layer 22 is, for example, 5 nm to 40 nm. The composition of the barrier layer 22 is, for example, Al Z Ga 1-Z N(0.15≦Z≦0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al atoms and Ga atoms (Al composition ratio) is between 15% and 55%. The conductivity type of the barrier layer 22 is, for example, n-type or undoped (i-type). The top surface 22A is an example of the first top surface.

[0029] The channel layer 23 is located on the upper surface 22A of the barrier layer 22. The channel layer 23 has an upper surface 23A with nitrogen polarity and a lower surface 23B opposite to the upper surface 23A. The channel layer 23 has a polarization P1 directed from the lower surface 23B toward the upper surface 23A. The channel layer 23 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 23 is, for example, 5 nm to 40 nm. The conductivity type of the channel layer 23 is, for example, n-type or undoped (i-type). The upper surface 23A is an example of a second upper surface, and the polarization P1 is an example of a first polarization.

[0030] The ferroelectric layer 24 is located on the upper surface 23A of the channel layer 23. The ferroelectric layer 24 has an upper surface 24A and a lower surface 24B opposite to the upper surface 24A. The ferroelectric layer 24 has a polarization P2 that points from the upper surface 24A to the lower surface 24B. That is, polarization P2 points in the opposite direction to polarization P1. Polarization P2 is an example of a second polarization.

[0031] A source recess 40S and a drain recess 40D are formed in the laminate of the ferroelectric layer 24 and the nitride semiconductor layer 20. The recesses 40S and 40D penetrate the ferroelectric layer 24 and the channel layer 23. The recesses 40S and 40D may further penetrate the barrier layer 22. The bottoms of the recesses 40S and 40D may be in the barrier layer 22 or in the buffer layer 21.

[0032] The insulating film 30 is located on the upper surface 24A of the ferroelectric layer 24. The insulating film 30 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 30 is, for example, 5 nm to 100 nm. An opening 30S for the source, an opening 30D for the drain, and an opening 30G for the gate are formed in the insulating film 30. The opening 30S is connected to a recess 40S, and the opening 30D is connected to a recess 40D. In a plan view, the opening 30G is located between the openings 30S and 30D. The opening 30G reaches the ferroelectric layer 24.

[0033] The regrowth layer 41S is located within the recess 40S on top of the barrier layer 22 or buffer layer 21. The regrowth layer 41D is located within the recess 40D on top of the barrier layer 22 or buffer layer 21. The regrowth layers 41S and 41D are, for example, n-type GaN layers. The regrowth layers 41S and 41D contain germanium (Ge) or silicon (Si) as n-type impurities.

[0034] The source electrode 42S is on the regrowth layer 41S, and the drain electrode 42D is on the regrowth layer 41D. The source electrode 42S is in contact with the regrowth layer 41S, and the drain electrode 42D is in contact with the regrowth layer 41D. The source electrode 42S is in ohmic contact with the regrowth layer 41S, and the drain electrode 42D is in ohmic contact with the regrowth layer 41D.

[0035] In a plan view, the gate electrode 43 is located between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is on the insulating film 30 and contacts the ferroelectric layer 24 through the opening 30G.

[0036] Here, an example of the band structure of nitride semiconductor transistor 1 will be described. Figure 2 is a diagram showing an example of the band structure of nitride semiconductor transistor 1 according to the embodiment. Figure 2 shows the Fermi level E F and the lower end E of the conduction band C This is shown in Figure 2. In Figure 2, the horizontal axis represents the depth relative to the upper surface 24A of the ferroelectric layer 24, and the vertical axis represents the Fermi level E F This indicates energy based on a specific value.

[0037] In the nitride semiconductor transistor 1, the upper surface 22A of the barrier layer 22 has nitrogen polarity, and the upper surface 23A of the channel layer 23 also has nitrogen polarity. Furthermore, the channel layer 23 has polarization P1, and the ferroelectric layer 24 has polarization P2 that is opposite to polarization P1. As a result, as shown in Figures 1 and 2, a two-dimensional electron gas (2DEG) 51 is generated near the lower surface 23B of the channel layer 23, and a two-dimensional electron gas 52 is generated near the upper surface 23A of the channel layer 23. That is, the channel layer 23 contains a two-dimensional electron gas 51 located closer to the lower surface 23B than to the upper surface 23A, and a two-dimensional electron gas 52 located closer to the upper surface 23A than to the lower surface 23B. The two-dimensional electron gas 51 is mainly generated by the spontaneous polarization of the barrier layer 22, and the two-dimensional electron gas 52 is mainly generated by the spontaneous polarization of the ferroelectric layer 24. Two-dimensional electron gas 51 is an example of a first two-dimensional electron gas, and two-dimensional electron gas 52 is an example of a second two-dimensional electron gas.

[0038] Furthermore, because the channel layer 23 has two-dimensional electron gases 51 and 52, the flatness of the transconductance gm can be improved, and the distortion characteristics of the output amplitude with respect to the input amplitude (AM-AM characteristics) can be improved. In other words, the linearity of the source-drain current Ids with respect to the gate-source voltage Vgs can be improved.

[0039] Figure 3 shows the characteristics of three nitride layer semiconductor transistors. The first example follows the embodiment. The second example has indium nitride (InN) as the back barrier layer, as described in Patent Document 1. The third example removes the ferroelectric layer 24 from the embodiment and has only one two-dimensional electron gas. In Figure 3, the horizontal axis of voltage shows the difference between the gate-source voltage Vgs and the threshold voltage Vth (Vgs-Vth), and the vertical axis shows the transconductance normalized by the peak value.

[0040] As shown in Figure 3, the first and second examples exhibit higher transconductance flatness than the third example. This is because the first and second examples may contain two two-dimensional electron gases. Furthermore, the first example exhibits higher transconductance flatness than the second example. This is because, in the second example, the indium contained in the indium nitride diffuses into the channel layer during its formation, reducing electron mobility, whereas such diffusion does not occur in the first example.

[0041] The ferroelectric layer 24 is, for example, a nitride layer having a wurtzite-type crystal structure, a hafnium oxide layer, or an oxide layer having a perovskite-type crystal structure.

[0042] Examples of the nitride layer include a nitride layer containing aluminum (Al) and at least one selected from the group consisting of scandium (Sc), boron (B), and yttrium (Y). In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer 24. When the ferroelectric layer 24 is an aluminum scandium nitride layer, in the aluminum scandium nitride layer, when the ratio of the number of Sc atoms to the total number of Al atoms and Sc atoms (Sc composition ratio) is 40% or less, the aluminum scandium nitride layer is likely to have a wurtzite crystal structure. When the ferroelectric layer 24 is an aluminum yttrium nitride layer, in the aluminum yttrium nitride layer, when the ratio of the number of Y atoms to the total number of Al atoms and Y atoms (Y composition ratio) is 80% or less, the aluminum yttrium nitride layer is likely to have a wurtzite crystal structure. The ferroelectric layer 24 may further contain gallium (Ga) or indium (In). When the ferroelectric layer 24 contains gallium, the breakdown voltage of the ferroelectric layer  24 can be lowered.

[0043] Examples of the hafnium oxide layer include a hafnium oxide layer containing at least one selected from zirconium (Zr), yttrium (Y), lanthanum (La), and silicon (Si). In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer  24. When the ferroelectric layer 24 is a hafnium zirconium oxide layer, in the hafnium zirconium oxide layer, when the ratio of the number of Zr atoms to the total number of Hf atoms and Zr atoms (Zr composition ratio) is 45% or more and 55% or less, a high concentration, for example, 1×10 11 cm -2 or more and 1×10 14 cm -2Two-dimensional electron gases 51 and 52 of the following concentrations are easily obtained. When the ferroelectric layer 24 is a hafnium yttrium oxide layer, high concentrations of two-dimensional electron gases 51 and 52 are easily obtained when the ratio of the number of Y atoms to the total number of Hf atoms and Y atoms in the hafnium yttrium oxide layer (Y composition ratio) is 3% or more and 7% or less. When the ferroelectric layer 24 is a hafnium lanthanum oxide layer, high concentrations of two-dimensional electron gases 51 and 52 are easily obtained when the ratio of the number of La atoms to the total number of Hf atoms and La atoms in the hafnium lanthanum oxide layer (La composition ratio) is 1% or more and 7% or less. When the ferroelectric layer 24 is a hafnium silicon oxide layer, high concentrations of two-dimensional electron gases 51 and 52 are easily obtained when the ratio of the number of Si atoms to the total number of Hf atoms and Si atoms in the hafnium silicon oxide layer (Si composition ratio) is 2% or more and 9% or less.

[0044] The Sc composition ratio, Y composition ratio, Zr composition ratio, La composition ratio, and Si composition ratio can be measured, for example, by transmission electron microscope energy dispersive X-ray spectroscopy (TEM-EDX), secondary ion mass spectrometry (SIMS), or X-ray photoelectron spectroscopy.

[0045] Examples of oxide layers having a perovskite-type crystal structure include oxide layers containing at least one selected from the group consisting of barium (Ba), bismuth (Bi), lead (Pb), and titanium (Ti). In this case, a large remanent polarization can be easily obtained in the ferroelectric layer 24.

[0046] The ferroelectric layer 24 may further contain at least one selected from the group consisting of indium (In), selenium (Se), molybdenum (Mo), and tellurium (Te).

[0047] Furthermore, the direction of polarization of the ferroelectric layer 24 can be determined by measuring the electric field inside the ferroelectric layer 24 using a transmission electron microscope (TEM) or the like.

[0048] Next, a method for manufacturing the nitride semiconductor transistor 1 according to the embodiment will be described. Figures 4 to 8 are cross-sectional views showing the method for manufacturing the nitride semiconductor transistor 1 according to the embodiment.

[0049] First, as shown in Figure 4, a buffer layer 21, a barrier layer 22, and a channel layer 23 are sequentially formed on the substrate 10, for example, by metal-organic chemical vapor deposition (MOCVD). At this point, the upper surface 21A of the buffer layer 21, the upper surface 22A of the barrier layer 22, and the upper surface 23A of the channel layer 23 are nitrogen polar, and a two-dimensional electron gas 51 is generated near the lower surface 23B of the channel layer 23. The channel layer 23 has a polarization P1 directed from the lower surface 23B towards the upper surface 23A.

[0050] Next, a ferroelectric layer 24 is formed on the channel layer 23, and an insulating film 30 is formed on the ferroelectric layer 24. The ferroelectric layer 24 can be formed by, for example, sputtering, CVD, electron beam epitaxy (MBE), or atomic layer deposition (ALD). At this point, the polarization of the ferroelectric layer 24 may be oriented in any direction.

[0051] Next, as shown in Figure 5, a source opening 30S and a drain opening 30D are formed in the insulating film 30, and a source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 20. The openings 30S, 30D, 40S, and 40D can be formed, for example, by reactive ion etching (RIE) or ion milling using a mask (not shown).

[0052] Next, as shown in Figure 6, a regrowth layer 41S is formed on the barrier layer 22 or buffer layer 21 within the recess 40S, and a regrowth layer 41D is formed on the barrier layer 22 or buffer layer 21 within the recess 40D. The regrowth layers 41S and 41D can be formed by physical vapor deposition (PVD) methods such as vapor deposition, sputtering, or MBE, or by MOCVD.

[0053] Next, as shown in Figure 7, a source electrode 42S is formed on the regrowth layer 41S, and a drain electrode 42D is formed on the regrowth layer 41D. In forming the source electrode 42S and the drain electrode 42D, first, a metal layer (not shown) that constitutes the source electrode 42S and the drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) with an opening formed in the region where the metal layer is to be formed is used for film deposition, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0054] Next, as shown in Figure 8, by applying an electric field E greater than or equal to the coelectric field of the ferroelectric layer 24 to the ferroelectric layer 24, the ferroelectric layer 24 is made to have a polarization P2 that faces the opposite direction to polarization P1. As a result, a two-dimensional electron gas 52 is generated near the upper surface 23A of the channel layer 23. The electric field E can be applied, for example, by irradiating the source electrode 42S with a corona charge while applying a ground potential, or by applying a voltage to an electrode (not shown) separately provided on the upper surface 24A of the ferroelectric layer 24. When controlling polarization P2, the ferroelectric layer 24 may be heated to a temperature of about 500°C or less.

[0055] Next, an opening 30G for the gate is formed in the insulating film 30 (see Figure 1). The opening 30G can be formed, for example, by RIE using a mask (not shown). Next, a gate electrode 43 that contacts the ferroelectric layer 24 through the opening 30G is formed on the insulating film 30 (see Figure 1). When forming the gate electrode 43, a metal layer is deposited using, for example, a growth mask (not shown) with an opening formed in the region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0056] In this way, nitride semiconductor transistor 1 can be manufactured.

[0057] Furthermore, the method and timing for controlling the polarization of the ferroelectric layer 24 are not particularly limited.

[0058] The nitride semiconductor transistor 1 may have an insulating layer between the ferroelectric layer 24 and the gate electrode 43, or an insulating layer between the ferroelectric layer 24 and the channel layer 23. The electron affinity of these insulating layers is smaller than the electron affinity of the ferroelectric layer 24.

[0059] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0060] 1 Nitride semiconductor transistor 10 circuit boards 20 Nitride semiconductor layer 21 Buffer Layer 21A, 22A, 23A, 24A top 22 Barrier layer 23 channel layers 23B, 24B bottom surface 24 Ferroelectric layer 30 insulating film 30D, 30G, 30S aperture 40D, 40S recess 41D, 41S regrowth layer 42D drain electrode 42S Source Electrode 43 gate 51, 52 Two-dimensional electron gas E electric field P1, P2 polarization

Claims

1. A barrier layer having a first upper surface with nitrogen polarity, A channel layer having a second upper surface located above the first upper surface and possessing nitrogen polarity, and having a first polarization in a first direction, A ferroelectric layer located on the second upper surface and having a second polarization in a second direction opposite to the first direction, A nitride semiconductor transistor having the following characteristics.

2. The channel layer has a lower surface opposite to the second upper surface, The aforementioned channel layer is A first two-dimensional electron gas located closer to the lower surface than the second upper surface, A second two-dimensional electron gas located closer to the second upper surface than the lower surface, A nitride semiconductor transistor according to claim 1, comprising:

3. The ferroelectric layer is Aluminum and At least one selected from the group consisting of scandium, boron, and yttrium, A nitride semiconductor transistor according to claim 1 or claim 2, wherein the nitride layer contains a nitride layer.

4. The ferroelectric layer is an aluminum scandium nitride layer. The nitride semiconductor transistor according to claim 3, wherein in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms is 40% or less.

5. The ferroelectric layer is an aluminum yttrium nitride layer. The nitride semiconductor transistor according to claim 3, wherein in the aluminum nitride yttrium layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms is 80% or less.

6. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the ferroelectric layer is a hafnium oxide layer containing at least one element selected from the group consisting of zirconium, yttrium, lanthanum, and silicon.

7. The ferroelectric layer is a hafnium zirconium oxide layer. The nitride semiconductor transistor according to claim 6, wherein in the hafnium zirconium oxide layer, the ratio of the number of zirconium atoms to the total number of hafnium atoms and zirconium atoms is 45% or more and 55% or less.

8. The ferroelectric layer is a hafnium yttrium oxide layer. The nitride semiconductor transistor according to claim 6, wherein in the hafnium-yttrium oxide layer, the ratio of the number of yttrium atoms to the total number of hafnium atoms and yttrium atoms is 3% or more and 7% or less.

9. The ferroelectric layer is a hafnium lanthanum oxide layer. The nitride semiconductor transistor according to claim 6, wherein in the hafnium lanthanum oxide layer, the ratio of the number of lanthanum atoms to the total number of hafnium atoms and lanthanum atoms is 1% or more and 7% or less.

10. The ferroelectric layer is a hafnium oxide silicon layer. The nitride semiconductor transistor according to claim 6, wherein in the hafnium oxide silicon layer, the ratio of the number of silicon atoms to the total number of hafnium atoms and silicon atoms is 2% or more and 9% or less.

11. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the ferroelectric layer is an oxide layer having a perovskite-type crystal structure and comprising at least one selected from the group consisting of barium, bismuth, lead, and titanium.

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