Semiconductor equipment

Abstract

To provide a semiconductor device with improved characteristics. [Solution] In a semiconductor device, the semiconductor chip 30 comprises a substrate 10, a plurality of units 20A to 20F arranged in the arrangement direction, each having a unit FET 21 with a gate electrode 16, a source electrode 12, and a drain electrode 14 provided on the substrate, and a gate pad 17 that extends in the arrangement direction and to which the gate electrodes of the plurality of units are electrically connected, and the semiconductor chip 30 comprises an input terminal to which a high-frequency signal is input, and a matching circuit including a plurality of bonding wires that are electrically connected between the input terminal and the gate pad and whose first ends are joined to a plurality of regions arranged in the arrangement direction within the gate pad, wherein the plurality of units include a first unit and a second unit, the first unit is closer to the center 50C in the arrangement direction of the plurality of units than the second unit, the first unit has a first capacitive element 56, and the second unit does not have a capacitive element.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor device used in a high-frequency circuit, it is known that a plurality of bonding wires are joined to pads of a semiconductor chip provided with transistors in a direction in which the pads extend, and the bonding wires are used as part of a matching circuit (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a transistor in which a plurality of unit FETs are arranged in an array direction, the pads become long in the array direction. In this case, the impedance seen by the matching circuit may be different between the central unit FET and the end unit FET in the array direction of the transistor. As a result, the characteristics of the transistor deteriorate.

[0005] An object of this disclosure is to provide a semiconductor device capable of improving characteristics.

Means for Solving the Problems

[0006] Embodiments of the present disclosure are semiconductor devices comprising: a substrate; a plurality of units arranged in the array direction, each having a unit FET having a gate electrode, a source electrode, and a drain electrode provided on the substrate; a gate pad provided on the substrate, extending in the array direction, to which the gate electrodes of the plurality of units are electrically connected; an input terminal for inputting a high-frequency signal; and a matching circuit including a plurality of bonding wires electrically connected between the input terminal and the gate pad, with each first end joined to a plurality of regions arranged in the array direction within the gate pad, wherein the plurality of units include a first unit and a second unit, the first unit being closer to the center of the plurality of units in the array direction than the second unit, the first unit having a first capacitive element electrically connected between the gate pad and the reference potential, and the second unit having either no capacitive element electrically connected between the gate pad and the reference potential, or having a second capacitive element electrically connected between the gate pad and the reference potential and having a smaller capacitance value than the first capacitive element.

[0007] Embodiments of the present disclosure are semiconductor devices comprising: a substrate; a plurality of units arranged on the substrate in an array direction, each having a unit FET having a gate electrode, a source electrode, and a drain electrode; and a gate pad provided on the substrate, to which the gate electrodes of the plurality of units are connected and which extends in the array direction, wherein the plurality of units include a first unit and a second unit, the first unit being closer to the center of the plurality of units in the array direction than the second unit, the first unit having a first capacitive element electrically connected between the gate pad and the reference potential, and the second unit having either no capacitive element electrically connected between the gate pad and the reference potential, or having a second capacitive element electrically connected between the gate pad and the reference potential and having a smaller capacitance value than the first capacitive element. [Effects of the Invention]

[0008] According to this disclosure, the characteristics can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a circuit diagram of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of the semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a plan view of the semiconductor chip in the first embodiment. [Figure 4] Figure 4 is a cross-sectional view of AA in Figure 3. [Figure 5] Figure 5 is a cross-sectional view of BB in Figure 3. [Figure 6] Figure 6 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a plan view showing a portion of the semiconductor chip in the simulation. [Figure 8] Figure 8 is a Smith chart showing the impedance Zin as a function of frequency in sample A. [Figure 9] Figure 9 shows the amplitude of impedance Zin as a function of frequency in sample A. [Figure 10] Figure 10 shows the phase of impedance Zin with respect to frequency in sample A. [Figure 11] Figure 11 shows the amplitude of impedance Zin against unit number at 2f0 (7.6 GHz) for sample A. [Figure 12] Figure 12 shows the phase of impedance Zin with respect to unit number at 2f0 (7.6 GHz) for sample A. [Figure 13] Figure 13 shows the volume values ​​added to each unit in Sample B. [Figure 14] Figure 14 is a magnified view of the Smith chart showing the impedance Zin as a function of frequency in sample A. [Figure 15]FIG. 15 is an enlarged view of a Smith chart showing impedance Zin with respect to frequency in Sample B. [Figure 16] FIG. 16 is a diagram showing the amplitude of impedance Zin with respect to unit number in Samples A and B. [Figure 17] FIG. 17 is a diagram showing the phase of impedance Zin with respect to unit number in Samples A and B. [Figure 18] FIG. 18 is a diagram showing the capacitance values added to each unit in Sample C. [Figure 19] FIG. 19 is a diagram showing the amplitude of impedance Zin with respect to unit number in Samples A and C. [Figure 20] FIG. 20 is a diagram showing the phase of impedance Zin with respect to unit number in Samples A and C. [Figure 21] FIG. 21 is a diagram showing the capacitance values added to each unit in Sample D. [Figure 22] FIG. 22 is a diagram showing the amplitude of impedance Zin with respect to unit number in Samples A and D. [Figure 23] FIG. 23 is a diagram showing the phase of impedance Zin with respect to unit number in Samples A and D.

MODE FOR CARRYING OUT THE INVENTION

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] (1) Embodiments of the present disclosure are semiconductor devices comprising: a substrate; a plurality of units arranged in the arrangement direction, each having a unit FET having a gate electrode, a source electrode, and a drain electrode provided on the substrate; a gate pad provided on the substrate, extending in the arrangement direction, to which the gate electrodes of the plurality of units are electrically connected; an input terminal for inputting a high-frequency signal; and a matching circuit including a plurality of bonding wires electrically connected between the input terminal and the gate pad, each having a first end joined to a plurality of regions arranged in the arrangement direction within the gate pad, wherein the plurality of units include a first unit and a second unit, the first unit being closer to the center of the plurality of units in the arrangement direction than the second unit, the first unit having a first capacitive element electrically connected between the gate pad and the reference potential, and the second unit having either no capacitive element electrically connected between the gate pad and the reference potential, or having a second capacitive element electrically connected between the gate pad and the reference potential and having a smaller capacitance value than the first capacitive element. This reduces the variation in characteristics between units, thereby improving overall performance. (2) In (1) above, the first unit may be the unit closest to the center among the plurality of units, and the second unit may be the unit furthest from the center among the plurality of units. This reduces the variation in characteristics among the units and improves the characteristics. (3) In (2) above, the first capacitive element may have the largest capacitance value among the capacitive elements electrically connected between the gate pad and the reference potential in the plurality of units. This makes it possible to increase the amplitude of the impedance of the first unit which has the smallest impedance amplitude. (4) In (2) or (3) above, the second unit does not need to have a capacitive element electrically connected between the gate pad and the reference potential. This reduces the degradation of high-frequency characteristics caused by an increase in gate-source capacitance. (5) In any of (1) to (4) above, the plurality of units have a third unit located between the first unit and the second unit, the third unit has a third capacitive element electrically connected between the gate pad and the reference potential and having a capacitance value smaller than that of the first capacitive element, and if the second unit has a second capacitive element, the capacitance value of the third capacitive element may be larger than that of the second capacitive element. This reduces the variation in characteristics between units and improves the characteristics. (6) In any of (1) to (5) above, the first capacitive element may have an electrode electrically connected to the gate pad and provided on the source electrode with an insulating layer in between. This allows for miniaturization. (7) In any of (1) to (6) above, the semiconductor chip is mounted on a base, the matching circuit is mounted on the base and has a dielectric substrate and electrodes provided on the dielectric substrate and extending in the direction of the arrangement, and the base has components, the second ends of the plurality of bonding wires may be bonded to a plurality of regions arranged in the direction of the arrangement within the electrodes. This can improve the characteristics. (8) In any of (1) to (7) above, the semiconductor chip may amplify the high-frequency signal input to the gate pad. This can improve the characteristics. (9) In the above (8), the semiconductor chip may be provided with an output terminal that outputs the amplified high-frequency signal, the source electrode may be electrically connected to the reference potential, and the drain electrode may be electrically connected to the output terminal. This can improve the characteristics. (10) In any of (1) to (9) above, when the Smith chart is represented in polar coordinates with the angle at the open position set to 0° and the angle increasing counterclockwise, the impedance angle seen from the gate electrode to the matching circuit at a frequency twice the center frequency in the operating band may be in the range of -15° or less and -150° or more. This makes it possible to increase the amplitude of the impedance by shunting the first capacitive element. (11) In (10) above, the first impedance seen from the gate electrode of the first unit to the matching circuit when the first capacitive element is not provided may have a smaller radius of motion in the polar coordinates than the second impedance seen from the gate electrode of the second unit to the matching circuit when the second capacitive element is not provided. This can improve the characteristics. (12) Embodiments of the present disclosure are semiconductor devices comprising a substrate, a plurality of units arranged on the substrate in an array direction, each having a unit FET having a gate electrode, a source electrode, and a drain electrode, and a gate pad provided on the substrate, to which the gate electrodes of the plurality of units are connected and which extends in the array direction, wherein the plurality of units include a first unit and a second unit, the first unit being closer to the center of the plurality of units in the array direction than the second unit, the first unit having a first capacitive element electrically connected between the gate pad and the reference potential, and the second unit not having a capacitive element electrically connected between the gate pad and the reference potential, or having a second capacitive element electrically connected between the gate pad and the reference potential and having a smaller capacitance value than the first capacitive element. This reduces the variation in characteristics between units and improves the characteristics.

[0012] [Details of the embodiments of this disclosure] Specific examples of semiconductor devices according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0013] (First Embodiment) An amplifier circuit will be used as an example of a high-frequency circuit. Figure 1 is a circuit diagram of a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 100 includes a transistor Q1, matching circuits 52 and 54, an input terminal Tin, and an output terminal Tout.

[0014] A high-frequency signal is input to the input terminal Tin. The frequency of the high-frequency signal is, for example, between 0.5 GHz and 20 GHz. The matching circuit 52 matches the impedance seen from the gate G of transistor Q1 with the impedance seen from the matching circuit 52 to the input terminal Tin. The matching circuit 52 has inductors L11 to L13 and capacitors C11 and C12. Inductors L11 to L13 are connected in series between the input terminal Tin and the gate G. Capacitor C11 is shunt-connected to the node between inductors L11 and L12. Capacitor C12 is shunt-connected to the node between inductors L12 and L13.

[0015] Transistor Q1 is a Field Effect Transistor (FET) and has a source S, a gate G, and a drain D. The source S is electrically connected to a reference potential such as ground. The gate G is electrically connected to the input terminal Tin via a matching circuit 52. The drain D is electrically connected to the output terminal Tout via a matching circuit 54. Transistor Q1 amplifies the high-frequency signal input to the gate G and outputs the amplified high-frequency signal from the drain D. Transistor Q1 is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0016] The matching circuit 54 matches the impedance seen from the output terminal Tout to the matching circuit 54 with the impedance seen from the matching circuit 54 to the drain D of transistor Q1. The matching circuit 54 includes inductors L21 to L23 and capacitors C21 and C22. Inductors L21 to L23 are connected in series between the drain D and the output terminal Tout. Capacitor C21 is shunt-connected to the node between inductors L21 and L22. Capacitor C22 is shunt-connected to the node between inductors L22 and L23. The output terminal Tout outputs the high-frequency signal amplified by transistor Q1. The circuit configurations of matching circuits 52 and 54 are examples, and the circuit configurations of matching circuits 52 and 54 can be set as appropriate.

[0017] Figure 2 is a plan view of a semiconductor device according to the first embodiment. The thickness direction of the base 25 is the Z direction, the direction from lead 28A to 28B is the X direction, and the direction perpendicular to the X direction is the Y direction.

[0018] As shown in Figure 2, the semiconductor device 100 comprises a package 24, a semiconductor chip 30, and capacitive components 31, 32, and 33. The package 24 comprises a base 25, dielectric layers 26A and 26B, pads 27A and 27B, and leads 28A and 28B. The package 24 may also have a lid covering the base 25.

[0019] The base 25 has at least its upper surface as a conductor and is a metal plate made of laminated copper plates, molybdenum plates, and copper plates. A reference potential, such as ground potential, is supplied to the base 25. Dielectric layers 26A and 26B are mounted on both ends of the base 25 in the X direction. Dielectric layers 26A and 26B may also form a frame surrounding the semiconductor chip 30 and capacitive components 31 to 33. Dielectric layers 26A and 26B are made of ceramic or resin. Pads 27A and 27B are provided on the dielectric layers 26A and 26B, respectively. Pads 27A and 27B are metal layers, such as copper layers. Leads 28A and 28B are provided on the pads 27A and 27B in electrical contact. Leads 28A and 28B may be feedthrough leads. Leads 28A and 28B are metal leads, such as copper leads.

[0020] Capacitive component 31, semiconductor chip 30, capacitive components 32 and 33 are mounted on a base 25 and arranged sequentially in the X direction. The semiconductor chip 30 has a substrate 30A, pads 30B and 30C provided on the substrate 30A, and electrodes provided below the substrate 30A. Pads 30B, 30C and the electrodes below the substrate 30A are electrically connected to and short-circuited to the gate G, drain D, and source S of transistor Q1, respectively. If transistor Q1 is a GaN HEMT, the substrate 30A is, for example, a silicon carbide substrate or a sapphire substrate. If transistor Q1 is an LDMOS, the substrate 30A is, for example, a silicon substrate. Pads 30B and 30C are metal layers such as a gold layer or a copper layer.

[0021] Capacitive component 31 has a dielectric substrate 31A, pads 31B and 31C, and electrodes beneath the dielectric substrate 31A. Capacitive components 32 and 33 each have dielectric substrates 32A and 33A, pads 32B and 33B, and electrodes beneath the dielectric substrate. Dielectric substrates 31A, 32A, and 33A are, for example, alumina substrates or barium titanate substrates. Pads 31B, 31C, 32B, and 33B are, for example, metal layers such as gold layers or copper layers. Dielectric substrate 31A, pads 31B sandwiching the dielectric substrate 31A, and electrodes beneath the dielectric substrate 31A correspond to capacitor C11. Dielectric substrate 31A, pads 31C sandwiching the dielectric substrate 31A, and electrodes beneath the dielectric substrate 31A correspond to capacitor C12. Dielectric substrate 32A, pads 32B sandwiching the dielectric substrate 32A, and electrodes beneath the dielectric substrate 32A correspond to capacitor C21. The dielectric substrate 33A, the pad 33B sandwiching the dielectric substrate 33A, and the electrode beneath the dielectric substrate 33A all correspond to the capacitor C22.

[0022] Bonding wire 40 electrically connects pads 27A and 31B, bonding wire 41 electrically connects pads 31B and 31C, bonding wire 42 electrically connects pads 31C and 30B. Bonding wire 43 electrically connects pad 30C and pad 32B, bonding wire 44 electrically connects pads 32B and 33B, and bonding wire 45 electrically connects pads 33B and 27B. Bonding wires 40 to 45 are thin metal wires, such as gold wire or aluminum wire. Bonding wires 40, 41, 42, 43, 44, and 45 correspond to inductors L11, L12, L13, L21, L22, and L23, respectively.

[0023] The semiconductor chip 30 will be described using GaN HEMT as an example. Figure 3 is a plan view of the semiconductor chip in the first embodiment. Figure 4 is a cross-sectional view of AA in Figure 3. Figure 5 is a cross-sectional view of BB in Figure 3. As shown in Figures 3 to 5, the semiconductor chip 30 comprises a substrate 10 and a plurality of units 20A to 20F. The substrate 10 has a substrate 10A and a semiconductor layer 10B provided on the substrate 10A. The substrate 10 is provided with an active region 11. In the inert regions other than the active region 11, the semiconductor layer 10B is deactivated. The substrate 10A is, for example, a silicon carbide substrate or a sapphire substrate. The semiconductor layer 10B has, for example, a gallium nitride electron transport layer and an aluminum gallium nitride electron supply layer provided on the electron transport layer.

[0024] Multiple units 20 are provided on a substrate 10 and are arranged in the Y direction (arrangement direction). The multiple units 20 include units 20A to 20F. Units 20A to 20F each have two unit FETs 21, a gate pad 17, and a drain pad 15. Each unit FET 21 has a source electrode 12, a drain electrode 14, and a gate electrode 16. The source electrode 12, drain electrode 14, and gate electrode 16 are provided on an active region 11. The source electrode 12, drain electrode 14, and gate electrode 16 are finger-shaped and extend in the X direction. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14 which are arranged in the Y direction. Adjacent unit FETs 21 share either a source electrode 12 or a drain electrode 14. The source electrode 12 and drain electrode 14 are metal layers such as a titanium film and an aluminum film provided on the substrate 10. The gate electrode 16 is a metal layer such as a nickel film and a gold film provided on the nickel film, provided on the substrate 10.

[0025] Units 20A to 20F each have the same number of unit FETs 21. Units 20A to 20F may have one unit FET 21 or three or more. Units 20A to 20F are partitioned so that they have the same planar shape and characteristics to the extent of manufacturing tolerances. In the example in Figure 3, adjacent unit FETs 21 are mirror-symmetric but not parallel-symmetric. Unit FETs 21 are parallel-symmetric in groups of two. In such cases, the number of unit FETs 21 in units 20A to 20F may be two or a multiple of two. To increase the output of transistor Q1, the number of unit FETs 21 and units 20A to 20F connected in parallel is increased. The number of unit FETs 21 is, for example, 20 or more or 40 or more, with 64 as an example. The number of units 20A to 20F is, for example, 10 or more or 20 or more, with 32 as an example.

[0026] Let 50C be the center in the Y direction of multiple units 20 (for example, 32 units), and 50E be the ends in the Y direction of multiple units 20A to 20F. Units 20C and 20D are the units closest to the center 50C among multiple units 20A to 20F. Units 20A and 20F are the units closest to the ends 50E among multiple units 20A to 20F.

[0027] The drain pad 15 corresponds to pad 30C in Figure 2, is located at the positive (+) end of the substrate 10 in the X direction, and extends in the Y direction. The drain pad 15 may be a single unit, or it may be divided into multiple units in the Y direction, as shown by pad 30B in Figure 2. The drain electrode 14 is electrically short-circuited to the drain pad 15 in common. The gate pad 17 is located at the negative (-) end of the substrate 10 in the X direction, and extends in the Y direction. The gate pad 17 may be a single unit, or it may be divided into multiple units in the Y direction, as shown by pad 30B in Figure 2. The gate electrode 16 is electrically short-circuited to the gate pad 17 in common.

[0028] A via 13 is provided that penetrates the substrate 10 in the Z direction. A metal layer 19 is provided on the -Z direction surface of the substrate 10 and on the side surface of the via 13. The metal layer 19 is electrically connected to the source electrode 12 via the via 13. This supplies a reference potential to the source electrode 12 via the base 25 and the metal layer 19. The metal layer 19 is, for example, a gold layer. An insulating layer 23A is provided on the substrate 10 so as to cover units 20A to 20F. The insulating layer 23A is not provided on the areas of the gate pad 17 and drain pad 15 where the bonding wires 42 and 43 are joined. An insulating layer 23B is provided on the insulating layer 23A. The insulating layers 23A and 23B are, for example, silicon nitride layers.

[0029] Units 20C and 20D have a capacitive element 56. The capacitive element 56 has an electrode 18. The electrode 18 is provided between insulating layers 23A and 22B and faces the source electrode 12 with the insulating layer 23A in between. The electrode 18 is electrically connected to the gate pad 17 and short-circuited. As a result, the insulating layer 23A, the source electrode 12 with the insulating layer 23A in between, and the electrode 18 function as a capacitive element 56 connected between the gate pad 17 and the reference potential. Units 20A, 20B, 20E, and 20F do not have a capacitive element 56.

[0030] Figure 6 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. As the physical length in the Y direction of the semiconductor chip 30 and capacitive components 31 to 33 increases, and the number of bonding wires 40 to 43 increases, the influence of the wavelength of the high-frequency signal in the matching circuits 52 and 54 becomes non-negligible, resulting in a distributed-parameter circuit. For this reason, the circuit of the semiconductor device 100 in Figure 1 can be equivalently represented as a circuit in which multiple paths 58 are connected in parallel between the input terminal Tin and the output terminal Tout, as shown in Figure 6. Each path 58 has matching circuits 52A, 54A, and transistor Q1A, respectively. Matching circuit 52A has inductors L11A, L12A, L13A, and capacitors C11A and C12A, respectively. Matching circuit 54A has inductors L21A, L22A, L23A, and capacitors C21A and C22A, respectively. Transistor Q1A corresponds to units 20A to 20F.

[0031] Each matching circuit 52A in each path 58 is influenced by adjacent matching circuits 52A. Therefore, the impedance and other characteristics of matching circuits 52A near the center and those near the ends of a set of matching circuits 52A may differ.

[0032] (simulation) An electromagnetic field analysis was performed between lead 28A and pad 30B of the semiconductor device 100 shown in Figure 2, and the impedance Zin viewed from gate electrode 16 to gate pad 17 (pad 30B) shown in Figure 3 was simulated. The simulated semiconductor device 100 is an amplifier circuit with a center frequency f0 of the operating bandwidth of approximately 3.8 GHz and an output power of 180 W. There are 32 units from 20A to 20F.

[0033] Figure 7 is a plan view showing a portion of the semiconductor chip in the simulation. Figure 7 shows one pad 30B in the semiconductor chip 30 of Figure 2. Seven bonding wires 42 are bonded to pad 30B. The first ends of the bonding wires 42 are bonded to multiple regions arranged in the Y direction within pad 30B. Sixteen gate electrodes 16 are connected to one pad 30B. In the simulation model, the ends of the gate electrodes 16 are located at the ends of the active region 11, and no gate electrodes 16 are provided on the active region 11. Since one unit 20 has two unit FETs 21, one pad 30B corresponds to eight units 20. Here, for the efficiency of the simulation, two units 20 have been set to units 22. As a result, one pad corresponds to four units 22. The semiconductor chip 30 as a whole has 16 units 22.

[0034] The impedance Zin was simulated for both the unit average and for each individual unit 22. For the unit average, the impedance Zin was calculated by treating the 16 units 22 as a single unit. The impedance Zin calculated using this method corresponds to the average impedance of the 16 units 22. The impedance Zin was also calculated for each of the 16 units 22 individually. The impedance Zin calculated using this method corresponds to the impedance seen from each individual unit 22.

[0035] (Sample A) As Sample A, the impedance Zin was calculated for a sample in which all capacitive elements 56 were not provided in any of the units 20. Figure 8 is a Smith chart showing the impedance Zin as a function of frequency in Sample A. The impedance Zin corresponds to the S-parameter S11 when the end of the gate electrode 16 is designated as port 1. Figure 9 is a diagram showing the amplitude of impedance Zin as a function of frequency in Sample A. Figure 10 is a diagram showing the phase of impedance Zin as a function of frequency in Sample A. The amplitude is defined as the radius of change when the Smith chart in Figure 8 is set to polar coordinates, with the center SC of the Smith chart as 0 and the outer circumference OC of the Smith chart as 1. The right end of the Smith chart is the open position SO. When the angle at position SO is set to 0° with the center SC as the center, the counterclockwise angle is called the phase. At the short position SS at the left end of the Smith chart, the phases are 180° and -180°.

[0036] As shown in Figures 8 to 10, at frequency f0 (3.8 GHz), the difference in amplitude between each unit is not very large, being greater than 0.9, and the phase is approximately 180°. Thus, the impedance Zin is located at approximately the short position SS. As the frequency increases, the phase rotates clockwise and the amplitude decreases. At frequency 2f0 (7.6 GHz), the amplitude is between 0.75 and 0.90, and the phase is approximately -110°. At 2f0, the amplitude is smaller for unit 22 closer to the center 50C in Figure 3 (the middle unit) and larger for unit 22 closer to the end 50E (the outer unit).

[0037] To allow a signal with center frequency f0 to pass through, the impedance Zin at center frequency f0 is positioned approximately at the short-circuit position SS. The position of impedance Zin on the Smith chart at 2f0, where the efficiency of semiconductor device 100 is highest, is where the amplitude is close to 1 and the phase is slightly greater than -180° (i.e., the absolute value of the phase is small). As the phase rotates clockwise from the position of impedance Zin where efficiency is highest, the efficiency decreases sharply. As the phase rotates counterclockwise from the position of impedance Zin where efficiency is highest, the efficiency decreases gradually. The efficiency is lowest when the phase of 2f0 is around 180°. Thus, there is a cliff where the efficiency drops sharply at a position where the phase of 2f0 is slightly greater than -180°. Therefore, considering manufacturing variations in the phase of 2f0, the phase of 2f0 is in the range of -15° to -150°.

[0038] Figure 11 shows the amplitude of impedance Zin against unit number at 2f0 (7.6 GHz) for sample A. Figure 12 shows the phase of impedance Zin against unit number at 2f0 (7.6 GHz) for sample A. In Figures 11 and 12, the horizontal axis represents the unit number. Center 50C is located between unit numbers 8 and 9, and end 50E is located outside unit numbers 1 and 16.

[0039] As shown in Figure 11, the Zin amplitude is smallest at unit numbers 8 and 9 and largest at unit numbers 1 and 16. The maximum difference in amplitude is 0.12. The amplitude decreases as you move from the edge 50E towards the center 50C. When there is such a large variation in amplitude, the impedance Zin differs depending on the unit 20. For example, units closer to the edge 50E have a large 2f0 amplitude and therefore high efficiency, but units closer to the center 50C have a small 2f0 amplitude and therefore low efficiency. As a result, the overall characteristics of unit 20 deteriorate.

[0040] As shown in Figure 12, the Zin phase is smallest at unit numbers 8 and 9 and largest at unit numbers 1 and 16. The maximum phase difference is 3°. The phase decreases as you move from the edge 50E towards the center 50C. Since the phase difference of 2f0 due to unit 20 is small, the degradation of characteristics due to phase variation is considered to be small.

[0041] Thus, the following are possible reasons why the amplitude of the impedance Zin at the second harmonic frequency 2f0 differs depending on the unit 20. In the matching circuit 52A, which corresponds to units 20C and 20D near the center 50C in the Y direction, the mutual inductance between bonding wires 40, bonding wires 41, and bonding wires 42 arranged in the Y direction is larger than that between units 20A and 20E near the end 50E. As a result, the inductance of inductors L11A to L13A in units 20C and 20D is larger than that of inductors L11A to L13A in units 20A and 20E. Furthermore, when considering pads 31B and 31C in terms of distributed parameters, the appearance of pads 31B and 31C corresponding to units 20C and 20D is different from that of pads 31B and 31C corresponding to units 20A and 20E. As a result, it is thought that the Zin amplitude in units 20C and 20D near the center 50C will be smaller than the Zin amplitude in units 20A and 20E near the end 50E.

[0042] As shown in Figure 8, when the impedance Zin is capacitive and located towards the bottom of the Smith chart, shunting a capacitor causes the impedance to shift downwards. For example, when a capacitor is shunted to unit 20, where the impedance Zin is located at the dot indicated by 2f0 in the Smith chart of Figure 8, the impedance Zin at 2f0 shifts to the lower left, and the amplitude of the impedance Zin increases.

[0043] (Sample B) Figure 13 shows the capacitance values ​​added to each unit in Sample B. In Sample B, a 0.40pF capacitor was shunt-connected to each of the 16 units 22 closest to the center 50C (unit numbers 8 and 9). That is, a 0.20pF capacitor was shunt-connected to each of units 20C and 20E. No capacitors were provided in the other units 22.

[0044] In Figures 3 and 5, when viewed from the Z direction, the length of the electrode 18 in the X direction where it overlaps with the source electrode 12 is 0.24 mm, the width of the electrode 18 in the Y direction is 0.1 mm, and the thickness of the insulating layer 23A in the Z direction between the source electrode 12 and the electrode 18 is 800 nm. If the insulating layer 23A is a silicon nitride layer with a dielectric constant of 7.5, the capacitance of the capacitive element 56 in unit 20 will be 0.20 pF, and the capacitance of unit 22, which has two units 20C and 20D, will be 0.40 pF.

[0045] Figure 14 is a magnified view of the Smith chart showing the impedance Zin against frequency in sample A. Figure 15 is a magnified view of the Smith chart showing the impedance Zin against frequency in sample B. Figures 14 and 15 are magnified views of the impedance Zin around frequency 2f0. Comparing Figures 14 and 15, in sample B, the variation in Zin amplitude by unit 22 around 2f0 is smaller than in sample A. In particular, the Zin amplitude of unit 22 close to the center 50C is larger.

[0046] Figure 16 shows the amplitude of impedance Zin against unit number in samples A and B. Figure 17 shows the phase of impedance Zin against unit number in samples A and B. As shown in Figure 16, in sample B, the amplitude of impedance Zin at units 8 and 9 (unit 22) is larger than in sample A. The Zin amplitudes of units 8 and 9 and units 1 and 16 are almost the same. As a result, the maximum amplitude difference in sample B is 0.06, which is about half of the 0.12 in sample A.

[0047] As shown in Figure 17, in sample B, the phase of impedance Zin in units 22 numbered 8 and 9 is larger, and the phase of impedance Zin in units 22 numbered 1 and 16 is smaller compared to sample A. The maximum phase difference in sample B is 4°, which is almost the same as the 3° in sample A.

[0048] As described above, in Sample B, the variation in the amplitude of impedance Zin at 2f0 due to unit 22 can be reduced. Therefore, the high-frequency characteristics of the semiconductor device can be improved.

[0049] (Sample C) Figure 18 shows the capacitance values ​​added to each unit in Sample C. In Sample C, a 0.27 pF capacitor was shunt-connected to each of the 16 units 22 closest to the center 50C (unit numbers 8 and 9). No capacitor was connected to the units 22 closest to the end 50E (unit numbers 1 and 16). For units 2 through 7 (and 15 through 10), the capacitance of the shunt-connected capacitors increases linearly as you move from the end 50E towards the center 50C.

[0050] Figure 19 shows the amplitude of impedance Zin against unit number in samples A and C. Figure 20 shows the phase of impedance Zin against unit number in samples A and C. As shown in Figure 19, in sample C, the Zin amplitudes of units 8 and 9 are almost the same as those of units 1 and 16, and the Zin amplitudes of units 3 through 5 and 12 through 14 approach the Zin amplitudes of units 8, 9, 1 and 16. As a result, the maximum amplitude difference in sample B is 0.03, which is about half of the 0.06 in sample B.

[0051] As shown in Figure 20, in sample C, the Zin phases of units 3 to 5 and 12 to 14 approach the Zin phases of units 8, 9, 1, and 16. As a result, the maximum difference in Zin phases in sample C is 2°, which is smaller than that of samples A and B.

[0052] (Sample D) Figure 21 shows the capacitance values ​​added to each unit in Sample D. For units 22, numbers 2 through 7 (and 15 through 10), the capacitance of the shunt-connected capacitors increases curvilinearly from the end 50E towards the center 50C. The relationship between the capacitance value Cn and unit number n is Cn = 0.11 × √(n-1) [pF] for units 1 through 8. Units 9 through 16 are symmetrical with respect to the capacitance values ​​of units 1 through 8 and the position of unit number 8.5.

[0053] Figure 22 shows the amplitude of impedance Zin against unit number in samples A and D. Figure 23 shows the phase of impedance Zin against unit number in samples A and D. As shown in Figure 22, in sample D, the maximum amplitude difference from sample B is 0.02, which is even smaller than the 0.03 for sample C.

[0054] As shown in Figure 23, in sample D, the maximum difference in Zin phase is 2°, which is smaller than that of samples A and B and similar to that of sample C.

[0055] As described above, as shown in Figures 2 and 3, each of the multiple units 20A to 20F has a unit FET 21 and is arranged in the Y direction. As shown in Figures 1 and 2, the matching circuit 52 includes multiple bonding wires 42. The multiple bonding wires 42 are electrically connected between the input terminal Tin and the gate pad 17, and their first ends are joined to multiple regions arranged in the Y direction within the gate pad 17. In such a configuration, as shown in sample A of Figure 11, the amplitude of the impedance Zin differs between the unit 22 closer to the center 50C and the unit 22 closer to the edge 50E. As a result, the high-frequency characteristics such as efficiency differ for each unit 20, and the overall characteristics deteriorate.

[0056] According to the first embodiment, as shown in Sample B in Figure 13, Sample C in Figure 18, and Sample D in Figure 21, the first unit 22 closer to the center 50C has a first capacitive element 56 electrically connected between the gate pad 17 and the reference potential. The second unit 22 closer to the end 50E than the first unit 22 does not have a capacitive element 56 electrically connected between the gate pad 17 and the reference potential. Alternatively, the second unit 22 has a second capacitive element electrically connected between the gate pad 17 and the reference potential, with a smaller capacitance value than the first capacitive element. As a result, as shown in Figures 16, 19, and 22, the variation in the amplitude of the impedance Zin at 2f0 can be reduced. Therefore, the variation in high-frequency characteristics such as efficiency in each unit 20 is reduced, and the overall characteristics can be improved.

[0057] As shown in Figures 13, 18, and 21, the first unit may be units 8 and 9, which are the closest units 22 to the center 50C. This allows the amplitude of impedance Zin of the first unit, which has the smallest amplitude, to be increased, as shown in Figure 15. The second unit may be units 1 and 16, which are the furthest units 22 from the center 50C. This allows the amplitude of impedance Zin of the second unit, which has the largest amplitude, to be maintained. As a result, variations in high-frequency characteristics such as efficiency among the units 20 are reduced, and the overall characteristics can be improved.

[0058] The first capacitive element 56 of units 8 and 9, which are closest to the center 50C, may have the largest capacitance value among the capacitive elements electrically connected between the gate pad and the reference potential in multiple units. This allows the amplitude of impedance Zin of the first unit, which has the smallest amplitude of impedance Zin, to be increased. If units 1 and 16, which are furthest from the center 50C, have capacitive elements electrically connected between the gate pad and the reference potential, then units 1 and 16 may have the smallest capacitance value among the capacitive elements electrically connected between the gate pad and the reference potential in multiple units.

[0059] As shown in Sample C in Figure 18 and Sample D in Figure 21, the third unit is located between the first and second units, electrically connected between the gate pad 17 and the reference potential, and has a third capacitive element with a smaller capacitance value than the first capacitive element. If the second unit has a second capacitive element, the capacitance value of the third capacitive element is greater than that of the second capacitive element. This reduces variations in high-frequency characteristics such as efficiency for each unit 20, and improves the overall characteristics.

[0060] By providing the capacitive element 56, the variation in impedance Zin between units 20 can be reduced. However, if many capacitive elements 56 are provided, the capacitance values ​​other than the intrinsic gate-source capacitance of transistor Q1 will increase. This will degrade the high-frequency characteristics of transistor Q1, such as its gain.

[0061] The second unit, which is furthest from the center 50C, does not have a capacitive element 56 that is electrically connected between the gate pad 17 and the reference potential. This reduces the degradation of the high-frequency characteristics of transistor Q1.

[0062] As shown in Sample A of Figure 13, units 1 to 7 and 10 to 16, other than units 8 and 9 closest to the center 50C, do not need to have capacitive elements 56. This reduces the degradation of the high-frequency characteristics of transistor Q1 caused by the capacitance value of the capacitive elements 56. As shown in Sample C of Figure 18 and Sample D of Figure 21, the capacitance of the capacitive elements 56 may gradually increase from the edge 50E to the center 50C. Although an example has been described in which units 22 of units 1 and 16, which are furthest from the center 50C, do not have capacitive elements 56, units 22 of units 1 and 16 may have capacitive elements 56.

[0063] The gate-source capacitance Cgs in unit 20 is approximately 1.5 pF per unit 20 under idle bias conditions. The capacitance of the capacitive element 56 for each unit 20 in unit 22 closest to the center 50C may be 0.02 times or more and 1.0 times or less of Cgs.

[0064] As shown in Figures 3 and 4, the capacitive element 56 has an electrode 18 electrically connected to the gate pad 17 and provided on the source electrode 12 with an insulating layer 23A in between. This allows the capacitive element 56 to be formed without changing the chip size. Therefore, the semiconductor device can be miniaturized. The capacitive element may also be an open stub with a length of less than 1 / 4 of the wavelength λ corresponding to 2f0. When an open stub is used, the chip size will be larger. As a capacitive element, an electrode to which a reference potential is supplied may be provided on the gate pad 17 with an insulating layer 23A in between. In this case, the area on which the bonding wire 42 is joined to the gate pad 17 becomes smaller.

[0065] As shown in Figure 2, the capacitive component 31 (component) is mounted on the base 25 and has a dielectric substrate 31A and a pad 31C (electrode) provided on the dielectric substrate 31A and extending in the Y direction. The second ends of multiple bonding wires 42 are bonded to multiple regions arranged in the Y direction within the pad 31C. In this case, the mutual inductance of the bonding wires 42 differs depending on the unit 22. Also, when the pad 31C is viewed as a distributed constant, the appearance of the pad 31C differs depending on the unit 22. As a result, the Zin amplitude differs depending on the unit 22. Therefore, by providing the capacitive element 56, the variation in impedance Zin can be reduced and the characteristics can be improved.

[0066] As shown in Figures 1 and 2, the semiconductor chip 30 amplifies the high-frequency signal input to the gate pad 17. In the amplification circuit, the efficiency and other characteristics vary depending on the input impedance Zin of transistor Q1. Therefore, by providing a capacitive element 56, the variation in impedance Zin in the amplification circuit can be reduced, thereby improving the characteristics.

[0067] As shown in Figures 1 and 2, the output terminal Tout is provided with an output terminal Tout that outputs a high-frequency signal amplified by the semiconductor chip 30. As shown in Figures 1 and 3, the source electrode 12 is electrically connected to a reference potential, and the drain electrode 14 is electrically connected to the output terminal Tout. In this case, the efficiency and other characteristics differ depending on the input impedance Zin of the transistor Q1. Therefore, by providing a capacitive element 56, the variation in impedance Zin can be reduced and the characteristics can be improved.

[0068] As shown in Figure 8, when the Smith chart is represented in polar coordinates with the phase (angle in polar coordinates) of the open position set to 0° and the angle increasing counterclockwise, the phase of the unit 22 average impedance Zin, as seen from the gate pad 17 to the matching circuit 52, at frequency 2f0 (twice the center frequency f0), lies in the range of -15° to -150°. This improves the efficiency of the semiconductor device. Furthermore, when the phase of impedance Zin at 2f0 is between -30° and -150°, the amplitude of impedance Zin at 2f0 can be increased by shunting the capacitive element 56. Thus, the characteristics can be improved. The phase of impedance Zin at 2f0 may be between -45° and -135°. The amplitude of impedance Zin at 2f0 can be made 0.7 or greater, with the center SC being 0 and the outer circumference OC being 1. This allows the amplitude of impedance Zin at 2f0 to be increased by shunting the capacitive element 56. Furthermore, making the amplitude of the impedance Zin at 2f0 close to 1 increases the efficiency of the semiconductor device.

[0069] Furthermore, as shown in Figure 8, the first impedance viewed from the gate electrode 16 of the first unit near the center 50C to the matching circuit 52 when the capacitive element 56 is not provided has a smaller radius in polar coordinates than the second impedance viewed from the gate electrode 16 of the second unit near the end 50E to the matching circuit 54 when the capacitive element 56 is not provided. In such cases, providing the capacitive element 56 in the first unit can reduce the variation in impedance Zin and improve the characteristics.

[0070] As the center frequency f0 increases, the matching circuit 52 behaves in a distributed-parameter manner. Furthermore, if the power of the output high-frequency signal is large, the gate pad 17 becomes longer in the Y direction, and the number of bonding wires 42 increases. Also, the number of units 20 increases. From these perspectives, the frequency of the high-frequency signal is 0.5 GHz or higher, and the output power is 50 W or higher. The number of bonding wires 42 is 5 or more. The number of units 20 is 10 or more.

[0071] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications in the sense and scope equivalent to the claims are intended. [Explanation of Symbols]

[0072] 10, 10A, 30A circuit boards 10B Semiconductor layer 11 Active area 12 Source electrodes 13 Beer 14 Drain electrode 15 Drain pad 16 Shuttle gates 17 Gate Pad 18 electrodes 19 Metal layer 20, 20A, 20B, 20C, 20D, 20E, 20F, 22 units 21 Unit FET 23A, 23B insulating layer 24 packages 25 base 26A, 26B Dielectric layer 27A, 27B, 30B, 30C, 31B, 31C, 32B, 33B pads 28A, 28B Lead 30 semiconductor chips 31, 32, 33 Capacitive components 31A, 32A, 33A Dielectric Substrates 40, 41, 42, 43, 44, 45 Bonding wires 50C center 50E end 52, 52A, 54, 54A matching circuit 56 Capacitive elements 58 routes 100 Semiconductor Equipment C11, C11A, C12, C21, C21A, C22 Capacitors f0 center frequency 2f0 frequency L11, L11A, L12, L12A, L13, L13A, L21, L21A, L22, L22A, L23, L23A Inductors Q1, Q1A transistors SC center SO, SS position Tin input terminal Tout output terminal Zin Impedance

Claims

1. circuit board and The substrate is provided with a plurality of units, each having a unit FET with a gate electrode, a source electrode, and a drain electrode, arranged in the direction of the array, The gate electrodes of the plurality of units are electrically connected, extend in the direction of the arrangement, and are provided on the substrate as gate pads, A semiconductor chip equipped with, An input terminal into which a high-frequency signal is input, A matching circuit including a plurality of bonding wires electrically connected between the input terminal and the gate pad, each having a first end joined to a plurality of regions arranged in the arrangement direction within the gate pad, Equipped with, The plurality of units includes a first unit and a second unit, wherein the first unit is closer to the center of the plurality of units in the arrangement direction than the second unit. The first unit has a first capacitive element electrically connected between the gate pad and the reference potential, The second unit does not have a capacitive element electrically connected between the gate pad and the reference potential, or it has a second capacitive element electrically connected between the gate pad and the reference potential and having a smaller capacitance value than the first capacitive element. Semiconductor equipment.

2. The first unit is the unit closest to the center among the plurality of units, The second unit is the unit furthest from the center among the plurality of units. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 2, wherein the first capacitive element has the largest capacitance value among the capacitive elements electrically connected between the gate pad and the reference potential in the plurality of units.

4. The semiconductor device according to claim 2 or 3, wherein the second unit does not have a capacitive element electrically connected between the gate pad and the reference potential.

5. The plurality of units include a third unit located between the first unit and the second unit. The third unit is electrically connected between the gate pad and the reference potential and has a third capacitive element having a smaller capacitance value than the first capacitive element. The semiconductor device according to any one of claims 1 to 3, wherein, if the second unit has the second capacitive element, the capacitance value of the third capacitive element is greater than the capacitance value of the second capacitive element.

6. The semiconductor device according to any one of claims 1 to 3, wherein the first capacitive element is electrically connected to the gate pad and has an electrode provided on the source electrode with an insulating layer in between.

7. The base comprises the aforementioned semiconductor chip, The matching circuit is mounted on the base and has a dielectric substrate and electrodes provided on the dielectric substrate and extending in the direction of the arrangement, and has components mounted on the base, The semiconductor device according to any one of claims 1 to 3, wherein the second ends of the plurality of bonding wires are bonded to a plurality of regions arranged in the arrangement direction within the electrode.

8. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor chip amplifies the high-frequency signal input to the gate pad.

9. The semiconductor chip is equipped with an output terminal that outputs the amplified high-frequency signal, The semiconductor device according to claim 8, wherein the source electrode is electrically connected to the reference potential and the drain electrode is electrically connected to the output terminal.

10. The semiconductor device according to any one of claims 1 to 3, wherein when the Smith chart is represented in polar coordinates with the angle at the open position set to 0° and the angle increasing counterclockwise, the impedance angle viewed from the gate electrode to the matching circuit at a frequency twice the center frequency in the operating band is located in the range of -15° or less and -150° or more.

11. The semiconductor device according to claim 10, wherein the first impedance viewed from the gate electrode of the first unit to the matching circuit when the first capacitive element is not provided has a smaller radius of motion in polar coordinates than the second impedance viewed from the gate electrode of the second unit to the matching circuit when the second capacitive element is not provided.

12. circuit board and A plurality of units are arranged on the substrate in the direction of arrangement, each having a unit FET with a gate electrode, a source electrode, and a drain electrode. The gate electrodes of the plurality of units are connected, extending in the direction of the arrangement, and a gate pad provided on the substrate, Equipped with, The plurality of units includes a first unit and a second unit, wherein the first unit is closer to the center of the plurality of units in the arrangement direction than the second unit. The first unit has a first capacitive element electrically connected between the gate pad and the reference potential, The second unit does not have a capacitive element electrically connected between the gate pad and the reference potential, or it has a second capacitive element electrically connected between the gate pad and the reference potential and having a smaller capacitance value than the first capacitive element. Semiconductor equipment.

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