Method for semiconductor process chamber

Abstract

A method for performing an etching process includes forming a first protective layer on chamber walls of a semiconductor process chamber and performing a first etching process on an exposed major surface of a first substrate loaded into the semiconductor process chamber. The exposed major surface includes a first metal oxide resist layer. After performing the first etching process on the first substrate, the first protective layer is removed from the chamber walls using a cleaning process.

Description

[Technical Field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing date of U.S. Non-Provisional Patent Application No. 18 / 163,934, filed February 3, 2023, the entirety of which is incorporated herein by reference.

[0002] The present invention relates generally to semiconductor manufacturing, and in a particular embodiment to a method for a semiconductor process chamber. [Background technology]

[0003] Photolithography is commonly used to pattern thin films during semiconductor processing, where a light source emits photons onto a light-sensitive photoresist to initiate chemical reactions in the photoresist, which is then developed to remove exposed or unexposed portions of the photoresist to form a pattern or mask.

[0004] In the area of ​​semiconductor manufacturing, there is a continuous effort to increase device density to improve speed and performance while reducing costs. The scaling of semiconductor devices has enabled significant technological advances, including advanced lithography techniques such as immersion lithography. Extreme ultraviolet (EUV) radiation can be used to provide improved pattern resolution in advanced integrated circuits, where reduced feature sizes are required. Typical EUV photoresists are polymer-based chemically amplified resists (CARs), which are deposited on substrates using liquid-based spin-on techniques that consume large amounts of precursor complexes. Recently, inorganic-based resists have attracted attention because they can be patterned using EUV radiation and can provide the high etch resistance and etch selectivity required for semiconductor manufacturing. However, processing and developing inorganic-based resists presents new challenges.

[0005] Existing techniques for developing photoresists used in semiconductor manufacturing rely heavily on wet development (e.g., development using a solvent). Wet development provides a high-throughput method that can result in complete removal of negative-tone-controlled (or positive-tone-controlled) areas of the developed photoresist, but one drawback of wet development techniques is the loss of structural integrity due to harmful capillary forces caused by solvent removal. To avoid the loss of structural integrity that results from wet development, dry development processes can be used. However, dry development processes may present new challenges. Summary of the Invention [Means for solving the problem]

[0006] According to one embodiment, a method of performing an etching process includes forming a first protective layer on a chamber wall of a semiconductor process chamber; performing a first etching process on an exposed major surface of a first substrate loaded into the semiconductor process chamber, the exposed major surface including a first metal oxide resist layer; and removing the first protective layer from the chamber wall using a cleaning process after performing the first etching process on the first substrate.

[0007] According to another embodiment, a method of performing an etching process includes loading a first wafer into a process chamber, depositing a protective coating on chamber walls of the process chamber and on the first wafer while monitoring the thickness of the protective coating on the first wafer, removing the first wafer from the process chamber, loading a second wafer into the process chamber, wherein a metal oxide resist is on the second wafer, performing a development process on the second wafer, removing the second wafer from the process chamber, and performing a cleaning process in the process chamber, wherein the cleaning process removes the protective coating.

[0008] According to yet another embodiment, a method of performing an etching process includes flowing a fluoro gas into a process chamber and igniting a first plasma comprising the fluoro gas, where the first plasma deposits a protective layer on an interior surface of the process chamber; loading a process wafer having a metal oxide resist into the process chamber; etching the metal oxide resist using HBr gas in the process chamber, where residue from the etching of the metal oxide resist is deposited on the protective layer; removing the process wafer from the process chamber; flowing an oxidizing gas into the process chamber; and igniting a second plasma comprising the oxidizing gas, where the second plasma removes the protective layer.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure, as claimed.

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1A-1B] 1 illustrates a cross-sectional view of an exemplary semiconductor processing system, according to some embodiments. [Figure 2-5] 1 illustrates a cross-sectional view of a process chamber having a protective layer formed on the chamber walls according to some embodiments. [Figure 6-8] 1 illustrates an etching process performed in a process chamber having a protective layer, according to some embodiments. [Figure 9-11] 1 illustrates a cleaning process for removing a protective layer from a process chamber according to some embodiments. [Figure 12] 10 is a graph illustrating experimental results from chamber health monitoring, according to some embodiments. [Figure 13-14]1 shows experimental X-ray photoelectron spectroscopy (XPS) results of substrates with fluorocarbon layers, according to some embodiments. [Figure 15-16] 1 shows X-ray photoelectron spectroscopy (XPS) experimental results of a substrate after the protective layer has been removed, according to some embodiments. [Figure 17-21] FIG. 1 shows a process flow chart diagram of a method for performing an etching process, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly show relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the extent of the feature.

[0013] The making and using of various embodiments is discussed in detail below. However, it should be understood that the various embodiments described herein can be applied in a wide variety of specific situations. The specific embodiments discussed are merely illustrative of specific ways to make and use the various embodiments and should not be construed as limiting in scope.

[0014] According to one or more embodiments of the present disclosure, the present application relates to a method for a semiconductor process chamber, e.g., a method for dry development of metal oxide resist. Current methods for dry development of metal oxide resist for dry etching can be based on a chemical reaction between the material and a gaseous precursor without additional excitation thereof (i.e., without ionization of the gaseous precursor). These dry development solutions can also be referred to as plasmaless processes. However, reaction byproducts of the developed and etched metal oxide resist can remain in the process chamber, leading to different chamber conditions before and after the process. For example, solid byproducts of the etching reaction can remain on the process chamber walls and can be difficult or time-consuming to completely remove. Effective removal of reaction byproducts can be useful for maintaining process stability and the basic functionality of the equipment (e.g., the process chamber) used.

[0015] Embodiments of the present disclosure are described with reference to the accompanying drawings. FIGS. 1A and 1B are used to describe an embodiment of an exemplary semiconductor processing system. FIGS. 2-5 are used to describe an embodiment of a method for forming a protective layer on a chamber wall of a process chamber. FIGS. 6-8 are used to describe an embodiment of an etching process performed in a process chamber having a protective layer. FIGS. 9-11 are used to describe an embodiment of a cleaning process for removing a protective layer from a chamber wall of a process chamber. FIG. 12 is used to describe experimental results from chamber health monitoring. FIGS. 13 and 14 are used to describe experimental X-ray photoelectron spectroscopy (XPS) results of a substrate having a fluorocarbon layer. FIGS. 15 and 16 are used to describe experimental X-ray photoelectron spectroscopy (XPS) results of a substrate after the protective layer has been removed. FIGS. 17-21 are used to describe an embodiment of a method for performing an etching process.

[0016] FIG. 1A illustrates a cross-sectional view of an exemplary semiconductor processing system 100, according to some embodiments. The semiconductor processing system 100 includes a process chamber 200. In various embodiments, the process chamber 200 includes stainless steel walls. However, any suitable material may be used for the walls of the process chamber 200, such as aluminum, other metals, ceramics, or combinations thereof. The semiconductor processing system 100 may be any system suitable for performing a semiconductor etching process, such as reactive ion etching (RIE). The semiconductor processing system 100 may include a method for supplying a plasma to the process chamber 200 to form a protective layer on the chamber walls of the process chamber 200 (see FIGS. 2-5, below).

[0017] 1B shows a cross-sectional view of an exemplary semiconductor processing system 105 including a process chamber 200 and an inductively coupled plasma (ICP) system. However, the semiconductor processing system 105 may include any suitable system for supplying plasma to the process chamber 200, such as a capacitively coupled plasma (CCP) system, a remote plasma system, etc. Any suitable apparatus or method for supplying plasma to or generating plasma within the process chamber 200 is within the scope of the disclosed embodiments.

[0018] The ICP system includes an RF generator 110 that supplies power to an inductive coil 130 through a matching circuit 120. The RF generator 110 generates an RF waveform or signal that is supplied to the inductive coil 130. The RF generator 110 may be a waveform (e.g., a sinusoidal waveform) generator, an analog RF generator, or the like. In some embodiments, the RF generator 110 has broadband capabilities. However, any suitable RF generator 110 may be used, such as an RF generator without broadband capabilities.

[0019] The matching circuit 120 (also called a matcher or impedance matching network) is coupled between the RF generator 110 and the induction coil 130. As forward power propagates from the RF generator 110 to the induction coil 130, some reflected power may be reflected back due to an impedance mismatch between the induction coil 130 and the RF generator 110. The matching circuit 120 is used to reduce the reflected power by transforming the impedance load on the matching circuit 120 coupled to the induction coil 130 to the same impedance as the RF generator 110 and the transmission line between the RF generator 110 and the induction coil 130. This improves the efficiency of delivering power to the induction coil 130.

[0020] Gases, such as precursors for the plasma, may be flowed into the process chamber 200 through an upper portion surrounded by the inductive coil 130. Power may be coupled from the RF generator 110 to the inductive coil 130 to excite the gases into a plasma and generate a high-density plasma for forming a protective layer on the chamber walls of the process chamber 200. However, any suitable method and apparatus may be used to provide a plasma to the process chamber 200.

[0021] The process chamber 200 includes a chuck 140 (e.g., an electrostatic chuck) for securing a test substrate or a substrate to be processed. A test substrate 160 (also referred to as a test wafer) may be mounted on the chuck 140. The test substrate 160 may be any suitable substrate, such as a silicon wafer. The test substrate 160 may have a silicon dioxide (SiO2) film thereon for chamber health monitoring. In some embodiments, the chuck 140 is coupled to a DC pulse bias generator 150 to enable precise ion energy control through negative DC pulsing. In some embodiments, the negative DC pulsing is performed using a bias voltage of Ar. +An appropriate pattern (e.g., 1 μs on and 2 μs off per cycle) can be implemented to control the physical sputtering of silicon dioxide (SiO2) films by ions. This can be used as a chamber wall health monitor for the process chamber 200. As an example, Ar + Physical sputtering of SiO2 films by ions can be carried out at a pressure of 10 mT using a sputtering gas consisting essentially of argon and a plasma power of 200 W (measured at the power supply).

[0022] For example, contamination of the chamber walls with tin can affect the sputtering rate of SiO films on test substrates 160 as a function of chamber health. For example, the sputtering rate of SiO in the test chamber was observed to drop sharply after a metal oxide resist etch process was performed in the test chamber. This may have been caused by some form of Sn-related etch by-product remaining in the test chamber.

[0023] The test substrate 160 can be held within the process chamber 200 during the formation of the protective layer so that the protective layer is also formed on the test substrate 160. In this manner, the thickness of the protective layer can be measured in real time as it is formed. One or more sensors 170 can be positioned around the process chamber 200 to take measurements of the protective layer formed on the test substrate 160. The one or more sensors 170 can be an ellipsometer, a quartz crystal microbalance (QCM), or the like. In some embodiments, the sensor 170 is an ellipsometer, and the sensor 170 includes two components: a light source with associated optical elements (e.g., a polarizer) and an analyzer / detector with associated optical elements. In other embodiments, two or more sensors 170 are used and aligned at different locations around the process chamber 200. In yet other embodiments, the sensor 170 is movable relative to the process chamber 200. Although one sensor 170 is shown in FIG. 1B, any suitable number of sensors can be used, such as one to ten sensors 170.

[0024] In some embodiments, the one or more sensors 170 are QCMs mounted on the sidewalls of the process chamber 200 to monitor the deposition rate of the protective layer. The test substrate 160 can be omitted and a waferless coating process can be performed in which the chuck 140 is also coated with the protective layer.

[0025] In some embodiments, one or more sensors 170 monitor the thickness of the protective layer formed on the test substrate 160 in real time (e.g., using in situ ellipsometry) to provide feedback on the expected thickness of the protective layer formed on the chamber walls of the process chamber 200. The feedback can be used to stop the process of forming the protective layer when the protective layer reaches a desired thickness (see FIG. 5, below). In other embodiments, a test substrate 160 is not included, and the film deposition rate is not monitored in real time during the formation of the protective layer.

[0026] 2-11 illustrate a method for forming a protective layer (also called a protective layer coating or a protective coating) on ​​the chamber walls of a process chamber to remove by-products from a subsequent semiconductor process performed in the process chamber. 2-5 illustrate the formation of a protective layer on the chamber walls of a process chamber.

[0027] 2 shows a cross-sectional view of a process chamber 200 that may be similar to the process chamber 200 described above with respect to FIGS. 1A and 1B, and details will not be repeated herein. In some embodiments, the process chamber 200 includes a chuck (not shown in FIG. 2; see FIG. 1B, above, for a description of the chuck 140) for securing a test substrate 160 within the process chamber 200. In some embodiments, the test substrate 160 is loaded into the process chamber 200 to monitor the thickness of a subsequently formed protective layer (see FIGS. 4 and 5, below). In other embodiments, loading the test substrate 160 into the process chamber 200 is omitted.

[0028] In Figure 3, the process chamber 200 is filled with precursor 310, which is subsequently excited into a plasma and used to form a protective layer on the chamber walls of the process chamber (see Figures 4 and 5, below). In some embodiments, precursor 310 includes a fluorogas such as C4F8, another fluorocarbon such as CF4, C2F6, or C3F6, a hydrofluorocarbon gas such as CHF3, CH3F, or CH2F2, the like, or a combination thereof. Precursor 310 may also include a noble gas, such as argon, neon, helium, xenon, or the like, or a combination thereof. However, any suitable gas may be used for precursor 310.

[0029] 4, a first plasma 320 is generated within the process chamber 200 by excitation of the precursor 310 to deposit a protective layer on the chamber walls of the process chamber 200. In some embodiments, the protective layer is deposited on the interior surfaces of the process chamber 200. The first plasma 320 can be ignited (i.e., ignited) by an ICP system (see FIG. 1B, above), a CCP system, etc. In some embodiments, the first plasma 320 is ignited externally and delivered to the process chamber 200 by a remote plasma system.

[0030] In some embodiments, the first plasma 320 includes argon and C4F8 in a volume ratio ranging from 1:99, e.g., 15:40. The first plasma 320 may be generated at a pressure ranging from 5 mT to 2000 mT, e.g., 50 mT, and the first plasma 320 may be generated using a power ranging from 2 W to 2000 W, e.g., 20 W (as measured at the power source). The first plasma 320 may be generated for a duration ranging from 1 minute to 30 minutes, e.g., 15 minutes, to deposit a desired thickness of material on the chamber walls of the process chamber 200 to form a protective layer 330 (see FIG. 5, below).

[0031] In some embodiments, the temperature of the process chamber 200 is maintained within a range of 20°C to 200°C during the deposition process. To control the deposition rate of the protective layer, the temperature of the chamber walls of the process chamber 200 can be controlled. As an example, to achieve a deposition rate of 1 to 100 nm / min, the process chamber 200 can be controlled to have a temperature of 80°C during the deposition process. The deposition rate should be reasonable to obtain a reasonable throughput, and the dependence of the deposition rate on temperature can depend on the reaction mechanism.

[0032] 5 shows a protective layer 330 deposited on the chamber walls of process chamber 200. Protective layer 330 may also be referred to as a protective coating, protective layer coating, or pre-coating. Protective layer 330 protects the chamber walls of process chamber 200 from contamination by reaction by-products (e.g., metals from metal oxide resists such as tin) that may be difficult or time-consuming to remove. In some embodiments, the protective layer includes a fluorocarbon chemical, which may be advantageous for providing good protection to the chamber walls of process chamber 200.

[0033] In some embodiments, the thickness of the protective layer 330 is measured in real time (e.g., by a sensor 170; see FIG. 1, above). For example, if a test substrate 160 is present, the thickness of portion 330a can be monitored in real time to provide feedback regarding the thickness of the protective layer 330. The deposition process of the protective layer 330 can be terminated when the protective layer 330 reaches a desired thickness, for example, a thickness in the range of 1 nm to 500 nm. Real-time feedback from one or more sensors 170 (e.g., an ellipsometer or QCM; see FIG. 1B, above) can be used to monitor the deposition process and terminate it when the protective layer 330 reaches the desired thickness. For example, a QCM can monitor the thickness of the protective layer 330 as it is formed. After the deposition process of the protective layer 330 is complete, the test substrate 160 (if present) can be removed from the process chamber 200. In other embodiments, the thickness of the protective layer 330 is not monitored as the protective layer is formed.

[0034] 6-8 illustrate an exemplary etching process performed in the process chamber 200 having the protective layer 330. In the example of Figures 6-8, the etching process is dry development of a metal oxide resist. However, any suitable semiconductor process may be performed in the process chamber 200 having the protective layer 330, and all such semiconductor processes are within the scope of the disclosed embodiments.

[0035] In FIG. 6, a substrate 400 (also referred to as a process substrate or process wafer) is loaded into process chamber 200. Substrate 400 may be secured on a chuck (e.g., chuck 140; see FIG. 1B, above). Substrate 400 may be a silicon wafer having a diameter in the range of 100 mm to 500 mm, such as 150 mm, 200 mm, 300 mm, or 450 mm. In various embodiments, substrate 400 may be part of or include a semiconductor device and may have undergone multiple processing steps, such as following conventional processing. Thus, substrate 400 may include layers of various semiconductors useful in microelectronics. For example, a semiconductor structure may include substrate 400 having various device regions formed thereon.

[0036] In one or more embodiments, substrate 400 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In particular embodiments, substrate 400 may include silicon germanium, silicon carbide, gallium arsenide, gallium nitride, or other compound semiconductors. In other embodiments, substrate 400 includes heterogeneous layers, such as silicon germanium-on-silicon, gallium nitride-on-silicon, or silicon carbon-on-silicon layers, or an SOI substrate. In various embodiments, substrate 400 is patterned or embedded with other components of a semiconductor device. In some embodiments, substrate 400 includes conductive features (e.g., metal wiring) embedded therein. The conductive features may be electrically coupled to active devices (not shown) further embedded within substrate 400.

[0037] The substrate 400 of FIG. 6 includes a photoresist film 404 (e.g., a metal oxide resist) deposited on a lower portion 402 of the substrate 400, such that the exposed major surface of the substrate 400 includes the photoresist film 404. In various embodiments, although not shown, the lower portion 402 of the substrate 400 may further include various layers useful in semiconductor device fabrication, which may collectively be considered part of the substrate 400 in this disclosure. For example, in certain embodiments, a dielectric layer may be present on the lower portion of the substrate 400, including a silicon-based dielectric material having a low dielectric constant (i.e., a low k value), such as organosilicate glass (SiCOH), dense SiCOH, porous SiCOH, and other porous dielectric materials. Additionally, a hard mask layer may be present on the lower portion 402 of the substrate 400, which may be patterned in a subsequent etching process after EUV photopatterning. In various embodiments, the hard mask may include titanium nitride, titanium, titanium oxide, tantalum, tungsten carbide, other tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds. The hard mask can also be a carbon-based or silicon-based mask material.

[0038] In one example, a photoresist film 404 is formed on the lower portion 402 prior to loading the substrate 400 into the process chamber 200. Additionally, the photoresist film 404 may be formed as part of a tri-layer stack commonly used in photolithographic patterning. The tri-layer stack may be used to generate and transfer a pattern to a hard mask and then to an underlying layer, such as a dielectric layer of the lower portion 402. In various embodiments, the multi-layer stack includes an underlayer and a photoresist film 404 as an EUV-sensitive photoresist on the underlayer. In one or more embodiments, the underlayer includes a carbon material (e.g., silicon carbide or silicon oxide) and may be formed by a spin-on process or vapor deposition such as CVD. The multi-layer stack may further include a layer of oxide (e.g., silicon oxide) or nitride (e.g., titanium nitride or silicon nitride) on the underlayer and the photoresist film 404. 6 only shows photoresist film 404 deposited directly on lower portion 402, however, as noted above, in various embodiments, any suitable multi-layer structure may be present as part of lower portion 402 of substrate 400. In some embodiments, photoresist film 404 has a thickness in the range of 10 nm to 300 nm, e.g., 150 nm.

[0039] In various embodiments, the photoresist film 404 includes tin (Sn), antimony (Sb), hafnium (Hf), zirconium (Zr), zinc (Zn), or the like, or a combination thereof. In certain embodiments, the photoresist film 404 includes a metal oxide, a metal alkoxide, or a methacrylate (MAA) of Sn, Sb, Hf, Zr, Zn, or the like. In other embodiments, the photoresist film 404 is a metal oxide-free photoresist, such as a photopolymerizable photoresist. However, the photoresist film 404 may include any suitable material. Deposition of the photoresist film 404 may be performed by a dry process or a wet process. In various embodiments, the photoresist film 404 may be deposited by vapor deposition, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD).

[0040] In certain embodiments, the deposition process for the photoresist film 404 may include exposing the substrate 400 to two precursors, a metal-containing precursor (e.g., a tin-containing precursor) and an oxygen-containing precursor, in a process chamber (e.g., a chamber different from process chamber 200). The exposure to these precursors may be performed stepwise or simultaneously. In various embodiments, the deposition process may be an ALD or pseudo-ALD process and may include two or more exposure steps. For example, the deposition process may be performed by first exposing the substrate 400 to a tin-containing precursor that forms an adsorbed layer on the lower portion 402 of the substrate 400, and then exposing the substrate 400 to an oxygen-containing precursor gas that reacts with the adsorbed tin-containing precursor. The exposure steps may be repeated one or more times to increase the thickness of the photoresist film 404 on the substrate 400. In certain embodiments, the exposure steps may be separated in time or space. Temporal separation of the exposure steps may be achieved by changing the gas composition in the process chamber. On the other hand, spatial separation of exposure steps may be possible by utilizing multiple spatially separated zones within the process chamber and transporting the substrate from one zone to another. To further separate the exposure steps in time, deposition may further include evacuating, purging, or both evacuating and purging the process chamber between exposure steps. These additional steps may be beneficial to ensure that reactions occur only on the surface and not in the gas phase. The ALD or pseudo-ALD method according to this embodiment may be particularly advantageous in enabling layer-by-layer growth of the photoresist film 404 with high uniformity.

[0041] In another embodiment, instead of an ALD-type process, precursors can be simultaneously delivered into the process chamber to grow the photoresist film 404. Such an embodiment can be advantageous by allowing for sequential growth of the photoresist film 404 in a single step. In this embodiment, reaction between the precursors may or may not occur in the gas phase and on the surface.

[0042] In another embodiment, the photoresist film 404 can be deposited by liquid deposition using alternating exposures of a tin-containing precursor liquid and an oxygen-containing precursor liquid. Liquid deposition can further include rinsing the substrate with a rinse solution between exposure steps to remove excess and / or unreacted portions of the precursor. The rinse solution can include deionized water, common organic solvents such as acetone, propylene glycol monomethyl ether acetate, 1-methoxy-2-propanol, methyl isobutyl carbinol, hexane, tert-butanol, and isopropanol, or mixtures thereof. In another embodiment, the liquid precursors can be mixed first, and the mixed solution can be applied to the substrate to grow the photoresist film 404. In one or more embodiments, one of the precursors can be gaseous and the other can be liquid, and accordingly, two different modes of delivery (vapor and liquid) can be utilized to perform the deposition process.

[0043] Next, the photoresist film 404 of the substrate 400 can be exposed to a light pattern, such as EUV light exposure. The EUV light pattern can be constructed using a photomask by placing the photomask between the substrate 400 and an EUV light source (not shown). In response to the exposure to the EUV light pattern, a photochemical reaction can occur in the exposed areas of the photoresist film 404, while the unexposed areas remain unchanged. As a result of the photochemical reaction, the exposed areas can include a crosslinked photoresist film, which can have material properties that are substantially different from the unreacted portions of the photoresist film 404. Such differences in material properties can include, among other things, volatility, reactivity, and / or solubility, which result from the tonality of the photoresist. After exposure to the light pattern, the substrate 400 can be loaded into the process chamber 200 for an etching process (also called a development process).

[0044] Next, in FIG. 7, an etching process (also called a developing process) is performed on the substrate 400 using a reactive precursor 340 flowed into the process chamber 200. In some embodiments, the etching process is a plasma-less process performed using a gaseous (non-ionized) reactive precursor 340 (also called a developing gas). The reactive precursor 340 reacts with, for example, unexposed areas of the photoresist film 404 to produce volatile by-products 342, which then evaporate from the surface of the substrate 400. This reaction develops the photoresist film 404. In some embodiments, the reactive precursor 340 is a reactive gas, such as hydrogen bromide (HBr), hydrogen chloride (HCl), boron trichloride (BCl), an organic acid such as a carboxylic acid, methanol, ethanol, isopropyl alcohol, or the like, or a mixture or combination thereof. In some embodiments, a carrier gas, such as argon, neon, nitrogen, helium, xenon, or the like, or a combination thereof, is also flowed into the process chamber 200 along with the reactive precursor 340.

[0045] In a particular embodiment, the reactive precursor 340 includes HBr and the photoresist film 404 includes a metal oxide resist including tin (Sn). The volatile byproducts 342 may contain tin, which may be deposited on the exposed chamber walls of the protective layer 330 to form an etch byproduct layer 350 (see FIG. 8 below). This may protect the chamber walls of the process chamber 200 from contamination by byproducts of the etch process (e.g., tin or other metals).

[0046] The etching process (also called the development step) may be performed using a flow rate of reactive precursor 340 in the range of 1 sccm to 2000 sccm. The reactive precursor 340 may be performed at a temperature in the process chamber 200 in the range of -100°C to 500°C. The reactive precursor 340 may be performed for a duration of 1 second to 1800 seconds.

[0047] 8 shows the substrate 400 and process chamber 200 after the etching process shown in FIG. 7 has been performed. An etch by-product layer 350 has been deposited on the protective layer 330 on the chamber walls of the process chamber 200. The presence of the protective layer 330 may reduce or prevent contamination of the chamber walls of the process chamber 200 by the etch by-product layer 350, which may include metals such as tin. For ease of explanation, the etch by-product layer 350 is shown as covering the chamber walls of the protective layer 330; it should be understood that the etch by-product layer 350 may be present as a continuous layer or intermittent patches disposed across the chamber walls of the protective layer 330.

[0048] After completion of the etching process shown above in FIG. 7 , the substrate 400 may be removed from the process chamber 200, for example, for further processing. While FIG. 8 shows the lower portion 402 of the substrate 400 remaining with the photoresist film 404 (see FIG. 7 above) completely removed, this is for ease of illustration. It should be understood that after completion of the etching process shown above in FIG. 7 , portions of the photoresist film 404 may remain on the lower portion 402 of the substrate 400. These remaining portions of the photoresist film 404 (not shown) may be used as an etch mask for subsequent processing of the substrate 400.

[0049] 9-11 illustrate a cleaning process for removing the protective layer 330 and restoring the process chamber 200 to its original state. In FIG. 9, the process chamber 200 is filled with a cleaning precursor 360. In some embodiments, the cleaning precursor 360 includes an oxidizing agent, such as oxygen gas (O), ozone (O), or the like, or a combination thereof. However, any suitable gas, such as chlorine (Cl), may be used for the cleaning precursor 360. In some embodiments, the cleaning precursor 360 also includes a noble gas, such as argon, neon, helium, xenon, or the like, or a combination thereof. However, any suitable gas may be used for the cleaning precursor 360.

[0050] 10, a second plasma 370 is generated within the process chamber 200 by excitation of the cleaning precursor 360. In some embodiments, the second plasma 370 includes oxygen. The second plasma 370 cleans the chamber walls of the process chamber 200 by removing the protective layer 330 and the etch by-product layer 350. The protective layer 330 and the etch by-product layer 350 are removed by the second plasma 370 as second volatile by-products 372. The second plasma 370 can be lit (i.e., ignited) in a manner similar to the first plasma 320, as described above with respect to FIG. 4, and the details will not be repeated here.

[0051] In some embodiments, the second plasma 370 includes oxygen (O) and argon (Ar) in a volume ratio ranging from 1:99, e.g., 1:1. The oxygen-containing plasma may be advantageous for removing fluorocarbon films (e.g., protective layer 330) and etch by-products (e.g., tin, etc.) from the etch by-product layer 350. The second plasma 370 may be generated at a pressure ranging from 1 mT to 2000 mT, e.g., 50 mT, and may be generated using a power (as measured at the power source) ranging from 1 W to 2000 W, e.g., 400 W. The second plasma 370 may be generated for a duration ranging from 0.5 minutes to 30 minutes, e.g., 2 minutes, to remove the protective layer 330 and the etch by-product layer 350. In some embodiments, the temperature of the process chamber 200 is maintained within a range of 20°C to 200°C during the cleaning process.

[0052] FIG. 11 shows the clean process chamber 200 after the cleaning process described above in FIG. 10 has removed the protective layer 330 and the etch by-product layer 350. The process chamber 200 is now near its original state, as shown in FIG. 2, and is ready for another cycle of forming a protective layer, performing one or more etching processes, and removing the protective layer. Forming and removing the protective layer may eliminate lengthy cleanings, such as using Cl gas for three hours or more, to remove contaminants such as tin from the chamber walls of the process chamber 200. Each etching step (e.g., an etching process on a separate wafer) does not necessarily require its own protective layer deposition and removal steps. The frequency of forming and removing the protective layer 330 can be adjusted to achieve a balance between throughput and effectiveness of the protective layer 330. Once the protective layer 330 is formed, multiple wafers can be processed. The protective layer 330 can be removed before it becomes saturated with etch by-products and becomes difficult to remove effectively.

[0053] 12 shows experimental results from chamber health monitoring to evaluate the degree of protection from contamination provided by a protective layer (e.g., protective layer 330; see above, FIGS. 5-10). The chamber health was measured by measuring Ar on a test substrate 160 (see above, FIG. 1B) for various chamber conditions. +The SiO2 etch rate (ER) is measured using physical sputtering of the SiO2 film by ions. Figure 12 is a graph of the SiO2 etch rate (ER) in Å per minute (i.e., the rate at which SiO2 is sputtered from the film on the test substrate 160) for bias voltages of 50 V, 80 V, and 100 V applied to the chuck 140 (see Figure 1B above). The chamber integrity was tested for four conditions: a clean chamber (i.e., a process chamber 200 in which no etching process involving dry development of metal oxide resist was performed; see FIG. 2 above); an uncoated chamber (i.e., a process chamber 200 in which an etching process involving dry development of metal oxide resist was performed without any protective layer); a chamber with a 1-minute coating (i.e., a process chamber 200 in which an etching process involving dry development of metal oxide resist was performed with a protective layer deposited for 1 minute); and a chamber with a 15-minute coating (i.e., a process chamber 200 in which an etching process involving dry development of metal oxide resist was performed with a protective layer deposited for 15 minutes). The 15-minute and 1-minute protective layers were removed after the metal oxide resist etching process, and physical sputtering tests of the respective SiO films were performed after removal of each protective layer.

[0054] As shown in Figure 12, the SiO2 etch rate was highest in the clean chamber and the chamber where the coating was formed for 15 minutes. This may indicate that the protective layer (formed by the 15 minute deposition) provides significant protection from contamination by etch by-products (e.g., tin), allowing the process chamber after the metal oxide resist etch process to retain similar performance to a clean process chamber in which the metal oxide resist etch process was not performed.

[0055] However, the chamber coated for 1 minute had only a slightly higher SiO etch rate than the uncoated chamber. This may indicate that the 1-minute coating did not provide significant protection from contamination by etching by-products (e.g., tin) compared to the chamber without a protective coating. The SiO etch rate was significantly higher for the 15-minute coating and the clean chamber than for the uncoated chamber or the 1-minute coating. This may indicate that contamination of the chamber walls with etching by-products (e.g., tin) significantly reduced the SiO etch rate and adversely affected the performance of the process chamber. The above-mentioned relative differences in SiO etch rate were observed for the 50 V, 80 V, and 100 V bias cases, and the magnitude of the SiO etch rate was proportionally affected by different bias voltages.

[0056] 12 appears to indicate that a 1-minute deposition process may be insufficient to reduce or prevent contamination, it is possible that similar performance to a 15-minute deposition process may be achieved using different process conditions. For example, the temperature of the walls of the process chamber 200 (see FIG. 4 above) may be increased to control the deposition rate, resulting in a thicker protective layer with a shorter deposition time, such as 1 minute.

[0057] FIG. 13 shows the experimental results of X-ray photoelectron spectroscopy (XPS) for a fluorocarbon layer deposited on a test substrate covered with a SiO2 film for 15 minutes, and FIG. 14 shows similar XPS results for a fluorocarbon layer (also referred to as a fluorocarbon film) deposited for 1 minute. A graph of counts per second (CPS) versus binding energy (eV) shows peaks indicating the presence of carbon and fluorine in the fluorocarbon layer (in other words, the deposited layer is fluorocarbon in nature) and silicon and oxygen in the SiO2 film. The magnitudes of the carbon and fluorine peaks are larger in FIG. 13 than in FIG. 14, while the magnitudes of the silicon and oxygen peaks are smaller in FIG. 13 than in FIG. 14. This may indicate that the fluorocarbon film formed on the SiO2 film is thicker in the 15-minute case of FIG. 13 than in the 1-minute case of FIG. 12, resulting in increased carbon and fluorine peaks and decreased oxygen and silicon peaks. The thickness of the fluorocarbon layer formed on the chamber wall of the process chamber can be proportional to the thickness of the fluorocarbon layer formed on the test substrate and measured according to FIGS.

[0058] 15 and 16 show XPS experimental results for each test substrate after the fluorocarbon layer of the test substrate has been removed (e.g., by the cleaning process described above with respect to FIGS. 9-10) for fluorocarbon layers formed by 15 minutes of deposition and 1 minute of deposition, respectively. An etching process for the substrate with the metal oxide resist may also be performed in each process chamber prior to removing the fluorocarbon layer.

[0059] Both Figures 15 and 16 show much smaller fluorine and carbon peaks than those in Figures 13 and 14, respectively. This may indicate that most of the CF polymer (i.e., the fluorocarbon film) was removed from the test substrate (and the chamber walls of the process chamber) by the cleaning process. In addition, the XPS results did not show the presence of tin (Sn) residue, suggesting that most or all of the impurities from the etching of the metal oxide resist were effectively removed during the cleaning process.

[0060] 17 shows a process flow diagram of a method 500 for performing an etching process while protecting the process chamber from contamination, according to some embodiments. In step 502, a protective layer 330 is formed on the chamber walls of the process chamber 200, as described above with respect to FIGS. 3-5. In step 504, a sample substrate (e.g., substrate 400) is loaded into the process chamber 200, as described above with respect to FIG. 6.

[0061] In step 506, an etching process is performed on the sample substrate, as described above with respect to Figure 7. In step 508, the sample substrate is removed from the process chamber 200, as described above with respect to Figure 8. In step 510, the protective layer 330 is removed from the chamber walls of the process chamber, as described above with respect to Figures 9-10. The method may then return to step 502 for any suitable number of cycles.

[0062] 18 shows a process flow diagram of another method 600 for performing an etching process, according to some embodiments. In step 602, a first protective layer (e.g., protective layer 330) is formed on a chamber wall of a semiconductor process chamber (e.g., process chamber 200), as described above with respect to FIGS.

[0063] In step 604, a first etching process is performed on an exposed major surface of a first substrate (e.g., substrate 400) loaded into a semiconductor process chamber, the exposed major surface of the first substrate including a first metal oxide resist layer (e.g., photoresist film 404), as described above with respect to FIG. 7. The first protective layer protects the chamber walls of the semiconductor process chamber from contamination by residue from the first etching process. After performing the first etching process on the first substrate, in step 606, the first protective layer is removed from the chamber walls of the semiconductor process chamber using a cleaning process, as described above with respect to FIGS. 9-10. The method may then return to step 602 for any suitable number of cycles.

[0064] 19 shows a process flow diagram of another method 700 for performing an etching process, according to some embodiments. In step 702, a first wafer (e.g., test substrate 160) is loaded into process chamber 200, as described above with respect to FIG. 2. In step 704, a protective coating (e.g., protective layer 330) is deposited on the chamber walls of process chamber 200 and on the first wafer, while monitoring the thickness of the protective coating on the first wafer, as described above with respect to FIGS. 3-5.

[0065] In step 706, the first wafer is removed from process chamber 200, as described above with respect to Figure 5. In step 708, a second wafer (e.g., substrate 400) having a metal oxide resist (e.g., photoresist film 404) thereon is loaded into process chamber 200, as described above with respect to Figure 6. In step 710, a development process is performed on the second wafer, as described above with respect to Figure 7.

[0066] In step 712, the second wafer is removed from the process chamber 200, as described above with respect to Figure 8. In step 714, a cleaning process is performed within the process chamber 200 to remove the protective coating, as described above with respect to Figures 9-10. The method may then return to step 702 for any suitable number of cycles.

[0067] 20 shows a process flow diagram of another method 800 for performing an etching process, according to some embodiments. In step 802, a fluoro gas (e.g., precursor 310) is flowed into process chamber 200, as described above with respect to FIG. 3. In step 804, a first plasma 320 containing the fluoro gas is ignited, as described above with respect to FIGS. 4-5, and first plasma 320 deposits a protective layer 330 on the interior surfaces of process chamber 200.

[0068] In step 806, a process wafer (e.g., substrate 400) having a metal oxide resist (e.g., photoresist film 404) is loaded into process chamber 200, as described above with respect to Figure 6. In step 808, the metal oxide resist is etched in process chamber 200 using HBr gas (e.g., reactive precursor 340), as described above with respect to Figure 7, resulting in residues (e.g., volatile byproducts 342) from the etching of the metal oxide resist being deposited on protective layer 330.

[0069] In step 810, the process wafer is removed from the process chamber 200, as described above with respect to Figure 8. In step 812, an oxidizing gas (e.g., cleaning precursor 360) is flowed into the process chamber 200, as described above with respect to Figure 9. In step 814, a second plasma 370 including the oxidizing gas is ignited, as described above with respect to Figure 10, and the second plasma 370 removes the protective layer 330. The method may then return to step 802 for any suitable number of cycles.

[0070] 21 shows a process flow diagram of a method 900 for performing multiple etching processes while protecting the process chamber from contamination, according to some embodiments. In step 902, a protective layer 330 is formed on the chamber walls of the process chamber 200, as described above with respect to FIGS.

[0071] In step 904, a first sample substrate (e.g., substrate 400) is loaded into process chamber 200, as described above with respect to Figure 6. In step 906, a first etching process is performed on the first sample substrate, as described above with respect to Figure 7. In step 908, the first sample substrate is removed from process chamber 200, as described above with respect to Figure 8.

[0072] In step 910, a second sample substrate (e.g., substrate 400) is loaded into process chamber 200, as described above with respect to Figure 6. In step 912, a second etching process is performed on the second sample substrate, as described above with respect to Figure 7. In step 914, the second sample substrate is removed from process chamber 200, as described above with respect to Figure 8.

[0073] In step 916, the protective layer 330 is removed from the chamber walls of the process chamber, as described above with respect to Figures 9-10. Although Figure 21 shows two etching processes performed on two sample substrates, any suitable number of etching processes may be performed on any suitable number of sample substrates before removing the protective layer 330. The method may then return to step 902 for any suitable number of cycles, each cycle including any suitable number of etching processes.

[0074]

[0013] Exemplary embodiments of the present disclosure are summarized here. Other embodiments may be understood from the entire specification and claims filed herewith.

[0075] Example 1. A method of performing an etching process, the method including: forming a first protective layer on a chamber wall of a semiconductor process chamber; performing a first etching process on an exposed major surface of a first substrate loaded into the semiconductor process chamber, the exposed major surface including a first metal oxide resist layer; and removing the first protective layer from the chamber wall using a cleaning process after performing the first etching process on the first substrate.

[0076] Example 2. The method of Example 1, wherein the first protective layer comprises carbon and fluorine.

[0077] Example 3. The method of example 1 or 2, wherein the cleaning process comprises an oxygen plasma.

[0078] Example 4. The method of one of Examples 1-3, wherein the first metal oxide resist layer comprises tin.

[0079] Example 5. The method of one of Examples 1-4, further comprising performing a second etching process on the exposed major surface of a second substrate loaded into the semiconductor process chamber before removing the first protective layer from the chamber walls.

[0080] Example 6. The method of one of Examples 1-4, further comprising monitoring the thickness of the first protective layer using a quartz crystal microbalance while forming the first protective layer.

[0081] Example 7. The method of one of Examples 1-4 or 6, further comprising, after removing the first protective layer, forming a second protective layer on the chamber walls of the semiconductor process chamber, and performing a second etching process on a second substrate loaded into the semiconductor process chamber, the second substrate including an exposed major surface that includes a second metal oxide resist layer.

[0082] Example 8. A method of performing an etching process, comprising: loading a first wafer into a process chamber; depositing a protective coating on chamber walls of the process chamber and on the first wafer while monitoring the thickness of the protective coating on the first wafer; removing the first wafer from the process chamber; loading a second wafer into the process chamber, wherein a metal oxide resist is on the second wafer; performing a development process on the second wafer; removing the second wafer from the process chamber; and performing a cleaning process in the process chamber, wherein the cleaning process removes the protective coating.

[0083] Example 9. The method of Example 8, wherein monitoring the thickness of the protective coating on the first wafer includes measuring the thickness in real time using an ellipsometer.

[0084] Example 10. The method of Example 9, further comprising using feedback from the ellipsometer to stop deposition of the protective coating when the protective coating reaches a desired thickness.

[0085] Example 11. The method of one of Examples 8-10, wherein depositing the protective coating includes forming a plasma in the process chamber, the plasma including carbon, fluorine, and argon.

[0086] Example 12. The method according to one of Examples 8 to 11, wherein the development process is a plasmaless process.

[0087] Example 13. The method of Example 12, wherein the plasma-less process includes HBr.

[0088] Example 14. The method of one of Examples 8-13, wherein the cleaning process includes forming a plasma in the process chamber, the plasma including oxygen and argon.

[0089] Example 15. A method of performing an etching process, the method including: flowing a fluoro gas into a process chamber; igniting a first plasma comprising the fluoro gas, wherein the first plasma deposits a protective layer on an interior surface of the process chamber; loading a process wafer having a metal oxide resist into the process chamber; etching the metal oxide resist using HBr gas in the process chamber, wherein residue from etching the metal oxide resist is deposited on the protective layer; removing the process wafer from the process chamber; flowing an oxidizing gas into the process chamber; and igniting a second plasma comprising the oxidizing gas, wherein the second plasma removes the protective layer.

[0090] Example 16. The method of Example 15, wherein the fluoro gas is C4F8.

[0091] Example 17. The method of Example 16, wherein the first plasma is formed using a 15:40 volume ratio of C4F8 and argon.

[0092] Example 18. The method of one of Examples 15-17, wherein the second plasma is formed using a 1:1 volume ratio of oxygen and argon.

[0093] Example 19. The method of one of Examples 15-18, wherein etching the metal oxide resist with HBr gas is a plasma-less process.

[0094] Example 20. The method of one of Examples 15-19, further comprising loading a test substrate into the process chamber before flowing the fluorogas into the process chamber, and removing the test substrate from the process chamber after depositing the protective layer.

[0095] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reading this specification. It is therefore intended that the appended claims cover any and all such modifications or embodiments.

Claims

1. 1. A method of performing an etching process, comprising: forming a first protective layer on a chamber wall of a semiconductor process chamber; performing a first etching process on an exposed major surface of a first substrate loaded into the semiconductor process chamber, the exposed major surface including a first metal oxide resist layer; removing the first protective layer from the chamber walls using a cleaning process after performing the first etching process on the first substrate; A method comprising:

2. The method of claim 1 , wherein the first protective layer comprises carbon and fluorine.

3. The method of claim 1 , wherein the cleaning process comprises an oxygen plasma.

4. The method of claim 1 , wherein the first metal oxide resist layer comprises tin.

5. 10. The method of claim 1, further comprising, prior to the step of removing the first protective layer from the chamber walls, performing a second etching process on an exposed major surface of a second substrate loaded into the semiconductor process chamber.

6. 10. The method of claim 1, further comprising the step of monitoring the thickness of the first protective layer using a quartz crystal microbalance during the step of forming the first protective layer.

7. moreover, forming a second protective layer on the chamber walls of the semiconductor process chamber after removing the first protective layer; performing a second etching process on a second substrate loaded into the semiconductor process chamber, the second substrate having an exposed major surface including a second metal oxide resist layer; 2. The method of claim 1, comprising:

8. 1. A method of performing an etching process, comprising: loading a first wafer into a process chamber; depositing a protective coating on chamber walls of the process chamber and on the first wafer while monitoring the thickness of the protective coating on the first wafer; removing the first wafer from the process chamber; loading a second wafer into the process chamber, the second wafer having a metal oxide resist thereon; performing a development process on the second wafer; removing the second wafer from the process chamber; performing a cleaning process in the process chamber, wherein the protective coating is removed; A method comprising:

9. 9. The method of claim 8, wherein monitoring the thickness of the protective coating on the first wafer comprises measuring the thickness in real time using an ellipsometer.

10. 10. The method of claim 9, further comprising using feedback from the ellipsometer to stop depositing the protective coating when the protective coating reaches a desired thickness.

11. 9. The method of claim 8, wherein depositing the protective coating comprises forming a plasma in the process chamber, the plasma comprising carbon, fluorine, and argon.

12. The method of claim 8 , wherein the development process is a plasmaless process.

13. The method of claim 12 , wherein the plasma-less process comprises HBr.

14. 9. The method of claim 8, wherein the cleaning process comprises forming a plasma in the process chamber, the plasma comprising oxygen and argon.

15. 1. A method of performing an etching process, comprising: flowing a fluoro gas into a process chamber; igniting a first plasma comprising the fluorogas, the first plasma depositing a protective layer on an interior surface of the process chamber; loading a process wafer having a metal oxide resist into the process chamber; etching the metal oxide resist using HBr gas in the process chamber, wherein residue from the etching of the metal oxide resist is deposited on the protective layer; removing the process wafer from the process chamber; flowing an oxidizing gas into the process chamber; igniting a second plasma comprising the oxidizing gas, the second plasma removing the protective layer; and A method comprising:

16. The fluoro gas is C ４ F ８ 16. The method of claim 15, wherein:

17. The first plasma is a mixture of C with a volume ratio of 15:

40. ４ F ８ and argon.

18. 16. The method of claim 15, wherein the second plasma is formed using a 1:1 volume ratio of oxygen and argon.

19. 16. The method of claim 15, wherein etching the metal oxide resist with HBr gas is a plasma-less process.

20. moreover, loading a test substrate into the process chamber prior to flowing the fluorogas into the process chamber; removing the test substrate from the process chamber after depositing the protective layer; 16. The method of claim 15, comprising:

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