Serdes Interface Circuit

Abstract

The Serdes interface circuit includes a plurality of receiving bridge units, each of which includes an alignment adjustment module for receiving decoded data from each channel of the Serdes interface, adjusting the decoded data to an aligned state, and outputting the alignment state data; a compensated frequency difference deletion module for deleting a special character skip pattern in the alignment state data and writing compensated frequency difference deletion data to a FIFO buffer; a data adjustment module for adjusting data read from the FIFO and outputting the adjusted data; a compensated frequency difference interpolation module for inserting the adjusted data and outputting the alignment adjustment data; and a status generation module for controlling multi-channel alignment and determining completion of alignment. This interface circuit eliminates the effects of changes in the spacing between the special character A patterns in each channel due to error codes, ensures smooth completion of data alignment, and improves Serdes transmission performance and system operation stability.

Description

[Technical field]

[0001] This application relates to the technical field of integrated circuit chips, and in particular to Serdes interface circuits. [Background technology]

[0002] To achieve higher data rates with fewer pins, FPGA chips use multiple channels to transfer data over the Serdes interface.

[0003] The PCS rx part in the serdes uses the special character Apattern in the data stream to combine multiple physically independent channels into parallel channels that are synchronized in timing logic, and at the same time, the resilient buffer circuit planned in the PCS rx can solve the problem of the recovered clock conflicting with the local clock. However, the multi-channel data alignment, recovered clock, and local clock frequency difference compensation functions are implemented at high speed, and the multi-channel alignment function needs to be restarted, which consumes a large amount of processing delay and has a great impact on the transmission efficiency of the entire serdes. Summary of the Invention

[0004] An object of the present application is to provide a Serdes interface circuit.

[0005] In order to achieve the above object, the present application provides a Serdes interface circuit for multi-channel data transmission, the Serdes interface circuit including a number of receiving bridge units, the receiving bridge units including an alignment adjustment module, a compensated frequency difference deletion module, a FIFO, a data adjustment module, a compensated frequency difference complementation module, and a status generation module, which are connected in sequence, the alignment adjustment module is used for receiving decoded data in each channel of a Serdes interface, adjusting the decoded data into an alignment state, and outputting alignment state data, the compensated frequency difference deletion module is used for performing a deletion operation on a special character skip pattern in the alignment state data, and writing the compensated frequency difference deletion data into a FIFO buffer, the data adjustment module is used for performing data adjustment on read data of the FIFO, and outputting the adjustment data, the compensated frequency difference complementation module is used for performing an insertion operation on the adjustment data, and outputting the alignment adjustment data, and the status generation module is used for controlling multi-channel alignment and determining completion of alignment.

[0006] Preferably, the number of said multi-channels is four and the number of said receiving bridge units is four.

[0007] Preferably, when the frequency of the FIFO write clock is greater than the frequency of the FIFO read clock, the compensation frequency difference deletion module performs a deletion operation on a special character "skip pattern" in the alignment status data, and writes the compensation frequency difference deletion data into the FIFO buffer.

[0008] Preferably, when the frequency of the FIFO read clock is greater than the frequency of the FIFO write clock, the compensation frequency difference complement module performs an insertion operation on the adjustment data.

[0009] Preferably, the data adjustment module includes a data selection module, a deletion information processing module, a deletion index comparison module and an output processing module, the data selection module is used to receive FIFO read data and output data to be compared to the deletion information processing module and the output processing module, the deletion information processing module is used to output a deletion index to be compared to the deletion index comparison module to perform a deletion operation and comparison, the deletion index comparison module is used to output a selection control signal and an output control signal, and the output processing module is used to output the adjustment data. Effect of the Invention

[0010] This application has the following beneficial effects: The interface circuit provided can eliminate the effect of special character Apattern spacing changes in each channel caused by error codes, ensure the smooth completion of data alignment, and improve the transmission performance of Serdes and the stability of system operation. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a structural diagram of a Serdes interface circuit according to an embodiment of the present application; [Diagram 2] FIG. 2 is a structural diagram of a data adjustment module in an embodiment of the present application; [Diagram 3] FIG. 2 is a timing diagram under a selection control signal of an embodiment of the present application; [Figure 4] FIG. 2 is a timing diagram under output control signals of an embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In order to make the objectives, technical solutions and advantages of the present specification clearer, the following will clearly and completely describe the technical solutions of the present specification in conjunction with the specific examples of the present specification and the corresponding accompanying drawings. Obviously, the described examples are only some examples of the present specification, but not all examples. Based on the examples of the present specification, other examples obtained by those skilled in the art without creative labor are all included in the scope of protection of the present specification. It should be noted that the examples of the present application and the features in the examples can be combined with each other unless there is a contradiction.

[0013] Terms such as "first", "second" and "third" in the specification and claims of this application and in the drawings are used to distinguish different objects and are not intended to describe a particular order. Moreover, "comprises" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or apparatus that includes a series of steps or units is not limited to the recited steps or units, but also includes unrecited steps or units or other steps or units that are inherent to these processes, methods, products or apparatus.

[0014] An embodiment of the present application provides a Serdes (SERializer / DESerializer) interface circuit, the Serdes interface circuit being used for multi-channel data transmission, including a number of receiving bridge units (rx_bridge_unit), the receiving bridge units including a sequentially connected alignment adjustment module bonding_ctrl, a compensation frequency difference deletion module ctc_del_ctrl, a FIFO (First in First out memory on chip), a data adjustment module rx_bu_adjuster, a compensation frequency difference complement module ctc_add_ctrl, and a status generation module cb_status_gen.

[0015] The alignment adjustment module is used to receive the decoded data data_after_decoder decoded in each channel of the Serdes interface, adjust the decoded data to an alignment state, and output alignment state data data_after_bonding. Furthermore, since the intervals of the special characters Apattern in the decoded data are all the same and fixed, adjusting the decoded data to an alignment state means adjusting the decoded data to an alignment state according to the detection result of the special character Apattern.

[0016] The compensated frequency difference deletion module is used to perform a deletion operation on the special character skip pattern in the alignment state data, compensate for the frequency difference between the FIFO read clock and the FIFO write clock, and write the compensated frequency difference deletion data data_after_ctc_del to the FIFO buffer. Specifically, when the frequency of the FIFO write clock is greater than the frequency of the FIFO read clock, the compensated frequency difference deletion module performs a deletion operation on the special character skip pattern in the alignment state data, and writes the compensated frequency difference deletion data to the FIFO buffer.

[0017] The data adjustment module is used to perform data adjustment on the read data fifo_rdata of the FIFO, and output the adjustment data data_after_adjuster, so as to eliminate the influence of the error code on the data alignment, and ensure the data alignment of each channel.

[0018] The compensation frequency difference complementation module performs a special character skip pattern insertion operation (skip-add) on the adjustment data, and outputs alignment adjustment data dout_after_ctc_and_ceb to ensure the realization of frequency difference compensation. Specifically, when the frequency of the FIFO read side clock is greater than the frequency of the FIFO write side clock, a skip-add operation is performed on the adjustment data.

[0019] The state generation module is used to control the multi-channel alignment and to determine the completion of the alignment.

[0020] The Serdes interface circuit of the present application can eliminate the influence of the change in the spacing of special characters Apattern in each channel caused by error codes, ensure the smooth completion of data alignment, and improve the transmission performance of the Serdes and the stability of system operation.

[0021] In one embodiment, there are four multi-channels and correspondingly four receiving bridge units.

[0022] As shown in FIG. 1, the Serdes interface circuit provided by the embodiment of the present application is used for multi-channel data transmission and includes a number of receiving bridge units, in which one is a master channel receiving bridge unit rx_bridge_unit in master channel, and the rest are slave channel receiving bridge units rx_bridge_unit in slave channel (only one slave channel receiving bridge unit is shown in the drawing), the master channel receiving bridge unit is used for master channel data transmission, and the slave channel receiving bridge unit is used for slave channel data transmission.

[0023] The master channel receiving bridge unit and the slave channel receiving bridge unit each include an alignment adjustment module, a compensation frequency difference deletion module, a FIFO, a data adjustment module, a compensation frequency difference complementation module and a status generation module, which are connected in series.

[0024] The alignment adjustment module is used to receive the decoded data data_after_decoder decoded in each channel of the Serdes interface, adjust the decoded data to an alignment state, and output alignment state data data_after_bonding. Furthermore, since the intervals of the special characters Apattern in the decoded data are all the same and fixed, adjusting the decoded data to an alignment state means adjusting the decoded data to an alignment state according to the detection result of the special character Apattern.

[0025] The compensated frequency difference deletion module is used to perform a deletion operation on the special character skip pattern in the alignment state data, compensate for the frequency difference between the FIFO read clock and the FIFO write clock, and write the compensated frequency difference deletion data data_after_ctc_del to the FIFO buffer. Specifically, when the frequency of the FIFO write clock is greater than the frequency of the FIFO read clock, the compensated frequency difference deletion module is used to perform a deletion operation on the special character skip pattern in the alignment state data, and write the compensated frequency difference deletion data to the FIFO buffer.

[0026] Here, the special character skip pattern is a codon inserted according to the protocol requirements in data transmission and is used when compensating for frequency difference. The insertion and deletion operations of the special character skip pattern ensure that the output data frequency meets the transmission requirements. The special character Apattern is a codon inserted according to a fixed interval in data transmission. At the start of multi-channel transmission, the special character Apattern in each channel data is aligned. In the receiving bridge unit rx_bridge_unit, the data is adjusted by identifying the special character Apattern, ensuring that the final output data from the Serdes is aligned for each channel.

[0027] The data adjustment module is used to perform data adjustment on the read data fifo_rdata of the FIFO, and output the adjustment data data_after_adjuster, so as to eliminate the influence of the error code on the data alignment, and ensure the alignment of each channel data.

[0028] The compensation frequency difference complementation module performs a skip-add operation on the adjustment data, outputs alignment adjustment data dout_after_ctc_and_ceb, and is used to ensure the realization of frequency difference compensation. Specifically, when the frequency of the FIFO read side clock is greater than the frequency of the FIFO write side clock, it performs a skip-add operation on the adjustment data.

[0029] The status generation module cb_status_gen is used to control the multi-channel alignment and to determine the completion of the alignment.

[0030] Furthermore, the status generation module cb_status_gen in the master channel receiving bridge unit is enabled, and the status generation module cb_status_gen controls multi-channel alignment via a built-in state machine and determines whether alignment is completed for all channels (master channels and slave channels).

[0031] This application installs a data adjustment module to adjust data, and ensures that the deletion operation (skip-del) process for the special character skip pattern of all channels is based on the master channel, and the interval of the special character Apattern is fixed, solving the problem that data is affected by error codes in the network channel transmission and serial transmission process on the board. When an error code occurs in the skip pattern, the skip pattern is not recognized, and each channel performs a different deletion operation, so the interval of the special character Apattern in the channel data changes, and the interval of the special character apattern changes due to the error code, so the multi-channel alignment function has to be restarted, which consumes a large amount of processing delay and has a great impact on the transmission efficiency of all serdes.

[0032] Here, skip-del-index-cin and skip-del-index-cout are master channel delete operation cascade information. The skip-del information of the master channel is transmitted to each slave channel in sequence, so that each slave channel performs delete operation and comparison, thus adjusting the data and ensuring the consistency of the special character apattern interval in each channel data.

[0033] Skip_add_index_cin, skip_add_index_cout are the master channel insertion operation cascade information. After the data is adjusted by the receiving bridge unit rx_bu_adjuster, it is guaranteed that the data of the slave channel is already consistent with the master channel. The special character skip pattern insertion operations required for frequency difference compensation are all controlled by the master channel to ensure the alignment of each channel data.

[0034] In one embodiment, as shown in FIG. 2, the data adjustment module includes a data selection module din_gen, a deletion information processing module din_del_index_gen, a deletion index comparison module del_index_compare, and an output processing module output_data_gen.

[0035] The data selection module din_gen is used to receive FIFO read data, and according to the destination address of the data, as shown in Figures 3 and 4, the FIFO read data received by the data selection module din_gen includes the current read data adjuster_din and the read data of the three following read addresses adjuster_din_nxt1, adjuster_din_nxt2, and adjuster_din_nxt3.

[0036] Furthermore, in the previous cycle, if the del_index comparison result in the deletion information processing module din_del_index_gen indicates that there is an error code in the slave channel, the data to be compared din, din_nxt are shifted and connected to achieve data alignment. To prevent repeated output of data, the data selection module din_gen of the slave channel selects the read data of the subsequent read address according to the selection control signal data_in_sel to ensure that the output data is not assigned to the data to be compared din, din_nxt.

[0037] In the previous cycle, if the del_index comparison result in the deletion information processing module din_del_index_gen indicates that there is an error code in the master channel, the output processing module output_data_gen of the slave channel inserts a special character skip pattern into the data to achieve data alignment, and after inserting a certain amount of skip, the din_gen module selects data according to the selection control signal data_in_sel to ensure that the data din, din_nxt to be compared maintain the data of the previous cycle, where the selection control signal data_in_sel selects data called adjuster_din_nxt1, adjuster_din_nxt2, and adjuster_din_nxt3.

[0038] The data selection module din_gen outputs the data din and din_nxt to be compared in response to the selection control signal data_in_sel to the deletion information processing module din_del_index_gen and the output processing module output_data_gen.

[0039] Based on the received data din, din_nxt to be compared, the deletion information processing module din_del_index_gen extracts the deletion operation skip-del for the special character skip pattern in this channel (slave channel) data, selects the deletion indexes din_del_index, din_nxt_del_index to be compared, and outputs them to the deletion index comparison module del_index_compare to perform the deletion operation and comparison.

[0040] The delete index comparison module del_index_compare of the slave channel is used to compare the skip-del operation of the master channel with that of the current slave channel and output the selection control signal data_in_sel and the output control signal data_out_sel. Specifically, the delete index comparison module del_index_compare compares the skip-del operation of the master channel with that of this channel based on the received delete indexes din_del_index, din_nxt_del_index to be compared and the master channel delete index master_del_index to determine whether data adjustment is required. Here, the master channel delete index comparison module del_index_compare does not operate, and all channels (slave channels) perform data adjustment based on the master channel.

[0041] Here, the selection control signal data_in_sel is used to control the generation of the next data din to be compared, and the output control signal data_out_sel is used by the processing module output_data_gen to output the adjusted data adjuster_dout.

[0042] The output processing module output_data_gen is used to output the adjusted data adjuster_dout, i.e., the adjusted data data_after_adjuster, depending on the selection of the output control signal data_out_sel, where the buffer left data buf_left_data signal in the output processing module output_data_gen temporarily stores data that has not been output due to data adjustment in the slave channel.

[0043] If there is an error code in the current master channel, the output control signal data_out_sel indicates '2', and the slave channel restores the deleted special character skip pattern to ensure the consistency of this channel data with the master channel.

[0044] When data is temporarily stored in buf_left_data, the data that has not been output is connected to the data din to be compared in the current cycle, and is output after satisfying the data bit width requirement.

[0045] If there is an error code in the slave channel and the special character skip pattern is not processed, the output control signal data_out_sel outputs '1', and the output processing module output_data_gen connects and shifts the data din, din_nxt to be compared according to the instruction of the master channel delete index master_del_index, ensuring the alignment of the current slave channel data and master channel data.

[0046] As can be seen from the figure, this application can eliminate the effect of error code, ensure that multi-channel alignment and frequency difference compensation functions are supported at the same time, and improve the stability and data transmission efficiency of the serdes system. CTC is clock compensation frequency difference.

[0047] The above is merely an embodiment of the present application, and any modifications made by those skilled in the art without departing from the creative idea of ​​the present application should be included in the protection scope of the present application.

Claims

1. A Serdes interface circuit for transmitting multi-channel data, comprising a plurality of receiving bridge units, the receiving bridge units including an alignment adjustment module, a compensation frequency difference deletion module, a FIFO buffer, a data adjustment module, a compensation frequency difference complement module, and a status generation module, which are connected in series; The alignment adjustment module is used for receiving decoded data in each channel of a Serdes interface, adjusting the decoded data into an alignment state, and outputting alignment state data; The compensation frequency difference deletion module is used for performing a deletion operation on a special character skip pattern in the alignment state data, and writing the compensation frequency difference deletion data into a FIFO buffer; The data adjustment module is used for performing data adjustment on the read data of the FIFO buffer and outputting the adjusted data; The compensated frequency difference complementation module is used for performing an insertion operation on the adjustment data and outputting alignment adjustment data; The Serdes interface circuit according to claim 1, wherein the state generation module is used to control alignment of multiple channels and to determine completion of alignment.

2. 2. The Serdes interface circuit according to claim 1, wherein the number of said multi-channels is four, and the number of said receiving bridge units is four.

3. 2. The Serdes interface circuit according to claim 1, wherein when a frequency of a FIFO write clock is greater than a frequency of a FIFO read clock, the compensation frequency difference deletion module performs a deletion operation on a special character "skip pattern" in the alignment status data, and writes the compensation frequency difference deletion data into a FIFO buffer.

4. 2. The Serdes interface circuit according to claim 1, wherein the compensation frequency difference complement module performs an insertion operation on the adjustment data when the frequency of the FIFO read clock is greater than the frequency of the FIFO write clock.

5. The data adjustment module includes a data selection module, a deletion information processing module, a deletion index comparison module, and an output processing module; The data selection module is used for receiving the read data of the FIFO buffer and outputting the compared data to the deletion information processing module and the output processing module; The deletion information processing module is used to output the deletion index to be compared to the deletion index comparison module to perform the deletion operation and comparison; The deletion index comparison module is used to output a selection control signal and an output control signal; 2. The Serdes interface circuit of claim 1, wherein the output processing module is used to output the conditioned data.

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