Electronic component embedded board

Abstract

To provide an electronic component built-in substrate that can reduce the whole thickness and by which high-frequency characteristics are less likely to fluctuate.SOLUTION: An electronic component built-in substrate 1 comprises: an insulating layer 13 having a core material C; an electronic component 40 buried in the insulating layer 13; and a conductor layer L3 provided on a surface of the insulating layer 13 and including signal wiring S1. One end of the signal wiring S1 is connected with a signal terminal 51, and the other end of the signal wiring S1 is led out to a position not overlapped with the electronic component 40. The core material C is removed at the periphery of the electronic component 40 and a position overlapped with the signal wiring S1 in a plan view. Such provision of the core material C on the insulating layer 13 with the buried electronic component 40 can reduce the whole thickness. Since the core material C is removed at the position overlapped with the signal wiring S1 in a plan view, high-frequency characteristics of high-frequency signals flowing in the signal wiring S1 are less likely to fluctuate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a substrate with built-in electronic components, and more particularly to a substrate with built-in electronic components having a multi-layer wiring structure. [Background technology]

[0002] Patent Document 1 discloses a substrate with built-in electronic components having a multi-layer wiring structure. The substrate with built-in electronic components disclosed in Patent Document 1 has an insulating layer in which electronic components are embedded, two wiring layers provided on one surface side of the insulating layer in which the electronic components are embedded, and two wiring layers provided on the other surface side of the insulating layer in which the electronic components are embedded. The insulating layer located between the two wiring layers uses a core material such as glass cloth impregnated with a resin material, thereby ensuring the mechanical strength of the entire substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-339421 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, since it is difficult to reduce the thickness of a core material in which a resin material is impregnated into a core material, there is a problem that the overall thickness becomes thick when the core material is provided on both sides of the insulating layer in which the electronic components are embedded. Moreover, there is a problem that when signal wiring is formed on the surface of the core material, the influence of the core material contained in the core material causes variations in high-frequency characteristics.

[0005] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, an object of the present invention is to provide a substrate with built-in electronic components that can be made thin overall and that is less susceptible to variations in high-frequency characteristics. [Means for solving the problem]

[0006] The electronic component-embedded substrate according to the present invention comprises a first insulating layer having a core material, an electronic component embedded in the first insulating layer, and a first conductor layer provided on one surface of the first insulating layer and including a first signal wiring, one end of the first signal wiring being connected to a first signal terminal at a position overlapping with the first signal terminal of the electronic component, and the other end of the first signal wiring being extended to a position not overlapping with the electronic component, and the first insulating layer forms a core-free region where the core material is not present around the electronic component and at a position overlapping with the first signal wiring in a planar view.

[0007] According to the present invention, since the core material is provided in the first insulating layer in which the electronic components are embedded, it is possible to reduce the overall thickness. In addition, since the electronic components are surrounded by a core-free area, the core material and the electronic components do not interfere with each other. Moreover, since the position overlapping with the first signal wiring in a plan view is also a core-free area, the high-frequency characteristics of the high-frequency signal flowing through the first signal wiring are less likely to vary.

[0008] In the present invention, the coreless region is formed along the periphery of the electronic component and along a position overlapping with the first signal wiring in a plan view, and thus the end of the coreless region may extend along the periphery of the electronic component and along the periphery of the first signal wiring in a plan view. This reduces the area of ​​the coreless region, making it possible to sufficiently ensure the overall mechanical strength.

[0009] In the present invention, the first conductor layer further includes a second signal wiring having one end connected to a second signal terminal of the electronic component, and a part of the second signal wiring may overlap with the core material in a plan view. This reduces the area of ​​the core-free region, making it possible to sufficiently ensure the overall mechanical strength.

[0010] The electronic component built-in substrate according to the present invention further includes a second insulating layer provided on one surface of the first insulating layer so as to embed the first conductor layer, and a second conductor layer provided on the surface of the second insulating layer, and the second insulating layer may be made of a resin material that does not contain a core material. This allows the thickness of the second insulating layer to be sufficiently thin. The electronic component built-in substrate according to the present invention further includes a third conductor layer provided on the other surface of the first insulating layer, a third insulating layer provided on the other surface of the first insulating layer so as to embed the third conductor layer, and a fourth conductor layer provided on the surface of the third insulating layer, and the third insulating layer may be made of a resin material that does not contain a core material. This allows the thickness of the third insulating layer to be sufficiently thin. Effect of the Invention

[0011] Thus, according to the present invention, it is possible to provide a substrate with built-in electronic components that has the strength of a substrate due to the core material, can have a thin overall thickness, and is less susceptible to variation in high-frequency characteristics. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 1 according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic plan view showing an enlarged portion of the conductor layers L1 to L3. [Diagram 3] FIG. 3 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Figure 4] FIG. 4 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Diagram 5] FIG. 5 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Figure 6] FIG. 6 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 7] FIG. 7 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 8] FIG. 8 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Figure 9] FIG. 9 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 10] FIG. 10 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 11] FIG. 11 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0014] FIG. 1 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 1 according to one embodiment of the present invention.

[0015] 1, the electronic component built-in substrate 1 according to this embodiment includes six conductor layers L1 to L6, and insulating layers 11 to 15 located between two conductor layers adjacent to each other in the stacking direction. Here, insulating layer 11 is located between conductor layers L1 and L2, insulating layer 12 is located between conductor layers L2 and L3, insulating layer 13 is located between conductor layers L3 and L4, insulating layer 14 is located between conductor layers L4 and L5, and insulating layer 15 is located between conductor layers L5 and L6. Each of insulating layers 11 to 15 is an interlayer film having conductor layers on both sides, and in this sense, solder resists 21 and 22 do not correspond to insulating layers.

[0016] The conductor layer L1 is located at the top layer, and a part of it is covered with a solder resist 21. The exposed part of the conductor layer L1 that is not covered with the solder resist 21 constitutes a terminal electrode E1 that is located on one surface 1a of the electronic component built-in substrate 1. The conductor layer L6 is located at the bottom layer, and a part of it is covered with a solder resist 22. The exposed part of the conductor layer L6 that is not covered with the solder resist 22 constitutes a terminal electrode E2 that is located on the other surface 1b of the electronic component built-in substrate 1. Electronic components such as semiconductor ICs and passive components (not shown) are mounted on the surface 1a of the electronic component built-in substrate 1. The surface 1b of the electronic component built-in substrate 1 is used as a mounting surface for another circuit board (not shown), or electronic components such as semiconductor ICs and passive components (not shown) are mounted on the surface 1a.

[0017] Of the insulating layers 11 to 15, the insulating layer 13 is made of a core material in which a core material C made of glass cloth or the like is impregnated with a resin material such as epoxy. Since the core material has high strength, the mechanical strength of the electronic component built-in substrate 1 is mainly ensured by the insulating layer 13. In contrast, the insulating layers 11, 12, 14, and 15 are made of a resin material that does not contain a core material such as glass cloth. A resin material that does not contain a core material such as glass cloth is more easily processed than a core material, and it is possible to form small-diameter via holes at a narrow pitch. In addition, since the insulating layers 11, 12, 14, and 15 do not contain a core material such as glass cloth, it is possible to make the thickness thereof sufficiently thin.

[0018] The insulating layer 13 is composed of two insulating layers 13a and 13b, and a core material C is provided at the interface between the two. The insulating layer 13 is thicker than the other insulating layers 11, 12, 14, and 15, and therefore the core material C can also be set to a sufficient thickness to ensure sufficient mechanical strength of the entire electronic component built-in substrate 1. The core material C is not provided at the entire interface between the insulating layers 13a and 13b, but is partially removed. The area from which the core material C is removed is a core-free area A, and an electronic component 40 such as a semiconductor IC is embedded in the core-free area A. In this way, since the core material C does not exist at the position overlapping with the electronic component 40 and around it, there is no interference between the electronic component 40 and the core material C. The electronic component 40 is mounted on the surface of the insulating layer 13a in a face-up manner so that the main surface 41 on which the electrode pads are provided faces the front surface 1a. When the electronic component 40 is a semiconductor IC, the chip thickness may be reduced to 200 μm or less, for example, about 50 to 100 μm.

[0019] As shown in Fig. 1, two conductor layers adjacent in the stacking direction are connected to each other by a via conductor. For example, the conductor layers L1 and L2 are connected to each other through a via conductor 31 provided to penetrate the insulating layer 11, the conductor layers L2 and L3 are connected to each other through a via conductor 32 provided to penetrate the insulating layer 12, the conductor layers L3 and L4 are connected to each other through a via conductor 33 provided to penetrate the insulating layer 13, the conductor layers L4 and L5 are connected to each other through a via conductor 34 provided to penetrate the insulating layer 14, and the conductor layers L5 and L6 are connected to each other through a via conductor 35 provided to penetrate the insulating layer 15. Furthermore, the conductor layer L3 and the electronic component 40 are connected to each other through a via conductor 36 provided to penetrate the insulating layer 13b.

[0020] Here, the insulating layer 13 made of a core material and the insulating layers 11, 12, 14, and 15 made of a resin material that does not contain a core material such as glass cloth are significantly different in processability. That is, the insulating layers 11, 12, 14, and 15 made of a resin material are excellent in processability, so that small-diameter via holes can be easily formed, whereas the insulating layer 13 made of a core material has a core material C such as glass cloth, so that it is difficult to form small-diameter via holes penetrating the insulating layer 13. However, the via conductors 36 connecting the conductor layer L3 and the electronic component 40 are provided in the core-free region A and do not need to penetrate the core material C, so that the via conductors 36 can also be formed at a narrow pitch.

[0021] FIG. 2 is a schematic plan view showing an enlarged portion of the conductor layers L1 to L3.

[0022] 2, six electrode pads including signal terminals 51, 52 and a ground terminal 53 are provided on main surface 41 of electronic component 40. Signal terminals 51, 52 are electrode pads for inputting and outputting high-frequency signals, and ground terminal 53 is an electrode pad for supplying a ground potential to electronic component 40.

[0023] As shown in FIG. 2, the conductor layer L3 includes signal wirings S1 and S2 and a ground wiring G1. One end of the signal wirings S1 and S2 is connected to the signal terminals 51 and 52 of the electronic component 40 through the via conductor 36 at a position where the signal wirings S1 and S2 overlap with the signal terminals 51 and 52 of the electronic component 40, respectively. One end of the ground wiring G1 is connected to the ground terminal 53. The core material C included in the insulating layer 13 is removed from the periphery of the electronic component 40 and the position where the signal wiring S1 overlaps in a planar view. Specifically, the core material C is removed from the periphery of the electronic component 40 and along the position where the signal wiring S1 overlaps in a planar view, so that the end B of the core-free region A extends along the periphery of the electronic component 40 and the periphery of the signal wiring S1 in a planar view. The core-free region A is a closed region that is not connected to the outside in a planar view, and therefore the end B of the core-free region A is not connected to the outer periphery of the core material C. In this way, since the area of ​​the core-free region A is kept to a minimum, the decrease in mechanical strength caused by the core-free region A is kept to a minimum.

[0024] Since the signal wiring S1 does not entirely overlap with the core material C in a planar view, the high-frequency characteristics of the high-frequency signal flowing through the signal wiring S1 are less likely to vary. On the other hand, the signal wiring S2 partially overlaps with the core material C in a planar view. In this manner, it is not necessary to remove the core material C from positions where it overlaps with all the signal wirings, and the core material C may be removed from a position where it overlaps with the signal wiring S1, which is particularly susceptible to the influence of the core material C. As an example, the signal flowing through the signal wiring S1 is a high-frequency antenna signal, and the signal flowing through the signal wiring S2 is a control signal.

[0025] 2, the other end of the signal wiring S1 is drawn out to a position where it does not overlap with any electronic components, and is connected to a signal wiring S3 included in the conductor layer L2 through a via conductor 32. The signal wiring S3 is connected to a signal terminal ES, which is one of the terminal electrodes E1 included in the conductor layer L1, through a via conductor 31. Meanwhile, the other end of the ground wiring G1 is connected to a ground pattern G2 included in the conductor layer L2 through a via conductor 32. The ground pattern G2 is a solid pattern that occupies most of the conductor layer L2, and the periphery of the signal wiring S2 is surrounded by the ground pattern G2. The ground pattern G2 is connected to a ground terminal EG, which is one of the terminal electrodes E1 included in the conductor layer L1, through the via conductor 31.

[0026] As described above, the electronic component built-in substrate 1 according to the present embodiment is provided with the core material C in the insulating layer 13 located at the center in the thickness direction and in which the electronic component 40 is embedded, and the other insulating layers 11, 12, 14, and 15 located above and below the insulating layer 13 are not provided with the core material C, so that it is possible to reduce the overall thickness while ensuring mechanical strength. Moreover, since the core material C is removed not only from the portion overlapping with the electronic component 40 but also from the position overlapping with the signal wiring S1 in a planar view, the high-frequency characteristics of the high-frequency signal flowing through the signal wiring S1 are less likely to vary. In addition, since the insulating layers 11, 12, 14, and 15 are made of a resin material that does not contain the core material C, the via conductors 31, 32, 34, and 35 can be formed at a narrow pitch. Therefore, even when electronic components with a narrow terminal pitch are mounted on the front surface 1a or 1b, the layout design is easy.

[0027] Next, a method for manufacturing the electronic component built-in substrate 1 according to this embodiment will be described.

[0028] 3 to 11 are process diagrams illustrating a method for manufacturing the electronic component built-in substrate 1 according to this embodiment.

[0029] First, as shown in FIG. 3, a base material is prepared in which conductor layers L4, L5 made of Cu foil or the like are formed on both sides of an insulating layer 14 made of a resin material not including a core material C, and this is fixed to a support 50. Next, as shown in FIG. 4, the conductor layer L4 is patterned using a known method such as photolithography to complete the conductor layer L4 having a desired pattern shape. Next, as shown in FIG. 5, an insulating layer 13a is formed by laminating, for example, an uncured (B-stage state) resin sheet or the like on the surface of the insulating layer 14 by vacuum pressure bonding or the like so as to embed the patterned conductor layer L4. Next, an electronic component 40 is placed on the surface of the insulating layer 13a. The electronic component 40 is mounted in a face-up manner so that a main surface 41 on which electrode pads are exposed faces upward.

[0030] Next, as shown in FIG. 6, the insulating layer 13b including the core material C and the conductor layer L3 are formed so as to cover the electronic component 40. The insulating layer 13b is preferably formed, for example, by applying an uncured or semi-cured thermosetting resin, and then heating the uncured resin to semi-cure it, and then hardening and molding it together with the conductor layer L3 using a press means. The core material C has a core-free region A formed in advance at a position where it overlaps with the electronic component 40. The resin material used for the insulating layer 13b may be the same as that used for the insulating layer 13a. Alternatively, a CCL material impregnated with resin or the like may be prepared in advance, and a part or all of the conductor layer formed on the surface of the CCL material may be removed, and a punching process using a drill, laser, or die press may be performed to form the core material C having the core-free region A, and the core material C may be embedded in the insulating layer 13b in the same manner as the electronic component 40.

[0031] 7, via holes are formed in the insulating layer 13, and then via conductors 33 and 36 are formed to fill the via holes. The conductor layer L3 is then patterned using a known method such as photolithography to complete the conductor layer L3 having a desired pattern shape. As a result, a part of the conductor layer L3 is connected to the conductor layer L4 through the via conductor 33, and another part of the conductor layer L3 is connected to the electronic component 40 through the via conductor 36.

[0032] Next, as shown in Fig. 8, the sheet in which the insulating layer 12 made of a resin material not including the core material C and the conductor layer L2 are laminated is vacuum hot pressed so as to embed the conductor layer L3. The material and thickness used for the insulating layer 12 may be the same as those of the insulating layer 14. Thereafter, the support 50 is peeled off as shown in Fig. 9.

[0033] 10, via holes are formed in the insulating layers 12 and 14, and then via conductors 32 and 34 are formed to fill the via holes. Furthermore, the conductor layers L2 and L5 are patterned using a known method such as photolithography to complete the conductor layers L2 and L5 having a desired pattern shape. As a result, a part of the conductor layer L2 is connected to the conductor layer L3 through the via conductor 32, and a part of the conductor layer L5 is connected to the conductor layer L4 through the via conductor 34. In this way, a precursor of an electronic component-embedded substrate having four conductor layers L2 to L5 is completed.

[0034] 11, a sheet in which insulating layer 11 and conductor layer L1 made of a resin material not including core material C are laminated, and a sheet in which insulating layer 15 and conductor layer L6 made of a resin material not including core material C are laminated are prepared, and a precursor having conductor layers L2 to L5 is sandwiched between these and vacuum hot pressed. Then, via holes are formed in insulating layers 11 and 15, and via conductors 31 and 35 are formed to fill the via holes. Furthermore, conductor layers L1 and L6 are patterned using a known method such as photolithography, and solder resists 21 and 22 are formed, completing electronic component-embedded substrate 1 shown in FIG.

[0035] Here, since insulating layers 11, 12, 14, and 15 do not contain core material C such as glass cloth, in the process of forming via holes in insulating layers 11, 12, 14, and 15, small diameter via holes can be formed at narrow pitches by laser processing or blasting.

[0036] Although a preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention, and it goes without saying that these modifications are also included within the scope of the present invention.

[0037] For example, the electronic component built-in substrate 1 according to the above embodiment has six conductor layers L1 to L6, but the number of conductor layers is not limited to this in the present invention. As an example, the number of conductor layers may be four by omitting the conductor layers L1 and L6. [Explanation of symbols]

[0038] 1. Electronic component embedded board 1a, 1b Surface of a substrate with built-in electronic components 11~15, 13a, 13b Insulating layer 21,22 Solder resist 31~36 Via conductor 40 Electronic Components 41 Main surface of electronic components 50 Support 51,52 Signal terminal 53 Ground terminal A Coreless area B End of non-core area C Core material E1,E2 terminal electrode EG Ground terminal ES signal terminal G1 Ground wiring G2 Ground Pattern L1~L6 conductor layer S1~S3 signal wiring

Claims

1. a first insulating layer having a core material; an electronic component embedded in the first insulating layer; a first conductor layer provided on one surface of the first insulating layer and including a first signal wiring; one end of the first signal wiring is connected to a first signal terminal of the electronic component at a position where the one end of the first signal wiring overlaps the first signal terminal of the electronic component; the other end of the first signal wiring is drawn out to a position where it does not overlap with the electronic component, the first insulating layer forms a core-free region where the core material is not present around the electronic component and at a position overlapping the first signal wiring in a plan view; An electronic component-embedded substrate characterized in that the coreless region is formed along the periphery of the electronic component and at a position that overlaps with the first signal wiring in a planar view, thereby causing the ends of the coreless region to extend along the periphery of the electronic component and along the periphery of the first signal wiring in a planar view.

2. the first conductor layer further includes a second signal wiring having one end connected to a second signal terminal of the electronic component; The electronic component built-in substrate according to claim 1 , wherein a portion of the second signal wiring overlaps with the core material in a plan view.

3. a second insulating layer provided on the one surface of the first insulating layer so as to embed the first conductor layer; A second conductor layer provided on a surface of the second insulating layer, 3. The electronic component-embedded substrate according to claim 1, wherein the second insulating layer is made of a resin material that does not contain a core material.

4. a third conductor layer provided on the other surface of the first insulating layer; a third insulating layer provided on the other surface of the first insulating layer so as to embed the third conductor layer; a fourth conductor layer provided on a surface of the third insulating layer, 4. The electronic component-embedded substrate according to claim 3, wherein the third insulating layer is made of a resin material that does not contain a core material.

Images