Switching Control Circuit

Abstract

To provide a switching control circuit that can output a suitable control signal even when the voltage on a high voltage side varies.SOLUTION: A switching control circuit controls switching of a switching element of a bridge circuit for driving a load. The switching control circuit includes: a control circuit that outputs a control signal with a first logic level for turning on the switching element on the basis of a set signal for turning on the switching element to a signal line, and outputs the control signal with a second logic level for turning off the switching element on the basis of a reset signal for turning off the switching element to the signal line; a setting circuit that sets the logic level of the signal line to the second logic level in a period after the reset signal is input to the control circuit and before the set signal is input to the control circuit; and a driving circuit that drives the switching element on the basis of the control signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a switching control circuit. [Background technology]

[0002] There is a control circuit that controls switching of a switching element in an upper arm based on a signal output from a microcomputer (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-172358 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the power supply on the high voltage side fluctuates, the control circuit may erroneously generate a control signal that turns on the switching element, instead of generating a control signal that turns off the switching element.

[0005] The present invention has been made in consideration of the above-mentioned problems in the conventional art, and has an object to provide a switching control circuit that can output an appropriate control signal even when the voltage on the high-voltage side fluctuates. [Means for solving the problem]

[0006] An aspect of the switching control circuit of the present invention that solves the above-mentioned problems is a switching control circuit that controls switching of a switching element of a bridge circuit for driving a load, and includes a control circuit that outputs a control signal of a first logic level for turning on the switching element to a signal line based on a set signal for turning on the switching element, and outputs the control signal of a second logic level for turning off the switching element to the signal line based on a reset signal for turning off the switching element, a setting circuit that sets the logic level of the signal line to the second logic level during a period after the reset signal is input to the control circuit and before the set signal is input to the control circuit, and a drive circuit that drives the switching element based on the control signal. Effect of the Invention

[0007] According to the present invention, it is possible to provide a switching control circuit that can output an appropriate control signal even when the voltage on the high voltage side fluctuates. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing an example of the configuration of a power module 10. FIG. [Diagram 2] 2 is a diagram showing an example of the configuration of a switching control circuit 20. FIG. [Diagram 3] 3 is a diagram showing an example of waveforms of main signals of a switching control circuit 20. FIG. [Figure 4] 11 is a diagram showing a truth table for explaining the logical operation of a signal output circuit 60 based on signals set and reset. FIG. [Diagram 5] 11 is a diagram showing the behavior of signals LTIN, ZLTIN, and LTOT when voltage Vb returns to normal after fluctuation. FIG. [Figure 6] FIG. 13 is a diagram showing an example of the configuration of a modified example of a circuit for controlling an NMOS transistor 112. [Figure 7] FIG. 2 is a diagram showing an example of the configuration of a switching control circuit 20a. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] At least the following points will become apparent from the description of this specification and the accompanying drawings.

[0010] =====This embodiment===== FIG. 1 is a diagram showing an example of the configuration of a power module 10 according to an embodiment of the present invention.

[0011] <<Power Module 10>> The power module 10 is a semiconductor device for driving a load 11 based on instructions from a microcomputer (not shown), and includes a capacitor 14, a switching control circuit 20, a half-bridge circuit 30, and terminals D, P, S, N, and COM.

[0012] The switching control circuit 20 is a high voltage integrated circuit (HVIC: High Voltage IC) that controls the operation of the half-bridge circuit 30 based on an input signal IN input from a microcomputer (not shown). The switching control circuit 20 is configured to include terminals DS, VB, H, VS, L, and G, which will be described in detail later.

[0013] The half-bridge circuit 30 is a circuit that drives the load 11, and includes NMOS transistors 31 and 32.

[0014] The NMOS transistor 31 is a high-side switching element, with a gate electrode connected to a terminal H and a source electrode connected to a terminal S. A predetermined voltage Vdc (e.g., “400 V”) is applied to the drain electrode of the NMOS transistor 31 via a terminal P.

[0015] The NMOS transistor 32 is a low-side switching element, with a gate electrode connected to the terminal L and a drain electrode connected to the terminal S. In addition, the source electrode of the NMOS transistor 32 is grounded.

[0016] The capacitor 12 is an element for stabilizing the power supply 13 that generates a predetermined voltage Vdc.

[0017] Capacitor 14 is an element to which a bootstrap voltage Vb for operating the high-side circuit is applied, with one end connected to terminal VB and the other end connected to terminal VS. Capacitor 14 is charged by applying the bootstrap voltage Vb to terminal VB from a charge pump circuit 101, which will be described later. As a result, the bootstrap voltage Vb is generated across capacitor 14.

[0018] For example, when the voltage Vs of the terminal VS is "0V," the NMOS transistor 31 turns on when the voltage of the gate electrode of the NMOS transistor 31 becomes higher than the threshold voltage of the NMOS transistor 31. However, when the NMOS transistor 31 turns on, the voltage Vs of the terminal VS approaches the voltage Vdc (e.g., "400V"), so that in order to keep the NMOS transistor 31 on, it is necessary to drive the NMOS transistor 31 so that the voltage of the gate electrode becomes higher than the threshold voltage of the NMOS transistor 31, with the voltage Vs of the terminal VS to which the source electrode of the NMOS transistor 31 is connected as a reference.

[0019] In this embodiment, a voltage higher than the voltage Vs of the terminal VS by a bootstrap voltage Vb is generated at the terminal VB, based on the voltage Vs of the power supply line L1 (see FIG. 2) applied to the terminal VS. Therefore, the switching control circuit 20 can turn on the NMOS transistor 31 by using the bootstrap voltage Vb, as will be described in detail later.

[0020] The NMOS transistors 31 and 32 correspond to a "switching element", and in particular, the NMOS transistor 31 corresponds to an "upper arm switching element".

[0021] <<Switching control circuit 20>> Fig. 2 is a diagram showing an example of the configuration of the switching control circuit 20. The switching control circuit 20 includes a high-side drive circuit 21 (hereinafter referred to as HDRV) (described later) that drives an NMOS transistor 31 of an upper arm, and a low-side drive circuit 22 (hereinafter referred to as LDRV) (described later) that drives an NMOS transistor 32 of a lower arm. For convenience of illustration, the terminal DS is omitted in Fig. 2.

[0022] << <hdrv21>>> The HDRV 21 is a circuit that drives the NMOS transistor 31 based on the input signal IN. The HDRV 21 includes an input circuit 41, a pulse generating circuit 42, a level shift circuit 50, a signal output circuit 60, a latch circuit 70, a buffer 80, a bootstrap circuit 100, and a pull-down circuit 110.

[0023] <<<<Input circuit 41>>>> The input circuit 41 detects the level of the input signal IN and outputs a signal HIN having the same logical level as the logical level of the input signal IN. Specifically, when the input signal IN becomes high level (hereinafter referred to as "H" level), the input circuit 41 outputs a signal HIN of "H" level, and when the input signal IN becomes low level (hereinafter referred to as "L" level), the input circuit 41 outputs a signal HIN of "L" level. The input circuit 41 is configured to include, for example, a comparator (not shown) and a low-pass filter (not shown) that removes high-frequency noise from the output of the comparator.

[0024] <<<<Pulse generating circuit 42>>>> The pulse generating circuit 42 outputs a set signal set for turning on the high-side NMOS transistor 31 and a reset signal reset for turning it off, based on the signal HIN from the input circuit 41. Specifically, when the signal HIN goes to "H" level, the pulse generating circuit 42 outputs a set signal set of "H" level, and when the signal HIN goes to "L" level, it outputs a reset signal reset of "H" level. Note that the set signal set and the reset signal reset in this embodiment are each pulse signals whose amplitude levels change from 0V to the level of a low voltage Vcc (for example, 5V).

[0025] <<<<Level shift circuit 50>>>> The level shift circuit 50 is a circuit that shifts the levels of the set signal set and the reset signal reset generated by the pulse generating circuit 42 that operates on the low voltage Vcc to a level at which a signal output circuit 60 (described later) of the HDRV21 of the high voltage Vb supplied by the power supply line L2 can operate. Specifically, the level shift circuit 50 shifts the level of the set signal set, and outputs a level-shifted set signal setdrn having an amplitude level of, for example, several tens of volts. The level shift circuit 50 also shifts the level of the reset signal reset, and outputs a level-shifted reset signal resdrn having an amplitude level of, for example, several tens of volts.

[0026] The level shift circuit 50 includes NMOS transistors 51 and 52, resistors 53, 54, 56, and 57, an inverter 55, and diodes 58 and 59.

[0027] The drain electrode of the NMOS transistor 51 is connected to a resistor circuit C1 consisting of resistors 53 and 56. When a set signal set, which is a positive pulse, is input to the gate electrode, the NMOS transistor 51 becomes conductive and sets the level-shifted set signal setdrn to the “L” level.

[0028] Similarly, the drain electrode of the NMOS transistor 52 is connected to a resistor circuit C2 consisting of resistors 54 and 57. When a reset signal reset, which is a positive pulse, is input to the gate electrode, the NMOS transistor 52 becomes conductive and sets the level-shifted reset signal resdrn to the “L” level.

[0029] The resistor circuit C1 formed by the resistors 53 and 56 changes based on an output signal LTOT of a latch circuit 70 (described later). Similarly, the resistor circuit C2 formed by the resistors 54 and 57 also changes based on an output signal LTOT of the latch circuit 70 (described later).

[0030] The relationship between the change in the combined resistance of the resistor circuits C1 and C2 and the operations of the level-shifted set signal setdrn and the level-shifted reset signal resdrn will be described later.

[0031] As an example, the resistance value of the resistors 53 and 54 is 10 kΩ, and the resistance value of the resistors 56 and 57 is 45 kΩ.

[0032] The diodes 58 and 59 clamp the drain electrodes of the NMOS transistors 51 and 52 with the voltage Vs of the power supply line L1. The anodes of the diodes 58 and 59 are connected to the power supply line L1, and the cathodes of the diodes 58 and 59 are connected to the drain electrodes of the NMOS transistors 51 and 52. This makes it possible to prevent an overvoltage from being applied to the signal output circuit 60.

[0033] The voltage Vb of the power supply line L2 corresponds to a "predetermined voltage." Either the power supply line L1 or the power supply line L2 corresponds to a "first line," and the other corresponds to a "second line." The combination of the resistance circuits C1 and C2 corresponds to an "adjustment circuit."

[0034] <<<<Signal Output Circuit 60>>>> The signal output circuit 60 is a circuit that generates a signal LTIN that controls a signal LTOT output by a latch circuit 70 (described later). The signal output circuit 60 includes an inverter 61, PMOS transistors 62 and 63, and NMOS transistors 64 and 65. The operation of the signal output circuit 60 will be described later.

[0035] <<<<Latch circuit 70>>>> The latch circuit 70 is a circuit that holds the signal LTIN output from the signal output circuit 60 and outputs it as a signal LTOT. The latch circuit 70 includes inverters 71 and 72, and a resistor 73.

[0036] When the signal LTIN goes to the "L" level, the output of the inverter 71 goes to the "H" level and the output of the inverter 72 goes to the "L" level in the latch circuit 70. At this time, the latch circuit 70 pulls down the signal line through which the signal LTIN is output by the resistor 73. As a result, the latch circuit 70 can hold the signal LTOT at the "L" level even if the output of the signal output circuit 60 goes to a high impedance state.

[0037] Conversely, when signal LTIN goes to "H" level, the output of inverter 71 goes to "L" level and the output of inverter 72 goes to "H" level. At this time, latch circuit 70 pulls up the signal line through which signal LTIN is output by resistor 73. As a result, latch circuit 70 can hold signal LTOT at "H" level even if the output of signal output circuit 60 goes to a high impedance state.

[0038] Furthermore, while an example has been given in which the latch circuit 70 includes two inverters, the latch circuit 70 may include an even number of inverters greater than two.

[0039] The latch circuit 70 corresponds to a "holding circuit," and the signal line through which the signal LTIN is output corresponds to a "signal line." The inverters 71 and 72 correspond to a "first inverting circuit" and a "second inverting circuit," and the "first inverting circuit" and the "second inverting circuit" may each include an odd number of inverters, which is greater than one. The resistor 73 corresponds to a "second resistor."

[0040] <<<<Buffer 80>>>> The buffer 80 is a circuit that outputs a signal HO based on a control signal, which is a signal LTOT, from the latch circuit 70 to drive the NMOS transistor 31 .

[0041] <<<<Pull-down circuit 110>>>> The pull-down circuit 110 is a circuit that prevents the signal LTIN from erroneously going to the “H” level when the signal LTOT should be at the “L” level when the voltage Vb returns to the normal state after fluctuating. The pull-down circuit 110 includes a resistor 111 and an NMOS transistor 112.

[0042] One end of the resistor 111 is connected to the signal LTIN which is the output of the signal output circuit 60, and the other end is connected to the drain electrode of the NMOS transistor 112. The source electrode of the NMOS transistor 112 is connected to the power supply line L1, and the output signal ZLTIN of the inverter 71 of the latch circuit 70 is input to the gate electrode of the NMOS transistor 112.

[0043] As a result, when the signal LTIN is at the “L” level and the output signal ZLTIN of the inverter 71 is at the “H” level, the NMOS transistor 112 is turned on and the output of the signal output circuit 60 is pulled down via the resistor 111 .

[0044] As a result, the pull-down circuit 110 operates to set the signal LTIN to the "L" level when the signal LTIN should be at the "L" level.

[0045] The pull-down circuit 110 corresponds to a "setting circuit." The NMOS transistor 112 corresponds to a "switch." Moreover, the resistor 111 corresponds to a "first resistor."

[0046] <<<<Bootstrap circuit 100>>>> The bootstrap circuit 100 is a circuit that generates, in a capacitor 14, a voltage Vb used to turn on the NMOS transistor 31. The bootstrap circuit 100 includes a charge pump circuit 101 that operates on a low voltage Vcc, and a bootstrap diode 102.

[0047] The charge pump circuit 101 generates a voltage for supplying a voltage Vb to the capacitor 14 from a low voltage Vcc.

[0048] The bootstrap diode 102 is an element for preventing the charge of the capacitor 14 from flowing to the charge pump circuit 101 .

[0049] In this way, the bootstrap circuit 100 charges the capacitor 14 using the low voltage Vcc, thereby supplying the voltage Vb that can turn on the NMOS transistor 31 even if the voltage Vs becomes a high voltage.

[0050] However, since the capacitor 14 is disposed outside the switching control circuit 20, the voltage Vb may fluctuate due to the influence of parasitic inductance generated in the wiring to the capacitor 14, etc.

[0051] << <ldrv22>>> The LDRV22 is a circuit that drives the NMOS transistor 32 based on a signal HIN from the input circuit 41. Specifically, the LVRV22 outputs a signal LO that is an inverted logical level of the signal HIN, and controls the switching of the NMOS transistor 32. The LDRV22 operates based on a power supply voltage E1.

[0052] <<Waveforms of main signals in the switching control circuit 20>> 3 is a diagram showing an example of waveforms of main signals of the switching control circuit 20. The set signal set and the reset signal reset are generated by the pulse generating circuit 42, and the level-shifted set signal setdrn and the level-shifted reset signal resdrn are generated by the level shift circuit 50.

[0053] The pulse generating circuit 42 generates a set signal set, which is a positive pulse, at the rising edge of the signal HIN from the input circuit 41. The pulse generating circuit 42 also generates a reset signal reset, which is a positive pulse, at the falling edge of the signal HIN from the input circuit 41.

[0054] The level shift circuit 50 generates a level-shifted set signal setdrn and a level-shifted reset signal resdrn, which are negative pulses, based on a set signal set and a reset signal reset, which are positive pulses.

[0055] When the level-shifted set signal setdrn at "L" level is input to the signal output circuit 60, the signal output circuit 60 sets the signal LTIN to "H" level. When the level-shifted reset signal resdrn at "L" level is input to the signal output circuit 60, the signal output circuit 60 sets the signal LTIN to "L" level. When the level-shifted set signal setdrn and the level-shifted reset signal resdrn become "H" level, the signal LTIN becomes a high impedance state.

[0056] The latch circuit 70 receives the signal LTIN and outputs the signal LTOT as described above.

[0057] <<Truth table of signal output circuit 60>> 4 is a diagram showing a truth table explaining the logical operation of the signal output circuit 60 based on the set signal set and the reset signal reset. Based on the set signal set and the reset signal reset output from the pulse generating circuit 42, the level shift circuit 50 outputs a level-shifted set signal setdrn and a level-shifted reset signal resdrn. The level-shifted set signal setdrn and the level-shifted reset signal resdrn are input to the signal output circuit 60.

[0058] When either the set signal set or the reset signal reset is at the "L" level, the level-shifted set signal setdrn and the level-shifted reset signal resdrn are both at the "H" level. At this time, the PMOS transistor 63 and the NMOS transistor 64 are turned on, and the PMOS transistor 62 and the NMOS transistor 65 are turned off. Therefore, the output of the signal output circuit 60 is in a high impedance output state. Note that when either the set signal set or the reset signal reset is at the "L" level, the state in which the output of the signal output circuit 60 is in a high impedance output state is called the "default state."

[0059] When the signal set is at "L" level and the signal reset is at "H" level, the level-shifted set signal setdrn is at "H" level and the level-shifted reset signal resdrn is at "L" level. At this time, the NMOS transistors 64 and 65 are turned on and the PMOS transistors 62 and 63 are turned off. Therefore, the output of the signal output circuit 60 is at "L" level. Note that when the signal set is at "L" level and the signal reset is at "H" level, the state in which the output of the signal output circuit 60 is at "L" level is called a "reset state."

[0060] When the signal set is at "H" level and the signal reset is at "L" level, the level-shifted set signal setdrn is at "L" level and the level-shifted reset signal resdrn is at "H" level. At this time, the PMOS transistors 62 and 63 are turned on and the NMOS transistors 64 and 65 are turned off. Therefore, the output of the signal output circuit 60 becomes "H" level. Note that when the signal set is at "H" level and the signal reset is at "L" level, the state in which the output of the signal output circuit 60 becomes "H" level is called the "set state."

[0061] There is no case where the set signal set and the reset signal reset are both at the "H" level, and there is no case where the level-shifted set signal setdrn and the level-shifted reset signal resdrn are both at the "L" level. Therefore, this state is called a "prohibited state."

[0062] As described above, when the signal set from the pulse generating circuit 42 goes to the "H" level, the signal output circuit 60 goes to the set state, and when the signal reset goes to the "H" level, the signal output circuit 60 goes to the reset state. When both the signals set and reset are at the "L" level, the signal output circuit 60 goes to the default state. In this embodiment, the "H" level corresponds to the "first logic level" and the "L" level corresponds to the "second logic level". In some cases, the "L" level corresponds to the "first logic level" and the "H" level corresponds to the "second logic level".

[0063] <<Operation of the switching control circuit 20>> ==When signal LTOT is at "L" level== FIG. 5 is a diagram showing the behavior of the signals LTIN, ZLTIN, and LTOT when the voltage Vb varies while the signal LTOT is at the "L" level.

[0064] First, at time t0, when the reset signal reset goes to "H" level, the level-shifted reset signal resdrn goes to "L" level. As a result, the signal output circuit 60 goes to a "reset state", and the signal LTOT goes to "L" level. As a result, the resistors 53 and 56 in the resistor circuit C1, one end of which is connected to the power supply line L2, are connected in parallel, and the node at which the level-shifted set signal setdrn is output is connected to the other end of the resistors 53 and 56. Therefore, the impedance between the power supply line L2 of the resistor circuit C1 and the node at which the level-shifted set signal setdrn is output decreases.

[0065] On the other hand, the resistor circuit C2 includes a resistor 54 connected to the power supply line L2 and a resistor 57 connected between the resistor 54 and the power supply line L1, and the level-shifted reset signal resdrn is output from the connection node of the resistors 54 and 57. Therefore, the impedance between the power supply line L2 of the resistor circuit C2 and the node at which the level-shifted reset signal resdrn is output increases.

[0066] Then, at time t1, when the reset signal reset goes to the "H" level, the signal output circuit 60 goes into the "default state."

[0067] Furthermore, between time t2 and time t3, for example, the voltage Vb fluctuates due to the influence of noise or the like. Here, the impedance of the resistor circuit C1 becomes smaller than the impedance of the resistor circuit C2. As a result, the level-shifted set signal setdrn rises earlier than the level-shifted reset signal resdrn. For this reason, when the voltage Vb returns, the signal output circuit 60 normally outputs the signal LTOT at the "L" level.

[0068] However, if the level of the voltage Vb drops significantly, the on-resistance of the PMOS transistors 62 and 63 may become small when the voltage Vb returns to normal. As a result, the signal output circuit 60 may output an "H" level signal LTOT. Therefore, the switching control circuit 20 of this embodiment is provided with a pull-down circuit 110 to prevent the "H" level signal LTOT from being erroneously output.

[0069] Specifically, at time t3, the signal LTOT is originally at the "L" level, and the NMOS transistor 112 is turned on. Therefore, even if the output signal LTIN of the signal output circuit 60 fluctuates below the threshold voltage of the inverter 71 of the latch circuit 70, the signal LTOT is pulled down by the pull-down circuit 110 and remains at the "L" level.

[0070] As a result, the signals LTIN, LTOT, and HO go to the "L" level, and the NMOS transistor 31 is turned off. Therefore, the switching control circuit 20 controls the NMOS transistor 31 to a safe state. That is, in this embodiment, even if a fluctuation occurs in the voltage Vb, the NMOS transistor 112 is turned on, so that the signal output circuit 60 can maintain the "reset state."

[0071] ==When signal LTOT is at "H" level== When the signal output circuit 60 is in the "set state", the signal LTOT becomes "H" level. As a result, the resistor circuit C1 in Fig. 2 includes a resistor 53 connected to the power supply line L2 and a resistor 56 connected between the resistor 53 and the power supply line L1, and the level-shifted set signal setdrn is output from the connection node of the resistors 53 and 56. Therefore, the impedance between the power supply line L2 of the resistor circuit C1 and the node where the level-shifted set signal setdrn is output increases.

[0072] On the other hand, in the resistor circuit C2, resistors 54 and 57, one end of which is connected to the power supply line L2, are connected in parallel, and the node at which the level-shifted reset signal resdrn is output is connected to the other end of the resistors 54 and 57. Therefore, the impedance between the power supply line L2 of the resistor circuit C2 and the node at which the level-shifted reset signal resdrn is output is reduced.

[0073] Thereafter, when the signal output circuit 60 is in the default state, if a fluctuation in the voltage Vb occurs, the impedance of the resistor circuit C2 becomes smaller than the impedance of the resistor circuit C1, and as a result, the level-shifted reset signal resdrn rises earlier than the level-shifted set signal setdrn. Therefore, when the signal output circuit 60 returns to normal after the fluctuation in the voltage Vb, the signal output circuit 60 operates so that the signal LTOT becomes the "H" level.

[0074] In this case, since the NMOS transistor 112 is turned off, the signal LTIN is not pulled down. Therefore, in this embodiment, when a fluctuation occurs in the voltage Vb, the signal LTIN can be reliably set to the "H" level. Therefore, even when a fluctuation occurs in the voltage Vb, the NMOS transistor 112 is turned off, so that the signal output circuit 60 can maintain the "set state."

[0075] The signal line through which the signal LTIN is output corresponds to the "signal line." The node through which the level-shifted set signal setdrn is output corresponds to the "first node," and the node through which the level-shifted reset signal resdrn is output corresponds to the "second node." The NMOS transistor 51 corresponds to the "first NMOS transistor," and the NMOS transistor 52 corresponds to the "second NMOS transistor."

[0076] === Variations === In this embodiment, the output signal ZLTIN of the inverter 71 of the latch circuit 70 is output to the gate electrode of the NMOS transistor 112 of the pull-down circuit 110.

[0077] 2, the NMOS transistor 112 may be controlled by the signal ZLTIN or by the output of the inverter 55. The buffer 80 may be implemented as a two-stage inverter, and the NMOS transistor 112 may be controlled by the output of the first-stage inverter. That is, depending on the design of the circuit subsequent to the signal output circuit 60, the NMOS transistor 112 may be controlled by a signal other than the signal ZLTIN and the output of the inverter 55 shown in FIG.

[0078] Alternatively, as shown in FIG. 6, a circuit for detecting a change in the voltage Vb may be used to output the signal ZLTIN. This circuit includes a comparator 121, a counter 122, and a switch control circuit 123. The comparator 121 compares the power supply Vb with a reference voltage VREF, and outputs a signal of the "L" level when the voltage Vb is lower than the reference voltage VREF. When the counter 122 receives a detection result of the "L" level signal from the comparator 121, the counter 122 starts counting and continues counting for a predetermined period. The switch control circuit 123 outputs a signal ZLTIN of the "H" level for a predetermined period. When the level-shifted set signal setdrn returns from the change, the switch control circuit 123 outputs a signal ZLTIN of the "L" level. The comparator 121 corresponds to a "detection circuit", and the counter 122 corresponds to a "counter".

[0079] In this embodiment, the circuit is configured such that when the signal LTIN is at an "L" level, the NMOS transistor 31 is turned off, and when the signal LTIN is at an "H" level, the NMOS transistor 31 is turned on. However, as an alternative configuration, the circuit may be configured such that when the signal LTIN is at an "H" level, the NMOS transistor 31 is turned off, and when the signal LTIN is at an "L" level, the NMOS transistor 31 is turned on. In this case, instead of the pull-down circuit 110, a pull-up circuit 110a that pulls up to the power supply line L2 may be adopted.

[0080] Specifically, an example of a switching control circuit 20a which is the above-mentioned modified example is shown in FIG. The switching control circuit 20a includes a pull-up circuit 110a instead of the pull-down circuit 110. The pull-up circuit 110a includes at least a PMOS transistor 112a. The pull-up circuit 110a may further include a resistor 111a. The switching control circuit 20a includes a signal output circuit 60a including PMOS transistors 62 and 63, NMOS transistors 64 and 65, and an inverter 66 which inverts the signal setdrn instead of the signal output circuit 60. The switching control circuit 20a includes a latch circuit 70a including inverters 71 and 72, a resistor 73, and an inverter 74 instead of the latch circuit 70.

[0081] The PMOS transistor 112a may be controlled by a signal ZLTIN, or may be controlled by a signal LTOT or a signal HO as shown in Fig. 7. That is, depending on the design of the circuit downstream of the signal output circuit 60a, the PMOS transistor 112a may be controlled by signals other than the signals ZLTIN, LTOT, and HO shown in Fig. 7.

[0082] ===Summary=== The power module 10 of this embodiment has been described above. For example, when the voltage Vb returns to normal after fluctuating, the output of the signal output circuit 60 may become unstable due to the relationship between the level-shifted set signal setdrn or the level-shifted reset signal resdrn and the signal output circuit 60. However, when a fluctuation in the voltage Vb occurs, a signal of an appropriate logic level can be output by setting the output signal LTIN of the signal output circuit 60 to the "L" level, and the NMOS transistor 31 can be prevented from being unintentionally turned on.

[0083] Furthermore, using the NMOS transistor 112 that is turned on based on the logic level of the signal LTIN in order to set the output signal LTIN of the signal output circuit 60 to the “L” level makes it possible to output a signal of an appropriate logic level without requiring a large circuit scale.

[0084] Furthermore, by providing the resistor 111 in series with the NMOS transistor 112, even if the signal LTIN goes to the "H" level, the operation of the pull-down circuit 110 is not affected.

[0085] Furthermore, providing the latch circuit 70 at the output of the signal output circuit 60 makes it possible to output a signal of an appropriate logic level even if the output of the signal output circuit 60 becomes high impedance.

[0086] Furthermore, the latch circuit 70 has a small circuit scale and is configured to include inverters 71 and 72 and a resistor 73. Furthermore, inputting the output of the inverter 71 to the NMOS transistor 112 makes it possible to appropriately control the logic level of the signal LTIN according to the logic level of the signal LTIN.

[0087] In addition, resistor circuits C1 and C2 are used that change the circuit configuration based on the signal LTOT. This adjusts the return timing of the level-shifted set signal setdrn and the level-shifted reset signal resdrn after the voltage Vb fluctuates, and makes it possible to make the logic level of the signal LTOT the same as before the fluctuation, even if the voltage Vb fluctuates.

[0088] Furthermore, when a fluctuation in the voltage Vb is detected, the logic level of the signal LTIN is appropriately controlled, so that the fluctuation in the voltage Vb can be directly reflected in the control of the logic level of the signal LTIN.

[0089] In addition, based on the comparator 121 detecting a fluctuation in the voltage Vb, the counter 122 counts a predetermined period and turns on the NMOS transistor 112 during that period, thereby determining the period for appropriately controlling the logic level of the signal LTIN.

[0090] Furthermore, providing the latch circuit 70 at the output of the signal output circuit 60 makes it possible to output a signal of an appropriate logic level even if the output of the signal output circuit 60 becomes high impedance.

[0091] The switching control circuit 20 can also be used to control the high side NMOS transistor 31 .

[0092] Furthermore, when the switching control circuit 20 is used on the high side, the use of the capacitor 14, the charge pump circuit 101, and the bootstrap diode 102 allows the NMOS transistor 31 to be turned on normally.

[0093] In this embodiment, the half-bridge circuit 30 drives the load 11 as the "bridge circuit", but the load 11 is not necessarily driven by the half-bridge circuit 30 alone. The "bridge circuit" may be any circuit that uses switching elements in upper and lower arms, and includes, for example, an H-bridge circuit, a three-phase inverter circuit, and the like.

[0094] The above-mentioned embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. Furthermore, the present invention can be modified or improved without departing from the spirit of the present invention, and it goes without saying that the present invention includes equivalents thereof. [Explanation of symbols]

[0095] 10 Power Module 11 Load 12,14 Capacitor 13 Power supply 20 Switching control circuit 21 HDRV 22LDRV 30 Half-bridge circuit 31, 32, 51, 52, 64, 65, 112 NMOS transistors 41 Input circuit 42 Pulse Generation Circuit 50 Level shift circuit 53,54,56,57,73,111 Resistance 58,59 Diodes 55,61,71,72 Inverter 60 Signal output circuit 62,63 PMOS transistors 80,90 Buffer 101 Charge pump circuit 102 Bootstrap Diode 110 Pull-down circuit 121 Comparator 122 Counter 123 Switch control circuit

Claims

1. A switching control circuit for controlling switching of switching elements of a bridge circuit for driving a load, comprising: a control circuit that outputs a control signal of a first logic level for turning on the switching element to one signal line based on a set signal for turning on the switching element, and outputs the control signal of a second logic level for turning off the switching element to the signal line based on a reset signal for turning off the switching element; a setting circuit that sets the logic level of the signal line to the second logic level during a period after the reset signal is input to the control circuit and before the set signal is input to the control circuit; a hold circuit for holding the logic level of the signal line; a drive circuit that drives the switching element based on an output of the holding circuit; Equipped with The setting circuit includes: a switch that is provided between a first line to which a voltage corresponding to the second logic level is applied and the signal line, the switch being turned on during a period after the reset signal is input to the control circuit and before the set signal is input to the control circuit; a first resistor provided between the first line and the signal line and connected in series to the switch; Equipped with Switching control circuit.

2. 2. The switching control circuit of claim 1, the holding circuit, the control circuit, and the drive circuit are connected to the first line as a power supply line and to a second line as another power supply line to which a voltage corresponding to the first logic level is applied; the setting circuit is connected to the first line and the signal line; the switch of the setting circuit is controlled by any one of the holding circuit, the control circuit, and the drive circuit; Switching control circuit.

3. A switching control circuit for controlling switching of switching elements of a bridge circuit for driving a load, comprising: a control circuit that outputs a control signal of a first logic level for turning on the switching element to one signal line based on a set signal for turning on the switching element, and outputs the control signal of a second logic level for turning off the switching element to the signal line based on a reset signal for turning off the switching element; a setting circuit that sets the logic level of the signal line to the second logic level during a period after the reset signal is input to the control circuit and before the set signal is input to the control circuit; a hold circuit for holding the logic level of the signal line; a drive circuit that drives the switching element based on an output of the holding circuit; Equipped with The holding circuit includes: a first inverter circuit for inverting a logic level of the signal line; a second inverter circuit that inverts a logic level of an output of the first inverter circuit; a second resistor connecting the signal line and the output of the second inverting circuit; Equipped with The setting circuit includes: a switch that is provided between a second line to which a voltage corresponding to the first logic level is applied and the signal line, the switch being turned on during a period after the set signal is input to the control circuit and before the reset signal is input to the control circuit; a first resistor provided between the second line and the signal line and connected in series to the switch; Equipped with the control circuit, the holding circuit, and the drive circuit are connected to a first line and a second line to which a voltage corresponding to the second logic level is applied; Switching control circuit.

4. A switching control circuit for controlling switching of switching elements of a bridge circuit for driving a load, comprising: a control circuit that outputs a control signal of a first logic level for turning on the switching element to one signal line based on a set signal for turning on the switching element, and outputs the control signal of a second logic level for turning off the switching element to the signal line based on a reset signal for turning off the switching element; a setting circuit that sets the logic level of the signal line to the second logic level during a period after the reset signal is input to the control circuit and before the set signal is input to the control circuit; a hold circuit for holding the logic level of the signal line; a drive circuit that drives the switching element based on an output of the holding circuit; Equipped with The control circuit includes: a level shift circuit that outputs a signal obtained by level-shifting the set signal from a first node and outputs a signal obtained by level-shifting the reset signal from a second node; a signal output circuit that outputs the control signal of the first logic level to the signal line based on a level-shifted set signal output from the first node, and outputs the control signal of the second logic level to the signal line based on a level-shifted reset signal output from the second node; an adjustment circuit that makes the impedance of the first node smaller than the impedance of the second node when the control signal of the second logic level is output to the signal line, and makes the impedance of the second node smaller than the impedance of the first node when the control signal of the first logic level is output to the signal line, The setting circuit includes: a switch that is provided between a second line to which a voltage corresponding to the first logic level is applied and the signal line, the switch being turned on during a period after the set signal is input to the control circuit and before the reset signal is input to the control circuit; a first resistor provided between the second line and the signal line and connected in series to the switch; Equipped with the control circuit, the holding circuit, and the drive circuit are connected to a first line and a second line to which a voltage corresponding to the second logic level is applied; Switching control circuit.

5. 2. The switching control circuit of claim 1, a detection circuit for detecting a change in voltage of a second line to which a voltage corresponding to the first logic level is applied; a switch control circuit that turns on the switch based on a detection result indicating that the detection circuit has detected a voltage fluctuation on the second line; A switching control circuit comprising:

6. 6. A switching control circuit according to claim 5, a counter that counts a predetermined period based on a detection result indicating that the detection circuit has detected a voltage fluctuation of the second line; The switch control circuit turns on the switch for the predetermined period. Switching control circuit.

7. 7. A switching control circuit according to claim 1, The switching element is a switching element of an upper arm of the bridge circuit.

8. 8. A switching control circuit according to claim 7, a charge pump circuit that generates a voltage that corresponds to the voltage of a second line to which a voltage corresponding to the first logic level is applied; a bootstrap diode connected between the charge pump circuit and the second line; Equipped with the voltage of the second line is supplied from a capacitor connected between the second line and the first line to which a voltage corresponding to the second logic level is applied; Switching control circuit.

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