Semiconductor Device

Abstract

To provide a semiconductor device capable of preventing an error operation of a gate driving circuit due to a negative voltage noise.SOLUTION: A semiconductor device includes: a pad 2; a control circuit 5; gate driving circuits 6u, 6v, and 6w; set side level shifters 71, 73, and 75; reset side level shifters 72, 74, and 76; and annular wirings 8u, 8v, and 8w, respectively. The semiconductor device further includes: a plurality of high potential side circuit regions 10u, 10v, and 10w in which a distance to the pad 2 is different each other; a set side wiring 21 electrically connecting the pad 2 with the set side level shifters 71, 73, and 75; and a reset side wiring 22 electrically connecting the pad 2 with the reset side level shifters 72, 74, and 76. Each of the annular wirings 8v and 8w positioned at the side near from the pad 2 is electrically connected to the set side wiring 21 and the reset side wiring 22 via the annular wiring 8u positioned at the side far from the pad 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device such as a high voltage integrated circuit device (HVIC). [Background technology]

[0002] Conventionally, transformers and photocouplers have been used for electrical insulation to drive the gates of semiconductor power switching elements such as insulated gate bipolar transistors (IGBTs) that make up bridge circuits for power conversion. However, in recent years, mainly for small-capacity applications, high-voltage integrated circuit devices (hereinafter referred to as "HVICs") that do not provide electrical insulation have been used to reduce costs (see Patent Document 1 and Non-Patent Document 1).

[0003] The HVIC comprises a gate drive circuit that drives the gate of a semiconductor power switching element, a control circuit that controls the gate drive circuit, and a level shifter that transmits signals between the control circuit and the gate drive circuit. The control circuit operates based on the ground potential (GND potential). The gate drive circuit operates based on the VS potential, which is a floating potential. The gate drive circuit and control circuit are separated from each other by a high-voltage junction termination region (HVJT). The high-voltage junction termination region is composed of a high-voltage diode with the gate drive circuit side (VS terminal side) as the cathode and the control circuit side (GND terminal side) as the anode.

[0004] The level shifter is composed of, for example, a high-voltage n-channel MOSFET. Two level shifters, a set side and a reset side, are built in and are integrated with the high-voltage junction termination region. The sources of the set side level shifter and the reset side level shifter are connected to the GND pad by two wirings, the set side wiring and the reset side wiring. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 3214818 specification [Non-patent literature]

[0006] [Non-Patent Document 1] Proc.of The 11th Int.Symp.on Power Semiconductor Devices and ICs IEEE and IEEJ 1999 pp.333-336 Summary of the Invention [Problem to be solved by the invention]

[0007] In the HVIC described in Patent Document 1 and Non-Patent Document 1, negative voltage noise called -Vs noise occurs at the VS terminal of the HVIC due to switching of the semiconductor power switching element. The GND pad is not necessarily arranged in a symmetrical position with respect to the set side level shifter and the reset side level shifter due to reasons of mounting and layout of the control circuit, and a difference occurs between the wiring resistance between the source of the set side level shifter and the GND pad and the wiring resistance between the source of the reset side level shifter and the GND pad. Due to this difference, when negative voltage noise occurs, only one of the set side level shifter and the reset side level shifter may erroneously turn on, causing erroneous inversion of the output of the gate drive circuit.

[0008] In view of the above problems, an object of the present invention is to provide a semiconductor device capable of preventing malfunction of a gate drive circuit caused by negative voltage noise. [Means for solving the problem]

[0009] One aspect of the present invention is a gate drive circuit having a reference potential of a first potential applied to the pad, a set-side level shifter that converts a set signal having the first potential as a reference potential into a set signal having the second potential as a reference potential, and a reset-side level shifter that converts a reset signal having the first potential as a reference potential into a reset signal having the second potential as a reference potential, each of which has a plurality of high-potential side circuit areas that are different in distance to the pad, and (d) a pad and a set-side level shifter of the high-potential side circuit area that is the furthest from the pad. The semiconductor device according to the present invention comprises: (a) set side wiring that electrically connects the reset side level shifters in the high potential side circuit area furthest from the pad; and (b) a pad and reset side wiring that electrically connects the reset side level shifter in the high potential side circuit area furthest from the pad, wherein the set side level shifter in the high potential side circuit area located closer to the pad than the high potential side circuit area furthest from the pad is electrically connected to the pad via the set side wiring, and the reset side level shifter in the high potential side circuit area located closer to the pad than the high potential side circuit area furthest from the pad is electrically connected to the pad via the reset side wiring.

[0010] Another aspect of the present invention is a semiconductor device comprising: (a) a pad; (b) a control circuit having a reference potential equal to a first potential applied to the pad; (c) a gate drive circuit having a reference potential equal to a second potential which is a floating potential; a set-side level shifter that converts a set signal having the first potential as a reference potential into a set signal having the second potential as a reference potential; a reset-side level shifter that converts a reset signal having the first potential as a reference potential into a reset signal having the second potential as a reference potential; and an annular wiring that connects the set-side level shifter and the reset-side level shifter, the aforesaid high-potential side circuit areas each having a different distance to the pad; (d) a set-side wiring that electrically connects the pad and the set-side level shifters of the plurality of high-potential side circuit areas; and (e) a reset-side wiring that electrically connects the pad and the reset-side level shifters of the plurality of high-potential side circuit areas, the annular wiring of the high-potential side circuit area located closer to the pad being electrically connected to the set-side wiring and the reset-side wiring via the annular wiring of the high-potential side circuit area located farther from the pad. Effect of the Invention

[0011] According to the present invention, it is possible to provide a semiconductor device capable of preventing malfunction of a gate drive circuit due to negative voltage noise. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a plan view of a semiconductor device according to an embodiment of the present invention with a portion thereof omitted; [Diagram 3] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along the line BB in FIG. [Diagram 5] 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. [Figure 6] 1 is a table showing the relationship between the state of the level shifter and the gate drive output. [Figure 7]FIG. 1 is a plan view of a semiconductor device according to a comparative example. [Figure 8] FIG. 1 is a circuit diagram of a semiconductor device according to a comparative example. [Figure 9] 11 is a plan view showing a path of a noise current when -Vs noise occurs in a U phase of a semiconductor device according to a comparative example. FIG. [Figure 10] 11 is a circuit diagram showing a path of a noise current when -Vs noise occurs in a U phase of a semiconductor device according to a comparative example. [Figure 11] 13 is a graph showing a noise current when −Vs noise occurs in a U phase of the semiconductor device according to the comparative example. [Figure 12] 13 is a graph showing a gate-source voltage generated in a W-phase level shifter when −Vs noise occurs in a U-phase of a semiconductor device according to a comparative example. [Figure 13] FIG. 13 is another plan view of the semiconductor device according to the comparative example. [Figure 14] FIG. 11 is still another plan view of the semiconductor device according to the comparative example. [Figure 15] 1 is a plan view showing a path of a noise current when −Vs noise occurs in a U phase of a semiconductor device according to an embodiment of the present invention. [Figure 16] 1 is a plan view showing a path of a noise current when −Vs noise occurs in a W phase of a semiconductor device according to an embodiment of the present invention. FIG. [Figure 17] 1 is a plan view showing a path of a noise current when −Vs noise occurs in a W phase of a semiconductor device according to an embodiment of the present invention. FIG. [Figure 18] 11 is a graph showing a noise current when −Vs noise occurs in a W phase of the semiconductor device according to the embodiment of the present invention. [Figure 19] 11 is a graph showing a gate-source voltage generated in a U-phase level shifter when −Vs noise occurs in a W-phase of the semiconductor device according to the embodiment of the present invention. [Figure 20] 11 is a table showing GND wiring resistances of semiconductor devices according to embodiments of the present invention and comparative examples. [Figure 21] FIG. 2 is a plan view of a semiconductor device according to a first modified example of the embodiment of the present invention. [Figure 22]FIG. 11 is a plan view of a semiconductor device according to a second modified example of the embodiment of the present invention. [Figure 23] FIG. 11 is a plan view of a semiconductor device according to a third modified example of the embodiment of the present invention. [Figure 24] FIG. 11 is a plan view of a semiconductor device according to a fourth modified example of the embodiment of the present invention. [Diagram 25] FIG. 13 is a plan view of a semiconductor device according to a fifth modified example of the embodiment of the present invention. [Figure 26] FIG. 13 is a plan view of a semiconductor device according to a sixth modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention and its modified examples will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0014] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field effect transistor (FET) or a static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a static induction (SI) thyristor or a gate turn-off (GTO) thyristor, the anode region serves as the carrier supply region. In addition, the term "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET or a SIT, or the collector region of an IGBT. In an SI thyristor or a GTO thyristor, the cathode region functions as the carrier receiving region. In addition, the term "control electrode" refers to the gate electrode of a FET, a SIT, an IGBT, an SI thyristor, or a GTO thyristor, and has the function of controlling the flow of the main current flowing between the carrier supply region and the carrier receiving region.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0016] In the following description, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. The "+" and "-" attached to "n" and "p" respectively mean that the semiconductor region has a relatively high or low impurity concentration compared to the semiconductor region without the "+" and "-" attached. However, even if the semiconductor region has the same "n" and "n" attached, it does not mean that the impurity concentration of each semiconductor region is strictly the same. Furthermore, in the following description, the members and regions to which the "first conductivity type" and "second conductivity type" are added mean members and regions made of semiconductor materials even if there is no particular explicit limitation.

[0017] (Embodiment) <Configuration of Semiconductor Device> As a semiconductor device according to an embodiment of the present invention, an HVIC for driving a three-phase inverter will be described. As shown in Fig. 1, the semiconductor device according to the embodiment of the present invention includes high-potential side circuit regions 10u, 10v, and 10w for multiple phases (three phases), namely, U phase, V phase, and W phase, and a control circuit 5 which is a low-potential side circuit region, on the same semiconductor substrate (semiconductor chip) 1. As the semiconductor substrate 1, for example, a silicon (Si) substrate can be used.

[0018] The high-potential circuit regions 10u, 10v, and 10w of the U, V, and W phases are arranged in a line in the vertical direction of FIG. 1. The high-potential circuit region 10u of the U phase includes a gate drive circuit 6u, a ring-shaped high-voltage junction termination region (HVJT) 9u arranged around the gate drive circuit 6u, and a ring-shaped wiring (ring wiring) 8u arranged around the HVJT 9u. The gate drive circuit 6u operates based on the VS potential, which is a floating potential. The ring wiring 8u is configured by connecting a first wiring 8u1 electrically connected to the set-side level shifter 71 and a second wiring 8u2 electrically connected to the reset-side level shifter 72 to each other so as to surround the gate drive circuit 6u.

[0019] Furthermore, the U-phase high potential side circuit area 10u includes a level shifter (set side level shifter) 71 for transmitting a set signal and a level shifter (reset side level shifter) 72 for transmitting a reset signal, which are provided around the gate drive circuit 6u so as to be integrated with the HVJT 9u. The set side level shifter 71 and the reset side level shifter 72 are used to transmit signals in a two-input method for a set signal and a reset signal. The set side level shifter 71 and the reset side level shifter 72 are composed of, for example, high voltage n-channel MOSFETs. A carrier supply region (source region) 71s of the set side level shifter 71 and a source region 72s of the reset side level shifter 72 are connected to the annular wiring 8u. A carrier receiving region (drain region) 71d of the set side level shifter 71 and a drain region 72d of the reset side level shifter 72 are connected to the gate drive circuit 6u.

[0020] The V-phase high potential side circuit region 10v includes a gate drive circuit 6v, a ring-shaped HVJT 9v provided around the gate drive circuit 6v, and a ring-shaped wiring (ring wiring) 8v provided around the HVJT 9v. The gate drive circuit 6v operates based on the VS potential, which is a floating potential. The ring wiring 8v is configured by connecting a first wiring 8v1 electrically connected to the set side level shifter 73 and a second wiring 8v2 electrically connected to the reset side level shifter 74 to each other so as to surround the gate drive circuit 6v.

[0021] Furthermore, the V-phase high potential side circuit region 10v includes a set side level shifter 73 and a reset side level shifter 74 that are provided around the gate drive circuit 6v so as to be integrated with the HVJT 9v. The set side level shifter 73 and the reset side level shifter 74 are composed of, for example, high voltage n-channel MOSFETs. A source region 73s of the set side level shifter 73 and a source region 74s of the reset side level shifter 74 are connected to the annular wiring 8v. A drain region 73d of the set side level shifter 73 and a drain region 74d of the reset side level shifter 74 are connected to the gate drive circuit 6v.

[0022] The W-phase high potential side circuit region 10w includes a gate drive circuit 6w, a ring-shaped HVJT 9w provided around the gate drive circuit 6w, and a ring-shaped wiring (ring wiring) 8w provided around the HVJT 9w. The gate drive circuit 6w operates based on the VS potential, which is a floating potential. The ring wiring 8w is configured by connecting a first wiring 8w1 electrically connected to the set side level shifter 75 and a second wiring 8w2 electrically connected to the reset side level shifter 76 to each other so as to surround the gate drive circuit 6w.

[0023] Furthermore, the W-phase high potential side circuit region 10w includes a set side level shifter 75 and a reset side level shifter 76 that are provided around the gate drive circuit 6w so as to be integrated with the HVJT 9w. The set side level shifter 75 and the reset side level shifter 76 are, for example, configured of high voltage n-channel MOSFETs. A source region 75s of the set side level shifter 75 and a source region 76s of the reset side level shifter 76 are connected to the annular wiring 8w. A drain region 75d of the set side level shifter 75 and a drain region 76d of the reset side level shifter 76 are connected to the gate drive circuit 6w.

[0024] The control circuit 5 is disposed on the W-phase high potential side circuit area 10w side, which is an end of the arrangement of the U-phase, V-phase, and W-phase high potential side circuit areas 10u, 10v, and 10w. The control circuit 5 is disposed in a position among the U-phase, V-phase, and W-phase high potential side circuit areas 10u, 10v, and 10w, closest to the W-phase high potential side circuit area 10w and farthest from the U-phase high potential side circuit area 10u. The control circuit 5 operates based on a ground potential (GND potential) and controls the U-phase, V-phase, and W-phase high potential side circuit areas 10u, 10v, and 10w.

[0025] Around the control circuit 5, there are arranged a pad (GND pad) 2 to which the GND potential, which is the reference potential of the control circuit 5, pads (HIN pads) 3u, 3v, and 3w to which input signals HIN(U), HIN(V), and HIN(W) to the control circuit 5 are input, and a pad (VCC pad) 4 that is electrically connected to the power supply of the control circuit 5 and to which the VCC potential, which is the power supply potential of the control circuit 5, is applied.

[0026] The GND pad 2 is disposed in a position closest to the W-phase high potential side circuit region 10w and farthest from the U-phase high potential side circuit region 10u among the U-phase, V-phase, and W-phase high potential side circuit regions 10u, 10v, and 10w. The GND pad 2 is disposed in the lower right corner of the planar pattern of the semiconductor substrate 1. The GND pad 2 is connected to the control circuit 5 via wiring 20. One end of the set side wiring 21 and one end of the reset side wiring 22 are connected to the GND pad 2. The set side wiring 21 and the reset side wiring 22 are disposed in a layer above the annular wirings 8u, 8v, and 8w. The set side wiring 21 has a linear pattern and is disposed so as to extend along the right side of the semiconductor substrate 1. The other end of the set side wiring 21 is electrically connected to the annular wiring 8u in a layer below the set side wiring 21 via a contact 24.

[0027] On the other hand, the reset side wiring 22 has an L-shaped pattern, and has a portion extending along the lower side of the semiconductor substrate 1 and a portion extending along the left side of the semiconductor substrate 1. The other end of the reset side wiring 22 is electrically connected to the annular wiring 8u in a layer lower than the reset side wiring 22 via a contact 23. Since the GND pad 2 is located at the lower right corner of the planar pattern of the semiconductor substrate 1, the length of the reset side wiring 22 is longer than the length of the set side wiring 21.

[0028] A source region 71s of the set-side level shifter 71 of the U-phase is electrically connected to the GND pad 2 via the annular wiring 8u and the set-side wiring 21. A source region 72s of the reset-side level shifter 72 of the U-phase is electrically connected to the GND pad 2 via the annular wiring 8u and the reset-side wiring 22. That is, the set-side wiring 21 electrically connects the GND pad 2 and the set-side level shifter 71 of the high-potential side circuit area 10u that is the farthest from the GND pad 2. The reset-side wiring 22 electrically connects the GND pad 2 and the reset-side level shifter 72 of the high-potential side circuit area 10u that is the farthest from the GND pad 2.

[0029] The connection wiring 81 is arranged in a layer above the annular wiring 8u and the annular wiring 8v so as to overlap the region between the U-phase annular wiring 8u and the V-phase annular wiring 8v. The connection wiring 81 is arranged in the same wiring layer as the set side wiring 21 and the reset side wiring 22, for example. The annular wiring 8u is electrically connected to the connection wiring 81 via a contact 82. The annular wiring 8v is electrically connected to the connection wiring 81 via a contact 83. The connection wiring 81 is configured by connecting a first connection wiring 81a that electrically connects the first wiring 8u1, 8v1 of the U-phase and V-phase high potential side circuit areas 10u, 10v and a second connection wiring 81b that electrically connects the second wiring 8u2, 8v2 of the U-phase and V-phase high potential side circuit areas 10u, 10v.

[0030] A source region 73s of the V-phase set-side level shifter 73 is electrically connected to the GND pad 2 via the annular wiring 8v, the connection wiring 81, the annular wiring 8u, and the set-side wiring 21. A source region 74s of the V-phase reset-side level shifter 74 is electrically connected to the GND pad 2 via the annular wiring 8v, the connection wiring 81, the annular wiring 8u, and the reset-side wiring 22.

[0031] A connection wiring 84 is arranged in a layer above the annular wiring 8v and the annular wiring 8w so as to overlap the region between the V-phase annular wiring 8v and the W-phase annular wiring 8w. The connection wiring 84 is arranged in the same wiring layer as the connection wiring 81, the set side wiring 21, and the reset side wiring 22, for example. The annular wiring 8v is electrically connected to the connection wiring 84 via a contact 85. The annular wiring 8w is electrically connected to the connection wiring 84 via a contact 86. The connection wiring 84 is configured by connecting a first connection wiring 84a that electrically connects the first wiring 8v1, 8w1 of the V-phase and W-phase high-potential side circuit areas 10v, 10w, and a second connection wiring 84b that electrically connects the second wiring 8v2, 8w2 of the U-phase and V-phase high-potential side circuit areas 10v, 10w.

[0032] A source region 75s of the W-phase set-side level shifter 75 is electrically connected to the GND pad 2 via the annular wiring 8w, the connection wiring 84, the annular wiring 8v, the connection wiring 81, the annular wiring 8u, and the set-side wiring 21. A source region 76s of the W-phase reset-side level shifter 76 is electrically connected to the GND pad 2 via the annular wiring 8w, the connection wiring 84, the annular wiring 8v, the connection wiring 81, the annular wiring 8u, and the reset-side wiring 22.

[0033] That is, in the semiconductor device according to the embodiment of the present invention, the W-phase annular wiring 8w, which is relatively close to the GND pad 2, is electrically connected to the GND pad 2 via the U-phase annular wiring 8u and the V-phase annular wiring 8v, which are relatively far from the GND pad 2. Also, the V-phase annular wiring 8v, which is relatively close to the GND pad 2, is electrically connected to the GND pad 2 via the U-phase annular wiring 8u, which is relatively far from the GND pad 2. Then, the set-side level shifters 73 and 75 of the high-potential side circuit regions 10v and 10w, which are located closer to the GND pad 2 than the high-potential side circuit region 10u, which is the farthest from the GND pad 2, are electrically connected to the GND pad 2 via the set-side wiring 21. Also, the reset-side level shifters 74 and 76 of the high-potential side circuit regions 10v and 10w, which are located closer to the GND pad 2 than the high-potential side circuit region 10u, which is the farthest from the GND pad 2, are electrically connected to the GND pad 2 via the reset-side wiring 22.

[0034] 2 shows a planar layout in which the set side wiring 21, reset side wiring 22, connection wiring 81, and connection wiring 84 on the upper layer side shown in FIG. 1 are omitted, along with the contacts 23, 24, 82, 83, 85, and 86. One end of a VCC wiring 41 is connected to the VCC pad 4. The VCC wiring 41 is arranged in a lower layer than the set side wiring 21, reset side wiring 22, connection wiring 81, and connection wiring 84 shown in FIG. The VCC wiring 41 has an L-shaped planar pattern, and is arranged to extend along the left side of the semiconductor substrate 1.

[0035] Three VCC wires 42, 43, and 44 branch out from the VCC wire 41. The VCC wire 42 is disposed so as to extend between the U-phase annular wire 8u and the V-phase annular wire 8v. The VCC wire 43 is disposed so as to extend between the V-phase annular wire 8v and the W-phase annular wire 8w. The VCC wire 44 is disposed so as to extend between the W-phase annular wire 8w and the control circuit 5. Although not shown in FIG. 2, an n-type semiconductor region is provided in the semiconductor substrate 1 directly below the VCC wires 42 to 44, and is connected to the VCC wire and fixed to the VCC potential. This n-type semiconductor region can prevent a noise current that may cause destruction or malfunction from flowing to the high-potential side circuit regions 10u, 10v, and 10w of the adjacent phases or the control circuit 5 when negative voltage noise occurs. The VCC wires 41 to 44 may be omitted.

[0036] 3 shows a cross section seen from the AA direction including the reset-side level shifter 72 in FIG. 1. As shown in FIG. 3, the semiconductor device according to the embodiment of the present invention includes an n-type well region 11 provided in the upper part of a p-type semiconductor substrate 1. A p-type junction isolation region (slit region) 13 is provided in the n-type well region 11. The p-type junction isolation region 13 has a depth that penetrates the n-type well region 11 and reaches the p-type semiconductor substrate 1, and junction-isolates the n-type well region 11. An n-type junction isolation region 13 is provided in the upper part of the n-type well region 11 on the inner side of the p-type junction isolation region 13. + A mold pick-up area 16 is provided. + On the mold pick-up area 16, a pick-up electrode 112 is provided, which is connected to the VB terminal, which is the high potential power supply terminal of the gate drive circuit 6u.

[0037] The n-type well region 11 is in contact with the n-type well region 11. - A type voltage resistant region 12 is provided. - A p-type base region 14 is provided in contact with the breakdown voltage region 12. A p-type base region 14 having a higher impurity concentration than the p-type base region 14 is provided in the upper part of the p-type base region 14. + The n-type contact region 17 is provided in a ring shape. -Insulating films 101, 102, and 103 are provided on the p-type breakdown voltage region 12 and the p-type base region 14. As shown in FIG. - A high-voltage diode D1 is formed by the pn junction between the high-voltage region 12 and the p-type base region 14, and this high-voltage diode D1 constitutes the HVJT 9u shown in FIG.

[0038] The reset side level shifter 72, which is a high-voltage n-channel MOSFET, - The reset-side level shifter 72 is formed by forming a p-type transistor on the upper portion of the p-type base region 14. + The n-type contact region 17 is provided adjacent to the n-type contact region 17. + The source region 72s is + Type contact region 17 and n + On the source region 72s, + Type contact region 17 and n + A ring-shaped wiring 8u is provided as a source electrode in contact with the type source region 72s. A reset side wiring 22 is connected to the ring-shaped wiring 8u via a contact .

[0039] The reset side level shifter 72 is an n-type well region 11. + The n-type drain region 72d. + On the drain region 72d, + A drain electrode 104 is provided in contact with the p-type drain region 72d. A gate electrode 111 is provided on the p-type base region 14 between the drain electrode 104 and the circular wiring 8u serving as a source electrode, with a gate insulating film interposed therebetween.

[0040] A level shift resistor 113 made of polycrystalline silicon or the like is provided on the n-type well region 11 via an insulating film 101. A first electrode 114 and a second electrode 115 are provided on the upper surface sides of both ends of the level shift resistor 113. In FIG. 3, for convenience, the electrical connection between the pickup electrode 112 and the first electrode 114 is shown by a solid line, but the pickup electrode 112 and the first electrode 114 may be formed in the same wiring layer as the pickup electrode 112 and the first electrode 114 or in a different wiring layer, and may be connected to the pickup electrode 112 and the first electrode 114 via a via. In FIG. 3, for convenience, the electrical connection between the drain electrode 104 and the second electrode 115 is shown by a solid line, but the pickup electrode 112 and the first electrode 114 may be formed in the same wiring layer as the drain electrode 104 and the second electrode 115 or in a different wiring layer, and may be connected to the drain electrode 104 and the second electrode 115 via a via. The pickup electrode 112 is electrically connected to the drain region 72d of the reset side level shifter 72 via the level shift resistor 113. The structures of the set-side level shifters 71, 73, and 75 and the reset-side level shifters 74 and 76 shown in FIG. 1 are similar to the structure of the reset-side level shifter 72 shown in FIG.

[0041] 4 shows a cross section seen from the BB direction including the connection wiring 81 in FIG. 1. As shown on the right side of FIG. 4, the high potential side circuit region 10u includes an n-type well region 11 provided on the upper part of a p-type semiconductor substrate 1. + A mold pick-up area 15 is provided. + On the mold pick-up area 15, a pick-up electrode 116 is provided, which is connected to the VB terminal, which is the high potential power supply terminal of the gate drive circuit 6u.

[0042] The n-type well region 11 is in contact with the n-type well region 11. - A type voltage resistant region 12 is provided. - A p-type base region 14 is provided in contact with the breakdown voltage region 12. A p-type base region 14 having a higher impurity concentration than the p-type base region 14 is provided in the upper part of the p-type base region 14. + The contact region 17 is provided in an annular shape. + On the contact region 17,+ A circular wiring 8u is provided in contact with the mold contact region 17.

[0043] 4, the high-potential side circuit region 10v includes an n-type well region 11a provided on the upper portion of a p-type semiconductor substrate 1. + A mold pick-up area 15a is provided. + A pickup electrode 117 is provided on the mold pickup area 15a and is connected to the VB terminal, which is the high potential power supply terminal of the gate drive circuit 6v.

[0044] A n well having a lower impurity concentration than the n well region 11a is provided so as to be in contact with the n well region 11a. - Further, the n - A p-type base region 14a is provided in contact with the breakdown voltage region 12a. A p-type base region 14a having a higher impurity concentration than the p-type base region 14a is provided in the upper part of the p-type base region 14a. + The contact region 17a is provided in an annular shape. + On the contact region 17a, + A circular wiring 8v is provided in contact with the mold contact region 17a.

[0045] 4, an n-type semiconductor region 18 is provided between the n-type well regions 11 and 11a in the upper part of the p-type semiconductor substrate 1. An n-type semiconductor region 18 having a higher impurity concentration than the n-type semiconductor region 18 is provided above the n-type semiconductor region 18. + A contact region 19 is provided. + On the contact region 19, + 4. A VCC wiring 42 is provided in contact with the n-type contact region 19. The n-type semiconductor region 18 is fixed to the VCC potential via the VCC wiring 42. A connection wiring 81 is provided on the VCC wiring 42 with an insulating film 103 interposed therebetween. One end of the connection wiring 81 is connected to the annular wiring 8u via a contact 82, and the other end of the connection wiring 81 is connected to the annular wiring 8v via a contact 83. The structure around the connection wiring 84 shown in FIG. 1 is similar to the structure around the connection wiring 81 shown in FIG. 4.

[0046] 5 shows an equivalent circuit of a semiconductor device according to an embodiment of the present invention. The gates of the set-side level shifter 71 and the reset-side level shifter 72 of the U phase are connected to the control circuit 5. The drain of the set-side level shifter 71 is connected to a level shift resistor r1 and a gate drive circuit 6u. The source of the set-side level shifter 71 is connected to a GND pad 2 via a wiring resistor Rsetu. The drain of the reset-side level shifter 72 is connected to a level shift resistor r2 and a gate drive circuit 6u. The source of the reset-side level shifter 72 is connected to a GND pad 2 via a wiring resistor Rrstu. The high potential (VB potential) side of the power supply 61 is connected to the level shift resistors r1 and r2. The high potential (VB potential) side and the low potential (VS potential) side of the power supply 61 are connected to the gate drive circuit 6u.

[0047] The gates of the V-phase set side level shifter 73 and reset side level shifter 74 are connected to the control circuit 5. The drain of the set side level shifter 73 is connected to a level shift resistor r3 and a gate drive circuit 6v. The source of the set side level shifter 73 is connected to a GND pad 2 via wiring resistors Rsetuv and Rsetu. The drain of the reset side level shifter 74 is connected to a level shift resistor r4 and a gate drive circuit 6v. The source of the reset side level shifter 74 is connected to a GND pad 2 via wiring resistors Rrstuv and Rrstu. The high potential (VB potential) side of the power supply 62 is connected to the level shift resistors r3 and r4. The high potential (VB potential) side and low potential (VS potential) side of the power supply 62 are connected to the gate drive circuit 6v.

[0048] The gates of the W-phase set-side level shifter 75 and reset-side level shifter 76 are connected to the control circuit 5. The drain of the set-side level shifter 75 is connected to a level shift resistor r5 and a gate drive circuit 6w. The source of the set-side level shifter 75 is connected to a GND pad 2 via wiring resistors Rsetvw, Rsetuv, and Rsetu. The drain of the reset-side level shifter 76 is connected to a level shift resistor r6 and a gate drive circuit 6w. The source of the reset-side level shifter 76 is connected to a GND pad 2 via wiring resistors Rrstvw, Rrstuv, and Rrstu. The high potential (VB potential) side of the power supply 63 is connected to the level shift resistors r5 and r6. The high potential (VB potential) side and low potential (VS potential) side of the power supply 63 are connected to the gate drive circuit 6w.

[0049] Next, referring to FIG. 5, an example of the switching operation of the semiconductor device according to the embodiment of the present invention will be described with a focus on the U phase. When the input signal HIN(U) input to the control circuit 5 changes from a low (L) level to a high (H) level, the control circuit 5 turns on the set-side level shifter 71 for a certain time and transmits a set signal SET based on the GND potential to the set-side level shifter 71. The set-side level shifter 71 converts the set signal SET based on the GND potential from the control circuit 5 to a set signal SET based on the VS potential, which is a floating potential, and transmits it to the gate drive circuit 6u. The gate drive circuit 6u changes the output HO(U) of the gate drive circuit 6u from the L level to the H level in response to the set signal SET based on the VS potential from the set-side level shifter 71. The output HO(U) of the gate drive circuit 6u drives the gate of a semiconductor power switching element such as an IGBT. This semiconductor power switching element is an element arranged on the higher potential side of two elements connected in series between the power supply and ground of the three-phase inverter.

[0050] On the other hand, when the input signal HIN(U) input to the control circuit 5 changes from H level to L level, the control circuit 5 turns on the reset-side level shifter 72 for a certain time and transmits a reset signal RST based on the GND potential to the reset-side level shifter 72. The reset-side level shifter 72 converts the reset signal RST based on the GND potential from the control circuit 5 to a reset signal RST based on the VS potential and transmits it to the gate drive circuit 6u. The gate drive circuit 6u changes the output HO(U) of the gate drive circuit 6u from H level to L level in response to the reset signal RST based on the VS potential from the reset-side level shifter 72. The switching operations of the V phase and W phase are similar to that of the U phase.

[0051] 6 shows the relationship between the states of the set-side level shifters 71, 73, 75 and the reset-side level shifters 72, 74, 76 and the outputs of the gate drive circuits 6u, 6v, 6w. State A is when the set-side level shifters 71, 73, 75 and the reset-side level shifters 72, 74, 76 are all off, and the outputs of the gate drive circuits 6u, 6v, 6w are unchanged. State B is when the set-side level shifters 71, 73, 75 are off and the reset-side level shifters 72, 74, 76 are on, and the gate drive circuits 6u, 6v, 6w are turned off. State C is when the set-side level shifters 71, 73, 75 are on and the reset-side level shifters 72, 74, 76 are off, and the gate drive circuits 6u, 6v, 6w are turned on. In state D, the set-side level shifters 71, 73, and 75 and the reset-side level shifters 72, 74, and 76 are all on, and the outputs of the gate drive circuits 6u, 6v, and 6w are unchanged.

[0052] <Comparative Example> Next, a semiconductor device according to a comparative example will be described. As shown in Fig. 7, the semiconductor device according to the comparative example is different from the semiconductor device according to the embodiment of the present invention shown in Fig. 1 in that the set side wiring 21 is connected to the annular wirings 8v, 8w via contacts 122, 124, and the reset side wiring 22 is connected to the annular wirings 8v, 8w via contacts 121, 123. Furthermore, the semiconductor device according to the comparative example is different from the semiconductor device according to the embodiment of the present invention shown in Fig. 1 in that it does not have the connection wirings 81, 84 for connecting the annular wirings 8u, 8v, 8w to each other.

[0053] 8 shows an equivalent circuit of a semiconductor device according to a comparative example. In the semiconductor device according to the comparative example, the source of the set side level shifter 75 of the W phase is connected to the GND pad 2 via a wiring resistance Rsetw. The source of the reset side level shifter 76 of the W phase is connected to the GND pad 2 via a wiring resistance Rrstw. As shown in FIG. 7, the lengths of the set side wiring 21 and the reset side wiring 22 from the GND pad 2 to the set side level shifter 75 and the reset side level shifter 76 of the W phase are different from each other, so the difference between the wiring resistances Rsetw and Rrstw shown in FIG. 8 becomes large.

[0054] The source of the V-phase set side level shifter 73 is connected to the GND pad 2 via wiring resistances Rsetw and Rsetvw. The source of the V-phase reset side level shifter 74 is connected to the GND pad 2 via wiring resistances Rrstw and Rrstvw. The source of the U-phase set side level shifter 71 is connected to the GND pad 2 via wiring resistances Rsetw, Rsetvw, and Rsetuv. The source of the W-phase reset side level shifter 72 is connected to the GND pad 2 via wiring resistances Rrstw, Rrstvw, and Rrstuv.

[0055] In the semiconductor device according to the comparative example, a negative voltage noise called -Vs noise occurs in the VS terminal of each phase due to switching of the semiconductor power switching element. For example, as shown in Fig. 9 and Fig. 10, when -Vs noise occurs in the U phase, the high voltage diode constituting the HVJT 9u of the U phase becomes forward biased, and a noise current flows from the GND pad 2 to the Vs terminal. In Fig. 9 and Fig. 10, the noise current is indicated by a dashed line with an arrow. As shown in Fig. 9, the noise current flows through the set side wiring 21, the reset side wiring 22, and the annular wirings 8u, 8v, and 8w, but since the set side wiring 21, the reset side wiring 22, and the annular wirings 8u, 8v, and 8w have wiring resistances R0 to R12, a voltage drop occurs in the set side wiring 21, the reset side wiring 22, and the annular wirings 8u, 8v, and 8w. Due to the voltage drop in the set side wiring 21, the reset side wiring 22, and the circular wiring 8u, 8v, and 8w, the source potentials of the W-phase set side level shifter 73 and reset side level shifter 74 and the source potentials of the V-phase set side level shifter 75 and reset side level shifter 76 become lower than the potential of the GND pad 2.

[0056] For example, if the noise current is Is, the wiring resistance from the GND pad 2 to the source of the W-phase set-side level shifter 73 is Rsetw, and the wiring resistance from the GND pad 2 to the source of the W-phase reset-side level shifter 74 is Rrstw, a voltage drop of Is×Rsetw occurs at the source of the W-phase set-side level shifter 73, and Is×Rrstw occurs at the source of the reset-side level shifter 74. The wiring resistances Rsetw and Rrstw are the combined resistance of the wiring resistances R0 to R12 shown in FIG. 9, and are mainly determined by the resistance values ​​of the wiring resistances R0 to R4.

[0057] On the other hand, the gate potential of the W-phase set-side level shifter 73 and reset-side level shifter 74 is the GND potential except when the set-side level shifter 73 and reset-side level shifter 74 are driven. Therefore, due to a drop in the source potential of the W-phase set-side level shifter 73 and reset-side level shifter 74, a positive voltage is applied between the gate and source of the set-side level shifter 73 and reset-side level shifter 74. If this voltage exceeds the threshold voltage of the set-side level shifter 73 and reset-side level shifter 74, unintended turn-on of the set-side level shifter 73 and reset-side level shifter 74 occurs.

[0058] In order to prevent such malfunction of the set side level shifters 71, 73, 75 and the reset side level shifters 72, 74, 76, the gate drive circuit 5 is configured not to change the output when the set signal and the reset signal are input simultaneously, as shown in states A and D in Fig. 6. Therefore, if the wiring resistance between the set side level shifters 71, 73, 75 and the GND pad 2 is the same as the wiring resistance between the reset side level shifters 72, 74, 76 and the GND pad 2, the set side level shifters 71, 73, 75 and the reset side level shifters 72, 74, 76 will be erroneously turned on simultaneously due to -Vs noise, and the output of the gate drive circuit will not change as in state D shown in Fig. 6.

[0059] However, in the semiconductor device according to the comparative example, there is a difference between the wiring resistance between the set side level shifters 71, 73, 75 and the GND pad 2 and the wiring resistance between the reset side level shifters 72, 74, 76 and the GND pad 2. As shown in FIG. 9, the reset side wiring 22 is larger than the set side wiring 21 by the wiring resistance R0. For example, if R0=0.86Ω, R1=R2=0.71Ω, R3=R4=R7=R8=R11=R12=0.47Ω, and R5=R6=R9=R10=0.34Ω, the wiring resistance Rsetw from the GND pad 2 to the source of the W-phase set side level shifter 75 is about 0.51Ω, and the wiring resistance Rrstw from the GND pad 2 to the source of the W-phase reset side level shifter 76 is about 0.57Ω.

[0060] If the threshold voltages of the set-side level shifter 75 and the reset-side level shifter 76 are, for example, 1.5 V, a noise current of about 2.6 A or more applies a voltage of 1.5 V or more between the gate and source of the reset-side level shifter 76, causing the reset-side level shifter 76 to erroneously fire. On the other hand, the set-side level shifter 75 causes erroneous firing due to a noise current of about 3.0 A or more. Therefore, when a noise current of about 2.6 A to 3.0 A flows, only the reset-side level shifter 76 erroneously fires. If the period during which only the reset-side level shifter 76 erroneously fires exceeds the filter period, the gate drive circuit 6w malfunctions.

[0061] Fig. 11 shows a noise current when -Vs noise occurs in the U phase of the semiconductor device according to the comparative example, and Fig. 12 shows a gate-source voltage generated in the set-side level shifter 75 and the reset-side level shifter 76 of the W phase when -Vs noise occurs in the U phase of the semiconductor device according to the comparative example. As shown in Fig. 12, in the semiconductor device according to the comparative example, the voltage difference between the set-side level shifter 75 and the reset-side level shifter 76 is large, so that the gate drive circuit 6w is likely to malfunction.

[0062] 13, it is considered that the wiring resistance between the set-side level shifters 71, 73, 75 and the GND pad 2 and the wiring resistance between the reset-side level shifters 72, 74, 76 and the GND pad 2 are made equal to each other by arranging the GND pad 2 at the center in the left-right direction of the semiconductor substrate 1 as shown in FIG. 14, it is considered that the wiring resistance between the set-side level shifters 71, 73, 75 and the GND pad 2 and the wiring resistance between the reset-side level shifters 72, 74, 76 and the GND pad 2 are made equal to each other by connecting one GND wiring 120 to the GND pad 2 and extending the GND wiring 120 to the center in the left-right direction of the semiconductor substrate 1 and connecting it to the set-side wiring 21 and the reset-side wiring 22 as shown in FIG.

[0063] However, due to reasons of mounting and layout of the control circuit 5, it is difficult to realize the planar layout as shown in Fig. 13 and Fig. 14, and generally, a difference occurs between the wiring resistance between the set side level shifters 71, 73, 75 and the GND pad 2 and the wiring resistance between the reset side level shifters 72, 74, 76 and the GND pad 2. Due to this difference, when -Vs noise occurs, only one of the set side level shifters 71, 73, 75 and the reset side level shifters 72, 74, 76 is erroneously turned on, resulting in state B or state C shown in Fig. 6, and the outputs of the gate drive circuits 6u, 6v, 6w are erroneously inverted. This problem is prominent in the W phase close to the GND pad 2.

[0064] <Effects of the semiconductor device> 1, the V-phase and W-phase annular wirings 8v and 8w, which are relatively close to the GND pad 2, are electrically connected to the GND pad 2 via the U-phase annular wiring 8u, which is relatively far from the GND pad 2, so that the wiring paths between the V-phase and W-phase annular wirings 8v and 8w and the GND pad 2 are extended by the same distance. As a result, like the semiconductor device according to the comparative example, even though the GND pad 2 is located asymmetrically with respect to the set side and reset side, the ratio Rset / Rrst of the wiring resistance Rset from the source of the set-side level shifters 73 and 75 of the V-phase and W-phase to the wiring resistance Rrst from the source of the reset-side level shifters 74 and 76 to the GND pad 2 can be made closer to 1 than in the semiconductor device according to the comparative example.

[0065] Next, referring to Fig. 15, a case where -Vs noise is applied to the U phase in the semiconductor device according to the embodiment of the present invention will be described. In Fig. 15, the noise current path when -Vs noise is applied to the U phase is shown by a dashed line with an arrow. Also, the wiring resistances R0 to R12 of the set side wiring 21, the reset side wiring 22, and the annular wirings 8u, 8v, and 8w are shown. When -Vs noise is applied to the U phase, the noise current flows through the set side wiring 21, the reset side wiring 22, and the annular wirings 8u, 8v, and 8w, and a voltage drop occurs in the set side wiring 21, the reset side wiring 22, and the annular wirings 8u, 8v, and 8w.

[0066] However, most of the noise current flows through the U-phase annular wiring 8u, and the noise current flowing through the V-phase and W-phase annular wirings 8v, 8w is small, so there is no large difference between the amount of drop in source potential of the set-side level shifters 73, 75 and reset-side level shifters 74, 76 for the V-phase and W-phase on the set side and the reset side. Therefore, even if erroneous firing occurs in the set-side level shifters 73, 75 and reset-side level shifters 74, 76 for the V-phase and W-phase, the set-side and reset-side level shifters turn on simultaneously, resulting in state D4 in FIG. 6, and erroneous inversion of the output of the gate drive circuit 6 does not occur.

[0067] Furthermore, since the set side level shifter 71 and reset side level shifter 72 of the U phase are in a reverse bias state while the -Vs noise is being applied, even if a voltage equal to or greater than the threshold voltage is applied between the gate and source due to a voltage drop in the set side wiring 21, the reset side wiring 22, and the annular wiring 8u, no signal is transmitted and erroneous inversion of the output of the gate drive circuit 6 does not occur.

[0068] Next, referring to Fig. 16 and Fig. 17, a case where -Vs noise is applied to the W phase in the semiconductor device according to the embodiment of the present invention will be described. In Fig. 16 and Fig. 17, the noise current path when -Vs noise is applied to the W phase is shown by a dashed line with an arrow. As shown in Fig. 16, when -Vs noise is applied to the W phase, the noise current flows through the set side wiring 21, the reset side wiring 22, and the annular wiring 8u connecting the GND pad 2 and the set side level shifter 71 and the reset side level shifter 72 of the U phase, and flows into the W phase via the connection wiring 81, the annular wiring 8v, the connection wiring 84, and the annular wiring 8w connecting the V phase and the W phase. This noise current causes a voltage drop in the set side wiring 21, the reset side wiring 22, the annular wiring 8u, the connection wiring 81, the annular wiring 8v, the connection wiring 84, and the annular wiring 8w, which may cause erroneous firing of the set side level shifters 71, 73 and the reset side level shifters 72, 74 of the U phase and the V phase.

[0069] Here, in the semiconductor device according to the comparative example, the wiring resistance ratio Rrst / Rset between the set side level shifter 75 and the reset side level shifter 76 of the W phase among the U phase, V phase, and W phase is the largest, and erroneous inversion of the output of the gate drive circuit 6w is likely to occur due to erroneous firing of the set side level shifter 75 and the reset side level shifter 76. On the other hand, in the semiconductor device according to the embodiment of the present invention, the wiring resistance ratio Rrst / Rset between the set side level shifter 71 and the reset side level shifter 72 of the U phase is the largest among the U phase, V phase, and W phase. However, the wiring resistance ratio Rrst / Rset between the set side level shifter 71 and the reset side level shifter 72 of the U phase of the semiconductor device according to the embodiment of the present invention is closer to 1 than the wiring resistance ratio Rrst / Rset between the set side level shifter 75 and the reset side level shifter 76 of the W phase of the semiconductor device according to the comparative example.

[0070] Fig. 18 shows a noise current when -Vs noise occurs in the W phase of the semiconductor device according to the embodiment of the present invention, and Fig. 19 shows a gate-source voltage generated in the set side level shifter 71 and reset side level shifter 72 of the U phase when -Vs noise occurs in the W phase of the semiconductor device according to the embodiment of the present invention. As shown in Fig. 19, in the semiconductor device according to the embodiment of the present invention, the voltage difference between the set side level shifter 71 and the reset side level shifter 72 is smaller than the voltage difference between the set side level shifter 75 and the reset side level shifter 76 of the W phase in the semiconductor device according to the comparative example shown in Fig. 12, and erroneous inversion of the output of the gate drive circuit 6u can be prevented.

[0071] FIG. 20 shows a detailed comparison of the GND wiring resistance in the semiconductor device according to the embodiment of the present invention (labeled as "present invention" in FIG. 20) and the semiconductor device according to the comparative example (labeled as "conventional structure" in FIG. 20). In the semiconductor device according to the comparative example, the resistance ratio of the set side to the reset side of the wiring resistance between the GND pad and the level shifter is the largest at 1.126 in the W phase of the three phases, and the difference in the source voltage drop amount is large at 0.168V. In contrast, in the semiconductor device according to the embodiment of the present invention, the resistance ratio of the set side to the reset side of the wiring resistance between the GND pad and the level shifter is the largest at 1.024 in the U phase of the three phases, but this is smaller than the resistance ratio of the W phase of the semiconductor device according to the comparative example, and the difference in the source voltage drop amount is 0.034V, which is smaller than the difference in the W phase of the semiconductor device according to the comparative example.

[0072] <First Modification> The semiconductor device according to the first modified example of the embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention shown in Fig. 1 in that the set-side level shifters 71, 73, 75 and reset-side level shifters 72, 74, 76 for the U, V, and W phases are arranged in the vertical direction of the paper as shown in Fig. 21. Other configurations of the semiconductor device according to the first modified example of the embodiment of the present invention are similar to those of the semiconductor device according to the embodiment of the present invention, so duplicated explanations will be omitted.

[0073] According to the semiconductor device of the first modified embodiment of the present invention, the positions of the set side level shifters 71, 73, 75 and reset side level shifters 72, 74, 76 for the U phase, V phase, and W phase are not particularly limited. For example, even if the set side level shifters 71, 73, 75 and reset side level shifters 72, 74, 76 for the U phase, V phase, and W phase are arranged in the vertical direction of the paper, the same effect as that of the semiconductor device of the embodiment of the present invention is achieved.

[0074] <Second Modification> As shown in Fig. 22, the semiconductor device according to the second modification of the embodiment of the present invention is different from the semiconductor device according to the embodiment of the present invention shown in Fig. 1 in that the set side wiring 21 is arranged in a lower layer than the reset side wiring 22. The set side wiring 21 is arranged in the same wiring layer as the annular wirings 8u, 8v, 8w, and is spaced apart from the annular wirings 8u, 8v, 8w. The set side wiring 21 is connected to the connection wiring 25 in a layer above the set side wiring 21 via a contact 26. The connection wiring 25 is connected to the annular wiring 8u via a contact 24. The other configurations of the semiconductor device according to the second modification of the embodiment of the present invention are the same as those of the semiconductor device according to the embodiment of the present invention, so that repeated explanations will be omitted.

[0075] According to the semiconductor device of the second modified example of the embodiment of the present invention, even if the set side wiring 21 is arranged in a lower layer than the reset side wiring 22, the set side wiring 21 can be connected to the annular wiring 8u via the connection wiring 25, thereby achieving the same effect as the semiconductor device of the embodiment of the present invention.

[0076] <Third Modification> As shown in Fig. 23, the semiconductor device according to the third modification of the embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention shown in Fig. 1 in that it does not have VCC wirings 41-44. Furthermore, the semiconductor device according to the third modification of the embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention in that the set side wiring 21 and the reset side wiring 22 are arranged in the same wiring layer as the annular wirings 8u, 8v, and 8w.

[0077] The set side wiring 21 is disposed at a distance from the annular wirings 8u, 8v, and 8w. The set side wiring 21 is connected to a connection wiring 25 in a layer above the set side wiring 21 via a contact 26. The connection wiring 25 is connected to the annular wiring 8u via a contact 24. The reset side wiring 22 is disposed at a distance from the annular wirings 8u, 8v, and 8w. The reset side wiring 22 is connected to a connection wiring 27 in a layer above the set side wiring 22 via a contact 28. The connection wiring 27 is connected to the annular wiring 8u via a contact 23. Other configurations of the semiconductor device according to the third modified example of the embodiment of the present invention are similar to those of the semiconductor device according to the embodiment of the present invention, and therefore, repeated explanations will be omitted.

[0078] According to the semiconductor device of the third modified example of the embodiment of the present invention, even if there are no VCC wirings 41-44 and the set side wiring 21 and the reset side wiring 22 are arranged in the same wiring layer as the annular wirings 8u, 8v, and 8w, the set side wiring 21 and the reset side wiring 22 can be connected to the annular wiring 8u via the connection wirings 25 and 27, thereby achieving the same effect as the semiconductor device of the embodiment of the present invention.

[0079] <Fourth Modification> As shown in Fig. 24, the semiconductor device according to the fourth modification of the embodiment of the present invention is common to the semiconductor device according to the third modification shown in Fig. 23 in that there are no VCC wirings 41-44 and the set side wiring 21 and the reset side wiring 22 are arranged in the same wiring layer as the annular wirings 8u, 8v, and 8w. However, the semiconductor device according to the fourth modification of the embodiment of the present invention is different from the semiconductor device according to the third modification in that the set side wiring 21 and the reset side wiring 22 are directly in contact with the annular wiring 8u without using the connection wirings 25 and 27. For example, in Fig. 24, the ends of the set side wiring 21 and the reset side wiring 22 are extended toward the annular wiring 8u, so that the set side wiring 21 and the reset side wiring 22 are directly in contact with the annular wiring 8u.

[0080] Furthermore, the semiconductor device according to the fourth modified example of the embodiment of the present invention differs from the semiconductor device according to the third modified example shown in FIG. 23 in that the U-phase, V-phase, and W-phase annular wirings 8u, 8v, and 8w are in direct contact with each other.

[0081] Furthermore, the connection wirings 81, 84 are arranged above the annular wirings 8u, 8v, 8w so as to overlap the portions where the annular wirings 8u, 8v, 8w of the U phase, V phase, and W phase are in direct contact with each other. The annular wirings 8u, 8v are connected to the connection wiring 81 via contacts 82, 83. The annular wirings 8v, 8w are connected to the connection wiring 84 via contacts 85, 86. By arranging the connection wirings 81, 84, it is possible to reduce the wiring resistance. It is also possible that the connection wirings 81, 84 are not provided and the annular wirings 8u, 8v, 8w are simply directly connected to each other. The other configurations of the semiconductor device according to the fourth modification of the embodiment of the present invention are the same as those of the semiconductor device according to the embodiment of the present invention, and therefore a duplicated description will be omitted.

[0082] According to the semiconductor device of the fourth modified example of the embodiment of the present invention, even when the set side wiring 21 and the reset side wiring 22 are in direct contact with the annular wiring 8u, or when the annular wirings 8u, 8v, and 8w are in direct contact with each other, the same effects as those of the semiconductor device of the embodiment of the present invention are achieved.

[0083] <Fifth Modification> As shown in FIG. 25, a semiconductor device according to a fifth modified embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention shown in FIG. 1 in that first wirings 8u1, 8v1, 8w1 electrically connected to set side level shifters 71, 73, 75 of the high potential side circuit areas 10u, 10v, 10w of the U phase, V phase, and W phase, and second wirings 8u2, 8v2, 8w2 electrically connected to reset side level shifters 72, 74, 76 are separated from each other.

[0084] 25, the p-type base region 14 provided in the semiconductor substrate 1 and the n-type semiconductor regions 18, 18a, and 18b provided in the semiconductor substrate 1 and located directly below the VCC wirings 42, 43, and 44 are shown by dashed lines. The VCC wirings 42, 43, and 44 are electrically connected to the n-type semiconductor regions 18, 18a, and 18b via contacts 42a, 43a, and 44a.

[0085] The first wirings 8u1, 8v1 of the adjacent U-phase and V-phase high potential side circuit areas 10u, 10v are spaced apart from each other, and the second wirings 8u2, 8v2 are spaced apart from each other. The first wirings 8v1, 8w1 of the adjacent V-phase and W-phase high potential side circuit areas 10v, 10w are spaced apart from each other, and the second wirings 8v2, 8w2 are spaced apart from each other.

[0086] The first wiring 8w1 of the W-phase high potential side circuit area 10w located closer to the GND pad 2 is electrically connected to the set side wiring 21 via the first wiring 8v1 of the V-phase high potential side circuit area 10v located farther from the GND pad 2. The second wiring 8w2 of the W-phase high potential side circuit area 10w located closer to the GND pad 2 is electrically connected to the reset side wiring 22 via the second wiring 8v2 of the V-phase high potential side circuit area 10v located farther from the GND pad 2.

[0087] The first wiring 8v1 of the V-phase high potential side circuit area 10v located closer to the GND pad 2 is electrically connected to the set side wiring 21 via the first wiring 8u1 of the U-phase high potential side circuit area 10u located farther from the GND pad 2. The second wiring 8v2 of the V-phase high potential side circuit area 10v located closer to the GND pad 2 is electrically connected to the reset side wiring 22 via the second wiring 8u2 of the U-phase high potential side circuit area 10u located farther from the GND pad 2.

[0088] Furthermore, the semiconductor device according to the fifth modified example of the embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention shown in FIG. 1 in that the first connection wirings 81a, 84a electrically connecting the first wirings 8u1, 8v1, 8w1 of the high potential side circuit areas 10u, 10v, 10w of the U phase, V phase, and W phase, and the second connection wirings 84a, 84b electrically connecting the second wirings 8u2, 8v2, 8w2 of the high potential side circuit areas 10u, 10v, 10w of the U phase, V phase, and W phase are separated from each other.

[0089] The first connection wiring 81a, 84a and the second connection wiring 81b, 94b are wirings in a layer above the first wiring 8u1, 8v1, 8w1 and the second wiring 8u2, 8v2, 8w2 of the U-phase, V-phase, and W-phase high-potential side circuit areas 10u, 10v, and 10w, respectively. The first connection wiring 81a electrically connects the first wiring 8u1, 8v1 of the adjacent U-phase and V-phase high-potential side circuit areas 10u, 10v to each other via contacts 82a and 83a. The second connection wiring 81b electrically connects the second wiring 8u2, 8v2 of the U-phase and V-phase high-potential side circuit areas 10u, 10v to each other via contacts 82b and 83b.

[0090] The first connection wiring 84a electrically connects the first wirings 8v1, 8w1 of the adjacent V-phase and W-phase high potential side circuit regions 10v, 10w via contacts 85a, 86a. The second connection wiring 84b electrically connects the second wirings 8v2, 8w2 of the adjacent V-phase and W-phase high potential side circuit regions 10v, 10w via contacts 85b, 86b. Other configurations of the semiconductor device according to the fifth modified example of the embodiment of the present invention are similar to those of the semiconductor device according to the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0091] According to the semiconductor device of the fifth modified example of the embodiment of the present invention, even if the first wirings 8u1, 8v1, 8w1 electrically connected to the set side level shifters 71, 73, 75 and the second wirings 8u2, 8v2, 8w2 electrically connected to the reset side level shifters 72, 74, 76 are separated from each other, and the first connection wirings 81a, 84a electrically connecting the first wirings 8u1, 8v1, 8w1 in the high potential side circuit areas 10u, 10v, 10w of the U phase, V phase, and W phase and the second connection wirings 84a, 84b electrically connecting the second wirings 8u2, 8v2, 8w2 in the high potential side circuit areas 10u, 10v, 10w of the U phase, V phase, and W phase are separated from each other, the same effects as those of the semiconductor device of the embodiment of the present invention are achieved.

[0092] <Sixth Modification> A semiconductor device according to the sixth modified example of the embodiment of the present invention has in common with the semiconductor device according to the fifth modified example of the embodiment of the present invention shown in FIG. 25 in that, as shown in FIG. 26, first wirings 8u1, 8v1, 8w1 electrically connected to set side level shifters 71, 73, 75 of the high potential side circuit areas 10u, 10v, 10w of the U phase, V phase, and W phase, and second wirings 8u2, 8v2, 8w2 electrically connected to reset side level shifters 72, 74, 76 are separated from each other.

[0093] However, the semiconductor device according to the sixth modified example of the embodiment of the present invention differs from the semiconductor device according to the fifth modified example of the embodiment of the present invention shown in FIG. 25 in that a first connection wiring electrically connecting the first wirings 8u1, 8v1, 8w1 of the same high potential side circuit areas 10u, 10v, 10w and a second connection wiring electrically connecting the second wirings 8u2, 8v2, 8w2 of the same high potential side circuit areas 10u, 10v, 10w are connected to form connection wirings 81, 84.

[0094] 26, similarly to FIG. 25, the p-type base region 14 and the n-type semiconductor regions 18, 18a, and 18b directly below the VCC wirings 42, 43, and 44 are shown by dashed lines. The VCC wirings 42, 43, and 44 are electrically connected to the n-type semiconductor regions 18, 18a, and 18b via contacts (not shown). Other configurations of the semiconductor device according to the sixth modified example of the embodiment of the present invention are similar to those of the semiconductor device according to the fifth modified example of the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0095] According to the semiconductor device of the sixth modified example of the embodiment of the present invention, even when the first wirings 8u1, 8v1, 8w1 electrically connected to the set side level shifters 71, 73, 75 and the second wirings 8u2, 8v2, 8w2 electrically connected to the reset side level shifters 72, 74, 76 are spaced apart from each other, and the first connection wirings electrically connecting the first wirings 8u1, 8v1, 8w1 of the same high potential side circuit areas 10u, 10v, 10w and the second connection wirings electrically connecting the second wirings 8u2, 8v2, 8w2 of the same high potential side circuit areas 10u, 10v, 10w are connected to form the connection wirings 81, 84, the same effects as those of the semiconductor device of the embodiment of the present invention are achieved.

[0096] (Other embodiments) As described above, the present invention has been described by the embodiment and its modified examples, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art from this disclosure.

[0097] For example, the configurations disclosed in the embodiments and the modifications of the present invention may be appropriately combined within a range that does not cause a contradiction. For example, in each of the semiconductor device according to the embodiment of the present invention and the semiconductor device according to the first to fourth modifications of the embodiment of the present invention, the annular wirings 8u, 8v, 8w may be replaced with first wirings 8u1, 8v1, 8w1 and second wirings 8u2, 8v2, 8w2 spaced apart from each other, as in the semiconductor device according to the fifth and sixth modifications of the embodiment of the present invention.

[0098] 1, the GND pad 2 is disposed at the right corner of the semiconductor substrate 1, but the position of the GND pad 2 is not particularly limited. For example, the GND pad 2 may be disposed at the left corner of the semiconductor substrate 1, and the length of the set side wiring 21 may be shorter than the length of the reset side wiring 22.

[0099] In the embodiment of the present invention, a Si substrate is used as the semiconductor substrate 1, but the present invention is also applicable to a case where a semiconductor material (wide band gap semiconductor) having a wider band gap than Si, such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN), is used in addition to Si.

[0100] Although the semiconductor device according to the embodiment of the present invention is an HVIC, the present invention is also applicable to semiconductor devices other than HVIC, and is particularly effective in semiconductor devices to which a high voltage of several tens of volts or more is applied. [Explanation of symbols]

[0101] 1...Semiconductor substrate (semiconductor chip) 2...GND pad 3u, 3v, 3w...input pad 4…VCC pad 5...Control circuit 6u, 6v, 6w...Gate drive circuit 8u, 8v, 8w...Circular wiring 8u1,8v1,8w1…1st wiring 8u2, 8v2, 8w2...Second wiring 9u, 9v, 9w...High voltage junction termination area 10u, 10v, 10w…High potential side circuit area 11, 11a...n-type well region 12,12a…n - Mold pressure range 13...p-type junction isolation region (slit region) 14, 14a...p-type base region 15, 15a, 16...Pickup area 17, 17a, 19…Contact area 18, 18a, 18b...n-type semiconductor region 20…Wiring 21…Set side wiring 22…Reset side wiring 23,24,26,28…Contact 25,27…Connection wiring 41,42,43,44…VCC wiring 42a, 43a, 44a…Contact 61,62,63…Power supply 71, 73, 75...Set side shift register 72, 74, 76...Reset side level shifter 71d, 72d, 73d, 74d, 75d, 76d...Drain area 71s, 72s, 73s, 74s, 75s, 76s...Source area 81,84…Connection wiring 81a, 84a...First connection wiring 81b, 84b...Second connection wiring 82,82a,82b,83,83a,83b,85,85a,85b,86,86a,86b…Contact 101, 102, 103...Insulating film 104...Drain electrode 111...gate electrode 112, 116, 117...Pickup electrodes 113...Level shift resistor 114...1st electrode 115…Second electrode 120...GND wiring 121, 122, 123, 124…Contact

Claims

1. Pads and a control circuit that uses a first potential applied to the pad as a reference potential; a gate drive circuit having a second potential, which is a floating potential, as a reference potential; a set-side level shifter that converts a set signal having the first potential as a reference potential into a set signal having the second potential as a reference potential; and a reset-side level shifter that converts a reset signal having the first potential as a reference potential into a reset signal having the second potential as a reference potential; a set-side wiring electrically connecting the pad and the set-side level shifter in the high-potential side circuit region farthest from the pad; a reset side wiring electrically connecting the pad and the reset side level shifter in the high potential side circuit region farthest from the pad; Equipped with the set-side level shifter of the high-potential side circuit region located closer to the pad than the high-potential side circuit region farthest from the pad is electrically connected to the pad via the set-side wiring; A semiconductor device characterized in that the reset side level shifter in the high potential side circuit region, which is located closer to the pad than the high potential side circuit region farthest from the pad, is electrically connected to the pad via the reset side wiring.

2. 2. The semiconductor device according to claim 1, wherein the set side wiring and the reset side wiring have different lengths.

3. Each of the plurality of high potential side circuit regions includes a first wiring electrically connected to the set side level shifter, and a second wiring electrically connected to the reset side level shifter; Equipped with a first wiring of the high potential side circuit region located closer to the pad is electrically connected to the set side wiring via the first wiring of the high potential side circuit region located farther from the pad; 3. The semiconductor device according to claim 1, wherein a second wiring of the high potential side circuit region located closer to the pad is electrically connected to the reset side wiring via the second wiring of the high potential side circuit region located farther from the pad.

4. a first connection wiring that electrically connects the first wirings in different high potential side circuit regions to each other; 4. The semiconductor device according to claim 3, further comprising: a second connection wiring that electrically connects the second wirings in different high potential side circuit regions to each other.

5. a first connection wiring that electrically connects the first wirings of the adjacent high potential side circuit regions to each other; 4. The semiconductor device according to claim 3, further comprising: a second connection wiring that electrically connects the second wirings in the adjacent high potential side circuit regions to each other.

6. the first connection wiring electrically connecting the first wirings in the same high potential side circuit region to each other; 6. The semiconductor device according to claim 5, wherein the second connection wirings electrically connect the second wirings in the same high potential side circuit region to each other.

7. 7. The semiconductor device according to claim 3, wherein the first wiring and the second wiring in one of the high-potential side circuit regions are connected to each other.

8. 8. The semiconductor device according to claim 7, wherein the first wiring and the second wiring connected to each other are circular wiring arranged so as to surround the gate drive circuit.

9. The semiconductor device according to any one of claims 4 to 6, characterized in that the first connection wiring and the second connection wiring are wirings in a layer above the first wiring and the second wiring in each of the multiple high potential side circuit areas.

10. 10. The semiconductor device according to claim 3, wherein the first wirings in the adjacent high potential side circuit regions are spaced apart from each other, and the second wirings in the adjacent high potential side circuit regions are spaced apart from each other.

11. 5. The semiconductor device according to claim 4, further comprising a VCC wiring arranged in a layer below the first connection wiring and the second connection wiring and electrically connected to a power supply of the control circuit.

12. 9. The semiconductor device according to claim 3, wherein the first wirings of the high potential side circuit regions adjacent to each other are directly connected, and the second wirings of the high potential side circuit regions adjacent to each other are directly connected.

13. Pads and a control circuit that uses a first potential applied to the pad as a reference potential; a gate drive circuit having a second potential which is a floating potential as a reference potential, a set-side level shifter which converts a set signal having the first potential as a reference potential into a set signal having the second potential as a reference potential, a reset-side level shifter which converts a reset signal having the first potential as a reference potential into a reset signal having the second potential as a reference potential, and an annular wiring which is connected to the set-side level shifter and the reset-side level shifter, and the distances to the pad are different from each other; a set-side wiring electrically connecting the pad and the set-side level shifters of each of the plurality of high-potential side circuit regions; a reset-side wiring electrically connecting the pad and the reset-side level shifters in each of the plurality of high-potential-side circuit regions; Equipped with A semiconductor device characterized in that the annular wiring of the high potential side circuit region located closer to the pad is electrically connected to the set side wiring and the reset side wiring via the annular wiring of the high potential side circuit region located farther from the pad.

14. 14. The semiconductor device according to claim 13, wherein the set side wiring and the reset side wiring are arranged in a layer above the annular wiring of each of the plurality of high potential side circuit regions, and are connected via contacts to the annular wiring of the high potential side circuit region located farther from the pad.

15. the set side wiring and the reset side wiring are arranged in the same layer as the annular wirings of each of the plurality of high potential side circuit regions; 14. The semiconductor device according to claim 13, further comprising a connection wiring arranged in a layer above the set side wiring and the reset side wiring, electrically connecting the set side wiring and the reset side wiring to the annular wiring of the high potential side circuit region located farther from the pad.

16. 14. The semiconductor device according to claim 13, wherein the set side wiring and the reset side wiring are arranged in the same layer as the annular wiring of each of the plurality of high potential side circuit regions, and are directly in contact with the annular wiring of the high potential side circuit region located farther from the pad.

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