Insulated gate semiconductor device

Abstract

To provide an insulated gate semiconductor device in which short-circuit withstand can be improved while increase of on-resistance is suppressed.SOLUTION: An insulated gate semiconductor device comprises: first conductivity type current diffusion layers (2a, 2b, 3a-3d) that are provided on a first conductivity type drift layer 1; second conductivity type embedded layers (4a-4e, 6a-6c) that are provided on the current diffusion layers (2a, 2b, 3a-3d); second conductivity type injection control regions 8a-8c that are provided on the current diffusion layers (2a, 2b, 3a-3d); second conductivity type high concentration regions 5a-5c that are provided in the injection control regions 8a-8c; first conductivity type carrier supply regions 10a-10d that are provided above the injection control regions 8a-8c; and insulation gate structures (12, 13a, 13b) within trenches 11a, 11b. Impurity concentration of an above portion of the current diffusion layers (2a, 2b, 3a-3d) is 4×1016 cm-3 through 6×1016 cm-3, and a ratio of the impurity concentration of the injection control region to the impurity concentration of the above portion is 0.5 through 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a trench-gate insulated gate semiconductor device. [Background technology]

[0002] Trench-gate MOS field-effect transistors (MOSFETs) are expected to have a reduced on-resistance due to a reduced cell pitch compared to planar-gate MOSFETs. However, in trench-gate MOSFETs made of wide-bandgap semiconductors such as silicon carbide (SiC), a high voltage is likely to be applied to the gate insulating film located at the bottom of the trench, which may cause the gate insulating film to break down. Therefore, in order to reduce the electric field strength at the bottom of the trench, a structure has been considered in which a p-type buried region is provided at the bottom of the trench and a p-type buried region is provided in the center of the adjacent trench (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 002766 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, when the on-resistance is reduced, the saturation current increases, the safe operating area when interrupting a short circuit current (SCSOA) shortens, and the short circuit withstand capability decreases. In other words, there is a trade-off between reducing the on-resistance and improving the short circuit withstand capability, and it is difficult to improve the short circuit withstand capability while suppressing an increase in the on-resistance.

[0005] In view of the above problems, an object of the present invention is to provide a trench-gate insulated gate semiconductor device that can improve short-circuit resistance while suppressing an increase in on-resistance. [Means for solving the problem]

[0006] One aspect of the present invention includes: (a) a drift layer of a first conductivity type; (b) a current diffusion layer of the first conductivity type provided on an upper surface of the drift layer; (c) a buried layer of a second conductivity type provided inside the current diffusion layer; (d) an injection control region of the second conductivity type provided on an upper surface of the current diffusion layer and the buried layer; (e) a high concentration region of the second conductivity type provided inside the injection control region and having a higher impurity concentration than the injection control region; (f) a carrier supply region of the first conductivity type selectively provided above the injection control region; 16 cm -3 Above and 6 x 10 16 cm -3 The present invention relates to an insulated gate semiconductor device having an impurity concentration of at least 0.5 and at most 2, and a ratio of the impurity concentration of the implantation control region to the impurity concentration of the portion is at least 0.5 and at most 2. Effect of the Invention

[0007] According to the present invention, it is possible to provide a trench-gate insulated gate semiconductor device that can improve short-circuit resistance while suppressing an increase in on-resistance. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a main part of an insulated gate semiconductor device according to an embodiment of the present invention. [Diagram 2] 2 is a horizontal cross-sectional view taken along the line AA in FIG. 1. [Diagram 3] 2 is a horizontal cross-sectional view seen from the direction BB in FIG. 1. [Figure 4] 1 is a graph showing the relationship between the donor areal density in the upper current spreading region and the saturation current and the on-state voltage. [Diagram 5] 1 is a graph showing the relationship between the donor areal density in the upper current spreading region and the ratio of short circuit protection delay time to a conventional ratio and on-state voltage. [Figure 6]1 is a graph showing the relationship between the ratio of the impurity concentration of the base region to the impurity concentration of the upper current diffusion region and the rate of increase in on-resistance. [Figure 7] 1 is a graph showing the relationship between the ratio of the impurity concentration of the base region to the impurity concentration of the upper current diffusion region and the short circuit protection delay time. [Figure 8] 1A to 1C are cross-sectional views illustrating process steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention. [Figure 9] 9A to 9C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, following FIG. 8. [Figure 10] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, continuing from FIG. 9. [Figure 11] 11A to 11C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, following FIG. 10. [Figure 12] 12A to 12C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, following FIG. 11. [Figure 13] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, following FIG. 12. [Figure 14] 14A to 14C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, continuing from FIG. 13. [Figure 15] 15A to 15C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, continuing from FIG. 14. [Figure 16] 16A to 16C are cross-sectional views illustrating steps in a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention, following FIG. 15. [Figure 17] FIG. 13 is a plan view showing a main portion of an insulated gate semiconductor device according to a modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicated explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0010] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers (majority carriers) that become the main current, such as the source region of a metal-insulated field-effect transistor (MISFET) or a metal-insulated static induction transistor (MISSIT), the emitter region of an insulated gate bipolar transistor (IGBT), or the anode region of a metal-insulated static induction thyristor (MIS-controlled SI thyristor). The term "carrier receiving region" refers to a semiconductor region that receives majority carriers that become the main current, such as the drain region of a MISFET or a MISSIT, the collector region of an IGBT, or the cathode region of a MIS-controlled SI thyristor. In semiconductor devices that operate as bipolar types, such as an IGBT or a MIS-controlled SI thyristor, carriers (carriers) of the opposite conductivity type to the majority carriers are injected from the carrier receiving region.

[0011] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0012] In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + or - attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions have the same n and n attached, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] (Embodiment) <Structure of insulated gate semiconductor device> As an example of an insulated gate semiconductor device according to an embodiment of the present invention, a MISFET will be described as shown in Fig. 1. While Fig. 1 shows two trench MOS structures (unit cells), the insulated gate semiconductor device according to an embodiment of the present invention configures a power semiconductor device (power device) that passes a large current by periodically arranging the structures shown in Fig. 1 as a multi-channel structure.

[0014] As shown in FIG. 1, an insulated gate semiconductor device according to an embodiment of the present invention includes a first conductivity type (n-type) carrier transport layer (1, 2a, 2b, 3a, 3b) and injection control regions (base regions) 8a-8c of a second conductivity type (p-type) provided on the carrier transport layer (1, 2a, 2b, 3a, 3b).

[0015] The carrier transport layers (1, 2a, 2b, 3a to 3d) are made of a semiconductor material (wide band gap semiconductor) having a wider band gap than silicon, such as silicon carbide (SiC). The carrier transport layers (1, 2a, 2b, 3a, 3b) have an n-type drift layer 1 and an n-type current spreading layer (CSL) (2a, 2b, 3a to 3d) provided on the upper surface of the drift layer 1.

[0016] The drift layer 1 is a region where majority carriers forming the main current run in a drift electric field. The drift layer 1 is made of, for example, an epitaxially grown layer of SiC. The impurity concentration of the drift layer 1 is, for example, 1×10 15 cm -3Above and 3 x 10 16 cm -3 It is about the following.

[0017] The current diffusion layers (2a, 2b, 3a to 3d) are regions where majority carriers injected from the base regions 8a to 8c move by diffusion. The current diffusion layers (2a, 2b, 3a to 3d) include n-type lower current diffusion regions 2a and 2b and n-type upper current diffusion regions 3a to 3d provided on the upper surface sides of the lower current diffusion regions 2a and 2b.

[0018] The lower current diffusion regions 2a and 2b are formed of, for example, an epitaxially grown layer of SiC. The impurity concentration of the lower current diffusion regions 2a and 2b is higher than the impurity concentration of the drift layer 1. The impurity concentration of the lower current diffusion regions 2a and 2b is, for example, 7×10 16 cm -3 Above and 1.5 x 10 17 cm -3 It is preferably about 8×10 16 cm -3 Above 1.2×10 17 cm -3 The thickness of the lower current diffusion regions 2a and 2b is, for example, about 0.3 μm to 0.5 μm.

[0019] The upper current diffusion regions 3a to 3d are formed of, for example, an epitaxially grown layer of SiC. The impurity concentrations of the upper current diffusion regions 3a to 3d are higher than the impurity concentration of the drift layer 1 and lower than the impurity concentrations of the lower current diffusion regions 2a and 2b. The impurity concentrations of the upper current diffusion regions 3a to 3d are, for example, 4×10 16 cm -3 Above and 6 x 10 16 cm -3 The impurity concentration of the upper current diffusion regions 3a to 3d is, for example, 4×10 16 cm -3 Above and 5 x 10 16 cm -3 It is preferable that the concentration is about 5×10 or less. 16 cm -3 Above and 6 x 10 16 cm -3It is preferable that the temperature is about the same or less.

[0020] The thickness of the upper current diffusion regions 3a to 3d is, for example, about 0.3 μm to 0.5 μm. The thickness of the upper current diffusion regions 3a to 3d may be the same as that of the lower current diffusion regions 2a and 2b, or may be thinner or thicker than that of the lower current diffusion regions 2a and 2b.

[0021] The current diffusion layers (2a, 2b, 3a to 3d) are formed with p + The buried layers (4a to 4e, 6a to 6c) are formed of p + The buried regions 4a to 4e below the mold, + The p + The mold has upper embedded regions 6a to 6c.

[0022] The lower buried regions 4a to 4e are selectively provided on the upper parts of the lower current diffusion regions 2a and 2b. The upper surfaces of the lower buried regions 4b and 4d are provided in contact with the bottom surfaces of the trenches 11a and 11b. The lower buried regions 4a, 4c, and 4e are spaced apart from each other at the center positions of the adjacent trenches 11a and 11b, sandwiching the upper parts of the lower current diffusion regions 2a and 2b. The lower current diffusion regions 2a and 2b constitute a junction field effect transistor (JFET) region, which is a region sandwiched between the lower buried regions 4a to 4e. The lower buried regions 4b and 4d have the function of reducing the electric field applied to the gate insulating film 12 located at the bottom surfaces of the trenches 11a and 11b, and protecting the gate insulating film 12. The impurity concentration of the lower buried regions 4a to 4e is, for example, 5×10 17 cm -3 Above and 2 x 10 19 cm -3 The thickness of the lower buried regions 4a to 4e is, for example, about 0.3 μm to 0.5 μm.

[0023] The lower surface sides of the lower buried regions 4a, 4c, and 4e are provided with n +The partial current diffusion layers (partial CSL) 7a to 7c are provided. The partial current diffusion layers 7a to 7c have the function of concentrating an electric field in the lower buried regions 4a, 4c, and 4e when a breakdown electric field is exceeded during application of a reverse bias, facilitating avalanche breakdown, and protecting the gate insulating film 12. The partial current diffusion layers 7a to 7c are not necessarily provided.

[0024] The upper buried regions 6a to 6c are selectively provided inside the upper current diffusion regions 3a to 3d so as to contact the upper surfaces of the lower buried regions 4a, 4c, and 4e. Both side surfaces of the upper buried regions 6a to 6c are spaced apart from the trenches 11a and 11b and contact the upper current diffusion regions 3a to 3d. The upper buried regions 6a to 6c form a JFET region that is a region sandwiched between the lower buried regions 4a to 4e.

[0025] The impurity concentration of the upper buried regions 6a to 6c is, for example, 5×10 17 cm -3 Above and 2 x 10 19 cm -3 The upper buried regions 6a to 6c may have an impurity concentration equal to or different from that of the lower buried regions 4a to 4e. The upper buried regions 6a to 6c have a thickness of, for example, about 0.3 μm to 0.5 μm. FIG. 1 illustrates a case in which the width of the upper buried regions 6a to 6c is the same as that of the lower buried regions 4a to 4e, but the width of the upper buried regions 6a to 6c may be different from that of the lower buried regions 4a to 4e.

[0026] Base regions 8a to 8c are provided on the upper surfaces of the upper current diffusion regions 3a to 3d and the upper buried regions 6a to 6c. That is, the lower surfaces of the base regions 8a to 8c are in contact with the upper surfaces of the upper current diffusion regions 3a to 3d and the upper buried regions 6a to 6c. The base regions 8a to 8c control the amount of majority carriers, which become the main current, injected into the upper current diffusion regions 3a to 3d. The base regions 8a to 8c are formed of, for example, an epitaxially grown layer of SiC. The impurity concentration of the base regions 8a to 8c is lower than the impurity concentration of the lower buried regions 4a to 4e and the upper buried regions 6a to 6c. The impurity concentration of the base regions 8a to 8c is, for example, 2×10 16 cm -3 Above 1.2×10 17 cm -3 The peak impurity concentration of the base regions 8a to 8c is, for example, 2×10 16 cm -3 Above and 5 x 10 16 cm -3 It is about 6×10 16 cm -3 Above 1.2×10 17 cm -3 It is about the following.

[0027] The base regions 8a to 8c are uniformly provided with p-type high concentration regions 5a to 5c in the center of the base regions 8a to 8c in the depth direction. The high concentration regions 5a to 5c are regions formed by ion-implanting p-type impurities into the base regions 8a to 8c, and are p-type regions with a higher impurity concentration than the base regions 8a to 8c. The high concentration regions 5a to 5c are not in contact with the upper current diffusion regions 3a to 3d, the base contact regions 9a to 9c, and the source regions 10a to 10d, which will be described later. The impurity concentration of the high concentration regions 5a to 5c is, for example, 2×10 17 cm -3 Above and 7 x 10 17 cm -3 The impurity concentration in the high concentration region is, for example, 3×10 17 cm -3 Above and 5 x 10 17 cm -3 It is about the following.

[0028] The impurity concentrations of the base regions 8a-8c and the upper buried regions 6a-6c are set, for example, so that the ratio of the impurity concentration of the base regions 8a-8c to the impurity concentration of the upper buried regions 6a-6c is approximately 0.5 or more and 2 or less. The impurity concentrations of the base regions 8a-8c and the upper buried regions 6a-6c are preferably set, for example, so that the ratio of the impurity concentration of the base regions 8a-8c to the impurity concentration of the upper buried regions 6a-6c is approximately 0.5 or more and 1 or less, or approximately 1.2 or more and 2 or less.

[0029] The upper portions of the base regions 8a to 8c are + The source regions 10a to 10d are selectively provided with impurity supply regions (source regions) 10a to 10d. The impurity concentration of the source regions 10a to 10d is higher than the impurity concentration of the drift layer 1. The impurity concentration of the source regions 10a to 10d is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3 It is about the following.

[0030] The upper portions of the base regions 8a to 8c are provided with p + The base contact regions 9a to 9c are selectively provided. Both side surfaces of the base contact regions 9a to 9c are in contact with the source regions 10a to 10d. The impurity concentration of the base contact regions 9a to 9c is higher than the impurity concentration of the base regions 8a to 8c. The impurity concentration of the base contact regions 9a to 9c is, for example, 1×10 20 cm -3 Above and 5 x 10 20 cm -3 It is about the following.

[0031] Trenches 11a and 11b are provided so as to penetrate through the source regions 10a-10d, the base regions 8a-8c, the high concentration regions 5a-5c, and the upper current diffusion regions 3a-3d and reach the upper surfaces of the lower buried regions 4b and 4d. The side surfaces of the trenches 11a and 11b contact the source regions 10a-10d, the base regions 8a-8c, the high concentration regions 5a-5c, and the upper current diffusion regions 3a-3d. The bottom surfaces of the trenches 11a and 11b contact the upper surfaces of the lower buried regions 4b and 4d.

[0032] The bottom surfaces of the trenches 11a and 11b may be located at the same depth as the upper surfaces of the lower buried regions 4b and 4d, or may be located inside the lower buried regions 4b and 4d. For example, the depth of the trenches 11a and 11b is about 1 μm or more and 2 μm or less, the width is about 0.3 μm or more and 1 μm or less, and the interval is about 1 μm or more and 5 μm or less.

[0033] The insulated gate semiconductor device according to the embodiment of the present invention has insulated gate structures (12, 13a), (12, 13b) provided inside trenches 11a, 11b. The insulated gate structures (12, 13a), (12, 13b) control the surface potential of base regions 8a-8c located on the sidewalls of trenches 11a, 11b. The insulated gate structures (12, 13a), (12, 13b) include a gate insulating film 12 provided on the bottom and side surfaces of trenches 11a, 11b, and gate electrodes 13a, 13b provided inside trenches 11a, 11b with gate insulating film 12 interposed therebetween.

[0034] The gate insulating film 12 may be, for example, a silicon oxide film (SiO2 film), or a single layer film of any one of a silicon oxynitride film (SiON film), a strontium oxide film (SrO film), a silicon nitride film (Si3N4 film), an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgO film), an yttrium oxide film (Y2O3 film), a hafnium oxide film (HfO2 film), a zirconium oxide film (ZrO2 film), a tantalum oxide film (Ta2O5 film), and a bismuth oxide film (Bi2O3 film), or a composite film formed by stacking a plurality of these films.

[0035] The gate electrodes 13a and 13b may be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type impurities such as boron (B) or n-type impurities such as phosphorus (P), or a high melting point metal. In FIG. 1, the upper surfaces of the gate electrodes 13a and 13b are flush with the upper surfaces of the source regions 10a to 10d, but the present invention is not limited to this. For example, the upper portions of the gate electrodes 13a and 13b may extend to the upper surfaces of the source regions 10a to 10d via the gate insulating film 12.

[0036] FIG. 2 corresponds to a horizontal cross-sectional view (plan layout) seen from the AA direction in FIG. 1. A vertical cross-sectional view seen from the CC direction in FIG. 2 corresponds to FIG. 1. As shown in FIG. 2, the lower buried regions 4a-4m form a lattice shape in a planar pattern. The lower buried regions 4a-4e form a plurality of stripe portions extending parallel to each other in the vertical direction in FIG. 3. The lower buried regions 4f-4m extend in a direction perpendicular to the direction in which the lower buried regions 4a-4e extend (the horizontal direction in FIG. 2), and form connection portions that connect to the lower buried regions 4a-4e. The lower current diffusion regions 2a-2f are provided so as to be surrounded by the lower buried regions 4a-4m.

[0037] FIG. 3 corresponds to a horizontal cross-sectional view (plan layout) seen from the BB direction in FIG. 1. A vertical cross-sectional view seen from the DD direction in FIG. 3 corresponds to FIG. 1. As shown in FIG. 3, the trenches 11a and 11b are striped in a planar pattern extending parallel to each other in the vertical direction of FIG. 3. Gate electrodes 13a and 13b are provided inside the trenches 11a and 11b via a gate insulating film 12. Upper current diffusion regions 3a to 3d and upper buried regions 6a to 6c are provided between the trenches 11a and 11b. The upper current diffusion regions 3a to 3d and upper buried regions 6a to 6c are striped in a planar pattern extending parallel to each other in the vertical direction of FIG. 3. The planar pattern of the trenches 11a and 11b is not limited to a striped pattern, and may be a polygon such as a hexagon.

[0038] An interlayer insulating film 14 is disposed on the gate electrodes 13a and 13b shown in Fig. 1. A non-doped silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B), known as "NSG", can be used as the interlayer insulating film 14. The interlayer insulating film 14 may also be a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), a silicon oxide film doped with boron and phosphorus (BPSG film), a silicon nitride film (Si3N4 film), or a laminate film of these.

[0039] First main electrodes (source electrodes) (15-18) are provided on the source regions 10a-10d and the base contact regions 9a-9c in contact with the source regions 10a-10d and the base contact regions 9a-9c. The source electrodes (15-18) are, for example, composed of a source contact layer 15 provided in contact with the upper surfaces of the base contact regions 9a-9c, barrier metal layers 16 and 17 provided in contact with the upper and side surfaces of the source contact layer 15 and covering the interlayer insulating film 14, and a metal layer 18 provided in contact with the barrier metal layer 17.

[0040] The material of the source contact layer 15 is, for example, nickel silicide (NiSi x ) can be used as the material for the barrier metal layers 16 and 17. For example, titanium (Ti) or titanium nitride (TiN) can be used as the material for the metal layer 18. For example, aluminum (Al) or an Al-Si based alloy can be used as the material for the metal layer 18.

[0041] The bottom surface of the drift layer 1 is + A carrier receiving region (drain region) 11 of the type is provided. The drain region 11 is made of, for example, a SiC substrate. The impurity concentration of the drain region 11 is higher than the impurity concentration of the drift layer 1. The impurity concentration of the drain region 11 is, for example, 1×10 17 cm -3 Above and 1×10 20 cm -3 It is about the following.

[0042] A second main electrode (drain electrode) (19-22) is disposed on the lower surface of the drain region 11. The drain electrodes (19-22) are configured, for example, by a structure in which a first metal layer 19, a second metal layer 20, a third metal layer 21, and a fourth metal layer 22 are laminated in this order from the lower surface side of the drain region 11. The first metal layer 19 is made of a silicide or carbide layer of a metal such as titanium (Ti), molybdenum (Mo), tungsten (W), or nickel (Ni). The second metal layer 20 is made of, for example, an aluminum (Al) film or a titanium (Ti) film. The third metal layer 21 is made of, for example, a nickel (Ni) film or an alloy (Ni-p) mainly composed of Ni. The fourth metal layer 22 is made of, for example, gold (Au).

[0043] During operation of the insulated gate semiconductor device according to the embodiment of the present invention, a positive voltage is applied to the drain electrodes (19-22) and a positive voltage equal to or greater than a threshold is applied to the gate electrodes 13a, 13b, whereby an inversion channel is formed in the base regions 8a-8c and the high concentration regions 5a-5c in contact with the trenches 11a, 11b, the device is turned on, and a main current consisting of majority carriers (electrons) flows. On the other hand, when the voltage applied to the gate electrodes 13a, 13b is less than the threshold, an inversion channel is not formed in the base regions 8a-8c including the high concentration regions 5a-5c, the device is turned off, and no main current flows.

[0044] 4 shows the results of a simulation of the relationship between the n-type impurity surface density (donor surface density) of the upper current diffusion regions 3a-3d and the saturation current Id,sat and on-voltage Von when the donor surface density of the upper current diffusion regions 3a-3d of the insulated gate type semiconductor device according to the embodiment of the present invention is changed. As shown in FIG. 4, when the donor surface density of the upper current diffusion regions 3a-3d is changed to 2×10 12 cm -2 That is, when the thickness of the upper current diffusion regions 3a to 3d is 0.5 μm, the impurity concentration is 4×10 16 cm -3 By doing so, it is possible to reduce the saturation current Id,sat while suppressing an increase in the on-state voltage Von, and it is possible to improve the short-circuit withstand capability.

[0045] 5 shows the results of a simulation of the relationship between the donor surface density of the upper current diffusion regions 3a to 3d, the conventional ratio of the short circuit protection delay time tsc, and the on-voltage Von when the donor surface density of the upper current diffusion regions 3a to 3d of the insulated gate type semiconductor device according to the embodiment of the present invention is changed. 17 cm -3 This is the ratio to the short circuit protection delay time tsc when the donor surface density of the upper current diffusion regions 3a to 3d is set to 2×10 12 cm -2 That is, when the thickness of the upper current diffusion regions 3a to 3d is 0.5 μm, the impurity concentration is 4×10 16 cm -3 By setting the on-state voltage Von at 3×10 or more, the short circuit protection delay time tsc can be increased while suppressing an increase in the on-state voltage Von, and the short circuit withstand capability can be improved. 12 cm -2 In other words, when the thickness of the upper current diffusion regions 3a to 3d is 0.5 μm, the impurity concentration is 6×10 16 cm -3 It is preferable that:

[0046] 6 shows the results of a simulation of the relationship between the impurity concentration ratio and the rate of increase in on-resistance ΔRonA when the impurity concentration of the upper current diffusion regions 3a-3d of the insulated gate type semiconductor device according to the embodiment of the present invention and the ratio of the impurity concentration of the base regions 8a-8c to the impurity concentration of the upper current diffusion regions 3a-3d (hereinafter, simply referred to as the "concentration ratio"). As shown in FIG. 6, when the impurity concentration of the upper current diffusion regions 3a-3d is changed to 4×10 16 cm -3 Above and 6 x 10 16 cm -3 By setting the impurity concentration of the upper current diffusion regions 3a to 3d at 5×10 or less and setting the concentration ratio at 0.5 to 1.0, the rate of increase in the on-resistance ΔRonA can be suppressed to 5% or less. 16 cm -3 Above and 6 x 10 16 cm -3or less, and by setting the concentration ratio to be 0.5 or more and 2 or less, the rate of increase ΔRonA of on-resistance can be suppressed to 5% or less. If the on-resistance increases, elements will exceed the upper limit specification of the on-voltage Von, reducing the yield rate; however, if the rate of increase ΔRonA of on-resistance can be suppressed to 5% or less, the increase in on-resistance RonA can be absorbed by thinning the wafer or reducing the resistance of the drift layer 1, making it possible to maintain a high yield rate.

[0047] 7 shows the results of a simulation of the relationship between the impurity concentration ratio and the short circuit protection delay time tsc when the impurity concentration of the upper current diffusion regions 3a-3d of the insulated gate type semiconductor device according to the embodiment of the present invention and the ratio (concentration ratio) of the impurity concentration of the base regions 8a-8c to the impurity concentration of the upper current diffusion regions 3a-3d are changed. As shown in FIG. 7, when the impurity concentration of the upper current diffusion regions 3a-3d is changed to 4×10 16 cm -3 Above and 6 x 10 16 cm -3 The short circuit protection delay time tsc can be increased to 5 μs or more by setting the impurity concentration of the upper current diffusion regions 3a to 3d to 4×10 or less and setting the concentration ratio to 1.2 or more and 2 or less. 16 cm -3 Above and 5 x 10 16 cm -3 or less, and the concentration ratio is 0.5 or more and 2 or less, the short circuit protection delay time tsc can be increased to 5 μs or more. If the short circuit protection delay time tsc can be increased to 5 μs or more, short circuit protection can be achieved with just the element itself, without the need to add an external short circuit protection circuit.

[0048] Therefore, in the insulated gate semiconductor device according to the embodiment of the present invention, the impurity concentration of the upper current diffusion regions 3a to 3d is set to 4×10 16 cm -3 Above and 6 x 10 16 cm -3or less, and the ratio (concentration ratio) of the impurity concentration of the base regions 8a-8c to the impurity concentration of the upper current diffusion regions 3a-3d is set to 0.5 or more and 2 or less, the short circuit protection delay time tsc can be increased while suppressing the increase rate ΔRonA of the low on-resistance. In other words, the short circuit withstand capability can be improved while suppressing the increase in on-resistance.

[0049] The impurity concentration of the upper current diffusion regions 3a to 3d is set to 4×10 16 cm -3 Above and 5 x 10 16 cm -3 By setting the ratio (concentration ratio) of the impurity concentration of the base regions 8a to 8c to the impurity concentration of the upper current diffusion regions 3a to 3d to be 0.5 or more and 1 or less, the rate of increase ΔRonA of the low on-resistance can be suppressed to 5% or less, while the short circuit protection delay time tsc can be increased to 5 μs or more.

[0050] The impurity concentration of the upper current diffusion regions 3a to 3d is set to 5×10 16 cm -3 Above and 6 x 10 16 cm -3 or less, and by setting the ratio (concentration ratio) of the impurity concentration of the base regions 8a to 8c to the impurity concentration of the upper current diffusion regions 3a to 3d to be 1.2 or more and 2 or less, the rate of increase ΔRonA of the low on-resistance can be suppressed to 5% or less, while the short circuit protection delay time tsc can be increased to 5 μs or more.

[0051] <Method of Manufacturing Insulated Gate Semiconductor Device> Next, a method for manufacturing an insulated gate semiconductor device according to an embodiment of the present invention will be described with reference to Figures 8 to 16. Here, the description will be focused on the cross section of the insulated gate semiconductor device shown in Figure 1. Note that the method for manufacturing an insulated gate semiconductor device described below is one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0052] First, we create n-type GaN- ...+ A type SiC substrate is prepared, and the SiC substrate is used as a drain region 11. Next, an n-type drift layer 1 is epitaxially grown on the SiC substrate. Next, as shown in FIG. 8, an n-type lower current diffusion region 2 is epitaxially grown on the upper surface of the drift layer 1. As a result, as shown in FIG. 8, a stacked structure of the drain region 11, the drift layer 1, and the lower current diffusion region 2 is formed.

[0053] Next, a photoresist film is applied to the upper surface of the lower current diffusion region 2, and the photoresist film is patterned using photolithography technology. Using the patterned photoresist film as a mask, n-type impurity ions such as nitrogen (N) are implanted. After removing the photoresist film, a new photoresist film is applied to the upper surface of the lower current diffusion region 2, and the photoresist film is patterned using photolithography technology. Using the patterned photoresist film as a mask, p-type impurity ions such as aluminum (Al) are implanted. After removing the photoresist film, a heat treatment is performed to activate the n-type impurity ions and p-type impurity ions. As a result, n-type impurity ions are implanted in the lower part of the lower current diffusion region 2, as shown in FIG. 9. + The p-type partial current diffusion layers 7a to 7c are selectively formed on the upper portion of the lower current diffusion region 2. + The lower buried regions 4a to 4e of the mold are selectively formed. The heat treatment for forming the partial current diffusion layers 7a to 7c and the lower buried regions 4a to 4e may be performed individually instead of all at once.

[0054] Next, as shown in FIG. 10, an n-type upper current diffusion region 3 is epitaxially grown on the upper surfaces of the lower current diffusion regions 2a, 2b and the lower buried regions 4a to 4e. A photoresist film is applied to the upper surface of the upper current diffusion region 3, and the photoresist film is patterned using photolithography technology. Using the patterned photoresist film as a mask, p-type impurity ions such as Al are implanted. After removing the photoresist film, a heat treatment is performed to activate the p-type impurity ions. As a result, p-type impurity ions are formed inside the upper current diffusion region 3, as shown in FIG. +Buried regions 6a to 6c above the mold are selectively formed.

[0055] Next, a p-type base region 8 is epitaxially grown on the upper surfaces of the upper current diffusion region 3 and the upper buried regions 6a to 6c. Then, p-type impurity ions such as aluminum (Al) are implanted into the entire surface of the base region 8 to form a high concentration region 5 in the center of the base region 8 in the depth direction. The state up to this point is shown in FIG. 12. A photoresist film is applied to the upper surface of the base region 8, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as a mask, n-type impurity ions such as nitrogen (N) are implanted. After removing the photoresist film, a new photoresist film is applied to the upper surface of the base region 8, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as a mask, p-type impurity ions such as Al are implanted. After removing the photoresist film, a heat treatment is performed to activate the n-type impurity ions and the p-type impurity ions. As a result, as shown in FIG. 13, n-type impurity ions are formed in the upper part of the base region 8. + Source regions 10x, 10y and p of type + The source regions 10x, 10y and the base contact regions 9a to 9c are selectively formed. The heat treatment for forming the source regions 10x, 10y and the base contact regions 9a to 9c may be performed individually instead of all at once.

[0056] Next, a photoresist film is applied to the upper surfaces of the source regions 10x, 10y and the base contact regions 9a-9c, and the photoresist film is patterned by photolithography. Using the patterned photoresist film as an etching mask, parts of the source regions 10x, 10y, the base region 8, the high concentration region 5, and the upper current diffusion region 3 are removed in the depth direction by dry etching such as reactive ion etching (RIE). Then, the photoresist film is removed. Note that an oxide film may be patterned and used as an etching mask instead of the photoresist film. As a result, trenches 11a, 11b reaching the lower buried regions 4b, 4d are selectively formed as shown in FIG.

[0057] Next, a gate insulating film 12 is formed on the bottom and side surfaces of the trenches 11a and 11b and on the top surfaces of the source regions 10a to 10d and the base contact regions 9a to 9c by thermal oxidation or chemical vapor deposition (CVD). Furthermore, a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type impurities such as Al is deposited by CVD using a dopant gas so as to fill the trenches 11a and 11b. Then, a part of the doped polysilicon layer is selectively removed by photolithography and dry etching. As a result, as shown in FIG. 15, a pattern of the gate electrodes 13a and 13b made of the doped polysilicon layer is formed, and the insulated gate structures (12, 13a) and (12, 13b) are formed.

[0058] Next, an interlayer insulating film 14 is deposited on the upper surfaces of the insulated gate structures (12, 13a), (12, 13b) by a CVD method or the like. Then, a portion of the interlayer insulating film 14 and the gate insulating film 12 are selectively removed by photolithography and dry etching. Thereafter, a Ni film is deposited on the entire surface by a sputtering method or the like, and then heat treatment is performed to react the SiC on the surfaces of the source regions 10a-10d and the base contact regions 9a-9c with the Ni film. Furthermore, by removing the unreacted Ni film, NiSi is selectively formed in the portion from which the interlayer insulating film 14 was removed. x Then, the source contact layer 15 is formed of the barrier metal layers 16 and 17 and the source electrode 18 are formed on the interlayer insulating film 14 by using a sputtering method, a photolithography technique, an RIE technique, or the like.

[0059] Furthermore, the thickness of the drain region 11 is adjusted by chemical mechanical polishing (CMP) or the like. Thereafter, a drain electrode (19-22) is formed on the lower surface of the drain region 11 by a sputtering method, a vapor deposition method, or the like. In this manner, the insulated gate semiconductor device according to the embodiment shown in FIG. 1 is completed.

[0060] (Modification) The insulated gate type semiconductor device according to the modification of the embodiment of the present invention differs from the insulated gate type semiconductor device according to the embodiment of the present invention in that the depth of the lower surfaces of the lower current diffusion regions 2a, 2b coincides with the depth of the lower surfaces of the lower buried regions 4a-4e, as shown in Fig. 17. Other configurations of the insulated gate type semiconductor device according to the modification of the embodiment of the present invention are similar to those of the insulated gate type semiconductor device according to the embodiment of the present invention, and therefore repeated explanations will be omitted.

[0061] According to the insulated gate type semiconductor device of the modified embodiment of the present invention, even if the depth of the lower surfaces of the lower current diffusion regions 2a, 2b coincides with the depth of the lower surfaces of the lower buried regions 4a to 4e, the same effects as those of the insulated gate type semiconductor device of the embodiment can be achieved.

[0062] In manufacturing an insulated gate semiconductor device according to a modified embodiment of the present invention, n-type n-type semiconductor layers are formed on the upper part of the n-type drift layer 1 by ion implantation and heat treatment. + After forming the mold partial current diffusion layers 7a to 7c, the epitaxially grown layers constituting the lower current diffusion regions 2a and 2b may be formed.

[0063] (Other embodiments) As described above, the present invention has been described by the embodiment, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art from this disclosure.

[0064] For example, in the embodiment of the present invention, as shown in FIG. 1, the lower current diffusion regions 2a, 2b and the upper current diffusion regions 3a to 3d constituting the current diffusion layer (2a, 2b, 3a to 3d) are formed of separate epitaxially grown layers. However, the current diffusion layer may be formed of a single epitaxially grown layer. In this case, the impurity concentration of at least the portion (upper portion) of the current diffusion layer that contacts the base regions 8a to 8c may be set to the impurity concentration of the above-mentioned upper current diffusion regions 3a to 3d. In addition, after the current diffusion layer is formed of a single epitaxially grown layer, multi-stage ion implantation may be performed at high acceleration to obtain a p +The buried regions 4a to 4e and p + In addition, the current diffusion layers (2a, 2b, 3a to 3d) may all be formed by ion implantation.

[0065] In the embodiment of the present invention, as shown in Fig. 1, a MISFET having insulated gate structures (12, 13a), (12, 13b) in trenches 11a, 11b is exemplified, but the present invention is not limited to this and can be applied to insulated gate type semiconductor devices having various insulated gate structures, such as an IGBT having an insulated gate structure in a trench. As a trench gate type IGBT, + The p-type source regions 10a to 10d are used as emitter regions, and a p + A collector region of the type may be provided.

[0066] In the embodiment of the present invention, an insulated gate semiconductor device using SiC is exemplified. However, the present invention is also applicable to various insulated gate semiconductor devices using semiconductor materials (wide band gap semiconductors) that have a wider band gap than silicon, such as gallium nitride (GaN) having a smaller diffusion coefficient than Si, diamond, or aluminum nitride (AlN). [Explanation of symbols]

[0067] 1. Drift layer 2,2a~2f…lower current diffusion area 3, 3a to 3d: Upper current diffusion region 4a~4m…lower embedded area 5a,5b,5c…High concentration area 6a to 6c: Upper buried region 7a~7c...Partial current diffusion layer 8, 8a to 8c...Injection control region (base region) 9a to 9c: Base contact region 10a to 10d, 10x, 10y... Carrier supply region (source region) 11... Carrier receiving region (drain region) 11a, 11b...Trench 12...Gate insulating film 13a, 13b...gate electrode 14...Interlayer insulating film 15…Source contact layer 16,17...Barrier metal layer 18~22…metal layer

Claims

1. A drift layer of a first conductivity type; a current diffusion layer of a first conductivity type provided on an upper surface of the drift layer; a buried layer of a second conductivity type provided inside the current spreading layer; an injection control region of a second conductivity type provided on an upper surface of the current spreading layer and the buried layer; a high concentration region of a second conductivity type provided inside the implantation control region and having a higher impurity concentration than the implantation control region; a first conductive type carrier supply region selectively provided above the injection control region; a trench extending through the injection control region to the current spreading layer; an insulated gate structure disposed inside the trench; Equipped with The impurity concentration of at least the portion of the current spreading layer in contact with the injection control region is 4×10 １６ cm －３ Above, and 6 x 10 １６ cm －３ and a ratio of an impurity concentration of said implantation control region to an impurity concentration of said portion is 0.5 or more and 2 or less.

2. The impurity concentration of the portion is 4×10 １６ cm －３ Above and 5 x 10 １６ cm －３ 2. The insulated gate semiconductor device according to claim 1, wherein the ratio of the impurity concentrations is 0.5 or more and 1 or less.

3. The impurity concentration of the portion is 5×10 １６ cm －３ Above, and 6 x 10 １６ cm －３ 2. The insulated gate semiconductor device according to claim 1, wherein the ratio of the impurity concentrations is 1.2 or more and 2 or less.

4. The current spreading layer is a lower current spreading region provided on an upper surface of the drift layer; an upper current diffusion region provided on an upper surface of the lower current diffusion region and having a lower impurity concentration than the lower current diffusion region; 4. The insulated gate semiconductor device according to claim 1, further comprising:

5. The buried layer is a lower buried region provided within the lower current spreading region; an upper buried region provided inside the upper current spreading region and on a top surface of a part of the lower buried region, the upper buried region being spaced apart from the trench; 5. The insulated gate semiconductor device according to claim 4, further comprising:

6. 6. The insulated gate semiconductor device according to claim 5, further comprising a partial current diffusion layer of the first conductivity type provided on a lower surface of a portion of the lower buried region and having a higher impurity concentration than the drift layer.

7. 7. The insulated gate semiconductor device according to claim 5, wherein another part of said lower buried region is in contact with a bottom surface of said trench.

8. 8. The insulated gate semiconductor device according to claim 5, wherein the depth of the lower surface of the lower current diffusion region is deeper than the depth of the lower surface of the lower buried region.

9. 2. The insulated gate semiconductor device according to claim 1, wherein the high concentration region is in contact with the trench.

10. The impurity concentration of the high concentration region is 2×10 １７ cm －３ Above, and 7 x 10 １７ cm －３ 2. The insulated gate semiconductor device according to claim 1, wherein:

11. 5. The insulated gate semiconductor device according to claim 4, wherein said portion is said upper current spreading region.

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