Semiconductor device manufacturing method

Abstract

To improve the reliability of a semiconductor device.SOLUTION: In a Schottky barrier diode region SBR, a Schottky barrier diode SBD is configured between an n-type drift layer DF and a metal layer M1. In a body diode region BDR, a p-type semiconductor region PH, a p-type semiconductor region PL, and a p-type semiconductor region PR are sequentially formed from a principal surface SBa side, on the drift layer DF, and a body diode BD2 is configured between the p-type semiconductor region PR and the drift layer DF. By making the impurity concentration in the p-type semiconductor region PL lower than those in the p-type semiconductor regions PH and PR, a reflux current flowing in the Schottky barrier diode SBD is increased to prevent a reflux current from flowing in the body diode BD2.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a SiC power device. [Background technology]

[0002] SiC (silicon carbide) semiconductors are being researched as power devices to replace Si semiconductors. Compared to Si power devices, SiC power devices can achieve higher voltage resistance, larger current, and lower on-resistance, and are used, for example, as switching elements in inverter circuits for motor control systems. A diode is connected in parallel to the switching element.

[0003] In an inverter circuit, when the SiC power device (switch element) is turned off to cut off the current flowing through the motor coil, a back electromotive force is generated in the motor coil due to electromagnetic induction in the motor coil. The current caused by this back electromotive force is passed through the motor coil as a return current via a diode, preventing a high back electromotive force from being applied to the switch element.

[0004] International Publication No. 2012-105609 (Patent Document 1) discloses a SiC power device with a built-in Schottky barrier diode (SBD). The SiC power device is a semiconductor device in which a trench-gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a Schottky barrier diode are formed on a SiC substrate. By making the on-initiation voltage of the Schottky barrier diode lower than the on-initiation voltage of the body diode (parasitic diode), the reflux current is caused to flow through the Schottky barrier diode, preventing the reflux current from flowing through the body diode. This prevents an increase in the on-resistance of the trench-gate type MOSFET. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2012-105609 Summary of the Invention [Problem to be solved by the invention]

[0006] In a semiconductor device having the above-mentioned trench-gate MOSFET with a built-in Schottky barrier diode, when the back electromotive force is small, the return current can flow only through the Schottky barrier diode, but when the back electromotive force becomes large, the return current also flows through the body diode. As a result, it has been found that the on-resistance of the trench-gate MOSFET increases and the reliability of the semiconductor device decreases. In other words, there is a demand for improving the reliability of the semiconductor device.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate including a first semiconductor layer having a first conductivity type and including a first main surface and a second main surface opposite to the first main surface; and a second semiconductor layer having the first conductivity type and having a higher concentration than the first semiconductor layer, the first semiconductor layer being disposed on the second main surface; (b) forming a first semiconductor region of the first conductivity type in the first semiconductor layer so as to be exposed on the first main surface side in a first region that is a region for forming a MOSFET; (c) forming a second semiconductor region having a second conductivity type opposite to the first conductivity type in the first region so as to be located on the second main surface side with respect to the first semiconductor region; and (d) forming a front semiconductor layer having a first conductivity type and a second semiconductor layer having a second conductivity type opposite to the first conductivity type in a second region that is a region for forming a body diode so as to be exposed on the first main surface side. The method includes the steps of: (a) forming a third semiconductor region of the second conductivity type, (b) forming a fourth semiconductor region of the second conductivity type in the second region on the second main surface side with respect to the third semiconductor region, (c) forming a fifth semiconductor region of the second conductivity type in the second region on the second main surface side with respect to the fourth semiconductor region, (d) forming a first trench in the first region, penetrating the first semiconductor region and the second semiconductor region and reaching the first semiconductor layer, (e) forming a third semiconductor region of the second conductivity type in the second region on the second main surface side with respect to the fourth semiconductor region, (f) forming a fifth semiconductor region of the second conductivity type in the second region on the second main surface side with respect to the fourth semiconductor region, (g) forming a first trench in the first region, penetrating the first semiconductor region and the second semiconductor region and reaching the first semiconductor layer, (h) forming a gate electrode in the first trench via a gate insulating film, and (i) forming a metal layer on the first main surface in the first region, the second region, and a third region which is a region for forming a Schottky barrier diode. The impurity concentration of the fourth semiconductor region is lower than the impurity concentrations of the third semiconductor region and the fifth semiconductor region, and in the second region, the body diode is formed between the fifth semiconductor region and the first semiconductor layer, and in the third region, the Schottky barrier diode is formed between the metal layer and the first semiconductor layer.

[0009] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate including a first semiconductor layer having a first conductivity type and including a first main surface and a second main surface opposite to the first main surface; a first semiconductor region having a second conductivity type opposite to the first conductivity type and distributed within the first semiconductor layer along the first main surface; and a second semiconductor layer disposed on the second main surface, having the first conductivity type, and having a higher concentration than the first semiconductor layer; (b) forming a second semiconductor region of the first conductivity type in the first semiconductor layer in a first region that is a region for forming a MOSFET, so as to be exposed to the first main surface; (c) forming a second semiconductor region of the first conductivity type in the first region, the second semiconductor region being disposed on the second main surface; (d) forming a fourth semiconductor region of the second conductivity type so as to be exposed to the first main surface side in the second region, which is a region for forming a body diode, (e) forming a first trench in the first region, which penetrates the second semiconductor region and the third semiconductor region and reaches the first semiconductor layer, (f) forming a gate electrode in the first trench via a gate insulating film, and (g) forming a metal layer on the first main surface in the first region, the second region, and a third region, which is a region for forming a Schottky barrier diode. The first semiconductor region is disposed apart from the fourth semiconductor region, a part of the first semiconductor layer is interposed between the first semiconductor region and the fourth semiconductor region, an impurity concentration of the first semiconductor region is lower than an impurity concentration of the fourth semiconductor region, the body diode is formed between the first semiconductor region and the first semiconductor layer in the second region, and the Schottky barrier diode is formed between the metal layer and the first semiconductor layer in the third region. Effect of the Invention

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment; [Figure 4] 4 is a graph showing voltage-current characteristics of the semiconductor device according to the embodiment. [Diagram 5] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 6] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 7] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 8] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 9] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 10] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 11] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 12] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 13] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 14] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 15] 1 is a cross-sectional view of a semiconductor device according to an embodiment during a manufacturing process; [Figure 16] FIG. 2 is a cross-sectional view of a semiconductor device according to a study example. [Figure 17] FIG. 2 is an equivalent circuit diagram of the semiconductor device of the study example. [Figure 18] 1 is a graph showing voltage-current characteristics of the semiconductor device of the study example. [Figure 19] FIG. 11 is a cross-sectional view of a semiconductor device according to a first modified example. [Figure 20] 11A to 11C are cross-sectional views of the semiconductor device of Modification 1 during the manufacturing process. [Figure 21] 11A to 11C are cross-sectional views of the semiconductor device of Modification 1 during the manufacturing process. [Figure 22] FIG. 11 is a cross-sectional view of a semiconductor device according to a second modified example. [Figure 23] 11A to 11C are cross-sectional views of a semiconductor device according to Modification 2 during a manufacturing process. [Figure 24] FIG. 11 is a cross-sectional view of a semiconductor device according to a third modified example. [Diagram 25] 11A to 11C are cross-sectional views of a semiconductor device according to Modification 3 during a manufacturing process. [Figure 26] 11A to 11C are cross-sectional views of a semiconductor device according to Modification 3 during a manufacturing process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the following embodiments, for convenience, when necessary, the embodiments will be divided into multiple sections or embodiments, but unless otherwise expressly stated, they are not unrelated to each other and one may be a partial or complete variation, detail, supplementary explanation, etc. of the other.

[0013] In addition, in the following embodiments, when referring to the number of elements (including the number, numerical values, quantities, ranges, etc.), unless specifically stated or clearly limited to a specific number in principle, the number is not limited to that specific number and may be more than or less than a specific number.

[0014] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless specifically stated otherwise or unless clearly considered essential in principle.

[0015] Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of components, etc., it is intended to include those that are substantially similar or similar to those shapes, etc., unless otherwise specified or considered to be obviously different in principle. The same applies to the above numerical values ​​and ranges.

[0016] In addition, in all the drawings for explaining the embodiments, the same members are generally given the same reference numerals, and the repeated explanations are omitted. In order to make the drawings easier to understand, hatching may be used even in plan views.

[0017] <Explanation of the study example> FIG. 16 is a cross-sectional view of the semiconductor device of the examined example, FIG. 17 is an equivalent circuit diagram of the semiconductor device of the examined example, and FIG. 18 is a graph showing the voltage-current characteristics of the semiconductor device of the examined example (particularly, the diode).

[0018] As shown in FIG. 17, the trench-gate MOSFET has a drain D, a source S, and a gate G, and a Schottky barrier diode (hereinafter referred to as SBD) SBD and a body diode BD1 are connected in parallel between the drain D and the source S.

[0019] As shown in FIG. 16, the semiconductor device SD0 of the study example is a trench-gate MOSFET with a built-in SBD, and is formed on a semiconductor substrate SB made of silicon carbide (SiC). An n-type drain region DR corresponds to the drain D, an n-type source region SR corresponds to the source S, and a gate electrode GE corresponds to the gate G. A p-type channel formation region CH is formed between the drift layer DF and the source region SR, and the gate electrode GE is formed via a gate insulating film GI in a trench GR2 that penetrates the source region SR and the channel formation region CH to reach the drift layer DF. In addition, a source electrode SE made of a stacked structure of metal layers M1 and M2 is provided on the semiconductor substrate SB, and the source electrode SE is connected to the source region SR.

[0020] A groove GR1 is provided between adjacent gate electrodes GE, and an SBD is formed on a bottom surface GR1b of the groove GR1. The SBD is composed of an n-type drift layer DF and a metal layer M1 in contact with the drift layer DF, and is connected to the source electrode SE. That is, the metal layer M1 is a metal that forms a Schottky junction in contact with the n-type drift layer DF, and is, for example, a titanium (Ti) film.

[0021] In addition, a p-type semiconductor region PR is formed on both ends of the trench GR1 and is connected to the source electrode SE. The p-type semiconductor region PR is provided to relax the electric field between the drain region DR and the gate electrode GE when a high voltage is applied to the drain region DR, and has, for example, a higher impurity concentration than the channel formation region CH.

[0022] Consider the case where a back electromotive force is generated in the motor coil in the semiconductor device SD0 of the study example. That is, in the equivalent circuit diagram shown in FIG. 17, the MOSFET is off and a high voltage is applied to the source S with respect to the drain D. As shown in FIG. 16, the relatively low concentration drift layer DF has resistors (parasitic resistors) Rn0 and Rn1 connected in series between the SBD and the relatively high concentration drain region DR. Point P in the figure corresponds to the end of the p-type semiconductor region PR on the drain region DR side. Explaining with reference to FIG. 16 to FIG. 18, when a high voltage is applied to the source electrode SE, the SBD is turned on at the on-start voltage Vf(SBD) of the SBD, and a current flows from the source electrode SE to the drain region DR via the SBD. Then, when the current increases to a current value i1 and the divided voltage Vn1 on the resistor Rn1 side becomes equal to or higher than the on-start voltage Vf(BD1) of the body diode BD1, a current flows from the source electrode SE to the drain region DR via the body diode BD1, and as shown in FIG. 18, the current between the source S / drain D increases. When a current flows through the drift layer DF via the body diode BD1, holes are injected from the p-type semiconductor region PR into the drift layer DF. The injected holes then recombine with electrons, which are the majority carriers in the drift layer DF, and the recombination energy expands the crystal defects (dislocations) present in the drift layer DF. This causes problems such as an increase in leakage current and an increase in on-resistance in the trench-gate MOSFET.

[0023] <Structure of Semiconductor Device> FIG. 1 is a plan view of a semiconductor device SD1 according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, FIG. 3 is an equivalent circuit diagram of the semiconductor device according to the embodiment of the present invention, FIG. 4 is a graph showing the voltage-current characteristics of the semiconductor device according to the embodiment of the present invention (particularly, a diode), and FIG. 5 is a cross-sectional view taken along line BB in FIG. 1.

[0024] As shown in Fig. 1, the semiconductor device SD1 has a cell region CR arranged in the center of the main surface SBa of the semiconductor substrate SB, and a peripheral region PER arranged to surround the periphery of the cell region CR. The source electrode SE has a first portion covering the cell region CR and a second portion arranged in a ring shape in the peripheral region PER, and the first portion and the second portion are connected. The gate wiring GW is substantially ring-shaped (C-shaped), is arranged between the first portion and the second portion of the source electrode SE, and surrounds the periphery of the cell region CR. In Fig. 1, the direction along the cutting lines AA and BB is the X-direction, and the direction perpendicular to the X-direction is the Y-direction.

[0025] As shown in FIG. 3, the trench-gate MOSFET has a drain D, a source S, and a gate G. Between the drain D and the source S, an SBD, a body diode BD2, and a resistor Rp that are connected in series are connected in parallel.

[0026] As shown in FIG. 2, the semiconductor device SD1 of the embodiment is a trench-gate MOSFET with an SBD built in, and is formed on a semiconductor substrate SB made of silicon carbide. The main surface SBa of the semiconductor substrate SB includes a transistor region TR, which is a region where the trench-gate MOSFET is formed, a body diode region BDR, which is a region where the body diode BD1 is formed, and a Schottky barrier diode region SBR, which is a region where the SBD is formed. The cell region CR includes a plurality of transistor regions TR, body diode regions BDR, and Schottky barrier diode regions SBR. The Schottky barrier diode region SBR is disposed between two adjacent transistor regions TR, and the body diode region BDR is disposed between the transistor region TR and the Schottky barrier diode region SBR. The transistor region TR, the body diode region BDR, and the Schottky barrier diode region SBR are repeatedly disposed in the X direction. If the range from the center of the gate electrode GE to the center of the adjacent gate electrode GE is defined as one cell in the X direction, a plurality of cells are repeatedly disposed in the X direction. The thickness direction of the semiconductor substrate SB is defined as the Z direction.

[0027] The semiconductor substrate SB has a laminated structure of a substrate (bulk substrate, semiconductor layer) BK made of silicon carbide containing n-type impurities and an epitaxial layer (semiconductor layer) EP made of silicon carbide containing n-type impurities. The substrate BK has a main surface (first main surface) BKa and a back surface (second main surface) BKb opposite to the main surface BKa, and the epitaxial layer EP has a main surface (first main surface) EPa and a back surface (second main surface) EPb opposite to the main surface EPa. The substrate BK is provided on the back surface EPb side of the epitaxial layer EP. The back surface EPb of the epitaxial layer EP is in contact with the main surface BKa of the substrate BK, the main surface EPa of the epitaxial layer EP coincides with the main surface (first main surface) SBa of the semiconductor substrate SB, and the back surface BKb of the substrate BK coincides with the back surface SBb of the semiconductor substrate SB. The impurity concentration of the substrate BK is, for example, 1×10 18 cm -3 ~1×10 21 cm -3The impurity concentration of the epitaxial layer EP is, for example, 1×10 15 cm -3 ~1×10 17 cm -3 , preferably 1×10 16 cm -3 The n-type impurity concentration of the epitaxial layer EP is lower than the n-type impurity concentration of the substrate BK. The thickness of the epitaxial layer EP depends on the withstand voltage allowed by the semiconductor device SD1, and is, for example, about 12 μm.

[0028] The n-type drain region DR corresponds to the drain D, the n-type source region SR corresponds to the source S, and the gate electrode GE corresponds to the gate G (see FIG. 3). In the transistor region TR, the drain region DR, drift layer DF, channel formation region CH, source region SR, gate electrode GE, and gate insulating film GI constitute a trench-gate MOSFET. The source region SR is formed in the semiconductor substrate SB (or epitaxial layer EP) so as to be exposed on the main surface SBa (or main surface EPa) side of the semiconductor substrate SB (or epitaxial layer EP). The impurity concentration of the source region SR is, for example, a peak concentration of 2×10 at a depth of 0.3 μm from the main surface SBa. 20 cm -3 The p-type channel formation region CH is formed on the back surface SBb side of the semiconductor substrate SB with respect to the source region SR, and is in contact with the source region SR and the drift layer DF. The channel region CH is disposed between the source region SR and the drift layer DF. The impurity concentration of the channel formation region CH is, for example, a peak concentration of 3×10 at a depth of 0.8 μm from the main surface SBa. 17 cm -3 That's about it.

[0029] A plurality of grooves GR2 are arranged at a predetermined interval in the X direction on the main surface SBa of the semiconductor substrate SB. In the Z direction, the grooves GR2 penetrate the source region SR and the channel formation region CH to reach the drift layer DF. To be precise, the grooves GR2 cut into the drift layer DF and are also formed inside the drift layer DF. The depth of the grooves GR2 is, for example, 1.2 μm from the main surface SBa. The main surface SBa used as the reference for the depth is the main surface SBa in the region in which the source region SR is formed. A gate insulating film GI is formed on the side and bottom of the groove GR2, and a gate electrode GE is formed on the gate insulating film GI. The gate insulating film GI is, for example, a silicon oxynitride film, and the gate electrode GE is, for example, made of a polysilicon film. The gate electrode GE is covered with an interlayer insulating film IF and is insulated and separated from the source electrode SE formed on the interlayer insulating film IF. On the other hand, the source electrode SE is electrically connected to the source region SR. The source electrode SE is in ohmic contact with the source region SR via the silicide layer SL. The source electrode SE has a laminated structure of a metal layer M1 and a metal layer M2 formed on the metal layer M1.

[0030] In the body diode region BDR, p-type semiconductor regions PH, PL, and PR are formed in the drift layer DF. The p-type semiconductor region PH is formed so as to be exposed on the main surface SBa side of the semiconductor substrate SB, the p-type semiconductor region PR is formed on the back surface EPb side of the epitaxial layer EP (in other words, the drift layer DF) with respect to the p-type semiconductor region PH, and the p-type semiconductor region PL is formed between the p-type semiconductor regions PH and PR.

[0031] The p-type semiconductor region PH is a semiconductor region with a relatively high impurity concentration, for example, 2×10 20 cm -3The source electrode SE is electrically connected to the p-type semiconductor region PH, and is in ohmic contact with the p-type semiconductor region PH via the silicide layer SL. The channel formation region CH formed in the transistor region TR extends to the body diode region BDR and overlaps with the p-type semiconductor region PH. In other words, the p-type semiconductor region PH is provided to connect the channel formation region CH to the source electrode SE.

[0032] The p-type semiconductor region PR is provided to relax the electric field between the drain region DR and the gate electrode GE when a high voltage is applied to the drain region DR, and has a higher impurity concentration than the channel formation region CH, for example. The p-type semiconductor region PR is provided at a position deeper than the trench GR2, and its depth is about 2.3 μm, and the peak impurity concentration is, for example, 1×10 18 cm -3 The p-type semiconductor region PR formed in the body diode region BDR is not formed in the transistor region TR and the Schottky barrier diode region SBR, and is separated from each other in the X direction. However, as shown in FIG. 2, a part of the p-type semiconductor region PR extends into the transistor region TR. A body diode BD2, which will be described later, is formed between the p-type semiconductor region PR and the drift layer DF.

[0033] The p-type semiconductor region PL is provided between the p-type semiconductor regions PH and PR in the depth direction (Z direction), and has an impurity concentration lower than that of the p-type semiconductor regions PH and PR. In the Z direction, the p-type semiconductor region PL overlaps with the channel formation region CH in a relatively shallow portion, and does not overlap with the channel formation region CH in a relatively deep portion. The portion that does not overlap with the channel formation region CH (relatively deep portion) is a portion that is between the channel formation region CH and the p-type semiconductor region PR in the Z direction and overlaps with the drift layer DF. In the portion that does not overlap with the channel formation region CH (relatively deep portion), the impurity concentration of the p-type semiconductor region PL is, for example, 1×10 17 cm -3The impurity concentration of the portion overlapping with the channel formation region CH (a relatively shallow portion) is preferably 4×10 or less, which is the sum of the impurity concentration of the channel formation region CH and the impurity concentration of the p-type semiconductor region PL. 17 cm -3 As will be described later, the p-type semiconductor region PL functions as a resistance (parasitic resistance) Rp when a current flows through the body diode BD2.

[0034] In the Schottky barrier diode region SBR, the drift layer DF is exposed to the main surface SBa of the semiconductor substrate SB, and the source electrode SE is in contact with the drift layer DF. In other words, the metal layer M1 constituting the source electrode SE is in contact with the drift layer DF to form a Schottky junction. That is, an SBD is formed between the source electrode SE and the drift layer DF. The metal layer M1 is made of a metal having a work function larger than that of the n-type semiconductor region constituting the drift layer DF, for example, titanium (Ti), nickel (Ni), molybdenum (Mo), aluminum (Al), gold (Au) or platinum (Pt). The metal layer M2 is made of a metal film containing aluminum (Al) as a main component, and may contain a small amount of silicon (Si), copper (Cu) or both as impurities. A metal layer serving as a barrier layer may be interposed between the metal layers M1 and M2, and the barrier layer may be made of, for example, titanium nitride (TiN) or the like.

[0035] In this embodiment, in the body diode region BDR and the Schottky barrier diode region SBR, a groove GR1 is formed in the main surface SBa of the semiconductor substrate SB to remove the source region SR, and the depth of the groove GR1 is greater than the thickness of the source region SR. In the body diode region BDR and the Schottky barrier diode region SBR, the bottom surface (bottom portion) GR1b of the groove GR1 coincides with the main surface SBa of the semiconductor substrate SB. That is, the main surface SBa of the semiconductor substrate SB has two surfaces with different heights, for example, based on the back surface EPb of the epitaxial layer EP.

[0036] A drain electrode DE is formed on the back surface SBb of the semiconductor substrate SB. The drain electrode DE has a laminated structure of, for example, nickel silicide (NiSi) / titanium (Ti) / gold (Au) in this order from the side in contact with the substrate BK.

[0037] Next, as in the study example, a case where a back electromotive force is generated in the motor coil in the semiconductor device SD1 is considered. That is, in the equivalent circuit diagram shown in FIG. 3, a high voltage is applied to the source S with respect to the drain D. Unlike the study example, in this embodiment, as shown in FIG. 2 and FIG. 3, a resistor (parasitic resistor) Rp connected in series with the body diode BD2 is provided between the source S and the drain D. The resistor Rp corresponds to the semiconductor region PL shown in FIG. 2. Explaining with reference to FIG. 2 to FIG. 4, the drift layer DF with a relatively low concentration has resistors (parasitic resistors) Rn0 and Rn1 connected in series between the SBD and the relatively high concentration drain region DR. Point P in the figure corresponds to the end of the p-type semiconductor region PR on the drain region DR side in the Schottky barrier diode region SBR. When a high voltage is applied to the source electrode SE, the SBD is turned on at the on-start voltage Vf(SBD) of the SBD, and a current flows from the source electrode SE to the drain region DR via the SBD. Then, when the divided voltage Vn1 on the resistor Rn1 side becomes equal to or greater than the sum of the voltage Vp1 applied to the resistor Rp and the on-state voltage Vf(BD2) of the body diode BD2, a current flows from the source electrode SE to the drain region DR via the body diode BD2, and the current between the source S and drain D increases.

[0038] In this embodiment, since there is a resistor Rp connected in series with the body diode BD2, the on-start voltage Vf(BD2) of the body diode BD2 can be increased by the voltage Vp1 applied to the resistor Rp, higher than the on-start voltage Vf(BD1) of the body diode BD1 in the study example. That is, compared to the study example, the return current through the SBD can be increased to a current value i2 without turning on the body diode BD2. Therefore, it is possible to increase the return current of the trench gate MOSFET without causing problems such as an increase in leakage current and an increase in on-resistance of the trench gate MOSFET caused by the body diode BD2 being turned on. That is, the reliability of the semiconductor device can be improved.

[0039] FIG. 5 shows the peripheral region PER of the semiconductor device SD1. The peripheral region PER has a structure similar to that of the body diode region BDR. That is, the p-type semiconductor region PH is formed so as to be exposed to the main surface SBa of the semiconductor substrate SB, the p-type semiconductor region PR is formed on the back surface EPb side of the epitaxial layer EP (in other words, the drift layer DF) with respect to the p-type semiconductor region PH, and the p-type semiconductor region PL is formed between the p-type semiconductor regions PH and PR. Furthermore, the p-type semiconductor regions PH, PL, and PR are electrically connected to the source electrode SE. Furthermore, a channel formation region CH and a p-type termination region TM are provided on the outside of the p-type semiconductor region PH (opposite side to the cell region CR). The termination region TM is provided to relieve the electric field applied to the p-type semiconductor region PR and the channel formation region CH, and it is preferable that the impurity concentration of the termination region TM is lower than the impurity concentration of the channel formation region CH and the P-type semiconductor region PR.

[0040] In the peripheral region PER, too, a body diode BD2 is formed between the p-type semiconductor region PR and the drift layer DF. Therefore, by interposing the p-type semiconductor region PL between the p-type semiconductor regions PH and PR, the return current through the SBD can be increased to a current value i2 without turning on the body diode BD2.

[0041] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device in this embodiment will be described with reference to Fig. 2 and Fig. 6 to Fig. 15. Fig. 6 to Fig. 15 are cross-sectional views showing the method for manufacturing the semiconductor device in this embodiment, and correspond to the cross-sectional view of Fig. 2.

[0042] 6 shows the steps of preparing the semiconductor substrate SB, which includes a step of preparing a substrate BK and a step of forming an epitaxial layer EP. First, a substrate BK made of n-type silicon carbide is prepared. An n-type impurity is introduced into the substrate BK at a relatively high concentration. The n-type impurity is, for example, nitrogen (N) or phosphorus (P), and the impurity concentration is, for example, 1×10 19 cm -3 That's about it.

[0043] Next, an epitaxial layer (semiconductor layer) EP made of silicon carbide is formed on the main surface BKa of the substrate BK by epitaxial growth. The epitaxial layer EP contains an n-type impurity at a lower impurity concentration than the substrate BK. The impurity concentration of the epitaxial layer EP depends on the breakdown voltage allowed by the semiconductor device SD1, but is, for example, 1×10 16 cm -3 The epitaxial layer EP becomes a path of a current flowing in the Z direction in the trench-gate MOSFET. That is, the substrate BK is the drain region DR of the semiconductor device SD1, and the epitaxial layer EP is the drift layer DF of the semiconductor device SD1. In this manner, a semiconductor substrate SB consisting of the substrate BK and the epitaxial layer EP is prepared.

[0044] 7 shows a process of forming the n-type semiconductor region NR1 and a process of forming the channel formation region CH. First, the n-type semiconductor region NR1 is formed by ion-implanting an n-type impurity (e.g., nitrogen (N) or phosphorus (P)) into the main surface SBa of the semiconductor substrate SB. The n-type semiconductor region NR1 is formed in the transistor region TR, the body diode region BDR, and the Schottky barrier diode region SBR. The impurity concentration of the n-type semiconductor region NR1 is, for example, a peak concentration of 2×10 at a depth of 0.3 μm from the main surface SBa. 20 cm -3 That's about it.

[0045] 7, a mask film MSK1 is provided on the main surface SBa to cover the Schottky barrier diode region SBR, and a p-type impurity (e.g., boron (B) or aluminum (Al)) is ion-implanted into the transistor region TR and the body diode region BDR exposed from the mask film MSK1 to form a channel formation region CH. The impurity concentration of the channel formation region CH is 3×10 at a peak concentration at a depth of 0.8 μm from the main surface SBa. 17 cm -3 After the ion implantation process is completed, the mask film MSK1 is removed. The mask film MSK1 can be a photoresist layer, a silicon oxide film, a silicon nitride film, or the like. The same applies to the following mask films MSK2 to MSK8. Although the channel formation region CH is formed following the n-type semiconductor region NR1, the formation process of the two may be reversed.

[0046] FIG. 8 shows a process of forming the source region SR. A mask film MSK2 is provided on the main surface SBa to cover the transistor region TR and expose the body diode region BDR and the Schottky barrier diode region SBR. Dry etching is performed on the semiconductor substrate SB to form a groove GR1 in the region exposed from the mask film MSK2, thereby removing the n-type semiconductor region NR1 in the body diode region BDR and the Schottky barrier diode region SBR, and forming a source region SR in the transistor region TR. In order to completely remove the n-type semiconductor region NR1 in the body diode region BDR and the Schottky barrier diode region SBR, it is essential that the depth of the groove GR1 is deeper than the thickness of the n-type semiconductor region NR1. After the dry etching process is completed, the mask film MSK2 is removed.

[0047] 9 shows a process of forming the p-type semiconductor region PH and a process of forming the p-type semiconductor region PL. A mask film MSK3 is provided on the main surface SBa to cover a part of the transistor region TR, the Schottky barrier diode region SBR, and the body diode region BDR and to expose the other part of the body diode region BDR, and p-type impurities are ion-implanted into the region exposed from the mask film MSK3 to form the p-type semiconductor region PH. The peak concentration of the p-type semiconductor region PH is 2×10 20 cm -3 The p-type semiconductor region PH is formed so as to be exposed on the main surface SBa (in other words, the bottom surface GR1b of the trench GR1). Next, n-type impurities are ion-implanted into the region exposed from the mask film MSK3 to impart a peak concentration of about 1×10 17 cm -3 The following p-type semiconductor region PL is formed. The p-type semiconductor region PL is in contact with the p-type semiconductor region PH and is formed on the back surface EPb side of the epitaxial layer EP (in other words, the drift layer DF) with respect to the p-type semiconductor region PH. After the ion implantation process is completed, the mask film MSK3 is removed.

[0048] Although the p-type semiconductor region PL is formed by ion implantation of n-type impurities, the p-type semiconductor region PH may be formed thinly, and the p-type semiconductor region PL may be formed by ion implantation of p-type impurities below the p-type semiconductor region PH.

[0049] 10 shows a process of forming a p-type semiconductor region PR. A mask film MSK4 is provided on the main surface SBa to cover a part of the transistor region TR and the Schottky barrier diode region SBR and to expose the other part of the transistor region TR and the body diode region BDR, and p-type impurities are ion-implanted into the region exposed from the mask film MSK4 to form the p-type semiconductor region PR. The p-type semiconductor region PR is formed away from the channel formation region CH in the Z direction, and the peak impurity concentration at a depth of 2.3 μm is, for example, 1×10 18 cm -3 The p-type semiconductor region PR is in contact with the p-type semiconductor region PL and is formed on the back surface EPb side of the epitaxial layer EP (in other words, the drift layer DF) with respect to the p-type semiconductor region PL.

[0050] Next, after removing the mask film MK4, the entire main surface SBa of the semiconductor substrate SB is covered with a protective film (e.g., an amorphous carbon film), and the semiconductor substrate SB is subjected to a high-temperature (e.g., 1700° C.) annealing process to activate the ion-implanted impurities. After the annealing process is completed, the protective film is removed.

[0051] FIG. 11 shows a process of forming the groove GR2. A mask film MSK5 is provided on the main surface SBa to cover a part of the transistor region TR, the body diode region BDR, and the Schottky barrier diode region SBR and to expose the other part of the transistor region TR, and the semiconductor substrate SB is dry-etched to form the groove GR2. The groove GR2 penetrates the source region SR and the channel formation region CH and reaches the drift layer DF. To be precise, the groove GR2 also extends into the drift layer DF and is also formed in a part of the drift layer DF. The depth of the groove GR2 is about 1.2 μm from the main surface SBa. After the dry etching process is completed, the mask film MSK5 is removed.

[0052] FIG. 12 shows a process of forming a gate insulating film GI, a gate electrode GE, and an interlayer insulating film IF. In the trench GR2, the gate insulating film GI and the gate electrode GE are formed in order. The gate insulating film GI is, for example, a silicon oxynitride film, and is formed by subjecting the bottom and side surfaces of the trench GR2 to oxynitridation (for example, heat treatment in nitric oxide (NO) at 1300° C.) or thermal oxidation (for example, heat treatment in dry O2 at 1200° C.) followed by oxynitridation. Next, a conductor layer such as a polysilicon film is deposited on the gate insulating film GI, and then the polysilicon film is selectively left in the trench GR2 to form the gate electrode GE. Next, an interlayer insulating film IF is formed that covers the gate electrode GE and the Schottky barrier diode region SBR and has an opening OP that exposes a part of the source region SR and the p-type semiconductor region PH. The interlayer insulating film IF is, for example, made of a silicon oxide film.

[0053] 13 shows a process for forming a silicide layer SL. The silicide layer SL is formed in a part of the source region SR and the p-type semiconductor region PH exposed from the opening OP of the interlayer insulating film IF. The silicide layer SL can be, for example, nickel silicide (NiSi) or platinum-containing nickel silicide (PtNiSi).

[0054] 14 shows a process of removing the interlayer insulating film IF. A mask film MSK6 is provided on the interlayer insulating film IF to cover the transistor region TR and a part of the body diode region BDR and to expose the other part of the body diode region BDR and the Schottky barrier diode region SBR, and the interlayer insulating film IF covering the Schottky barrier diode region SBR is removed by, for example, wet etching. Then, in the Schottky barrier diode region SBR, the main surface SBa of the semiconductor substrate SB (in other words, the main surface EPa of the epitaxial layer EP, the main surface of the drift layer DF, or the bottom surface GR1b of the groove GR1) is exposed.

[0055] Next, as shown in FIG. 15, a source electrode SE is formed on the main surface SBa, and then, as shown in FIG. 2, a drain electrode DE is formed on the back surface SBb. As shown in FIG. 15, the source electrode SE has a laminated structure of a metal layer M1 and a metal layer M2 formed on the metal layer M1. In the Schottky barrier diode region SBR, the metal layer M1 contacts the n-type drift layer DF to form a Schottky junction. That is, an SBD is formed between the source electrode SE and the drift layer DF. Therefore, the metal layer M1 is made of a metal having a work function larger than the work function of the n-type semiconductor region constituting the drift layer DF, and is made of, for example, titanium (Ti), nickel (Ni), molybdenum (Mo), aluminum (Al), gold (Au), or platinum (Pt). The drain electrode DE has, for example, a laminated structure of nickel silicide (NiSi) / titanium (Ti) / gold (Au) in this order from the side in contact with the drain region DR (in other words, the substrate BK).

[0056] <Variation 1> FIG. 19 is a cross-sectional view of the semiconductor device SD2 of the first modification, and FIG. 20 and FIG. 21 are cross-sectional views of the semiconductor device SD2 of the first modification during the manufacturing process. The first modification is a modification of the above embodiment, and in the semiconductor device SD2 of the first modification, the groove GR1 is not provided in the body diode region BDR and the Schottky barrier diode region SBR. That is, the main surface SBa of the semiconductor substrate SB in the transistor region TR and the main surface SBa of the semiconductor substrate SB in the body diode region BDR and the Schottky barrier diode region SBR have almost the same height with respect to the back surface SBb of the semiconductor substrate SB. Even if there is a difference in height between the two, the difference in height is smaller than the thickness of the source region SR. The other components are the same as those of the semiconductor device SD1 of the above embodiment, and are denoted by the same reference numerals.

[0057] The semiconductor device SD2 in FIG. 19 also has the p-type semiconductor region PL, and therefore has the equivalent circuit diagram shown in FIG. 3 and the voltage-current characteristics shown in FIG. 4, and can increase the return current without turning on the body diode BD2.

[0058] Regarding the manufacturing method of the semiconductor device SD2 of the modified example 1, steps different from the manufacturing process of the semiconductor device SD1 of the above embodiment will be described. FIG. 20 shows a process of forming the source region SR. After preparing the semiconductor substrate SB, a mask film MSK7 is formed on the main surface SBa to cover the body diode region BDR and the Schottky barrier diode region SBR and expose the transistor region TR. Then, n-type impurities are ion-implanted into the epitaxial layer EP (in other words, the drift layer DF) exposed from the mask film MSK7 to form the source region SR. The source region SR is formed in the epitaxial layer EP (in other words, the drift layer DF) so as to be exposed to the main surface SBa. After the ion-implantation process is completed, the mask film MSK7 is removed.

[0059] 21 shows a process of forming a channel formation region CH. A mask film MSK8 that covers the Schottky barrier diode region SBR and exposes the transistor region TR and the body diode region BDR is formed on the main surface SBa. Then, p-type impurities are ion-implanted into the epitaxial layer EP (in other words, the drift layer DF) exposed from the mask film MSK8 to form the channel formation region CH. The p-type channel formation region CH is formed on the back surface SBb side of the semiconductor substrate SB with respect to the source region SR, and is in contact with the drift layer DF. After the ion implantation process is completed, the mask film MSK8 is removed.

[0060] Next, in the manufacturing method of the above embodiment, the steps subsequent to the step of forming the p-type semiconductor region PH described with reference to FIG. 9 are performed to manufacture the semiconductor device SD2 of the modified example 1.

[0061] According to the semiconductor device SD2 of the first modification, the dry etching for forming the groove GR1 in the Schottky barrier diode region SBR can be omitted, which reduces roughness (damage) of the main surface SBa of the semiconductor substrate SB caused by dry etching and reduces the leakage current of the SBD.

[0062] <Variation 2> Fig. 22 is a cross-sectional view of the semiconductor device SD3 of Modification 2, and Fig. 23 is a cross-sectional view of the semiconductor device SD3 of Modification 2 during a manufacturing process. Modification 2 is a modification of Modification 1, and in the semiconductor device SD3 of Modification 2, the channel formation region CH1 is formed only in the transistor region TR. The other components are similar to those of the semiconductor device SD2 of Modification 1 described above, and are denoted by similar reference numerals.

[0063] As shown in FIG. 22, the channel formation region CH1 of the transistor region TR and the p-type semiconductor region PL of the body diode region BDR are in contact with each other. Unlike the above embodiment and modification 1, the channel formation region CH1 does not extend to the body diode region BDR. Therefore, even in a relatively shallow portion of the p-type semiconductor region PL, the impurity concentration can be made lower than the impurity concentration of the channel formation region CH1 without being affected by the channel formation region CH1. That is, in the entire region in the Z direction between the p-type semiconductor region PH and the p-type semiconductor region PR, the impurity concentration of the p-type semiconductor region PL can be made lower than the impurity concentration of the channel formation region CH1. Therefore, the resistance (parasitic resistance) Rp1 of the p-type semiconductor region PL can be made larger than that of the above embodiment and modification 1, and the reflux current can be increased without turning on the body diode BD2.

[0064] Next, the manufacturing method of the semiconductor device SD3 of the second modification will be described in terms of the differences from the first modification. As shown in FIG. 23, in the process of forming the source region SR and the channel formation region CH1, after preparing the semiconductor substrate SB, a mask film MSK9 is formed on the main surface SBa to cover the body diode region BDR and the Schottky barrier diode region SBR and expose the transistor region TR. Then, n-type impurities are ion-implanted into the epitaxial layer EP (in other words, the drift layer DF) exposed from the mask film MSK7 to form the source region SR, and p-type impurities are ion-implanted to form the channel formation region CH1. After the ion-implantation process is completed, the mask film MSK9 is removed.

[0065] Next, in the manufacturing method of the above embodiment, the steps subsequent to the step of forming the p-type semiconductor region PH described with reference to FIG. 9 are performed to manufacture the semiconductor device SD3 of the modified example 2.

[0066] The configuration of the channel formation region CH1 of the second modification can also be applied to the above embodiment.

[0067] <Modification 3> Fig. 24 is a cross-sectional view of the semiconductor device SD4 of Modification 3, and Fig. 25 and Fig. 26 are cross-sectional views during a manufacturing process of the semiconductor device SD4 of Modification 3. Modification 3 is a modification of the above embodiment, and the semiconductor device SD4 does not have a p-type semiconductor region PL.

[0068] 24, the p-type semiconductor regions PR1 that relieve the electric field between the drain region DR and the gate electrode GE are arranged in the transistor region TR, the body diode region BDR, and the Schottky barrier diode region SBR at predetermined intervals in the X direction. In the Z direction, the p-type semiconductor region PR1 is arranged away from the p-type semiconductor region PH, and an n-type drift layer DF having a resistance (parasitic resistance) Rn2 is interposed between the p-type semiconductor region PH and the p-type semiconductor region PR1.

[0069] In the semiconductor device SD4 as well, an n-type drift layer DF having a resistance (parasitic resistance) Rn2 is interposed between the p-type semiconductor region PH and the p-type semiconductor region PR1, and therefore the equivalent circuit diagram shown in FIG. 3 and the voltage-current characteristics shown in FIG. 4 are obtained, and the return current can be increased without turning on the body diode BD2.

[0070] Next, a manufacturing method of the semiconductor device SD4 of the third modification will be described. The epitaxial layer EP of the semiconductor device SD4 has a laminated structure of epitaxial layers EP1 and EP2. As shown in Fig. 25, an epitaxial layer EP1 having a thickness of about 9 µm is formed on a main surface BKa of a substrate BK. Next, p-type impurities are ion-implanted into a main surface EP1a of the epitaxial layer EP1 to form a plurality of p-type semiconductor regions PR1.

[0071] 26, an epitaxial layer EP2 having a thickness of about 3 μm is formed on the main surface EP1a of the epitaxial layer EP1, and a semiconductor substrate SB having a plurality of p-type semiconductor regions PR1 embedded therein is formed. The steps subsequent to the step of forming the source region SR in the above embodiment are then carried out to manufacture the semiconductor device SD4 of the third modification. However, the step of forming the p-type semiconductor regions PL and PR in the body diode region BDR is excluded.

[0072] The configuration of the third modification can also be applied to the first modification.

[0073] The present invention has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. A part of the contents described in the above-described embodiments is described below.

[0074] [Appendix 1] (a) preparing a semiconductor substrate including a first semiconductor layer having a first conductivity type and including a first main surface and a second main surface opposite to the first main surface, and a second semiconductor layer having the first conductivity type and having a higher concentration than the first semiconductor layer, the second semiconductor layer being disposed on the second main surface; (b) forming a first semiconductor region of the first conductivity type in the first semiconductor layer so as to be exposed on the first main surface side in a first region where a MOSFET is to be formed; (c) forming a second semiconductor region having a second conductivity type opposite to the first conductivity type in the first region, the second semiconductor region being located on the second main surface side with respect to the first semiconductor region; (d) forming a third semiconductor region of the second conductivity type in a second region where a body diode is to be formed, so as to be exposed on the first main surface side; (e) forming a fourth semiconductor region of the second conductivity type in the second region so as to be located on the second main surface side with respect to the third semiconductor region; (f) forming a fifth semiconductor region of the second conductivity type in the second region so as to be located on the second main surface side with respect to the fourth semiconductor region; (g) forming a first trench in the first region, the first trench penetrating the first semiconductor region and the second semiconductor region and reaching the first semiconductor layer; (h) forming a gate electrode in the first trench with a gate insulating film interposed therebetween; (i) forming a metal layer on the first main surface in the first region, the second region, and a third region in which a Schottky barrier diode is to be formed; having an impurity concentration of the fourth semiconductor region is lower than impurity concentrations of the third semiconductor region and the fifth semiconductor region; the body diode is configured between the fifth semiconductor region and the first semiconductor layer in the second region; the Schottky barrier diode is configured between the metal layer and the first semiconductor layer in the third region.

[0075] [Appendix 2] In the method for manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b-1) forming the first semiconductor region in the first region, the second region, and the third region; (b-2) forming a second groove in the first main surface of the first semiconductor layer in the second region and the third region, thereby removing a part of the first semiconductor region and leaving another part of the first semiconductor region in the first region; A method for manufacturing a semiconductor device comprising the steps of:

[0076] [Appendix 3] In the method for manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b-3) forming a first mask film covering the second region and the third region; (b-4) implanting the first conductive type impurity into the first semiconductor layer in the first region exposed from the first mask film to form the first semiconductor region; A method for manufacturing a semiconductor device comprising the steps of:

[0077] [Appendix 4] In the method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the step (c) comprises forming the second semiconductor region selectively in the first region using a second mask film that covers the second region and the third region.

[0078] [Appendix 5] In the method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are made of silicon carbide.

[0079] [Appendix 6] (a) preparing a semiconductor substrate including: a first semiconductor layer having a first conductivity type and including a first main surface and a second main surface opposite to the first main surface; first semiconductor regions having a second conductivity type opposite to the first conductivity type and dispersed within the first semiconductor layer along the first main surface; and a second semiconductor layer having the first conductivity type and having a higher concentration than the first semiconductor layer, which is disposed on the second main surface; (b) forming a second semiconductor region of the first conductivity type in the first semiconductor layer so as to be exposed on the first main surface side in a first region where a MOSFET is to be formed; (c) forming a third semiconductor region having the second conductivity type in the first region so as to be located on the second main surface side with respect to the second semiconductor region; (d) forming a fourth semiconductor region of the second conductivity type in a second region where a body diode is to be formed, so as to be exposed on the first main surface side; (e) forming a first trench in the first region, the first trench penetrating the second semiconductor region and the third semiconductor region and reaching the first semiconductor layer; (f) forming a gate electrode in the first trench via a gate insulating film; (g) forming a metal layer on the first main surface in the first region, the second region, and a third region in which a Schottky barrier diode is to be formed; having the first semiconductor region is disposed apart from the fourth semiconductor region; a portion of the first semiconductor layer is interposed between the first semiconductor region and the fourth semiconductor region; an impurity concentration of the first semiconductor region is lower than an impurity concentration of the fourth semiconductor region; the body diode is configured between the first semiconductor region and the first semiconductor layer in the second region; the Schottky barrier diode is configured between the metal layer and the first semiconductor layer in the third region. [Explanation of symbols]

[0080] BD1, BD2 body diodes BDR Body diode region BK substrate (bulk substrate, semiconductor layer) BKa main surface (first main surface) BKb Back side (second main surface) CH, CH1 Channel formation region (p-type semiconductor region) CR Cell Area D Drain DE Drain electrode DF Drift layer (n-type semiconductor region, drift region) DR Drain region (n-type semiconductor region, semiconductor layer) EP, EP1, EP2 Epitaxial layer (semiconductor layer) EPa Main surface (first main surface) EPb Back side (second main surface) FET G Gate GE gate electrode GI Gate Insulator GR1, GR2 groove GR1b bottom (bottom) GW Gate wiring IF Interlayer Insulating Film M1, M2 metal layer MSK1~MSK8 Mask membrane NR1 n-type semiconductor region OP Opening PER surrounding area PH p-type semiconductor region PL p-type semiconductor region PR, PR1 p-type semiconductor region Rn0, Rn1, Rn2, Rp, Rp1 Resistance (parasitic resistance) S Source SB Semiconductor Substrate SBa Principal surface (first principal surface) SBb Back side (second main surface) SBD Schottky Barrier Diode SBR Schottky Barrier Diode Area SD0, SD1, SD2, SD3, SD4 Semiconductor device SE source electrode SL Silicide layer SR source region (n-type semiconductor region) TM Termination Area TR Transistor area

Claims

1. (a) preparing a semiconductor substrate including a first semiconductor layer having a first conductivity type and including a first main surface and a second main surface opposite to the first main surface, and a second semiconductor layer having the first conductivity type and having a higher concentration than the first semiconductor layer, the second semiconductor layer being disposed on the second main surface; (b) forming a first semiconductor region of the first conductivity type in the first semiconductor layer so as to be exposed on the first main surface side in a first region that is a formation region of a MOSFET; (c) forming a second semiconductor region having a second conductivity type opposite to the first conductivity type in the first region, the second semiconductor region being located on the second main surface side with respect to the first semiconductor region; (d) forming a third semiconductor region of the second conductivity type in a second region where a body diode is to be formed, so as to be exposed on the first major surface side; (e) forming a fourth semiconductor region of the second conductivity type in the second region so as to be located on the second main surface side with respect to the third semiconductor region; (f) forming a fifth semiconductor region of the second conductivity type in the second region so as to be located on the second main surface side with respect to the fourth semiconductor region; (g) forming a first trench in the first region, the first trench penetrating the first semiconductor region and the second semiconductor region and reaching the first semiconductor layer; (h) forming a gate electrode in the first trench via a gate insulating film; (i) forming a metal layer on the first main surface in the first region, the second region, and a third region in which a Schottky barrier diode is to be formed; having an impurity concentration of the fourth semiconductor region is lower than impurity concentrations of the third semiconductor region and the fifth semiconductor region; the body diode is configured between the fifth semiconductor region and the first semiconductor layer in the second region; the Schottky barrier diode is configured between the metal layer and the first semiconductor layer in the third region.

2. 2. The method of manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b-1) forming the first semiconductor region in the first region, the second region, and the third region; (b-2) forming a second groove in the first main surface of the first semiconductor layer in the second region and the third region, thereby removing a part of the first semiconductor region and leaving another part of the first semiconductor region in the first region; A method for manufacturing a semiconductor device comprising the steps of:

3. 2. The method of manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b-3) forming a first mask film covering the second region and the third region; (b-4) forming the first semiconductor region by implanting the first conductive type impurity into the first semiconductor layer in the first region exposed from the first mask film; A method for manufacturing a semiconductor device comprising the steps of:

4. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the step (c) comprises forming the second semiconductor region selectively in the first region using a second mask film that covers the second region and the third region.

5. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are made of silicon carbide.

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