System and method for identifying potential reliability defects in semiconductor devices - Patents.com

Abstract

A system and method for identifying potential reliability defects (LRDs) in a semiconductor device is configured to perform one or more stress tests on at least some of a plurality of wafers received from one or more in-line sample analysis tools using one or more stress test tools to determine a pass set of the plurality of wafers and a fail set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the fail set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more chains of die failure due to the one or more potential reliability defects (LRDs), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more chains of die failure due to the LRDs.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to a system and method for identifying potential reliability defects in semiconductor devices. [Background technology]

[0002] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 62 / 967,964, filed on January 30, 2020, which application is hereby incorporated by reference in its entirety.

[0003] The creation of semiconductor devices typically requires hundreds or thousands of processing steps to form a functioning device. During these processing steps, various inspection and / or metrology measurements can be performed to identify defects and / or monitor various parameters on the devices. Electrical tests can also be performed to confirm or evaluate the functionality of the device. However, while some of the detected defects and metrology errors are very significant in clearly indicating device failure, smaller variations can also cause early reliability failure of the device after exposure to their working environment. Risk-averse users of semiconductor devices, such as automotive, military, aerospace, and medical applications, are beginning to expect failure rates beyond the current parts-per-million (PPM) levels and into the parts-per-billion (PPB) range. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 1,076,128 Summary of the Invention [Problem to be solved by the invention]

[0005] Given the ever-increasing demand for semiconductor devices in automotive, military, aircraft and medical applications, recognizing and controlling reliability defects is key to meeting such industrial demands. Accordingly, it is desirable to provide a reliability defect detection system and method. [Means for solving the problem]

[0006] A system according to one or more embodiments of the present disclosure is disclosed. In an exemplary embodiment, the system includes a controller communicatively coupled to one or more in-line sample analysis tools and one or more stress test tools. In an exemplary embodiment, the controller includes one or more processors configured to execute program instructions to execute one or more stress tests on at least some of the plurality of wafers with the one or more stress test tools to identify a passing set of the plurality of wafers and a failing set of the plurality of wafers. In an exemplary embodiment, the plurality of wafers are received from the one or more in-line sample analysis tools. In an exemplary embodiment, each of the plurality of wafers includes a plurality of layers. In an exemplary embodiment, each of the plurality of layers includes a plurality of dies. In one illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a reliability hit-back analysis on at least a portion of the failing set of the plurality of wafers, and in one illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains due to one or more latent reliability defects (LRDs).Additionally, in one illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a geographic hit-back analysis of one or more geographic locations of one or more die reject chains due to the LRD.

[0007] A method according to one or more embodiments of the present disclosure is disclosed. In accordance with an exemplary embodiment, the method may include, but is not limited to, performing one or more stress tests on at least some of the wafers with one or more stress test tools to identify a pass set of the wafers and a fail set of the wafers. In an exemplary embodiment, the wafers are received from one or more in-line sample analysis tools. In an exemplary embodiment, each wafer of the wafers includes a plurality of layers. In an exemplary embodiment, each layer of the layers includes a plurality of dies. In an exemplary embodiment, the method may include, but is not limited to, performing a reliability hitback analysis on at least some of the fail set of the wafers. In accordance with certain illustrative embodiments, the method may include, but is not limited to, performing a reliability hitback analysis to determine one or more geographic locations of one or more die-rejected chains due to one or more potential reliability defects (LRDs). In accordance with certain illustrative embodiments, the method may include, but is not limited to, performing a geographic hitback analysis to one or more geographic locations of one or more die-rejected chains due to one or more LRDs.

[0008] A system according to one or more embodiments of the present disclosure is disclosed. In an exemplary embodiment, the system includes one or more in-line sample analysis tools. In an exemplary embodiment, the system includes one or more stress test tools. In an exemplary embodiment, the system includes a controller communicatively coupled to the one or more in-line sample analysis tools and the one or more stress test tools. In an exemplary embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform one or more stress tests on at least some of the plurality of wafers with the one or more stress test tools to identify a pass set of the plurality of wafers and a fail set of the plurality of wafers. In an exemplary embodiment, the plurality of wafers are received from the one or more in-line sample analysis tools. In an exemplary embodiment, each wafer of the plurality of wafers has a plurality of layers. In an exemplary embodiment, each layer of the plurality of layers includes a plurality of dies. In an exemplary embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a reliability hit-back analysis on at least a portion of the rejection set of the plurality of wafers. In an exemplary embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform the reliability hit-back analysis to determine one or more geographic locations of one or more die rejection chains due to one or more potential reliability defects (LRDs).Additionally, in one illustrative embodiment, the controller includes one or more processors configured to execute program instructions that cause the one or more processors to perform a geographic hitback analysis for one or more geographic locations of one or more die reject chains due to the LRD.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention.

[0010] Those skilled in the art will be able to better appreciate the many advantages of the present disclosure by referring to the accompanying drawings, in which: [Brief description of the drawings]

[0011] [Figure 1A] FIG. 1 is a block diagram of a potential reliability defect (LRD) identification system according to one or more embodiments of the present disclosure. [Figure 1B] FIG. 1 is a block diagram of an LRD identification system according to one or more embodiments of the present disclosure. [Figure 2A] FIG. 2 is a conceptual diagram of in-line defect inspection results for multiple layers of a wafer in accordance with one or more embodiments of the present disclosure. [Figure 2B] FIG. 1 is a conceptual diagram of an end-of-line (EOL) sort yield map for a wafer in accordance with one or more embodiments of the present disclosure. [Figure 2C] FIG. 1 is a conceptual diagram of a hit-back analysis for defect aggregations based on in-line defect inspection results and end-of-line (EOL) sort yield map in multiple layers of a wafer in accordance with one or more embodiments of the present disclosure. [Diagram 3]FIG. 1 is a plot illustrating the relationship between overlay threshold and total defect hits in accordance with one or more embodiments of the present disclosure. [Figure 4] FIG. 1 is a flow diagram depicting steps performed in a method for LRD identification in accordance with one or more embodiments of the present disclosure. [Figure 5A] FIG. 5 is a conceptual diagram of an LRD identification system 500 according to one or more embodiments of the present disclosure. [Figure 5B] FIG. 2 is a depiction of LRD observed on a wafer in accordance with one or more embodiments of the present disclosure. [Figure 5C] 1 is a bar graph depicting the relationship between the type of LRD observed on a wafer and the frequency of the LRD type in accordance with one or more embodiments of the present disclosure. [Figure 6] FIG. 1 is a flow diagram depicting steps performed in a method utilizing an LRD identification system and method according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. The present disclosure has been specifically shown and described with reference to certain embodiments and specific features thereof. The embodiments described herein should be considered as illustrative and not limiting. It will be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the present disclosure.

[0013] Embodiments of the present disclosure are directed to systems and methods for identifying potential reliability defects (LRDs) in semiconductor devices. In particular, embodiments of the present disclosure are directed to identifying sources of LRDs in a baseline manufacturing process for devices, including but not limited to semiconductor devices. Certain embodiments of the present disclosure are directed to detecting LRDs that do not result in manufacturing / test failures or lead to immediate device failure during operation, but may lead to early failure of the device during operation when used in a work environment.

[0014] Defects that occur during the manufacturing process can have a wide range of effects on the performance of devices in the field. For example, "killer" defects can result in immediate device failure, while many minor defects can have little or no effect on the performance of the device over its entire life. However, there are defect classes that are referred to herein as potential reliability defects (LRDs) (or reliability defects or latent defects in the context of this disclosure), i.e., defects that do not lead to failures during manufacturing / testing or immediate device failure during operation, but may lead to early failure of the device during operation when used in the working environment. LRDs can be caused by defect mechanisms within the manufacturing line operating at nominal conditions without excursions. LRDs are not yield-limiting and therefore are not or cannot be identified by traditional e-test and baseline Pareto methods.

[0015] Note that for purposes of this disclosure, "LRD" may refer to a single potential reliability defect or multiple potential reliability defects. Also, for purposes of this disclosure, the terms "manufacturing process" and "fabrication process" may be considered equivalent, as may variations of each of those terms (e.g., "manufacturing line" and "fabrication line," etc.).

[0016] Various strategies can be used to monitor or control device reliability based on the fabrication LRD baseline Pareto of semiconductor devices. These various strategies allow the fabrication process to achieve baseline reliability defect control at parts-per-million (PPM) levels depending on the chip complexity and size. Current requirements in high-end semiconductor fabrication industries (e.g., automotive, military, aerospace, and medical industries) are for parts-per-billion (PPB) control levels, calling for improved reliability defect source identification systems and methods.

[0017] One strategy would be to complement end-of-line (EOL) reliability testing with burn-in or other stress testing. Semiconductor device manufacturers currently use EOL electrical reliability testing in conjunction with burn-in and other stress testing to generate electrical reliability or ("rel") Pareto. This methodology is primarily limited by the type of information that can be collected with e-test; failure mechanism identification typically only provides reference to the electrical characteristics of the failure (e.g., "type 1 failure" or "single bit failure"). While this may provide clues to the source, it often does not provide enough useful information about the root cause in the semiconductor fabrication process to effectively guide engineering improvement studies. In practice, EOL reliability testing complemented with burn-in and other stress testing is often used to identify the source of intrinsic defects (e.g., rather than extrinsic mechanisms such as defects) and to quantify reliability rates (e.g., rather than classifying failures or enabling their root cause identification).

[0018] For example, electrical testing of a die can be performed to evaluate the functionality of one or more aspects of the die as data for reliability analysis. In addition, burn-in and other stress tests can be performed at any point during the manufacturing process, including, but not limited to, pre-burn-in electrical wafer sort and final test (e.g., e-test) and post-burn-in electrical testing. Semiconductor devices that fail the electrical test step can be separated from other semiconductor devices that pass. For example, the die or wafer can be removed from the supply chain (e.g., scrapped) or flagged for further testing.

[0019] However, electrical testing alone does not provide enough information to meet stringent reliability standards while maintaining cost and throughput targets. For example, post-burn-in electrical testing allows accurate analysis of die functionality since the die is in near-final condition, but may not be practical on a large scale due to cost, time, or potential long-term reliability issues. For example, any production electrical test may provide pass / fail information adequate to identify devices that have already failed fully or partially, but may not be adequate to identify devices that may fail later (e.g., devices with latent defects). For example, it is often impractical, and sometimes impossible, to fully characterize each die using electrical test, resulting in slippages in the electrical test. For example, there may be defects that are theoretically possible in a particular circuit layout but cannot be detected using electrical test, and thus may not be detected by a "perfect" test strategy. It is noted that because it is neither cost-effective nor practical to fully characterize all sides of each die, the selected test strategy may deviate from an otherwise "complete" or otherwise optimized test strategy. For example, but not limited to, incomplete test coverage may occur due to untestable areas of a particular circuit, analog circuits that may be difficult to test (e.g., high voltage analog circuits), or circuits that may require cumbersome simultaneous or sequential driving of multiple portions. For purposes of this disclosure, the term "test coverage" may be used to broadly describe a metric used to evaluate the performance of a test strategy.

[0020] Another strategy would be to combine standard in-line defect baseline Pareto methodology with the inference that the defects causing reliability problems are the same or similar to the yield-limiting defects or ("yield") Pareto. Semiconductor device manufacturers generate an in-line defect baseline Pareto for yield-limiting defects. This information can be used in reliability studies under the assumption that defect-driven (external) reliability failure sources are proportional to the yield-limiting failures. One difficulty with this approach is that the potential reliability defect Pareto will almost certainly differ from the yield-limiting Pareto in both relative frequency and priority. This uncertainty can be partially reduced by biasing the yield Pareto with the reliability Pareto (or rel Pareto). However, it is noted that some LRDs are not correlated with the yield-limiting defects. It is also noted that many LRDs are only formed within a narrow size range for the yield-limiting defects, and that size is often device or technology specific.

[0021] Another strategy may involve physical failure analysis (PFA) of field reliability returns. Automotive semiconductor device manufacturers typically require PFA of field reliability returns. For example, these may be from first-tier component suppliers, assembly at the automotive OEM, or warranty field returns from the end consumer. These field reliability returns may not provide enough information to generate a useful Pareto of in-line reliability sources. For example, there may be a lack of statistical significance because the number of PPM failures is too small to reach a comprehensive understanding of the baseline reliability Pareto from a handful of field returns. Also, for example, there may be a significant delay (e.g., potentially years) between production and observation, since the information that a field return may provide reflects reliability issues in the semiconductor fabrication process at the time the failed device was manufactured. Overall, PFA is expensive, time-consuming, and / or often inconclusive or inaccurate.

[0022] One limitation of the proposed strategies is that the root cause of the failure is destroyed by the LRD activation process or by secondary damage originating from the PFA retardation process.

[0023] As can be appreciated, the labels "potential defect," "reliability defect," "potential reliability defect" or LRD, etc. are used herein for illustrative purposes only and should not be construed as limiting. Furthermore, the defect-based reliability determination and control examples described herein and associated with specific types of defects (e.g., potential defect, reliability defect, LRD, etc.) are also presented for illustrative purposes only and should not be construed as limiting. Rather, in general, the various defect-based reliability prediction methodologies can be used to identify any type of defect or types of defects, regardless of the label used to describe the defect.

[0024] 1A-6, a system and method for identifying LRDs in a semiconductor device according to one or more embodiments of the present disclosure will now be described.

[0025] 1A and 1B generally depict a block diagram of an LRD identification system 100 in accordance with one or more embodiments of the present disclosure.

[0026] In one embodiment, the system 100 includes at least one inspection tool 102 (e.g., an in-line specimen analysis tool) that can detect defects in one or more layers of the specimen 104. The system 100 can generally include any number or type of inspection tools 102. One example of an inspection tool 102 is an optical inspection tool configured to detect defects upon interrogation of the specimen 104 with light from any source, such as, but not limited to, a laser source, a lamp source, an x-ray source, a broadband plasma source, or the like. Another example of an inspection tool 102 is a beam-based inspection tool configured to detect defects upon interrogation of the specimen 104 with one or more beams, such as, but not limited to, an electron beam, an ion beam, a neutral beam, or the like. For example, the inspection tool 102 can include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). It should be noted that, for purposes of this disclosure, the at least one inspection tool 102 may be representative of a single inspection tool 102 or a group of inspection tools 102 .

[0027] Also, in some embodiments, the specimen 104 is a wafer of a plurality of wafers, each of which has a plurality of layers. Also, in some embodiments, each of the plurality of layers includes a plurality of dies. Also, in some embodiments, each of the plurality of dies includes a plurality of blocks. For purposes of this disclosure, a defect may be considered to be any deviation of a fabricated layer or pattern within a layer from a design characteristic, such as, but not limited to, a physical, mechanical, chemical, or optical characteristic. Furthermore, a defect may have any size relative to a die or a feature thereon. That is, a defect may be smaller than a die (e.g., on the scale of one or more patterned features) or larger than a die (e.g., a wafer-scale scratch or part of a pattern). One example of a defect would be a deviation in thickness or composition of a specimen layer before and after patterning. Another example of a defect would be a deviation in size, shape, orientation, or position of a patterned feature. Another example of a defect may be a defect associated with a lithography and / or etching process, such as, but not limited to, a bridge (or lack thereof) between adjacent structures, a pit or hole, etc. Another example of a defect may be a damaged portion of the specimen 104, such as, but not limited to, a scratch, a chip, etc. For example, the severity of the defect (e.g., the length of the scratch, the depth of the pit, a measurement of the size or polarity of the defect, etc.) may be significant and may be taken into consideration. Another example of a defect may be a foreign particle that has become embedded in the specimen 104. Thus, as can be appreciated, the example defects in this disclosure are presented for illustrative purposes only and should not be construed as limiting.

[0028] Additionally, in one embodiment, the system 100 includes at least one metrology tool 106 (e.g., an in-line specimen analysis tool) that can measure one or more characteristics of the specimen 104 or one or more layers thereon. For example, the metrology tool 106 can characterize characteristics such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, lithography processing parameters (e.g., illumination intensity or dose during a lithography step), etc. This configuration of metrology tool 106 can provide information about the fabrication of the specimen 104, one or more layers thereon, or one or more dies thereon, that can be related to the probability of fabricating defects that may lead to reliability issues in the final fabricated device. For purposes of this disclosure, the at least one metrology tool 106 can be a representation of a single metrology tool 106 or a group of metrology tools 106.

[0029] In one embodiment, the system 100 also includes at least one stress test tool 108 for testing the functionality of a portion or portions of the fabricated device. Any number or type of stress test tools 108 may be incorporated into the system 100 to characterize, e.g., test, inspect, etc., a portion or portions of the fabricated device at any point in its fabrication cycle. An example of a stress test tool 108 may be, but is not limited to, a pre-burn-in or post-burn-in electrical test tool configured to heat the specimen 104 (e.g., an oven or other heat source), remove heat from the specimen 104 (e.g., a freezer or other cold source), operate the specimen 104 at an improper voltage (e.g., a power supply), etc.

[0030] According to one embodiment, the system 100 includes a controller 110. The controller 110 may include one or more processors 112 configured to execute program instructions maintained on a memory 114 (e.g., a storage medium, a memory device, etc.). Additionally, the controller 110 may be communicatively coupled to any of the components of the system 100, including, but not limited to, the inspection tool 102, the metrology tool 106, the stress test tool 108, etc.

[0031] In this configuration, the one or more processors 112 in the controller 110 may perform any of a variety of process steps described elsewhere in this disclosure, such as characterizing one or more of the plurality of wafers with high-sensitivity defect inspection of one or more critical layers, performing electrical wafer sorting (EWS) on the plurality of wafers based on the characterization of the one or more critical layers of the one or more wafers with high-sensitivity defect inspection, performing hit-back analysis on at least a portion of a set of wafers that fail the EWS, performing one or more stress tests on at least a portion of a set of wafers that pass the EWS, and performing one or more stress tests on wafers that pass the EWS and that were subjected to the one or more stress tests. The system may be configured to perform one or more of the following: testing at least a portion of the set; performing a reliability hit-back analysis on at least a portion of the set of wafers that pass the EWS and fail the one or more stress tests; analyzing the hit-back analysis and a combination of the reliability hit-back analysis to determine geographic locations of failures due to the LRD; performing a geographic hit-back analysis on the geographic locations of failures due to the LRD; generating one or more defect images that include the LRD; and / or generating one or more statistical representations of the LRD.

[0032] The one or more processors 112 of the controller 110 may include any processor or processing element known in the art. For purposes of this disclosure, the terms "processor" and "processing element" may be broadly defined to include any device having one or more processing or logic elements, such as one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs). In this sense, the one or more processors 112 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in a memory). According to one embodiment, the one or more processors 112 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a networked computer, or any other computer system configured to execute appropriately configured programs to operate or interact with the system 100 as described elsewhere in this disclosure.

[0033] The memory 114 may include any storage medium known in the art suitable for storing program instructions executable by the associated processor(s) 112. For example, the memory 114 may include a non-transitory storage medium. For example, the memory 114 may include, but is not limited to, a read-only memory (ROM), a random access memory (RAM), a magnetic or optical storage device (e.g., disk), a magnetic tape, a solid state drive, etc. It is further noted that the memory 114 may be housed in a common controller housing with the processor(s) 112. In some embodiments, the memory 114 may be located remotely relative to the physical location of the processor(s) 112 and the controller 110. For example, the processor(s) 112 of the controller 110 may access a remote memory (e.g., a server) accessible over a network (e.g., the Internet, an intranet, etc.).

[0034] In one embodiment, a user interface 116 is communicatively coupled to the controller 110. In one embodiment, the user interface 116 may include, but is not limited to, one or more desktops, laptops, tablets, etc. In one embodiment, the user interface 116 may include a display through which data from the system 100 is displayed to a user. The display of the user interface 116 may include any display known in the art. Examples of such displays may include, but are not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a CRT display, etc. Those skilled in the art should recognize that any display device that may be integrated with the user interface 116 is suitable for implementation in the present disclosure. In one embodiment, a user may input selections and / or commands through a user input device on the user interface 116 in response to the data displayed to the user.

[0035] In accordance with an embodiment, the system 100 includes at least one semiconductor manufacturing tool or semiconductor fabrication tool 118. For example, the semiconductor fabrication tool 118 may include any tool known in the art, including, but not limited to, an etcher, scanner, stepper, cleaner, etc. The fabrication process may involve fabricating a plurality of dies distributed over a surface of a specimen (e.g., a semiconductor wafer, etc.), with each die having a plurality of patterned layers of material that form device components. Each patterned layer may be created by the semiconductor fabrication tool 118 through a series of steps, including material deposition, lithography, etching to create a pattern of interest, and / or one or more exposure steps (e.g., as performed by a scanner, stepper, etc.). For purposes of this disclosure, the at least one semiconductor fabrication tool 118 may be a representation of a single semiconductor fabrication tool 118 or a group of semiconductor fabrication tools 118.

[0036] In some embodiments, LRDs are identified using some combination of in-line sample analysis tools (e.g., inspection tool 102 or metrology tool 106) after one or more processing steps (e.g., lithography, etch, etc.) of layers of interest in the dies, in which case defect detection at the stages of the manufacturing process may be referred to as in-line defect detection.

[0037] It should be noted that the embodiment depicted in Figure 1A and the embodiment depicted in Figure 1B may, for purposes of this disclosure, be considered separate systems 100 or portions of the same system 100. It is additionally noted that the components in the system 100 depicted in Figure 1A and the components in the system 100 depicted in Figure 1B may communicate directly or through a controller 110.

[0038] 2A-2C are conceptual diagrams of defect clusters in multiple layers of a specimen 104 according to one or more embodiments of the present disclosure.

[0039] In advanced yield-based hit-back analysis methodologies and processes for defect-limited yield Pareto, EOL yield failures are correlated to the in-line sources that cause the failures. In many cases, PFA is guided by EOL yield failures in the form of cross-sectional TEM confirmation of physical defects, whose physical locations are then overlaid on in-line defect locations for correlation with in-line learning. In many cases, this analysis provides clear causal attribution for yield failures, but is slow (e.g., on the order of a few dozen per week) and can be blind to defect modes that are difficult to localize or image in a TEM.

[0040] In advanced yield-based hit-back analysis methodologies and processes for defect-limited yield Pareto, the EOL electrical failure locations are directly overlaid on the in-line defect data. For example, advanced logic design methodologies and analysis tools can localize electrical failures to the "chain" locations where they are likely to occur. In addition, advanced technology allows in-line inspection to be guided to potential chain location failures based purely on the design layout.

[0041] As depicted in FIG. 2A, various defects 200 can be detected within one or more layers 202 (e.g., three layers 202 depicted in FIG. 2A) of the specimen 104 by any of the components of the system 100, including but not limited to the inspection tool 102, metrology tool 106, etc.

[0042] As illustrated in FIG. 2B, in addition to the various defects 200 detected within one or more layers 202 of the specimen 104, an EOL sort yield map 204 can provide reference information regarding one or more locations 206 on the specimen 104 that contain one or more die reject chains 208.

[0043] 2C , one or more layers 202 containing one or more defects 200 and an EOL sort yield map 204 including one or more locations 206 with one or more die reject chains 208 can be graphically represented as a hit-back analysis map 210 that aggregates all detected defects in a single top view of the specimen 104. In the hit-back analysis map 210, the potential die reject chains 208 are overlaid with in-line inspection results to determine one or more miss locations 212 and / or one or more hit locations 214. For example, a miss location 212 may be one where the one or more defects 200 do not overlap and / or are not statistically determined to cause the one or more die reject chains 208. Also for example, a hit location 214 may be one or more defects 200 that overlap and / or that are determined to have a selected statistical probability of causing one or more die reject chains 208 .

[0044] The miss(s) 212 and / or the hit(s) 214 may be represented by an area based on the die reject chain(s) 208. For example, the area may display a threshold (e.g., in microns (μm)) that will cause the die reject chain with a selected percentage chance of having a defect in the failure range. The miss(s) 212 and / or the hit(s) 214 may have characteristics, such as, but not limited to, film or layer thickness, film composition, wafer flatness, wafer topography, resistivity, local stress measurements, or critical dimension measurements, that may indicate hot spots, i.e., spatial patterns where additional defects are likely to occur or where reliability may be particularly affected.

[0045] FIG. 3 illustrates a plot 300 of hits (counts) versus overlay threshold size (in μm) according to one or more embodiments of the present disclosure. In some embodiments, area 302 representing a small overlay threshold, i.e., an area that would be on the left side of plot 300, may miss defects that cause failures, resulting in overlay failures. For example, area 302 may be dependent on an in-line sample analysis tool defect location accuracy (DLA). In some embodiments, area 304 representing a large overlay threshold, i.e., an area that would be on the right side of plot 300, may capture defects that do not cause failures, resulting in false positives. In some embodiments, area 306 representing an optimal overlay threshold may be near the middle of plot 300. For example, area 306 may be large enough to capture the in-line sample analysis tool DLA, but small enough that the statistical probability of an LRD false positive determination is low or reduced. For example, but not by way of limitation, an area exhibiting at least 5 μm along one direction may be selected.

[0046] Additionally, stacking the dies allows for graphical comparison of dies originating from different locations on a specimen 104 or dies on different specimens 104. If performed correctly, the hit back capture metric (percentage) can quantify the number of failures associated with in-line defects. For example, hit back capture rates of over 70% may not be uncommon in an in-line monitoring process.

[0047] 4 and 5A-5C generally depict an LRD methodology or process as described in accordance with one or more embodiments of the present disclosure. An LRD methodology or process according to one embodiment incorporates an LRD baseline Pareto using overlay-based hit-back analysis in conjunction with high temperature operating life (HTOL) burn-in.

[0048] 4 depicts a flow diagram of a method or process 400 illustrating an LRD methodology or process in accordance with one or more embodiments of the present disclosure. It should be noted that the steps of the method or process 400 may be performed, in whole or in part, by the system 500 depicted in FIGS. 5A-5C. However, it should be further recognized that the method or process 400 is not limited to the system 500 depicted in FIGS. 5A-5C, and that all or a portion of the steps of the method or process 400 may be performed by another or alternative system level embodiment.

[0049] It should be noted that any step of the method or process 400 may incorporate any specified die within any specified number of specimens 104. For example, a population may include, but is not limited to, die selected from a single specimen 104, multiple specimens 104 within a single lot (e.g., production lot), or specimens 104 selected across multiple lots.

[0050] In step 402, one or more of the wafers are characterized with high sensitivity defect inspection targeted at one or more critical layers. Box 502, according to one embodiment, represents at least a portion of the system 100 depicted in FIGS. 1A and 1B. In this configuration, the steps of the method or process 400 may be performed in whole or in part by the system 100 depicted in FIGS. 1A and 1B. In box 502, the wafers are fabricated through a number of steps (e.g., tens, hundreds, or thousands) performed by a number of fabrication processes. For example, the fabrication may be performed by at least one semiconductor fabrication tool 118.

[0051] Once prepared, one or more of the wafers undergo a complete or near complete SEM review, with highly sensitive inspection (e.g., broadband plasma inspection, etc.) targeting all critical layers (e.g., 20-50 layers).

[0052] For example, a wafer or wafers may have 20-50 critical layers depending on the design rules of the wafer or wafers. In selective patterned wafer inspection systems, design-driven technologies can define small inspection areas (e.g., on the order of a few microns) that focus exclusively on critical features. Using these design-driven technologies to inspect features associated with potential chain failures results in inspection results that consist of defects that are highly correlated to end-of-line yield. These more direct techniques allow for faster turnaround of analysis, faster sampling (hundreds of defects per wafer), and better causation of defect modes that are difficult to find physically at EOL.

[0053] Also for example, the SEM review can be 100%. The inspection tool 102 attribute information can be used in conjunction with on-tool deterministic binning or machine learning analysis systems to recognize potential LRDs and determine the types of critical defects. This can be performed directly on the inspection tool 102, on the metrology tool 106, or in an offline analysis system.

[0054] Also, according to some embodiments, processing of the wafer can be continued (e.g., through one or more fabrication processes) while selecting additional layers subsequent to the critical layer(s) and observing the change in morphology associated with the critical defect, e.g., removing the defect by subsequent cleaning, embedding the defect in a deposited film, decorating the defect with an etch-back process, etc.

[0055] In step 404, electrical wafer sorting (EWS) is performed on the wafers based on the characterization of the critical layer or layers of the wafer or wafers by high sensitivity defect inspection. In box 504, the wafers are subjected to wafer level testing with the die physically present on each wafer and packaged. The wafers are sorted into EWS pass and EWS fail sets of the wafers.

[0056] In step 406, a hit-back analysis is performed on at least a portion of the set of wafers that failed the EWS. In box 506, a hit-back analysis is performed on a portion or all of the set of wafers that failed the EWS. The wafer-level tests for the failed set of wafers are associated with one or more critical layers using overlay. This hit-back analysis process is depicted and described in Figures 2A-2C and 3.

[0057] In step 408, one or more stress tests are performed on at least a portion of the set of EWS passing wafers. In box 508, one or more stress tests are performed on some or all of the set of EWS passing wafers. For example, the set of EWS passing wafers may include all dies or a target sample of dies with reliability related defects. For example, an on-tool deterministic binning or machine learning analysis system may determine which set of wafers passed the EWS. The EWS passing set of wafers is sorted into a stress test passing set and a stress test failing set of wafers.

[0058] Note that removal of the EWS failing set of wafers in step 404 / box 504 before application of the stress test bank in step 408 / box 508 results in non-LRD related information being subtracted before the stress test bank is applied. It is additionally noted that the stress test bank or banks may need to be controlled to ensure that good wafers are not accidentally damaged, resulting in false negatives, as well as that bad wafers are not passed, resulting in false positives.

[0059] The battery or batteries of stress tests may include a high acceleration factor burn-in, e.g., an intensive HTOL burn-in test. For example, the HTOL burn-in test may stress the device for a period of time at one or more of high temperature, high voltage, and / or dynamic operation. In some embodiments, the battery or batteries of stress tests may include a burn-to-failure test. For example, the wafer may be stressed to activate the LRD by one or more of heating the wafer in an oven and testing at a high temperature, removing the wafer from the oven and testing at a low temperature (e.g., -20 degrees Celsius (°C)), testing at an incorrect voltage (e.g., 5V instead of 3V), etc.

[0060] At least a portion of the set of wafers that pass the EWS and that have been subjected to the set or sets of stress tests are subjected to a final test in step 410. The final test can result in removal of the set of wafers that pass the stress test after the set or sets of stress tests in box 510. Note that the removal of the set of wafers that fail the EWS in step 404 / box 504 before the set or sets of stress tests in step 408 / box 508 and the removal of the set of wafers that pass the stress test after the set or sets of stress tests allow for wafer discrimination by LRD.

[0061] In step 412, a reliability hit-back analysis is performed on the set of wafers that pass the EWS and fail the stress test or tests. In box 512, a hit-back analysis is performed on some or all of the set of wafers that fail the EWS. The wafer-level tests of the failing set of wafers are associated with the critical layer or layers using overlay. The hit-back analysis process is depicted and described in Figures 2A-2C and 3. The reliability hit-back analysis provides a reference to the LRDs that cause reliability failures before the LRDs are activated.

[0062] In step 414, the hitback analysis and the reliability hitback analysis are analyzed in conjunction to determine the geographic location of the failure due to the LRD. The analysis in box 514 may include a bitmap analysis and / or a blockchain fault analysis. For example, the bitmap analysis and / or the blockchain fault analysis may determine an (x,y) location for an individual LRD, i.e., locate the failure for the individual LRD. Alternatively, only the reliability hitback analysis may be analyzed to determine the geographic location of the failure due to the LRD.

[0063] In step 416, a geographic hit-back analysis is performed on the geographic location of the LRD-caused failure. In box 516, a geographic hit-back analysis from the electrical die reject chain to the in-line defect location utilizes a geometry-based overlay algorithm to combine the point-based in-line defect location with the area-based EOL chain notification. For example, an (x,y) mapping can be used at the electrical die reject chain location along with layer information. The geographic hit-back analysis overlays information originating from the bitmap analysis and / or block chain failure analysis in box 514 with information originating from a yield management system depicted in box 518. For example, the yield management system in box 518 can receive a result file from the system 100 in box 502 and / or components of the system 100 (e.g., at least one semiconductor fabrication tool 118, etc.). It should be noted that the wafers utilized in this geographic hit-back analysis should be inspected at all critical process steps of the method or process 400 to avoid missing potential causal links that led to the EOL failure. For example, all defects found should be utilized in the analysis, not just those that are classified in a subsequent review step.

[0064] It should be noted that a separate system for recording and storing raw defect information for use during overlay may also be incorporated into the potential reliability defect identification system depicted in FIGS. 5A-5C.

[0065] In step 418, one or more defect images are generated that include the LRD. Now, referring to FIG. 5B, after the geographic hitback analysis of box 516, a gallery or set 520 of defect images 520a is generated. For example, each defect image 520a includes a representation of the LRD 520b that caused the reliability failure, providing useful information about the root cause of the failure before the LRD is activated. Note that showing the LRD 520b in the defect image 520a before the LRD 520b is activated is important because activation of the LRD would make it impossible to determine what caused the failure (e.g., due to partial or complete destruction of the LRD during activation, etc.). For example, copper cladding within the process margin may be identified as a possible LRD that can be reviewed and addressed by an engineering team (e.g., provide value to a manufacturing process, system, or team accordingly) before the copper cladding is destroyed upon activation.

[0066] At step 420, one or more statistical representations of the LRDs are generated. Now, referring to FIG. 5C, after the geographic hitback analysis of box 516, a graph 522 is generated contrasting a number of LRD types and the frequency of each LRD type. According to an example, the graph 522 can be used as an illustration or teaching tool for sustained improvement by reducing the number of LRD types and the frequency of each LRD type, thereby driving sustained improvement in baseline LRD Pareto reduction and thus providing value to businesses employing the in-semiconductor device LRD identification system and method.

[0067] It is noted that the set 520 of defect images 520a and / or the graph 522 may be displayed on the user interface 116 depicted in Figures 1A and 1B and described elsewhere in this disclosure. It is additionally noted that the set 520 of defect images 520a and / or the graph 522 may be displayed on a display device separate from the user interface 116.

[0068] It should be noted that while this potential reliability defect identification system and method may address extrinsic (defect) reliability failures, it is not envisioned to address intrinsic failures (e.g., time-dependent dielectric breakdown, hot carrier injection, etc.).

[0069] Given the descriptions provided throughout this disclosure, one non-limiting combination of embodiments of the system and method for identifying potential reliability defects in a semiconductor device is combining an in-line defect inspection tool (e.g., broadband plasma, etc.) with in-line technology that leverages design data to define small (e.g., micron-order) inspection areas focused on critical patterns, yield management analysis systems and processes, EWS test data, final test data, and stress testing (e.g., HTOL burn-in, etc.). This combination of embodiments of the system and method for identifying LRDs in a semiconductor device provides an accurate description (e.g., textual and / or figurative description) of the LRD baseline in the semiconductor fabrication process with sufficient detail to drive sustained reduction of reliability defects. For example, the system and method for identifying potential reliability defects in a semiconductor device can provide an in-line SEM image of the LRD prior to activation and without collateral damage caused by PFA delayering. For example, the system and method for identifying potential reliability defects in a semiconductor device can provide an LRD Pareto based on actual failure mechanisms instead of resulting electrical characteristics. For example, the system and method for identifying potential reliability defects in a semiconductor device can reduce reliability failures from PPM levels to PPB levels.

[0070] FIG 6 illustrates a method or process 600 utilizing an LRD identification system and method in accordance with one or more embodiments of the present disclosure. It should be noted that the steps of the method or process 600 may implement all or a portion of the method or process 400 illustrated in FIG 4 or the system 500 illustrated in FIG 5A-5C. However, it should be further recognized that the method or process 600 is not limited to the method or process 400 illustrated in FIG 4 or the system 500 illustrated in FIG 5A-5C, and all or a portion of the steps of the method or process 600 may be implemented in another or alternative system level embodiment.

[0071] In step 602, the LRD identification system and method may be utilized at specified intervals to determine changes in LRD within a semiconductor device. According to an embodiment, some or all of the steps of the method or process 400 may be utilized in conjunction with the system 500. For example, a semiconductor device manufacturer may utilize the LRD identification system and method within a semiconductor device at regularly spaced or irregularly spaced intervals to provide a true picture of the LRD Pareto that is constantly changing over time, where the intervals may be defined at least in part by the output of one or more semiconductor fabrication processes, by the time between executions of the one or more semiconductor fabrication processes, or the like.

[0072] In step 604, the selected LRD Pareto items are reviewed in light of the results of the LRD identification system and method. For example, an engineering team selected by a semiconductor device manufacturer can review the top three Pareto items (e.g., selected based on unweighted or weighted frequency of occurrence) and use the in-semiconductor device potential reliability defect identification system and method to better understand process windows, process defect rates, tool defect rates, and other influencing factors for LRD formation.

[0073] In step 606, one or more adjustments are determined for the selected semiconductor fabrication tools based on the review of the selected LRD Pareto items. For example, the engineering teams may determine adjustments, including, but not limited to, process tool recipe changes, updated process tool changes, new process tool changes, new raw material changes, etc. For example, the changes may be to the design specifications of the wafers or dies on the wafers (e.g., film thickness, size, shape, orientation, or location of fabricated features, etc.). The engineering teams may generate control signals, which may be provided to the selected semiconductor fabrication tools via feed-forward or feedback loops (e.g., transmitted via wired or wireless connections, communicated via storage devices, etc.), received by the selected semiconductor fabrication tools, and executed by the selected semiconductor fabrication tools. It is noted, however, that the engineering teams may also manually perform the adjustments.

[0074] In step 608, additional LRD Pareto items are reviewed in light of the results of the LRD identification system and method. For example, since the LRD sources associated with the top three Pareto items are reduced after tuning the semiconductor fabrication tools, the engineering teams can begin working on the new top three Pareto items (e.g., items 4-6 in the results of the LRD identification system and method as an example). In this way, the semiconductor device manufacturer experiences an overall improvement in LRD levels over time. The semiconductor device manufacturer can understand new and reoccurring LRD mechanisms, especially those that are tied to certain technologies but not others.

[0075] It should be noted that the semiconductor device manufacturer may evaluate the effectiveness of changes through its LRD Pareto after some or all of the steps of the method or process 600 through designed experiments on dedicated wafers.

[0076] In this configuration, semiconductor device manufacturers can utilize results from the in-semiconductor device potential reliability defect identification system and method as part of a production audit process and / or production validation to document their commitment to continuous improvement by systematically targeting sources of potential reliability defect issues with appropriate defect reduction activities and to monitor excursions in their semiconductor fabrication processes to determine whether their semiconductor fabrication processes are and / or may be the source of those potential reliability defects.

[0077] It should be noted that the methods or processes 400 and 600 are not limited to the steps and / or sub-steps presented. The methods or processes 400 and 600 may include more or fewer steps and / or sub-steps. The steps and / or sub-steps in the methods or processes 400 and 600 may be performed simultaneously. The steps and / or sub-steps in the methods or processes 400 and 600 may be performed sequentially, for example, in the order presented or in another order. Thus, the above description should be taken as merely illustrative, and not as a limitation on the scope of the present disclosure.

[0078] Further non-limiting examples of how and / or when to utilize the system and method for identifying potential reliability defects in semiconductor devices include U.S. Patent Application No. 17 / 101,856, filed November 23, 2020, and U.S. Patent Application Publication No. 2020 / 0133636, issued September 1, 2020, both of which are incorporated herein by reference in their entireties. For example, the system and method for identifying potential reliability defects in semiconductor devices can provide an understanding of how and / or when to apply part average testing (PAT), in-line part average testing (I-PAT), and geographic part average testing (G-PAT) to screen and monitor wafers as described in the above-incorporated references.

[0079] Thus, one advantage of the present disclosure is that hitbacks are performed on final test data after intensive HTOL burn-in or other stress tests designed to activate LRDs and highlight them as defects. Another advantage of the present disclosure is that analysis software scans the chain data by performing test overlays to remove yield-limiting defects from the data set. Another advantage of the present disclosure is that defect evolution can be observed by capturing in-line SEM images at multiple layers.

[0080] The subject matter described herein at various times shows various components embedded within or connected to other components. As will be appreciated, such illustrated configurations are merely exemplary, and many other configurations can be implemented to achieve the same functionality. Conceptually, any arrangement of components that can achieve the same functionality is effectively "associated" with one another to achieve the desired functionality. Thus, any two components in this application that are combined to achieve a particular functionality can be considered to be "associated" with one another to achieve the desired functionality, regardless of the configuration or intervening components. Similarly, any two components that are so associated can also be viewed as "connected" or "coupled" to one another to achieve the desired functionality, and any two components that can be so associated can also be viewed as "combinable" with one another to achieve the desired functionality. Examples of coupleable include, but are not limited to, components being capable of and / or physically interacting with each other, and / or components being capable of and / or wirelessly interacting with each other, and / or components being capable of and / or logically interacting with each other.

[0081] The present disclosure and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes in the form, construction and arrangement of the parts may be made without departing from the disclosed subject matter or diminishing all of its essential advantages. The form described is merely illustrative, and it is the intent of the following claims to encompass and embrace all such modifications. Moreover, it is the appended claims which define the invention.

Claims

1. a controller communicatively coupled to one or more in-line sample analysis tools and one or more stress test tools, the controller having one or more processors configured to execute program instructions, the one or more processors: characterizing at least some of the plurality of wafers; performing electrical wafer sorting (EWS) on the plurality of wafers based on the characterization, thereby distinguishing between an EWS pass set of the plurality of wafers and an EWS fail set of the plurality of wafers; performing one or more stress tests with the one or more stress test tools on at least a portion of the EWS pass set of the plurality of wafers to identify a pass set of the plurality of wafers and a fail set of the plurality of wafers, wherein the plurality of wafers were received from the one or more in-line sample analysis tools, each wafer of the plurality of wafers has a plurality of layers, and each layer of the plurality of layers includes a plurality of dies; performing a reliability hitback analysis on at least a portion of the rejected set of the plurality of wafers; analyzing the reliability hit-back analysis to determine one or more geographic locations of one or more die failure chains due to one or more potential reliability defects (LRDs); The system performs a geographic hit-back analysis on the one or more geographic locations of the one or more die-reject chains due to the LRD.

2. 2. The system of claim 1, wherein the controller comprises the one or more processors configured to execute the program instructions, the one or more processors: performing a yield hit-back analysis on at least a portion of the EWS rejected set of the plurality of wafers; The system analyzes a combination of the yield hit-back analysis and the reliability hit-back analysis to determine one or more geographic locations of chains of die rejects due to the LRD.

3. 3. The system of claim 2, wherein in at least one of the reliability hit-back analysis, the geographic hit-back analysis, and the yield hit-back analysis, a hit-back analysis map is generated by overlaying an end-of-line (EOL) sort yield map on a merged set of images representing a plurality of layers of a wafer of the plurality of wafers, the hit-back analysis map including an overlay threshold, the overlay threshold being selected to take into account in-line sample analysis tools and to reduce the statistical probability of LRD false positive determinations.

4. 4. The system of claim 3, wherein a wafer of the plurality of wafers is rejected by the EWS when the EOL sort yield map includes the one or more die rejection chains and the hit-back analysis map includes one or more defects that are determined for at least some of the one or more defects to cause at least some of the one or more die rejection chains with a selected statistical probability.

5. 3. The system of claim 2, wherein the combination of the yield hit-back analysis and the reliability hit-back analysis is analyzed with at least one of a bitmap analysis and a blockchain failure analysis.

6. 2. The system of claim 1, wherein the controller comprises the one or more processors configured to execute the program instructions, the one or more processors: generating one or more defect images including the LRD; and generating one or more statistical representations comprising said LRD; A system that performs at least one of the following:

7. The system of claim 6, further comprising: The system comprises one or more user interfaces communicatively coupled to the controller, the one or more user interfaces configured to display at least one of the one or more defect images including the LRD and the one or more statistical representations including the LRD.

8. 7. The system of claim 6, wherein the controller comprises the one or more processors configured to execute the program instructions, the one or more processors:

1. A system for determining one or more adjustments for one or more semiconductor fabrication tools, wherein the one or more adjustments are determined based on review of at least one of the one or more defect images that include the LRD and the one or more statistical representations that include the LRD.

9. 9. The system of claim 8, wherein the controller comprises the one or more processors configured to execute the program instructions, the one or more processors: A system for generating one or more control signals based on the determined adjustment(s).

10. 10. The system of claim 9, wherein the controller comprises the one or more processors configured to execute the program instructions, the one or more processors: The system provides the one or more control signals to the one or more semiconductor fabrication tools via at least one of a feedforward loop and a feedback loop.

11. 2. The system of claim 1, wherein the one or more in-line specimen analysis tools: A system comprising at least one of an inspection tool and a metrology tool.

12. 2. The system of claim 1, wherein the one or more stress testing tools include at least one of a pre-burn-in electrical testing tool and a post-burn-in electrical testing tool.

13. 13. The system of claim 12, wherein the one or more stress testing tools are configured to at least one of: heat at least some of the plurality of wafers; remove heat from at least some of the plurality of wafers; and operate at least some of the plurality of wafers at an improper voltage.

14. Characterizing at least some of a plurality of wafers received from one or more in-line sample analysis tools; performing electrical wafer sorting (EWS) on the plurality of wafers based on the characterization, thereby distinguishing between an EWS pass set of the plurality of wafers and an EWS fail set of the plurality of wafers; performing one or more stress tests with one or more stress test tools on at least a portion of the EWS pass set of the plurality of wafers to identify a pass set of the plurality of wafers and a fail set of the plurality of wafers, wherein the plurality of wafers were received from one or more in-line sample analysis tools, wherein each wafer of the plurality of wafers has a plurality of layers, and wherein each layer of the plurality of layers includes a plurality of dies; performing a reliability hitback analysis on at least a portion of the rejected set of the plurality of wafers; analyzing the reliability hit-back analysis to determine one or more geographic locations of one or more die failure chains due to one or more potential reliability defects (LRDs); A method for performing a geographic hit-back analysis on the one or more geographic locations of the one or more die-reject chains due to the LRD.

15. 15. The method of claim 14, further comprising: performing a yield hit-back analysis on at least a portion of the EWS rejected set of the plurality of wafers; The method further comprising: determining one or more geographic locations of chains of die failures due to the LRD by analyzing a combination of the yield hit-back analysis and the reliability hit-back analysis.

16. 16. The method of claim 15, wherein in at least one of the reliability hit-back analysis, the geographic hit-back analysis, and the yield hit-back analysis, a hit-back analysis map is generated by overlaying an end-of-line (EOL) sort yield map on a merged set of images representing a plurality of layers of a wafer of the plurality of wafers, the hit-back analysis map including an overlay threshold, the overlay threshold being selected to account for in-line sample analysis tools and to reduce the statistical probability of LRD false positive determinations.

17. 17. The method of claim 16, wherein a wafer of the plurality of wafers is rejected by the EWS when the EOL sort yield map includes the one or more die rejection chains and the hit-back analysis map includes one or more defects that are determined for at least some of the one or more defects to cause at least some of the one or more die rejection chains with a selected statistical probability.

18. 16. The method of claim 15, wherein the combination of the yield hit-back analysis and the reliability hit-back analysis is analyzed with at least one of a bitmap analysis and a blockchain failure analysis.

19. 15. The method of claim 14, further comprising: generating one or more defect images including the LRD; and generating one or more statistical representations comprising said LRD; A method for performing at least one of the following:

20. 20. The method of claim 19, further comprising displaying at least one of the one or more defect images including the LRD and the one or more statistical representations including the LRD on one or more user interfaces.

21. 20. The method of claim 19 further comprising:

11. A method for determining one or more adjustments for one or more semiconductor fabrication tools, the one or more adjustments being determined based on a review of at least one of the one or more defect images that include the LRD and the one or more statistical representations that include the LRD.

22. 22. The method of claim 21 further comprising: generating one or more control signals based on the determined adjustment(s).

23. 23. The method of claim 22 further comprising: The method provides the one or more control signals to the one or more semiconductor fabrication tools via at least one of a feedforward loop and a feedback loop.

24. 15. The method of claim 14, further comprising: The method comprises at least one of an inspection tool and a metrology tool.

25. 15. The method of claim 14, wherein the one or more stress testing tools include at least one of a pre-burn-in electrical testing tool and a post-burn-in electrical testing tool.

26. 26. The method of claim 25, wherein the one or more stress testing tools are configured to at least one of: heat at least some of the plurality of wafers, remove heat from at least some of the plurality of wafers, and operate at least some of the plurality of wafers at an improper voltage.

27. one or more in-line sample analysis tools; one or more stress testing tools; a controller communicatively coupled to the one or more in-line sample analysis tools and the one or more stress test tools, the controller having one or more processors configured to execute program instructions that cause the one or more processors to: characterizing at least some of the plurality of wafers; performing electrical wafer sorting (EWS) on the plurality of wafers based on the characterization, thereby distinguishing between an EWS pass set of the plurality of wafers and an EWS fail set of the plurality of wafers; performing one or more stress tests with the one or more stress test tools on at least a portion of the EWS pass set of the plurality of wafers to identify a pass set of the plurality of wafers and a fail set of the plurality of wafers, wherein the plurality of wafers were received from the one or more in-line sample analysis tools, each wafer of the plurality of wafers has a plurality of layers, and each layer of the plurality of layers includes a plurality of dies; performing a reliability hitback analysis on at least a portion of the rejected set of the plurality of wafers; analyzing the reliability hit-back analysis to determine one or more geographic locations of one or more die failure chains due to one or more potential reliability defects (LRDs); The system performs a geographic hit-back analysis on the one or more geographic locations of the one or more die-reject chains due to the LRD.

Images