LAYOUT DESIGN APPARATUS AND LAYOUT DESIGN METHOD

Abstract

To suppress displacements of a metal pattern of a vertical hierarchy caused by a layout and reduce variations in the interlayer capacity.SOLUTION: In a layout design device which constructs a layout cell of a metal capacitor in a semiconductor integrated circuit by a parameterized cell and designs the layout of the metal capacitor in reception of an input instruction of the parameter, the layout design device includes: metal pattern shape calculation means 31 for calculating, when wire information on the comb-shaped wire of a metal capacitor in a parameterized cell as a design target is instructed to be input, a metal pattern shape in a linear symmetry from the center line to the outside of the parameterized cell; and layout cell shape generation and change means 32 for generating and changing the shape of the layout cell according to the shape of the metal pattern calculated by the metal pattern shape calculation means 31.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a layout design apparatus and a layout design method. [Background technology]

[0002] In the layout design of the layout cells of metal capacitors in semiconductor integrated circuits, conventionally, the layout cells of metal capacitors are created manually, left-justified or right-justified. Metal capacitors are formed with a metal array pattern, but due to lithography, end-processing metal patterns with different wiring widths and spacing are placed on the left and right ends (see Figure 1). In Figure 1, L is the wiring width in the array pattern, S is the wiring space in the array pattern, L1 to L3 are the wiring widths in the end-processing metal patterns, and S1 to S3 are the wiring spaces in the end-processing metal patterns.

[0003] However, if the wiring width and space of the metal patterns for end processing in the upper and lower wiring layers are different, a misalignment in wiring pitch occurs in the metal generation in the next stage after the left-justified or right-justified part. That is, as shown in FIG. 2, the generation of wiring starts from the left-side reference line K in FIG. 2, and the layout is performed with the desired wiring width and wiring pitch. According to such a conventional method, a misalignment in wiring pitch occurs in the metal of the upper and lower layers. The misalignment in wiring pitch causes a difference in the overlapping area between the array patterns of the upper and lower layers, so the desired interlayer capacitance cannot be secured, and there is a problem that a constant capacitance value cannot be obtained depending on the change in wiring pitch. In particular, in the array pattern region, there are many wirings, and the non-uniform overlap of the wirings of the upper and lower layers in this region means that a metal capacitor with the desired characteristics cannot be generated.

[0004] Patent Document 1 discloses a semiconductor integrated circuit device equipped with a metal capacitor. Patent Document 1 describes the current situation as follows: Even in semiconductor integrated circuit devices in which copper-embedded wiring is the main wiring layer, the uppermost wiring layer is often an aluminum-based pad layer in order to ensure wire bonding characteristics. This aluminum-based pad layer is generally also used as a wiring layer (general interconnection wiring such as power supply wiring and signal wiring). However, such general interconnection wiring has a disadvantage in that the device is easily damaged during plasma processing due to the antenna effect due to the relatively long wiring length.

[0005] In view of the above-mentioned current situation, the invention of Patent Document 1 is a semiconductor integrated circuit device in which a metal multilayer wiring system has a lower buried type multilayer wiring layer and an upper non-buried type aluminum-based pad metal layer, and the non-buried type aluminum-based pad metal layer has a configuration that does not substantially have a power supply ring wiring. This invention does not go as far as to solve the problem of misalignment of the array patterns of upper and lower layers of metal capacitors.

[0006] Patent Document 2 discloses a semiconductor device design method that aims to improve operability when modifying parameterized cells that have been laid out in a semiconductor layout design using parameterized cells.

[0007] The invention of Patent Document 2 is a semiconductor device design method for designing the layout of a semiconductor device using parameterized cells whose cell attributes are represented by parameters, and includes the steps of accepting, via a GUI, a user's specification of the parameterized cell to be displaced and the amount of displacement when displacing the parameterized cell, and displacing the parameterized cell to be displaced on the GUI in accordance with the amount of displacement. This invention makes it possible to improve operability when modifying a parameterized cell that has been laid out.

[0008] Furthermore, Patent Document 3 discloses a placement and wiring method for reducing the number of steps in layout design while maintaining the relative positions of components. This method includes an object description step S1 in which a transistor Q1 and a wire W1 are described as transistor and wire objects QO1 and WO1, respectively, and include adjacent designations ST, SB, SL, and SR, which are relative position information with respect to adjacent objects adjacent to each of them, and connection information CN1 indicating each connection destination, a transistor object processing step S4 in which a transistor Q1 is generated according to this object description and this transistor Q1 is placed taking into consideration the adjacent designation ST, etc., a wire object processing step S5 in which wiring positions in the horizontal and vertical directions of the wire are determined, an object end point determination step S6 in which final wiring end points P1 and P2 of each of the objects QO1 and WO1 are determined, and a post-wiring processing step S7 in which the wire is wired in a specified wiring layer. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2013-58584 A [Patent Document 2] JP 2013-143000 A [Patent Document 3] Japanese Patent Application Publication No. 10-173058 Summary of the Invention [Problem to be solved by the invention]

[0010] As described above, there are layout design devices and layout design methods that have been developed with the aim of reducing the number of steps required for layout design and improving operability. However, there have been no layout design devices and methods that take into account the variation in interlayer capacitance that occurs due to misalignment of metal patterns in upper and lower layers caused by manual left-justified or right-justified layout.

[0011] An object of the embodiments of the present invention is to provide a layout design apparatus and a layout design method capable of suppressing misalignment of metal patterns in upper and lower layers caused by the layout and reducing variations in interlayer capacitance. [Means for solving the problem]

[0012] The layout design device according to the present embodiment constructs a layout cell of a metal capacitor in a semiconductor integrated circuit using parameterized cells, and performs layout design of the metal capacitor in response to an input instruction of parameters. The layout design device is characterized in that it comprises: a metal pattern shape calculation means for calculating a metal pattern shape line-symmetrically from a center line of the parameterized cell outward when wiring information related to comb-shaped wiring of the metal capacitor in the parameterized cell to be designed is input; and a layout cell shape generation / modification means for generating / modifying a layout cell shape corresponding to the shape calculated by the metal pattern shape calculation means.

[0013] In the layout design apparatus according to this embodiment, the metal pattern shape calculation means and the layout cell shape generating / modifying means execute processing for layers above and below a metal capacitor.

[0014] In the layout design apparatus according to this embodiment, the metal pattern shape calculation means is characterized in that it designs and places a predetermined number of metal patterns, each having a different wiring width, at the end portions of the parameterized cells, and designs and places a plurality of metal patterns, each having the same wiring width, in the array pattern area excluding the end portions of the parameterized cells.

[0015] In the layout design apparatus according to this embodiment, the metal pattern shape calculation means designs and places a plurality of metal patterns with the same wiring space in the array pattern region.

[0016] In the layout design apparatus according to this embodiment, the metal pattern shape calculation means designs and places a wiring space of a predetermined width and a metal pattern of a predetermined length at the end portion of the parameterized cell.

[0017] The layout design method according to the present embodiment is a layout design method for constructing a layout cell of a metal capacitor in a semiconductor integrated circuit using parameterized cells and designing the layout of the metal capacitor in response to an input instruction of parameters, the method comprising: a metal pattern shape calculation step for calculating a metal pattern shape line-symmetrically from a center line of the parameterized cell outward when wiring information related to comb-shaped wiring of the metal capacitor in the parameterized cell to be designed is inputted; and a layout cell shape generation / modification step for generating / modifying a layout cell in accordance with the shape calculated in the metal pattern shape calculation step.

[0018] The layout design method according to the present embodiment is characterized in that the metal pattern shape calculation step and the layout cell shape generation / modification step execute processing for layers above and below a metal capacitor.

[0019] The layout design method according to this embodiment is characterized in that, in the metal pattern shape calculation step, a predetermined number of metal patterns, each having a different wiring width, are placed and designed at the end portions of the parameterized cells, and a plurality of metal patterns, each having the same wiring width, are placed and designed in the array pattern area excluding the end portions of the parameterized cells.

[0020] In the layout design method according to the present embodiment, in the metal pattern shape calculation step, a plurality of metal patterns are designed and placed with the same wiring space in the array pattern region.

[0021] The layout design method according to this embodiment is characterized in that in the metal pattern shape calculation step, a wiring space of a predetermined width and a metal pattern of a predetermined length are designed and placed at the end portions of the parameterized cells. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are plan views showing the upper and lower layers of a layout cell of a metal capacitor. [Diagram 2] FIG. 1 is a perspective plan view showing a layout cell in which upper and lower layers of a metal capacitor are overlapped, the layout cell being generated by a conventional layout design method; [Diagram 3] FIG. 1 is a block diagram of a computer constituting a layout design apparatus according to an embodiment of the present invention. [Figure 4] 1 is a block diagram showing each unit for realizing a layout design apparatus according to an embodiment of the present invention; [Diagram 5] 4 is a flowchart showing an operation of a lower layer in the layout design apparatus according to the embodiment of the present invention. [Figure 6] 4 is a flowchart showing an operation in an upper layer of the layout design apparatus according to the embodiment of the present invention. [Figure 7] FIG. 2 is a diagram showing a lower layer layout cell generated by the layout design apparatus according to the embodiment of the present invention. [Figure 8] FIG. 2 is a diagram showing upper layer layout cells generated by the layout design apparatus according to the embodiment of the present invention. [Figure 9] 1 is a perspective plan view showing a layout cell in which upper and lower layers of a metal capacitor are overlapped, the layout cell being generated by a layout design device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A layout design apparatus and a layout design method according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are designated by the same reference numerals and duplicated explanations will be omitted.

[0024] The layout design device according to the embodiment of the present invention having the above configuration can be configured using a computer, as shown in Fig. 3. That is, a CPU 10 configures the layout design device using programs and data in a main memory 11. An external storage interface 13, an input interface 14, a display interface 15, and a network interface 16 are connected to the CPU 10 via a bus 12.

[0025] An external storage device 23 is connected to the external storage interface 13. The external storage device 23 stores programs and data for the layout design device to operate, and the CPU 10 can read these into the main memory 11 as appropriate and use them. For this reason, the external storage device 23 stores programs for implementing each means of the layout design device, which will be described later. An input device 24 such as a keyboard or a touch panel and a pointing device 22 such as a mouse are connected to the input interface 14. A display device 25 having a screen such as an LCD is connected to the display interface 15, and the display device 25 realizes the display of images and the like required for the layout design device. A network is connected to the network interface 16, and the layout design device can import data to be designed for wiring. An input device 24 such as a keyboard for inputting data and commands and a pointing device 22 such as a mouse are connected to the input interface 14, and the input device 24 and the pointing device 22 such as a mouse can be operated to cause the layout design device to perform operations and processes required for the layout design device.

[0026] The external storage device 23 stores each means for realizing the layout design device as shown in FIG. 4. Each of these means is composed of a metal pattern shape calculation means 31 and a layout cell shape generation / change means 32. The layout design device according to this embodiment constructs a layout cell of a metal capacitor in a semiconductor integrated circuit by a parameterized cell, and performs layout design of the metal capacitor upon receiving an input instruction of parameters. When wiring information on the comb-shaped wiring of the metal capacitor in the parameterized cell to be designed is input, the metal pattern shape calculation means 31 calculates a metal pattern shape line-symmetrically from the center line C (FIGS. 7 to 9) of the parameterized cell toward the outside. The input wiring information here is the wiring width, the wiring space, and the number of wirings or the cell width for calculating the number of wirings. The layout cell shape generation / change means 32 generates / changes the layout cell shape corresponding to the shape calculated by the metal pattern shape calculation means 31.

[0027] The layout design device according to this embodiment performs processing corresponding to the flowcharts shown in Figures 5 and 6, and the operation will be described according to these flowcharts. In this embodiment, the layout cells of all metal capacitors in a semiconductor integrated circuit chip are constructed using parameterized cells, and each parameterized cell is assigned with identification information. Using the identification information, data of a desired parameterized cell can be called up and a layout can be designed. First, processing for a lower layer is performed. In step S11, data of a parameterized cell corresponding to the inputted identification information (e.g., cell size information, etc.) is called up and layout design is prepared (S11).

[0028] Since the capacitance of the metal capacitor is determined, the wiring width L, number of wires N, and wiring pitch of the array pattern area in the lower layer are also determined, and this wiring information is input, and the length of the array pattern area is calculated from the wiring space S of the array pattern area based on the wiring width L and number of wires N of the array pattern area (S12).

[0029] Next, the metal pattern shape is calculated (S13) in line symmetry from the center line C of the cell (FIGS. 7 and 9) outward. For example, if the number of wires N is an odd number, wires of width L are placed around the center line of the cell (FIGS. 7 and 9), then the spacing between the wiring spaces S is placed on the left and right, and wires of width L are placed adjacent to the outside of the wiring spaces S on the left and right. The placement is similarly continued, and when the placement design for the array pattern area is completed, the wires are placed around the edge processing area. Also, if the number of wires N is an even number, the wiring space S is placed around the center line of the cell (FIGS. 7 and 9), then wires of width L are placed on the left and right, then adjacent to the wiring space S on the outside, and wires of width L are placed outside of that. The rest of the layout is similarly designed, and thus the metal pattern shape calculation means 31 designs and places a predetermined number of metal patterns, each having a different wiring width, at the end portions of the parameterized cells, and designs and places a plurality of metal patterns, each having the same wiring width, in the array pattern region excluding the end portions of the parameterized cells. After the layout design for the array pattern region is completed, the wiring is designed and placed in the end processing metal pattern region.

[0030] Next, the wiring width and wiring space of the end processing metal pattern region in the cell for which the layout design is performed are input, and the length of the end processing metal pattern region is calculated (S14). In the example of Fig. 1, L1+L2+L3+S1+S2+S3 is calculated by inputting L1 to L3 and S1 to S3. Note that it is assumed that the size of the cell (length x width), the width of the base of the metal capacitor (W1 in Fig. 1), and the distance from the base of the metal capacitor to the head of the wiring (W2 in Fig. 1) have already been input and stored.

[0031] Next, it is confirmed that twice the length of the end processing metal pattern region plus the length of the array pattern region is within the length of the cell (S15). The wiring of the end processing metal pattern region is placed and designed (S16). If (twice the length of the end processing metal pattern region) + (the length of the array pattern region) is not within the length of the cell, a display is displayed requesting a change in the wiring width and wiring space of the end processing metal pattern region, new input is received (S17), and the process returns to step S15. In this manner, the process of placing and designing the lower layer metal pattern is completed. In this manner, the metal pattern shape calculation means 31 places and designs a wiring space of a predetermined width and a predetermined number of metal patterns at the end portions of the parameterized cell.

[0032] Next, the layout cells of the lower layer are generated and modified in accordance with the shape of the metal pattern calculated in the metal pattern shape calculation step (S18). As a result, an image of the layout cells of the lower layer is created as shown in Fig. 7. At this stage, the metal patterns of the lower layer may be displayed. Next, in step S19, a confirmation input is received that the generation and modification of the layout cells of the lower layer has been completed, and the process proceeds to the layout of the upper layer from step 32 onwards.

[0033] The wiring width LU and the number of wires N of the array pattern area on the upper layer have been determined, and these are input to calculate the wiring width LU and the number of wires N of the array pattern area on the upper layer, as well as the length of the array pattern area and the wiring space SU of the upper layer of the array pattern area (S32).

[0034] Next, the shape of the upper layer metal pattern is calculated in line symmetry from the center line C of the cell (FIGS. 8 and 9) outward (S33). For example, if the number of wires N is an odd number, wires of width LU are placed around the center line of the cell (FIGS. 8 and 9), then the spacing between the wiring spaces SU is placed on the left and right, and wires of width LU are placed adjacent to the outside of the wiring spaces SU on the left and right. The same arrangement is carried out, and when the arrangement design for the array pattern area is completed, the wires are placed around the metal pattern area for edge processing. Also, if the number of wires N is an even number, the wiring space SU is placed around the center line of the cell (FIGS. 8 and 9), then wires of width LU are placed on the left and right, then the wiring space SU is placed adjacent to the wiring space SU on the outside, and wires of width LU are placed outside of that. The same arrangement is carried out, and when the arrangement design for the array pattern area is completed, the wires are placed around the metal pattern area for edge processing. As a result of the above wiring layout design, in the array pattern area, the lower layer wiring and the upper layer wiring overlap at the center line of their widths (FIGS. 8 and 9).

[0035] Next, the length of the end processing metal pattern region is calculated by receiving input of the wiring width and wiring space of the upper layer end processing metal pattern region in the cell for which the layout design is performed (S34). In the example of the lower layer shown in Fig. 1, it was L1 to L3 and S1 to S3, but in the upper layer, it is LU1 to LU3 and SU1 to SU3 as shown in Fig. 8. By inputting these LU1 to LU3 and SU1 to SU3, LU1+LU2+LU3+SU1+SU2+SU3 is calculated. Note that it is assumed that the size of the cell (length x width), the width of the base of the metal capacitor (W1 in Fig. 1), and the distance from the base of the metal capacitor to the head of the wiring (W2 in Fig. 1) have already been input and stored.

[0036] Next, it is confirmed that twice the length of the upper layer metal pattern area for edge processing plus the length of the array pattern area is within the length of the cell (S35). The wiring of the metal pattern area for edge processing is designed and placed (S36). If (twice the length of the metal pattern area for edge processing) + (the length of the array pattern area) is not within the length of the cell, a display is displayed requesting a change to the wiring width and wiring space of the metal pattern area for edge processing, new input is received (S37), and the process returns to step S35. In this manner, the process of designing and placing the metal pattern of the upper layer is completed.

[0037] Next, upper layer layout cells are generated corresponding to the shape of the metal pattern calculated in the metal pattern shape calculation step (S38). As a result, an image of the upper layer layout cells is created as shown in Fig. 8. At this stage, the upper layer metal patterns may be displayed. Next, in step S39, confirmation is received that the generation and modification of the upper layer layout cells has been completed, and the process ends.

[0038] 9 shows an image of a lower layer layout cell and an upper layer layout cell overlapped with each other, obtained by the layout design device according to this embodiment. In the array pattern area, it can be seen that the lower layer wiring and the upper layer wiring overlap at the center of the width. Therefore, even if the parameters of the cell width and the wiring pitch are changed, the interlayer capacitance can always be maintained at the maximum value.

[0039] As described above, by constructing the layout of a metal capacitor using parameterized cells, the layout designer can obtain the desired shape by simply updating the parameters. This reduces the amount of work required for layout design of boost circuits, decoupling capacitance, etc. In addition, it eliminates the unevenness of interlayer capacitance caused by misalignment of metal patterns in upper and lower layers due to manual left-justified or right-justified layout, and contributes to ensuring the maximum value of interlayer capacitance. [Explanation of symbols]

[0040] 10 CPU 11 Main Memory 12 Bus 13 External memory interface 14 Input Interface 15 Display Interface 16 Network Interfaces 22 Pointing Device 23 External storage device 24 Input Devices 25 Display device 31 Metal pattern shape calculation means 32 Layout cell shape generation and modification method

Claims

1. A layout design apparatus for constructing a layout cell of a metal capacitor in a semiconductor integrated circuit using parameterized cells and designing a layout of the metal capacitor in response to an input instruction of parameters, comprising: a metal pattern shape calculation means for calculating a metal pattern shape that is line-symmetric from a center line of the parameterized cell toward an outer side when wiring information on comb-shaped wiring of a metal capacitor in a parameterized cell to be designed is input; a layout cell shape generating / changing means for generating / changing a layout cell shape corresponding to the shape calculated by the metal pattern shape calculating means; A layout design apparatus comprising:

2. 2. The layout design apparatus according to claim 1, wherein said metal pattern shape calculation means and said layout cell shape generation / modification means execute processing for layers above and below a metal capacitor.

3. 2. The layout design device according to claim 1, wherein the metal pattern shape calculation means designs and places a predetermined number of metal patterns, each having a different wiring width, at end portions of the parameterized cells, and designs and places a plurality of metal patterns, each having the same wiring width, in an array pattern area excluding the end portions of the parameterized cells.

4. 4. The layout design device according to claim 3, wherein said metal pattern shape calculation means designs and arranges a plurality of metal patterns with the same wiring space in said array pattern region.

5. 5. The layout design device according to claim 4, wherein said metal pattern shape calculation means designs and places a wiring space of a predetermined width and a metal pattern of a predetermined length at an end portion of the parameterized cell.

6. A layout design method in which a CPU constituting a layout design device which constructs layout cells of metal capacitors in a semiconductor integrated circuit using parameterized cells and designs the layout of the metal capacitors in response to input instructions of parameters is executed by appropriately reading out programs and data for the operation of the layout design device for the semiconductor integrated circuit from an external storage device in which the programs and data are stored, into a main memory, and using the programs and data, The CPU, a metal pattern shape calculation step of calculating a metal pattern shape in line symmetry from a center line of the parameterized cell toward an outer side when wiring information regarding comb-shaped wiring of a metal capacitor in a parameterized cell to be designed is input; a layout cell shape generating / changing step of generating / changing a layout cell corresponding to the shape calculated by the metal pattern shape calculating step; 2. A layout design method comprising the steps of:

7. 7. The layout design method according to claim 6, wherein the metal pattern shape calculation step and the layout cell shape generation / change step are realized by the CPU executing processing for layers above and below a metal capacitor.

8. 7. The layout design method according to claim 6, wherein in the metal pattern shape calculation step, the CPU designs and places a predetermined number of metal patterns, each having a different wiring width, at end portions of the parameterized cells, and designs and places a plurality of metal patterns, each having the same wiring width, in an array pattern area excluding the end portions of the parameterized cells.

9. 9. The layout design method according to claim 8, wherein in said metal pattern shape calculation step, said CPU designs and arranges a plurality of metal patterns with the same wiring space in said array pattern region.

10. 10. The layout design method according to claim 9, wherein in said metal pattern shape calculation step, said CPU designs and places a wiring space of a predetermined width and a metal pattern of a predetermined length at an end portion of the parameterized cell.

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