Semiconductor memory device

Abstract

To provide a semiconductor storage device capable of being easily miniaturized.SOLUTION: A semiconductor storage device comprises first and second electrodes, a phase change layer provided between the first and second electrodes, and a first layer provided between the first electrode and the phase change layer. The phase change layer includes at least one of germanium (Ge), antimony (Sb), and tellurium (Te). The first layer includes aluminum (Al) and antimony (Sb), or tellurium (Te), as well as at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a first electrode, a second electrode, and a phase change layer provided between the first electrode and the second electrode. The phase change layer includes, for example, germanium (Ge), antimony (Sb), tellurium (Te), or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-18838 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that can be easily miniaturized is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a first electrode, a second electrode, a phase change layer provided between the first electrode and the second electrode, and a first layer provided between the first electrode and the phase change layer. The phase change layer includes at least one of germanium (Ge), antimony (Sb), and tellurium (Te), and the first layer includes at least one of aluminum (Al) and antimony (Sb) or tellurium (Te), zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0006] A semiconductor memory device according to one embodiment includes a first electrode, a second electrode, a phase change layer provided between the first electrode and the second electrode, and a first layer provided between the first electrode and the phase change layer. The phase change layer includes cubic crystals, and the first layer includes crystals with a zinc blende structure or a face-centered cubic lattice. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Diagram 3] 2 is a schematic cross-sectional view of a memory cell MC of the semiconductor memory device. [Figure 4] 4 is a schematic graph showing the current-voltage characteristics of a memory cell MC of the semiconductor memory device. [Diagram 5] 5 is a schematic cross-sectional view for explaining a write operation of the memory cell MC according to the first embodiment. FIG. [Figure 6] 11 is a schematic cross-sectional view for explaining a write operation of a memory cell MC according to a comparative example. FIG. [Figure 7] 1 is a schematic cross-sectional view of a memory cell MC of a semiconductor memory device according to a first modification. [Figure 8] 11 is a schematic cross-sectional view of a memory cell MC of a semiconductor memory device according to a second modification. FIG. [Figure 9] FIG. 11 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 10] 13 is a schematic cross-sectional view of a resistance change element section VRP in the semiconductor memory device. FIG. [Figure 11] 13 is a schematic cross-sectional view of a resistance change element portion VRP2 of a semiconductor memory device according to a modified example. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0009] In this specification, a predetermined direction parallel to the surface of the substrate is called the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the surface of the substrate is called the Z direction.

[0010] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0011] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, when the first direction intersects with the surface of the substrate, the direction away from the substrate along the first direction is called "up," and the direction toward the substrate along the first direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration on the substrate side, and when referring to an upper surface or upper end, refers to the surface or end of the configuration on the opposite side to the substrate. Furthermore, a surface that intersects with the second or third direction is called a side surface, etc.

[0012] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0013] Furthermore, in this specification, when it is said that a first configuration is "electrically insulated" from a second configuration, this means, for example, that an insulating layer or the like is provided between the first configuration and the second configuration, and that no contacts, wiring, etc. are provided to connect the first configuration and the second configuration.

[0014] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0015] Hereinafter, a circuit configuration of a semiconductor memory device according to an embodiment will be described with reference to the drawings. Note that the drawings are schematic, and for the sake of convenience, some components may be omitted.

[0016] [First embodiment] [Schematic configuration] Fig. 1 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to the first embodiment, and Fig. 2 is a schematic perspective view showing the configuration of a portion of the semiconductor memory device.

[0017] The semiconductor memory device according to this embodiment includes a memory cell array MCA and a peripheral circuit PC that controls the memory cell array MCA.

[0018] The memory cell array MCA includes, for example, a plurality of memory mats MM arranged in the Z direction as shown in FIG. 2. The memory mats MM include bit lines BL, word lines WL, and memory cells MC. A plurality of bit lines BL are arranged in the X direction and extend in the Y direction. A plurality of word lines WL are arranged in the Y direction and extend in the X direction. A plurality of memory cells MC are arranged in the X direction and Y direction corresponding to the bit lines BL and word lines WL. As shown in the figure, the bit lines BL or word lines WL may be provided in common for two memory mats MM arranged in the Z direction. In the example of FIG. 1, the cathode E of the memory cells MC Cis connected to the bit line BL. Also, the anode E of the memory cell MC A is connected to a word line WL. The memory cell MC includes a resistance change element VR and a nonlinear element NO.

[0019] The peripheral circuit PC is connected to the bit lines BL and word lines WL. The peripheral circuit PC includes, for example, a step-down circuit, a selection circuit, a sense amplifier circuit, and a sequencer for controlling these. The step-down circuit steps down the power supply voltage and outputs it to a voltage supply line. The selection circuit connects the bit line BL and word line WL corresponding to a selected address to the corresponding voltage supply line. The sense amplifier circuit outputs data of 0 or 1 according to the voltage or current of the bit line BL.

[0020] [Configuration of memory cell MC] 3A and 3B are schematic cross-sectional views of a memory cell MC according to this embodiment. Fig. 3A corresponds to a memory cell having a bit line BL provided below and a word line WL provided above. Fig. 3B corresponds to a memory cell having a word line WL provided below and a bit line BL provided above.

[0021] 3A includes a conductive layer 102, a chalcogen layer 103, a conductive layer 104, a barrier conductive layer 105, a crystallization promoting layer 106, a chalcogen layer 107, a barrier conductive layer 108, and a conductive layer 109, which are stacked in this order on a barrier conductive layer 101 on the upper surface of a bit line BL. A barrier conductive layer 110 is provided on the conductive layer 109 and on the lower surface of a word line WL.

[0022] The barrier conductive layer 101 functions as a part of the bit line BL. The barrier conductive layer 101 may be, for example, tungsten nitride (WN), titanium nitride (TiN), or the like, or may be another conductive layer such as tungsten carbonitride (WCN) or tungsten carbonitride silicide (WCNSi).

[0023] The conductive layer 102 is connected to a bit line BL provided immediately below the memory cell MC, and is connected to the cathode E CThe conductive layer 102 may be, for example, carbon (C), carbon nitride (CN), or the like, or may be tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), vanadium (V), vanadium nitride (VN), zirconium (Zr), zirconium nitride (ZrN), hafnium (Hf), hafnium nitride (HfN), yttrium (Y), yttrium nitride (YN), scandium (Sc), scandium nitride (ScN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), rhenium (Re), niobium (Nb), aluminum (Al), or the like. Furthermore, the conductive layer 102 may be, for example, polycrystalline silicon doped with N-type impurities such as phosphorus (P), or may be another conductive layer such as tungsten carbide (WC), tungsten carbonitride (WCN), or tungsten carbonitride silicide (WCNSi).

[0024] The chalcogen layer 103 functions as a nonlinear element NO. For example, when a voltage lower than a predetermined threshold is applied to the chalcogen layer 103, the chalcogen layer 103 is in a high resistance state. When the voltage applied to the chalcogen layer 103 reaches a predetermined threshold, the chalcogen layer 103 enters a low resistance state, and the current flowing through the chalcogen layer 103 increases by several orders of magnitude. When the voltage applied to the chalcogen layer 103 falls below the predetermined voltage for a certain period of time, the chalcogen layer 103 enters a high resistance state again.

[0025] Chalcogen layer 103 includes, for example, at least one type of chalcogen. Chalcogen layer 103 may include, for example, chalcogenide, which is a compound including chalcogen. Chalcogen layer 103 may also include at least one element selected from the group consisting of B, N, Al, Zn, Ga, In, C, Si, Ge, Sn, As, P, and Sb.

[0026] The term "chalcogen" used here refers to elements belonging to Group 16 of the periodic table, excluding oxygen (O). Chalcogen includes, for example, sulfur (S), selenium (Se), tellurium (Te), and the like.

[0027] The conductive layer 104 functions as an electrode that connects the nonlinear element NO and the resistance change element VR. The conductive layer 104 may include, for example, the same material as the conductive layer 102.

[0028] The barrier conductive layer 105 may, for example, include the same material as the barrier conductive layer 101 .

[0029] The crystallization promoting layer 106 is a cathode E C The crystallization promoting layer 106 contacts the side surface and functions as a crystal base (template) capable of controlling the crystal structure of the chalcogen layer 107. The crystallization promoting layer 106 includes, for example, cubic crystals. The cubic crystals include, for example, crystals with a zinc blende structure and crystals with a face-centered cubic (fcc) lattice structure (hereinafter referred to as "fcc crystals"). The crystallization promoting layer 106 has at least one layer made of constituent atoms described below.

[0030] The crystallization promoting layer 106 also functions as a heater that supplies heat necessary for the set operation and reset operation, which will be described later, to the chalcogen layer 107. To function as an effective heater, the crystallization promoting layer 106 includes a material that has a relatively large band gap, which will be described later, i.e., exhibits relatively low electrical conductivity.

[0031] The crystallization promoting layer 106 also functions as a heat shielding member. The crystallization promoting layer 106 contains a material having a relatively low thermal conductivity, which will be described later, so that Joule heat generated in the crystallization promoting layer 106 is less likely to escape to the chalcogen layer 103 side.

[0032] The chalcogen layer 107 functions as a resistance change element VR. The chalcogen layer 107 is put into an amorphous state (reset state: high resistance state) by, for example, heating to a temperature equal to or higher than the melting temperature and then rapidly cooling. The chalcogen layer 107 is put into a crystalline state (set state: low resistance state) by, for example, heating to a temperature lower than the melting temperature and higher than the crystallization temperature.

[0033] The chalcogen layer 107 includes, for example, at least one type of chalcogen. The chalcogen layer 107 may include, for example, a chalcogenide that is a compound including a chalcogen. The chalcogen layer 107 may be, for example, GeSbTe, GeCuTe, GeTe, SbTe, SiTe, or the like. The chalcogen layer 107 may also include at least one element selected from germanium (Ge), antimony (Sb), and tellurium (Te). The chalcogen layer 107 may also include nitrogen (N), carbon (C), boron (B), or the like.

[0034] Barrier conductive layer 108 may, for example, include the same material as barrier conductive layer 101 .

[0035] The conductive layer 109 is connected to a word line WL provided directly above the memory cell MC, and is connected to an anode E A The conductive layer 109 may include, for example, the same material as the conductive layer 102.

[0036] The barrier conductive layer 110 functions as a part of the word line WL. The barrier conductive layer 110 may include, for example, the same material as the barrier conductive layer 101.

[0037] The memory cell MC shown in Fig. 3(b) is basically configured in the same manner as the memory cell MC shown in Fig. 3(a). However, in the memory cell MC shown in Fig. 3(b), the barrier conductive layer 110, instead of the barrier conductive layer 101, functions as a part of the bit line BL, and the barrier conductive layer 101, instead of the barrier conductive layer 110, functions as a part of the word line WL. Also, the conductive layer 109, instead of the conductive layer 102, functions as the cathode E C The conductive layer 102, rather than the conductive layer 109, serves as the anode E A It functions as:

[0038] [Electrical characteristics of memory cell MC] 4 is a schematic graph showing the current-voltage characteristics of the memory cell MC according to this embodiment. The horizontal axis represents the cathode E C Anode E when the voltage is referenced to AThe vertical axis indicates the voltage (hereinafter referred to as "cell voltage Vcell") flowing through the memory cell MC (hereinafter referred to as "cell current Icell") on a logarithmic scale.

[0039] In a range where the cell current Icell is smaller than a predetermined current value I1, the cell voltage Vcell increases monotonically with the increase in the cell current Icell. When the cell current Icell reaches the current value I1, the cell voltage Vcell of the memory cell MC in the low resistance state reaches a voltage V1. Also, the cell voltage Vcell of the memory cell MC in the high resistance state reaches a voltage V2. The voltage V2 is greater than the voltage V1.

[0040] In the range where the cell current Icell is greater than the current value I1 and less than the current value I2, the cell voltage Vcell monotonically decreases as the cell current Icell increases. In this range, the cell voltage Vcell of the memory cell MC in the high resistance state is greater than the cell voltage Vcell of the memory cell MC in the low resistance state.

[0041] In the range where the cell current Icell is greater than the current value I2 and less than the current value I3, the cell voltage Vcell temporarily decreases and then increases as the cell current Icell increases. In this range, the cell voltage Vcell of the memory cell MC in the high resistance state decreases rapidly as the cell current Icell increases, and becomes approximately the same as the cell voltage Vcell of the memory cell MC in the low resistance state.

[0042] In the range where the cell current Icell is greater than the current value I3, the cell voltage Vcell temporarily decreases as the cell current Icell increases, and then increases.

[0043] When the cell current Icell is rapidly reduced from this state to a value smaller than the current value I1, the chalcogen layer 107 enters a high resistance state. When the cell current Icell is reduced to a predetermined value and maintained in this state for a certain period of time, the chalcogen layer 107 enters a low resistance state.

[0044] [Operation] 5 is a schematic cross-sectional view for explaining a write operation of a memory cell MC according to this embodiment. In FIG. 5, a set operation and a reset operation are illustrated as examples of the write operation. The set operation is an operation for transitioning the memory cell MC from a high resistance state to a low resistance state. The reset operation is an operation for transitioning the memory cell MC from a low resistance state to a high resistance state.

[0045] FIG. 5(a) shows the state of the memory cell MC after a reset operation has been performed, and FIG. 5(b) shows the state of the memory cell MC after a set operation has been performed.

[0046] In the following description, an example in which the main component of the chalcogen layer 107 is Ge2Sb2Te5 will be described.

[0047] When the reset operation is performed on the memory cell MC shown in FIG. 5(b), as shown in FIG. 5(a), the chalcogen layer 107 is formed with an amorphous chalcogen layer 107_a. In the reset operation, for example, the cell voltage Vcell is adjusted to a reset voltage Vreset that is higher than the voltage V2 (FIG. 4). As a result, a current flows through the memory cell MC, and Joule heat is generated in the chalcogen layer 107. In addition, Joule heat is generated in large amounts from the crystallization promoting layer 106 and supplied to the chalcogen layer 107. This is because the crystallization promoting layer 106 has a higher electrical resistance than the chalcogen layer 107. The Joule heat at this time is large enough to melt the entire chalcogen layer 107. Next, the cell voltage Vcell is reduced to 0V. As a result, Joule heat is no longer supplied to the chalcogen layer 107, and the melted chalcogen layer 107 is rapidly cooled. During this time, the chalcogen layer 107 is not given the time required for crystallization. As a result, the chalcogen layer 107 is solidified in an amorphous state (reset state: high resistance state), and an amorphous chalcogen layer 107_a is formed.

[0048] When a set operation is performed on the memory cell MC shown in FIG. 5(a), the chalcogen layer 107_a in the amorphous state becomes the chalcogen layer 107_c in the crystalline state as shown in FIG. 5(b). In the set operation, for example, the cell voltage Vcell is adjusted to a set voltage Vset smaller than the reset voltage Vreset, and the state is maintained for a certain period of time. As a result, a current flows through the memory cell MC, and Joule heat is supplied to the chalcogen layer 107_a. The Joule heat at this time is large enough that the chalcogen layer 107_a crystallizes but does not melt. The set voltage Vset is maintained for a period of time required for the chalcogen layer 107_a to crystallize. After that, the cell voltage Vcell is set to 0V. As a result, the chalcogen layer 107_a in the amorphous state becomes the chalcogen layer 107_c in the crystalline state (set state: low resistance state).

[0049] In the set operation, the crystals of Ge2Sb2Te5 in the chalcogen layer 107 grow based on the crystal planes of cubic crystals, such as zinc blende crystals and fcc crystals, contained in the crystallization promoting layer 106. As a result, the Ge2Sb2Te5 in the chalcogen layer 107_c is generated mainly as fcc crystals, which are cubic crystals.

[0050] Similarly, when a reset operation is performed on the memory cell MC shown in Fig. 5(b), the chalcogen layer 107_c in a crystalline state becomes the chalcogen layer 107_a in an amorphous state. Also, when a set operation is performed on the memory cell MC shown in Fig. 5(a), the chalcogen layer 107_a in an amorphous state becomes the chalcogen layer 107_c in a crystalline state.

[0051] [Comparative Example] 6 is a schematic cross-sectional view for explaining a write operation of a memory cell MC according to a comparative example. The memory cell MC according to the comparative example is basically configured similarly to the memory cell MC according to the first embodiment. However, the memory cell MC according to the comparative example does not have a crystallization promoting layer 106.

[0052] FIG. 6(a) shows the state of the memory cell MC after a reset operation has been performed, and FIG. 6(b) shows the state of the memory cell MC after a set operation has been performed.

[0053] 6, the set operation and reset operation of the memory cell MC according to the comparative example are performed in the same manner as the set operation and reset operation of the memory cell MC according to the first embodiment. However, in the memory cell MC according to the comparative example, after the set operation, a chalcogen layer 107_c' is formed instead of the chalcogen layer 107_c.

[0054] In the memory cell MC according to the comparative example, in a set operation, it takes a longer time for the chalcogen layer 107_a to be crystallized into the chalcogen layer 107_c' to be completed than in the first embodiment. At this time, since there is no crystallization promoting layer 106 in contact with the chalcogen layer 107_c', there is no reference plane for the crystal growth of the chalcogen layer 107_a, and the constituent atoms of the chalcogen layer 107 move freely relative to each other. In such a state, crystal nuclei serving as seeds for crystallization are repeatedly generated and annihilated inside the chalcogen layer 107, and as a result, it takes a longer time for the crystallization to be completed. In addition, since there is no crystallization promoting layer 106 for controlling the orientation when the crystals grow into the chalcogen layer 107_c', fcc crystals are unlikely to be generated in the chalcogen layer 107_c'.

[0055] Moreover, the memory cell MC according to the comparative example does not have the crystallization promoting layer 106 that functions as a heater. Therefore, the heat required for the set operation and the reset operation cannot be efficiently supplied to the chalcogen layer 107, and the time required to complete the set operation and the reset operation becomes longer than that of the first embodiment.

[0056] Moreover, the memory cell MC according to the comparative example does not have the crystallization promoting layer 106 that also functions as a heat shielding member. Therefore, Joule heat generated in the chalcogen layer 107 is likely to escape to the chalcogen layer 103 side, and the time until the set operation and the reset operation are completed becomes longer than that of the first embodiment.

[0057] [effect] To perform a high-speed write operation, it is necessary to increase the speed of both the set operation and the reset operation.

[0058] In order to perform a high-speed set operation, it is particularly preferable that the time required for crystallization of the chalcogen layer 107 to be completed is short.

[0059] Therefore, in this embodiment, as described with reference to FIG. 3, the cathode E C A crystallization promoting layer 106 containing cubic crystals is provided on the chalcogen layer 107 side. In this structure, as described above, crystals having a cubic fcc structure can be generated in the chalcogen layer 107 at high speed during the set operation.

[0060] Next, in order to perform a high-speed reset operation, it is preferable that the total amount of heat required for melting the crystallized chalcogen layer 107_c is small, and that the melting heat can be effectively supplied to the chalcogen layer 107_c.

[0061] The total amount of heat required to melt the chalcogen layer 107_c differs depending on the crystal structure, composition, etc. of the chalcogen layer 107_c. Therefore, hereinafter, Ge2Sb2Te5 will be given as an example of the chalcogen layer 107.

[0062] Ge2Sb2Te5 has a hcp (Hexagonal close-packed) lattice structure as a stable crystal structure, and an fcc lattice structure as a metastable state. It is known that Ge2Sb2Te5 with an fcc lattice structure melts with less thermal energy than Ge2Sb2Te5 with an hcp lattice structure. Therefore, the total amount of heat required for melting can be reduced if the chalcogen layer 107_c contains a large amount of crystals with an fcc structure.

[0063] However, it may be difficult to generate crystals with an fcc lattice structure in the chalcogen layer 107_c. In particular, when the temperature of the entire semiconductor memory device becomes high due to long-term use, the proportion of crystals with an hcp lattice structure may increase when a set operation is performed.

[0064] Therefore, in this embodiment, as described above, the crystallization promoting layer 106 containing cubic crystals is provided. In such a structure, as described above, Ge2Sb2Te5 having an fcc lattice structure can be stably generated in the chalcogen layer 107_c during the set operation. This reduces the total amount of heat required to melt the chalcogen layer 107_c during the reset operation, thereby realizing a high-speed reset operation.

[0065] [Configuration of crystallization promoting layer 106] [Crystalline structure of crystallization promoting layer 106] As described with reference to FIG. 3 and the like, the crystallization promoting layer 106 contains cubic crystals, zinc blende crystals, fcc crystals, and the like.

[0066] Examples of materials that form zinc blende crystals include AlSb (0.614 nm) and ZnTe (0.611 nm) (the numbers in parentheses indicate the lattice constants of the zinc blende crystals that each material forms). The crystallization promoting layer 106 may contain, for example, aluminum (Al) and antimony (Sb), or tellurium (Te) and zinc (Zn), which form these materials.

[0067] Materials that make up fcc crystals include LaTe (0.642 nm), CeTe (0.636 nm), PrTe (0.632 nm), NdTe (0.626 nm), SmTe (0.659 nm), EuTe (0.659 nm), GdTe (0.614 nm), TbTe (0.610 nm), DyTe (0.609 nm), HoTe (0.605 nm), ErTe (0.606 nm), TmTe (0.604 nm), YbTe (0.635 nm), LuTe (0.595 nm), etc. (The numbers in parentheses are the lattice constants of the fcc crystals that each material makes up). The crystallization promoting layer 106 may include, for example, at least one of the following materials: tellurium (Te), zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0068] Moreover, it is preferable that the lattice constant of the zinc blende crystal or fcc crystal contained in the crystallization promoting layer 106 is close to the lattice constant of the fcc crystal contained in the chalcogen layer 107_c. This is because the crystal structure of the crystal contained in the chalcogen layer 107_c can be more suitably controlled when these crystals have lattice constants close to each other. In particular, it is preferable that the lattice constant of the crystal contained in the crystallization promoting layer 106 is greater than 90% and less than 110% of the lattice constant of the crystal contained in the chalcogen layer 107.

[0069] Take for example a case where the chalcogen layer 107 contains Ge2Sb2Te5. Since the lattice constant of the fcc crystal of Ge2Sb2Te5 is 0.598 nm, it is preferable that the crystal contained in the crystallization promoting layer 106 also has a lattice constant of approximately the same level. Preferred materials for the crystallization promotion layer 106 include, for example, AlSb (0.614 nm), ZnTe (0.611 nm), LaTe (0.642 nm), CeTe (0.636 nm), PrTe (0.632 nm), NdTe (0.626 nm), GdTe (0.614 nm), TbTe (0.610 nm), DyTe (0.609 nm), HoTe (0.605 nm), ErTe (0.606 nm), TmTe (0.604 nm), YbTe (0.635 nm), LuTe (0.595 nm), etc. (The numbers in parentheses are the lattice constants of each material).

[0070] Further, an example will be taken in which the chalcogen layer 107 contains GeCu2Te3. Since the lattice constant of the fcc crystal of GeCu2Te3 is 0.599 nm, it is preferable that the crystal contained in the crystallization assisting layer 106 also has a lattice constant of approximately the same level. Preferred materials for the crystallization promotion layer 106 include, for example, AlSb (0.614 nm), ZnTe (0.611 nm), LaTe (0.642 nm), CeTe (0.636 nm), PrTe (0.632 nm), NdTe (0.626 nm), SmTe (0.659 nm), EuTe (0.659 nm), GdTe (0.614 nm), TbTe (0.610 nm), DyTe (0.609 nm), HoTe (0.605 nm), ErTe (0.606 nm), TmTe (0.604 nm), YbTe (0.635 nm), LuTe (0.595 nm), and the like (the numbers in parentheses are lattice constants).

[0071] Even if the chalcogen layer 107 contains other materials, it is preferable that the lattice constant of the crystals contained in the crystallization promoting layer 106 is greater than 90% and smaller than 110% of the lattice constant of the crystals contained in the chalcogen layer 107.

[0072] The composition ratio of each material in the chalcogen layer 107 and the crystallization promoting layer 106 can be observed by, for example, a method such as EDS (Energy Dispersive X-ray Spectrometry). It is also possible to set an approximation line by the least squares method or perform moving average processing on the composition ratio obtained by a method such as EDS, and to determine the composition ratio based on the results.

[0073] The crystal structure and lattice constant of the crystals contained in the chalcogen layer 107 and the crystallization promoting layer 106 can be analyzed by a method such as the NBD (Nano Beam Diffraction) method.

[0074] [Melting point of crystallization promoting layer 106] As described above, in the reset operation, the chalcogen layer 107 is melted. Here, when the crystallization promoting layer 106 functions as a heater, the heat in the crystallization promoting layer 106 becomes larger than the heat in the chalcogen layer 107 in the reset operation. Here, if the crystallization promoting layer 106 also melts at the same time when the chalcogen layer 107 melts, the constituent elements of the layers may be mixed with each other, changing the characteristics of each layer, and causing a problem in the subsequent writing operation. Therefore, it is preferable that the melting point of the crystallization promoting layer 106 is sufficiently high so that the crystallization promoting layer 106 does not melt in the reset operation. For example, it is preferable that the melting point of the crystallization promoting layer 106 is about 300° C. higher than the melting point of the chalcogen layer 107. It is preferable that the melting point of the crystallization promoting layer 106 is at least higher than the melting point of the chalcogen layer 107.

[0075] Take for example a case where the chalcogen layer 107 contains Ge2Sb2Te5. Since the melting point of the fcc crystal of Ge2Sb2Te5 is 630°C, it is preferable that the melting point of the crystallization promoting layer 106 is higher than 630°C. More preferably, it is preferable that the melting point of the crystallization promoting layer 106 is higher than 930°C. Preferred materials for the crystallization promotion layer 106 that satisfy the conditions include, for example, AlSb (1060°C), ZnTe (1295°C), LaTe (1720°C), CeTe (1820°C), PrTe (1950°C), NdTe (2025°C), SmTe, EuTe (1526°C), GdTe (1825°C), TbTe, DyTe (1850°C), HoTe (1370°C), ErTe (1500°C), TmTeYbTe (1730°C), LuTe, etc. (the melting points of each material are shown in parentheses).

[0076] Even if the chalcogen layer 107 contains other materials, it is preferable that the melting point of the material contained in the crystallization promoting layer 106 is higher than the melting point of the material contained in the chalcogen layer 107. It is more preferable that the melting point of the crystallization promoting layer 106 is higher than the melting point of the chalcogen layer 107 by about 300° C.

[0077] The melting points of the materials contained in the chalcogen layer 107 and the crystallization promoting layer 106 can be analyzed by, for example, measuring the temperature at which the crystal structure is not maintained by cross-sectional TEM (Transmission Electron Microscope) observation while the memory cell MC is heated. The melting points of the materials can also be estimated from literature values.

[0078] [Band gap and electrical conductivity of crystallization promoting layer 106] As described above, when the crystallization promoting layer 106 functions as a heater, it is preferable that the crystallization promoting layer 106 has low electrical conductivity, that is, the band gap of the crystallization promoting layer 106 is larger. In particular, it is preferable that the band gap of the crystallization promoting layer 106 is larger than the band gap of the chalcogen layer 107. The crystallization promoting layer 106 and the chalcogen layer 107 are arranged in series, and the same amount of current flows during operation. Since the crystallization promoting layer 106 has lower electrical conductivity than the chalcogen layer 107, the temperature rise of the crystallization promoting layer 106 is larger than that of the chalcogen layer 107. Therefore, the crystallization promoting layer 106 functions as a heater more effectively.

[0079] Take the case where the chalcogen layer 107 contains Ge2Sb2Te5 as an example. Since the band gap of Ge2Sb2Te5 is 0.4 eV, it is preferable that the band gap of the crystallization promoting layer 106 is higher than 0.4 eV. Materials for the crystallization promoting layer 106 that satisfy the conditions are preferably, for example, AlSb (1.58 eV), ZnTe (2.26 eV), etc. (The melting points of each material are shown in parentheses).

[0080] Even if the chalcogen layer 107 contains other materials, it is preferable that the material contained in the crystallization assisting layer 106 has a higher band gap than the material contained in the chalcogen layer 107 .

[0081] The band gap of the material contained in the crystallization assisting layer 106 can be analyzed by a method such as optical absorption spectrum measurement.

[0082] [Thermal conductivity of crystallization promoting layer 106] As described above, the crystallization promoting layer 106 also functions as a heat shielding member for efficiently utilizing the heat required for the write operation. In order to function as a heat shielding member, it is preferable that the thermal conductivity of the crystallization promoting layer 106 is low. In particular, it is preferable that the thermal conductivity of the crystallization promoting layer 106 is lower than that of the chalcogen layer 107. This is because Joule heat generated in the crystallization promoting layer 106 is less likely to escape to the chalcogen layer 103 side.

[0083] The thermal conductivity of the materials contained in the chalcogen layer 107 and the crystallization promoting layer 106 can be estimated from literature values ​​based on the measured values ​​of the composition, crystal structure, etc. of the materials that constitute them.

[0084] [Modification 1 of the first embodiment] [Configuration of memory cell MC] 7A and 7B are schematic cross-sectional views of a memory cell MC according to Modification 1 of the first embodiment. Fig. 7A corresponds to a memory cell MC having a bit line BL provided below and a word line WL provided above. Fig. 7B corresponds to a memory cell MC having a word line WL provided below and a bit line BL provided above.

[0085] 7(a) and 7(b), the memory cell MC according to this embodiment includes a conductive layer 102, a chalcogen layer 103, a conductive layer 104, a barrier conductive layer 105, a chalcogen layer 107, a barrier conductive layer 108, and a conductive layer 109, which are stacked in this order in the Z direction, similarly to the first embodiment. Meanwhile, the memory cell MC according to this embodiment differs from the first embodiment in that it includes a crystallization promoting layer 106_1 instead of the crystallization promoting layer 106 between the barrier conductive layer 105 and the chalcogen layer 107. In addition, it includes a crystallization promoting layer 106_2 between the chalcogen layer 107 and the barrier conductive layer 108.

[0086] The crystallization promoting layers 106_1 and 106_2 contact the lower and upper surfaces of the chalcogen layer 107. The crystallization promoting layers 106_1 and 106_2 function as a crystallization base (template) capable of controlling the crystal structure of the chalcogen layer 107. The crystallization promoting layers 106_1 and 106_2 contact the chalcogen layer 107 from both the upper and lower surfaces, thereby enabling more suitable control of the crystal structure of the chalcogen layer 107. Furthermore, the time required for the chalcogen layer 107 to be crystallized can be further shortened.

[0087] The material contained in the crystallization promoting layers 106_1 and 106_2 may be, for example, the same material as the material contained in the crystallization promoting layer 106 according to the first embodiment. The material contained in the crystallization promoting layers 106_1 and 106_2 may have, for example, properties similar to those of the material contained in the crystallization promoting layer 106 according to the first embodiment.

[0088] For example, the lattice constant of the crystals contained in the crystallization promoting layers 106_1 and 106_2 is preferably greater than 90% and smaller than 110% of the lattice constant of the crystals contained in the chalcogen layer 107.

[0089] Moreover, the melting points of the materials contained in the crystallization promoting layers 106_1 and 106_2 are preferably higher than the melting point of the chalcogen layer 107. More preferably, the melting point of the crystallization promoting layer 106 is higher than the melting point of the chalcogen layer 107 by about 300° C.

[0090] In addition, the band gap of the material contained in the crystallization promoting layers 106_1 and 106_2 is preferably higher than the band gap of the material contained in the chalcogen layer 107.

[0091] Moreover, it is preferable that the thermal conductivity of the material contained in the crystallization promoting layers 106_1 and 106_2 is lower than the thermal conductivity of the chalcogen layer 107.

[0092] [Modification 2 of the First Embodiment] [Configuration of memory cell MC] 8A and 8B are schematic cross-sectional views of a memory cell MC according to Modification 2 of the first embodiment. Fig. 8A corresponds to a memory cell MC having a bit line BL provided below and a word line WL provided above. Fig. 8B corresponds to a memory cell MC having a word line WL provided below and a bit line BL provided above.

[0093] 8(a) and 8(b), the memory cell MC according to this embodiment includes a conductive layer 102, a chalcogen layer 103, a conductive layer 104, a barrier conductive layer 105, a barrier conductive layer 108, and a conductive layer 109, which are stacked in this order in the Z direction, similarly to the first embodiment. On the other hand, the memory cell MC according to this embodiment includes a plurality of crystallization promoting layers 106_3 and a plurality of chalcogen layers 107_1, which are alternately stacked between the barrier conductive layer 105 and the barrier conductive layer 108, unlike the first embodiment.

[0094] The crystallization promoting layers 106_3 are in contact with the lower and upper surfaces of the chalcogen layers 107_1, respectively. The crystallization promoting layers 106_3 function as a crystallization base (template) capable of controlling the crystal structure of the chalcogen layer 107_1.

[0095] In this modification, the thickness of each chalcogen layer 107_1 is reduced and the chalcogen layer 107_1 is divided into multiple layers, so that the multiple chalcogen layers 107_1 can be melted in a shorter time than in the first embodiment. In addition, by providing multiple crystallization promotion layers 106_3 in contact with both the upper and lower surfaces of each of the thinned chalcogen layers 107_1, the crystal structure of the chalcogen layer 107_1 can be more suitably controlled. In addition, by forming the chalcogen layer 107_1 into multiple thin layers, the time required to complete crystallization of all of the multiple chalcogen layers 107_1 can be shortened compared to the first embodiment.

[0096] The material contained in the crystallization promoting layer 106_3 may be, for example, the same material as the material contained in the crystallization promoting layer 106 according to the first embodiment. Also, the material contained in the crystallization promoting layer 106_3 may have the same characteristics as the material contained in the crystallization promoting layer 106 according to the first embodiment.

[0097] For example, the lattice constant of the crystals contained in the crystallization promoting layer 106_3 is preferably greater than 90% and smaller than 110% of the lattice constant of the crystals contained in the chalcogen layer 107_1.

[0098] The melting point of the material contained in the crystallization promoting layer 106_3 is preferably higher than that of the chalcogen layer 107_1, and more preferably, the melting point of the crystallization promoting layer 106_3 is higher than that of the chalcogen layer 107_1 by about 300° C.

[0099] In addition, the band gap of the material contained in the crystallization promoting layer 106_3 is preferably higher than the band gap of the material contained in the chalcogen layer 107_1.

[0100] Moreover, it is preferable that the thermal conductivity of the material contained in the crystallization assisting layer 106_3 is lower than the thermal conductivity of the chalcogen layer 107_1.

[0101] [Other Modifications of the First Embodiment] The configurations described with reference to FIGS. 3, 7, and 8 are merely examples, and the specific configurations can be adjusted as appropriate.

[0102] For example, in the example shown in FIG. 3(a), the crystallization promoting layer 106 is A 3(a), the crystallization promoting layer 106 may be provided between the chalcogen layer 107 and the barrier conductive layer 108. In the example shown in FIG. 3(b), the crystallization promoting layer 106 is provided so as to contact the cathode E C 3B, the crystallization promoting layer 106 may be provided between the chalcogen layer 107 and the barrier conductive layer 108.

[0103] 3, 7, and 8, the crystallization promoting layer 106 may be provided on at least one of the sidewall portions in the X direction and the Y direction of the chalcogen layers 107 and 107_1. In such a case, the crystallization promoting layer 106 may or may not be provided on at least one of the upper surface and the lower surface of the chalcogen layers 107 and 107_1.

[0104] [Second embodiment] [Schematic configuration] Next, a semiconductor memory device according to a second embodiment will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to the second embodiment. Fig. 10 is a schematic cross-sectional view of a resistance change element section VRP according to this embodiment.

[0105] 9, the semiconductor memory device according to this embodiment includes a memory cell array MCA2 and a peripheral circuit PC2 that controls the memory cell array MCA2. The memory cell array MCA2 includes a plurality of word lines WL2, a plurality of plate lines PL, and a plurality of bit lines BL2. The memory cell array MCA2 also includes, for example, a plurality of memory cells MC2.

[0106] The peripheral circuit PC2, like the first embodiment, includes, for example, a step-down circuit, a selection circuit, a sense amplifier circuit, and a sequencer for controlling these circuits.

[0107] Each of the memory cells MC2 is connected to a bit line BL2, a word line WL2, and a plate line PL. For example, multiple memory cells MC2 connected to the same word line WL2 are connected to the same plate line PL. On the other hand, multiple memory cells MC2 connected to the same word line WL2 are each connected to a different bit line BL2. Each of the memory cells MC2 includes a field effect transistor Tr and a resistance change element portion VRP.

[0108] The transistor Tr includes a gate terminal connected to the word line WL2, a drain terminal connected to the bit line BL2, and a source terminal connected to a node N1 which is one end of the resistance change element portion VRP. The transistor Tr has a function of selecting a memory cell MC2 to be operated.

[0109] 10, the resistance change element section VRP includes a conductive layer 202, a barrier conductive layer 205, a crystallization promoting layer 106_4, a chalcogen layer 107, a barrier conductive layer 208, and a conductive layer 209, which are stacked in this order above a semiconductor substrate (not shown). The conductive layer 202, the barrier conductive layer 205, the barrier conductive layer 208, and the conductive layer 209 are basically configured in the same manner as the conductive layer 102, the barrier conductive layer 105, the barrier conductive layer 108, and the conductive layer 109 described with reference to FIGS. 3(a) and 3(b). However, in the example of FIGS. 3(a) and 3(b), the widths of the conductive layer 102, the barrier conductive layer 105, the barrier conductive layer 108, and the conductive layer 109 in the X direction and the Y direction are approximately the same as the widths of the crystallization promoting layer 106 and the chalcogen layer 107 in the X direction and the Y direction. 10, the widths in the X and Y directions of the conductive layer 202, the barrier conductive layer 205, the barrier conductive layer 208, and the conductive layer 209 are larger than the widths in the X and Y directions of the crystallization promoting layer 106_4 and the chalcogen layer 107. The conductive layer 202 is connected to the node N1, not to the bit line BL or the word line WL. The conductive layer 209 is connected to the plate line PL, not to the word line WL or the bit line BL.

[0110] The crystallization promoting layer 106_4 is in contact with the lower surface of the chalcogen layer 107. The crystallization promoting layer 106_4 functions as a crystallization base (template) capable of controlling the crystal structure of the chalcogen layer 107.

[0111] The material contained in the crystallization promoting layer 106_4 may be, for example, the same material as the material contained in the crystallization promoting layer 106 according to the first embodiment. Also, the material contained in the crystallization promoting layer 106_4 may have the same characteristics as the material contained in the crystallization promoting layer 106 according to the first embodiment.

[0112] For example, the lattice constant of the crystals contained in the crystallization promoting layer 106_4 is preferably greater than 90% and smaller than 110% of the lattice constant of the crystals contained in the chalcogen layer 107.

[0113] Moreover, the melting point of the material contained in the crystallization promoting layer 106_4 is preferably higher than the melting point of the chalcogen layer 107. More preferably, the melting point of the crystallization promoting layer 106 is higher than the melting point of the chalcogen layer 107 by about 300° C.

[0114] In addition, the band gap of the material contained in the crystallization promoting layer 106_4 is preferably higher than the band gap of the material contained in the chalcogen layer 107.

[0115] Moreover, it is preferable that the thermal conductivity of the material contained in the crystallization assisting layer 106_4 is lower than the thermal conductivity of the chalcogen layer 107.

[0116] [Operation] First, the write operation to the memory cell MC2 according to this embodiment will be described. An ON voltage is applied to the word line WL2 connected to the target memory cell MC2 to be written to, and an OFF voltage is applied to the other word lines WL2, thereby turning the transistor Tr of the target memory cell MC2 ON and turning the other transistors Tr OFF. Next, for example, a write voltage and a ground voltage are applied to the bit line BL2 and plate line PL connected to the target memory cell MC2, respectively. As a result, a current is supplied to the resistance change element portion VRP of the target memory cell MC2, and data is written in the same manner as in the above-mentioned set operation.

[0117] Next, the read operation according to this embodiment will be described. As in the write operation, the transistor Tr of the target memory cell MC is turned on, and the other transistors Tr are turned off. Next, for example, a read voltage and a ground voltage are applied to the plate line PL and the bit line BL2 connected to the target memory cell MC, respectively. Next, the current flowing through the bit line BL2 or the voltage level of the bit line BL2 is detected to determine the data stored in the target memory cell MC.

[0118] [Modification of the second embodiment] FIG. 11 is a schematic cross-sectional view of a resistance change element section VRP2 according to a modification of the second embodiment.

[0119] 11, the resistance change element section VRP2 according to this modification is basically configured similarly to the resistance change element section VRP in the second embodiment. However, in the resistance change element section VRP2 shown in FIG. 11, instead of the crystallization promoting layer 106_4, two crystallization promoting layers 106_5 are provided so as to be in contact with the upper and lower surfaces of the chalcogen layer 107, respectively.

[0120] The crystallization promoting layer 106_5 functions as a crystallization base (template) capable of controlling the crystal structure of the chalcogen layer 107.

[0121] The material contained in the crystallization promoting layer 106_5 may be, for example, the same material as the material contained in the crystallization promoting layer 106 according to the first embodiment. Also, the material contained in the crystallization promoting layer 106_5 may have the same characteristics as the material contained in the crystallization promoting layer 106 according to the first embodiment.

[0122] For example, the lattice constant of the crystals contained in the crystallization promoting layer 106_5 is preferably greater than 90% and smaller than 110% of the lattice constant of the crystals contained in the chalcogen layer 107.

[0123] Moreover, the melting point of the material contained in the crystallization promoting layer 106_5 is preferably higher than the melting point of the chalcogen layer 107. More preferably, the melting point of the crystallization promoting layer 106 is higher than the melting point of the chalcogen layer 107 by about 300° C.

[0124] In addition, the band gap of the material contained in the crystallization promoting layer 106_5 is preferably higher than the band gap of the material contained in the chalcogen layer 107.

[0125] Moreover, it is preferable that the thermal conductivity of the material contained in the crystallization assisting layer 106_5 is lower than the thermal conductivity of the chalcogen layer 107.

[0126] [Other embodiments] The above describes the semiconductor memory devices according to the first and second embodiments. However, the above-described semiconductor memory devices are merely examples, and specific configurations and the like can be appropriately adjusted.

[0127] 1 and 2, two memory mats MM are arranged in the Z direction, the lower memory mat MM has a bit line BL located below and a word line WL located above, and the upper memory mat MM has a word line WL located below and a bit line BL located above. Also, the word line WL is provided in common to the memory mat MM located below and the memory mat MM located above. However, this configuration is merely an example, and for example, the bit line BL shown in FIG. 2 may be replaced with a word line WL, and the word line WL shown in FIG. 2 may be replaced with a bit line BL.

[0128] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0129] 102...conductive layer, 103...chalcogen layer, 104...conductive layer, 106...crystallization promoting layer, 107...chalcogen layer, 109...conductive layer, MC...memory cell, MCA...memory cell array, PC...peripheral circuit.

Claims

1. A first electrode and a second electrode; A plurality of phase change layers and a plurality of first layers are alternately provided between the first electrode and the second electrode. Equipped with the phase change layer includes at least one of germanium (Ge), antimony (Sb), and tellurium (Te); The first layer comprises: Aluminum (Al) and antimony (Sb), or Tellurium (Te), and at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Includes Semiconductor memory device.

2. The first electrode and the second electrode are aligned in a first direction, a sidewall layer is provided in contact with a surface of the plurality of phase change layers and the plurality of first layers on a second direction side intersecting with the first direction; The sidewall layer comprises: Aluminum (Al) and antimony (Sb), or Tellurium (Te), and at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Includes 2. The semiconductor memory device according to claim 1.

3. A first electrode and a second electrode aligned in a first direction; a phase change layer provided between the first electrode and the second electrode; a first layer provided in contact with a surface of the phase-change layer on a second direction side intersecting the first direction; Equipped with the phase change layer includes at least one of germanium (Ge), antimony (Sb), and tellurium (Te); The first layer comprises: Aluminum (Al) and antimony (Sb), or Tellurium (Te), and at least one of zinc (Zn), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Includes Semiconductor memory device.

4. the first layer includes a crystal having a first lattice constant; the phase change layer includes a crystal having a second lattice constant; The first lattice constant is greater than 90% and less than 110% of the second lattice constant.

4. The semiconductor memory device according to claim 1.

5. The melting point of the first layer is higher than the melting point of the phase change layer.

5. The semiconductor memory device according to claim 1.

6. The band gap of the first layer is greater than the band gap of the phase change layer.

6. The semiconductor memory device according to claim 1.

7. The thermal conductivity of the first layer is lower than the thermal conductivity of the phase change layer.

7. The semiconductor memory device according to claim 1.

8. The first layer includes cubic crystals.

8. The semiconductor memory device according to claim 1.

9. The phase change layer includes cubic crystals.

9. The semiconductor memory device according to claim 1.

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