Backside design for flat silicon carbide susceptors

Abstract

A susceptor for use in a processing chamber for supporting a wafer includes a susceptor substrate having a front surface and a back surface opposite the front surface, and a coating layer deposited on the susceptor substrate. The front surface has a pocket configured to hold a wafer to be processed in the processing chamber, the pocket being textured with a first pattern. The back surface is textured with a second pattern.

Description

[Technical field]

[0001] The embodiments described herein relate generally to susceptors used in semiconductor wafer processing, and more particularly to silicon carbide coated susceptors having a textured backside for use in epitaxial deposition processes. [Background technology]

[0002] Chemical vapor deposition (CVD) processes are used in semiconductor wafer processing, among other processes, to epitaxially deposit thin layers (typically less than 10 microns) on the wafer. The CVD process requires that the wafer held on a susceptor be heated to a high temperature, for example, to about 1200°C. The wafer is typically heated from room temperature to the high temperature within about 30 minutes. For high quality epitaxy deposition, the susceptor needs to be manufactured to have precise dimensions and to maintain its shape, especially flatness, during repeated rapid heating and cooling processes. That is, the susceptor is required to have excellent thermal shock resistance, high mechanical strength, and high thermal stability. In addition, the susceptor material needs to be impermeable to gases and not outgas so that the susceptor acts as a barrier against contaminants emitted from both the susceptor and the external environment within the CVD chamber. An example of such a material is silicon carbide (SiC), and thus the susceptor is typically made from a graphite substrate having a front surface with a pocket for holding the wafer inside and a back surface with a flat and planar surface that is coated with silicon carbide (SiC) by a CVD process. However, typical SiC-coated graphite susceptors are known to warp and bend during the CVD process. Such warping and bending is induced by the interface stress between the graphite substrate and the SiC coating layer due to the mismatch of coefficient of thermal expansion (CTE) and design differences between the front and back surfaces of the susceptor. The interface stress is further increased by recent demands in semiconductor wafer processing, such as the increase in the size of the susceptor to process larger size wafers, the increase in the thickness ratio of the SiC coating layer to the graphite substrate for a lightweight and durable susceptor, and the sophisticated design of the pocket on the front surface of the susceptor.

[0003] Therefore, there is a need for a susceptor that can reduce warping and bowing while still meeting size, weight, and design requirements. Summary of the Invention

[0004] An embodiment of the present disclosure includes a susceptor for use in a processing chamber for supporting a wafer. The susceptor includes a susceptor substrate having a front surface and a back surface opposite the front surface, and a coating layer deposited on the susceptor substrate. The front surface has a pocket configured to hold a wafer to be processed in the processing chamber, the pocket being textured with a first pattern, and the back surface being textured with a second pattern.

[0005] An embodiment of the present disclosure also includes a processing chamber. The processing chamber includes a chamber body in fluid communication with one or more gas sources and a substrate support assembly including a susceptor. The susceptor includes a susceptor substrate having a front surface and a back surface opposite the front surface, and a coating layer deposited on the susceptor substrate. The front surface has a pocket configured to hold a wafer to be processed in the processing chamber, the pocket being textured with a first pattern, and the back surface being textured with a second pattern.

[0006] An embodiment of the present disclosure further includes a method for manufacturing a susceptor for use in a processing chamber for supporting a wafer, the method including forming a susceptor substrate having a front surface and a back surface opposite the front surface, forming a pocket configured to hold a wafer to be processed in the processing chamber, texturing the pocket with a first pattern, texturing the back surface with a second pattern, and forming a coating layer on the susceptor substrate.

[0007] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description, briefly summarized above, may be made by reference to examples, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings show only some examples, and therefore should not be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective examples. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic top view of an exemplary multi-chamber processing system in accordance with certain examples of the present disclosure. [Diagram 2] 1 is a cross-sectional view of a thermal processing chamber that can be used to perform epitaxial growth, according to some examples of the present disclosure. [Figure 3A] FIG. 2 is a cross-sectional view of a scanning electron microscope (SEM) image of a susceptor according to one embodiment. [Figure 3B] FIG. 2 is a top view scanning electron microscope (SEM) image of a susceptor according to one embodiment. [Figure 4] 1 is a flow diagram of a method that may be utilized to manufacture a susceptor according to one embodiment. [Figure 5A] 5 is a schematic cross-sectional view of a portion of a susceptor 500 according to one embodiment. [Figure 5B] 5 is a schematic cross-sectional view of a portion of a susceptor 500 according to one embodiment. [Figure 5C] 5 is a schematic cross-sectional view of a portion of a susceptor 500 according to one embodiment. [Figure 6A] FIG. 2 is a perspective view of a susceptor according to one embodiment. [Figure 6B] FIG. 2 is a front view of a susceptor according to one embodiment. [Figure 6C] FIG. 2 is an enlarged front view of a susceptor according to one embodiment. [Figure 6D] FIG. 2 is a rear view of a susceptor according to one embodiment. [Figure 7A] 4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. [Figure 7B] 4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. [Figure 7C] 4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. [Figure 7D] 4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. [Figure 7E] 4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. [Figure 7F]4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. [Figure 7G] 4 is a pattern that can be applied to the backside of a susceptor according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] To facilitate understanding, wherever possible, the same reference numbers have been used to designate identical elements that are common to the figures.

[0010] In general, embodiments described herein relate to susceptors for holding wafers for semiconductor wafer processing, and more particularly to silicon carbide coated susceptors having a textured backside for use in epitaxial deposition processes. The texture on the backside of the susceptor reduces interfacial stress between the susceptor substrate and the coating layer during the epitaxy deposition process, reducing warping and curvature of the susceptor and improving the flatness of the susceptor.

[0011] 1 is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 may be processed in and transferred between various chambers without exposing the wafers to an ambient environment outside the processing system 100 (e.g., an atmospheric ambient environment such as may exist in a fab). For example, wafers may be processed in and transferred between various chambers in a low pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low pressure or vacuum environment between various processes performed on the wafers in the processing system 100. Thus, the processing system 100 can provide an integrated solution for processing a portion of a wafer.

[0012] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems available from Applied materials, Inc., Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0013] 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate transfer of wafers. The docking station 140 is configured to receive one or more front opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally comprises a blade 148 disposed at one end of the respective factory interface robot 142 configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0014] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings having slit valves for transferring wafers by transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas passing between the respective chambers. Generally, any port is open to transfer a wafer and is otherwise closed.

[0015] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 to the load lock chamber 104 or 106 via the port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down the load lock chambers 104 or 106 facilitates the transfer of wafers between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0016] With the wafer in the pumped down load lock chamber 104 or 106, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 into the transfer chamber 108 via ports 154 or 156. The transfer robot 112 can then transfer the wafer to and / or between any of the processing chambers 120, 122 for processing via respective ports 162, 164, and can transfer the wafer to the holding chambers 116, 118 for holding to await further transfer via respective ports 158, 160. Similarly, the transfer robot 114 can access wafers in the holding chambers 116 or 118 via ports 166 or 168, can transfer wafers to and / or between any of the processing chambers 124, 126, 128, 130 for processing via respective ports 170, 172, 174, 176, and can transfer wafers to the holding chambers 116, 118 for holding to await further transfer via respective ports 166, 168. Transfer and holding of wafers in and between the various chambers can occur in a low pressure or vacuum environment provided by a gas and pressure control system.

[0017] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing wafers. In some examples, the processing chamber 122 may perform a cleaning process, the processing chamber 120 may perform an etching process, and the processing chambers 124, 126, 128, 130 may perform respective epitaxial growth processes. The processing chamber 122 may be a SiCoNi™ Preclean chamber available from Applied Materials of Santa Clara, California. The processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials of Santa Clara, California.

[0018] The system controller 190 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 190 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 enables data collection and feedback from each chamber to regulate the performance of the processing system 100.

[0019] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 may be one of any form of general-purpose processor that can be used in an industrial environment. The memory 194 or non-transitory computer-readable medium is accessible by the CPU 192 and may be one or more of memory such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote. The support circuits 196 are coupled to the CPU 192 and may include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be performed under the control of the CPU 192 by the CPU 192 executing computer instruction codes stored in the memory 194 (or the memory of a particular process chamber) as, for example, software routines. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls the chamber to perform processes according to various methods.

[0020] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer apparatus in a processing system.

[0021] FIG. 2 is a cross-sectional view of a processing chamber 200 that may be used to perform epitaxial growth. The processing chamber 200 may be any one of the processing chambers 120, 122, 124, 126, 128, 130 of FIG. 1. Non-limiting examples of suitable processing chambers that may be modified according to embodiments disclosed herein may include RP EPI reactors, Elvis chambers, and Lennon chambers, all of which are commercially available from Applied Materials, Inc., Santa Clara, Calif. The processing chamber 200 may be added to a CENTURA® integrated processing system available from Applied Materials, Inc., Santa Clara, Calif. The processing chamber 200 is described below as utilized to perform various embodiments described herein, although other semiconductor processing chambers from different manufacturers may also be used to perform embodiments described in this disclosure.

[0022] The processing chamber 200 includes a chamber body 202, a support system 204, and a controller 206. The chamber body 202 includes an upper portion 208 and a lower portion 210. The upper portion 208 includes the area within the chamber body 202 between an upper dome 212 and the wafer W. The lower portion 210 includes the area within the chamber body 202 between a lower dome 214 and the bottom of the wafer W. A deposition process typically takes place on the top surface of the wafer W in the upper portion 208.

[0023] The support system 204 includes components used to perform and monitor a given process, such as the growth of an epitaxial film, in the processing chamber 200. A controller 206 is coupled to the support system 204 and adapted to control the processing chamber 200 and the support system 204. The controller 206 may be the system controller 190 or a controller controlled by the system controller 190 to control a process in the processing chamber 200.

[0024] The processing chamber 200 includes a number of heat sources, such as lamps 216 adapted to supply thermal energy to components disposed in the processing chamber 200. For example, the lamps 216 may be adapted to supply thermal energy to the wafer W, the susceptor 218, and / or the preheat ring 220. The lower dome 214 may be formed from an optically transparent material, such as quartz, to facilitate the passage of thermal radiation therethrough. It is contemplated that the lamps 216 may be positioned to supply thermal energy through the upper dome 212 as well as the lower dome 214.

[0025] The chamber body 202 includes a number of plenums formed therein. The plenums are in fluid communication with one or more gas sources 222, such as a carrier gas, and one or more precursor sources 224, such as a deposition gas and a dopant gas. For example, a first plenum 226 may be adapted to supply a deposition gas 228 therethrough to an upper portion 208 of the chamber body 202, and a second plenum 230 may be adapted to exhaust the deposition gas 228 from the upper portion 208. In this manner, the deposition gas 228 may flow parallel to the top surface of the wafer W.

[0026] If a liquid precursor is used, the processing chamber 200 may include a liquid vaporizer 232 in fluid communication with a liquid precursor source 234. The liquid vaporizer 232 is used to vaporize the liquid precursor supplied to the processing chamber 200. Although not shown, it is contemplated that the liquid precursor source 234 may include, for example, one or more ampoules of precursor liquid and solvent liquid, shut-off valves, and liquid flow meters (LFMs).

[0027] A substrate support assembly 236 is disposed in the lower portion 210 of the chamber body 202. The substrate support assembly 236 is shown supporting a wafer W in a processing position. The substrate support assembly 236 includes a susceptor support shaft 238 formed from an optically transparent material and a susceptor 218 supported by the susceptor support shaft 238. A shaft 240 of the susceptor support shaft 238 is disposed within a shroud 242 to which a lift pin contact 244 is coupled. The susceptor support shaft 238 is rotatable to facilitate rotation of the wafer W during processing. Rotation of the susceptor support shaft 238 is facilitated by an actuator 246 coupled to the susceptor support shaft 238. The shroud 242 is generally fixed in position and therefore does not rotate during processing. Support pins 248 couple the susceptor support shaft 238 to the susceptor 218.

[0028] The lift pins 250 are disposed through openings (not labeled) formed in the susceptor support shaft 238. The lift pins 250 are vertically actuable and adapted to contact the underside of the substrate W to lift the substrate W from a processing position (as shown) to a substrate removal position.

[0029] The preheat ring 220 is removably disposed on a lower liner 252 coupled to the chamber body 202. The preheat ring 220 is disposed about the interior volume of the chamber body 202 and surrounds the substrate W while the substrate W is in a processing position. The preheat ring 220 facilitates preheating of the process gases as they enter the chamber body 202 through a first plenum 226 adjacent to the preheat ring 220.

[0030] The central window portion 254 of the upper dome 212 and the bottom portion 256 of the lower dome 214 may be formed from an optically transparent material such as quartz. A peripheral flange 258 of the upper dome 212, which engages the central window portion 254 around its circumference, and a peripheral flange 260 of the lower dome 214, which engages the bottom portion 256 around its circumference, may all be formed from opaque quartz to prevent an O-ring 262 adjacent the peripheral flanges from being directly exposed to thermal radiation. The peripheral flange 258 may be formed from an optically transparent material such as quartz.

[0031] 3A and 3B are a cross-sectional view and a top view of a scanning electron microscope (SEM) image of a susceptor 300 according to one embodiment. The susceptor 300 may be the susceptor 218 disposed in the processing chamber 200 of FIG. 2. The susceptor 300 includes a susceptor substrate 302 and a coating layer 304. The susceptor substrate 302 is formed of graphite. The coating layer 304 is formed of silicon carbide (SiC). The graphite substrate 302 may be porous having pores 306 formed with tendrils of silicon carbide (SiC). The formation of silicon carbide (SiC) results in improved mechanical properties of the susceptor 300.

[0032] FIG. 4 is a flow diagram of a method 400 that may be utilized to fabricate a susceptor 500 having a front surface 508 and a back surface 510 opposite the front surface 508, according to one embodiment. FIGS. 5A, 5B, and 5C are schematic cross-sectional views of a portion of the susceptor 500 corresponding to various stages of the method 400. FIGS. 6A, 6B, 6C, and 6D are perspective, front, close-up, and back views of a susceptor 500 fabricated according to the method 400. FIGS. 7A, 7B, 7C, 7D, 7E, 7F, and 7G show various patterns that may be applied to the back surface 510 of the susceptor 500 according to the method 400. The susceptor 500 may be the susceptor 218 disposed in the processing chamber 200 of FIG. 2.

[0033] In block 402, a susceptor substrate 502 is formed. First, the susceptor substrate 502 is prepared by sawing any suitable graphite billet into a disk-shaped plate and grinding the surface of the disk-shaped plate, as shown in FIG. 5A. The susceptor substrate 502 may be formed of graphite having a purity of at least 99%. The susceptor substrate 502 may have a diameter of about 150 mm to about 400 mm, for example about 370 mm, and a thickness of about 1 mm to about 15 mm, for example about 3.70 mm.

[0034] In block 404, the susceptor substrate 502 may then undergo surface processing, such as precision machining, to provide a specific surface structure on the surface of the susceptor substrate 502. The surface structure may be provided using conventional methods known in the art. During surface processing, as shown in FIG. 5B, a pocket 512 is formed in the front surface 508 of the susceptor 500 for holding a wafer (not shown) within a susceptor ledge 514. The pocket 512 may be a cylindrical recess having a diameter of about 150 mm to about 300 mm, e.g., about 300 mm, and a depth of about 0.30 mm to about 1.00 mm, e.g., about 0.40 mm. The susceptor ledge 514 may have a width of about 15 mm to about 70 mm, e.g., about 35 mm. The back surface 510 of the susceptor is machined to a flat and planar surface.

[0035] The surface 516 of the pocket 512 on the front surface 508 is then textured by precision machining with a grid pattern 518, as shown in Figures 6B and 6C. The grid pattern 518 can have a width of about 0.20 mm to about 3.00 mm, e.g., about 0.43 mm, a pitch of about 0.80 mm to about 3.00 mm, e.g., about 1.14 mm, and a depth of about 0.10 mm to about 5.00 mm, e.g., about 0.31 mm.

[0036] In block 404, the back surface 510 is also textured by precision machining. In some embodiments, the surface 520 of the back surface 510 is uniformly textured with a pattern. One example of a pattern is a grid pattern that matches the grid pattern 518 applied to the surface 516 of the pocket 512 of the front surface 508. Another example of a pattern is a stripe pattern having a width of about 0.50 mm to about 30.00 mm, e.g., about 3 mm, a pitch of about 0.50 mm to about 3.00 mm, e.g., about 0.8 mm, and a depth of about 0.10 mm to about 5.00 mm, e.g., about 0.3 mm. In some other embodiments, a ring pattern 522 is formed on the outer edge of the surface 520 of the back surface 510. The ring pattern 522 can have a thickness of about 0.10 mm to about 5.00 mm, e.g., about 0.30 mm, and a width of about 5.00 mm to about 50.00 mm, e.g., about 35.00 mm. The width of the ring pattern 522 may be similar to the width of the susceptor ledge 514 on the front surface 508 to compensate for the interface stress induced by the structural difference between the front surface 508 and the back surface 510. In one example, the ring pattern 522 includes a gap 524, as shown in FIG. 7A. The gap 524 may have a width of about 5 mm to about 45 mm, for example about 30 mm, and a length of about 50 mm to about 120 mm, for example about 100 mm. In another example, the ring pattern 522 is formed of an array of bar-shaped portions 526 radially arranged on the outer edge of the surface 520 of the back surface 510, as shown in FIG. 7B. Each bar-shaped portion 526 may have a length of about 10 mm to about 50 mm, for example about 30 mm, and a width of about 0.50 mm to about 5.00 mm, for example about 1.00 mm. The ring pattern 522 may include other shapes as shown in FIG. 7C and FIG. 7D. In some other embodiments, a plurality of ring patterns 528 as shown in FIG. 7E, a plurality of radial line patterns 530 as shown in FIG. 7F, and a combination of a plurality of ring patterns 528 and a plurality of radial line patterns 530 as shown in FIG. 7G may be formed on the surface 520 of the back surface 510.Each of the plurality of ring patterns 528 may have a width of about 1 mm to about 20 mm, e.g., about 1.60 mm, a depth of about 0.1 mm to about 5 mm, e.g., about 0.30 mm, a diameter that varies from about 150 mm to about 300 mm, and a radial distance between adjacent ring patterns 528 of about 1 mm to about 20 mm, e.g., about 1.60 mm. Each of the plurality of radial line patterns 530 may have a width of about 1 mm to about 20 mm, e.g., about 1.60 mm, a depth of about 0.1 mm to about 5 mm, e.g., about 0.30 mm, a length of about 150 mm to about 300 mm, e.g., about 300 mm, and an angle between adjacent radial line patterns 530 of about 0.5° to about 45°, e.g., about 5°.

[0037] At block 406, the susceptor substrate 502 may then undergo a purification and chlorination process. The susceptor substrate 502 may be heated in a furnace and purged with nitrogen gas at a temperature of about 2000° C. Chlorine gas is purged into the furnace to remove metallic elemental impurities from the susceptor substrate 502 by chlorinating carbonaceous materials such as graphite to remove metallic elemental impurities. In the purification and chlorination process, the impurity levels of the susceptor substrate 502 may be reduced to less than about 5 ppm.

[0038] In block 408, a coating layer 504 is formed on the susceptor substrate 502 by conformally depositing silicon carbide (SiC) on the susceptor substrate 502 by a CVD process. The silicon carbide (SiC) is deposited by using an organosilicon precursor. The coating layer 504 can have a thickness of about 40 μm to about 300 μm, for example about 80 μm.

[0039] The susceptor 500 having the coating layer 504 on the susceptor substrate 502 then undergoes quality assurance (QA) inspection in block 410. The final dimensions of the susceptor 500 are determined by coordinate measuring machine (CMM) measurements by sensing discrete points on the surface of the susceptor 500.

[0040] The inventors observed warping and curvature of approximately 3.70 mm thick susceptors 500 having a flat, planar surface on the backside 510 manufactured according to blocks 402-410 of method 400 described above (i.e., not including block 410 for texturing the backside 510 of susceptor 500), and no reduction in warping and curvature was observed for approximately 5.00 mm thick and approximately 6.35 mm thick susceptors 500, each having a flat, planar surface on the backside. The inventors have observed that compared to an approximately 3.70 mm thick susceptor 500 having a flat, planar surface on the back surface 510, an approximately 3.70 mm thick susceptor having a back surface 510 textured with a grid pattern matching the grid pattern 518 on the surface 516 of the pocket 512 on the front surface 508 exhibits approximately 75.5% reduction in warping and curvature, and an approximately 3.70 mm thick susceptor having a back surface 510 textured with a stripe pattern exhibits approximately 64.6% reduction in warping and curvature.

[0041] In an embodiment described herein, a silicon carbide coated susceptor for holding a wafer in an epitaxial deposition process has a textured backside thereof, which reduces the interface stress between the susceptor substrate and the coating layer during the epitaxy deposition process, reduces warping and curvature of the susceptor, and improves the flatness of the susceptor.

[0042] It should be noted that the specific configurations described above are among several possible exemplary designs of a flat susceptor according to the present disclosure, and are not intended to limit the possible configurations, specifications, etc. of patterns according to the present disclosure. For example, the texture of the back surface of the susceptor is not limited to the patterns described above. In other examples, the back surface of the susceptor may be textured with other patterns to reduce interfacial stress between the susceptor substrate and the coating layer induced during the epitaxial process.

[0043] While the forgoing is directed to specific embodiments, other and further embodiments may be devised without departing from the basic scope thereof, which is determined by the claims that follow.

Claims

1. A processing chamber comprising: a chamber body in fluid communication with one or more gas sources; 1. A substrate support assembly comprising a susceptor, the susceptor comprising: a susceptor substrate having a front surface and a back surface opposite the front surface, the susceptor substrate comprising porous graphite; and a coating layer deposited on the susceptor substrate; Equipped with the front surface having a pocket configured to hold a wafer to be processed in a processing chamber, the pocket being textured with a first pattern; the back surface is textured with a second pattern, the second pattern including a ring pattern formed on an outer edge of the back surface, the ring pattern including two or more cuts disposed therein; a substrate support assembly; A processing chamber comprising:

2. 2. The processing chamber of claim 1, wherein the first pattern is a grid pattern having a width between 0.20 mm and 3.00 mm, a pitch between 0.80 mm and 3.00 mm, and a depth between 0.10 mm and 5.00 mm.

3. The processing chamber of claim 2 , wherein the ring pattern comprises a width between 5.00 mm and 50.00 mm, and a thickness between 0.10 mm and 5.00 mm.

4. The processing chamber of claim 2 , wherein the two or more cuts comprise a width between 5.00 mm and 45.00 mm and a length between 50.00 mm and 120.00 mm.

5. the susceptor substrate comprises graphite; The coating layer comprises silicon carbide (SiC); The processing chamber of claim 2 .

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