Electronic component embedded board

Abstract

To provide an electronic component built-in substrate having a structure including electronic components embedded in a plurality of insulation layers and capable of suppressing the occurrence of a warp.SOLUTION: An electronic component built-in substrate 1 has a structure including conductor layers L1-L5 and insulation layers 11-14 alternately laminated. The insulation layers 11-14 include the insulation layer 13 including embedded electronic components 52 and the insulation layer 12 including embedded electronic components 51; the total volume of the electronic components 52 is smaller than that of the electronic components 51; a core material 60 having the coefficient of thermal expansion different from that of an insulation material constituting the insulation layer 13 and functioning as a thermal expansion coefficient control member is further embedded in the insulation layer 13; and thereby, the core material 60 can suppress a warp resulting from a difference between the total volume of the electronic components 51 and that of the electronic components 52.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a substrate with built-in electronic components, and more particularly to a substrate with built-in electronic components having a structure in which electronic components are embedded in a plurality of insulating layers. [Background technology]

[0002] Patent Documents 1 and 2 disclose substrates with built-in electronic components, each having a structure in which electronic components such as semiconductor ICs are embedded in a plurality of insulating layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-191831 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-208367 Summary of the Invention [Problem to be solved by the invention]

[0004] Since electronic components such as semiconductor ICs have significantly different thermal expansion coefficients from the insulating materials, such as resin, that make up the insulating layers, if the volumes of electronic components embedded in multiple insulating layers differ, there is a problem in that the difference in thermal expansion coefficients on the front and back of the electronic component-embedded substrate can cause warping.

[0005] Therefore, an object of the present invention is to suppress the occurrence of warpage in an electronic component built-in substrate having a structure in which electronic components are embedded in a plurality of insulating layers. [Means for solving the problem]

[0006] The electronic component-embedded substrate according to the present invention is a substrate with an electronic component-embedded structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked, and the plurality of insulating layers include a first insulating layer in which one or more first electronic components are embedded, and a second insulating layer in which one or more second electronic components are embedded, the total volume of the first electronic components being smaller than the total volume of the second electronic components, and the first insulating layer further having embedded therein a thermal expansion coefficient adjusting member having a thermal expansion coefficient different from that of the insulating material constituting the first insulating layer.

[0007] According to the present invention, the thermal expansion coefficient adjusting member embedded in the first insulating layer makes it possible to suppress warpage caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component.

[0008] In the present invention, the first electronic component may have a smaller thermal expansion coefficient than the insulating material constituting the first insulating layer, the second electronic component may have a smaller thermal expansion coefficient than the insulating material constituting the second insulating layer, and the thermal expansion coefficient adjusting member may have a smaller thermal expansion coefficient than the insulating material constituting the first insulating layer. This reduces the thermal expansion coefficient of the entire first insulating layer including the first electronic component and the thermal expansion coefficient adjusting member, making it possible to make the thermal expansion coefficient closer to that of the entire second insulating layer including the second electronic component.

[0009] In the present invention, the first electronic component and the second electronic component may overlap in the stacking direction, which makes it possible to reduce the planar size of the electronic component-embedded substrate.

[0010] In the present invention, the thermal expansion coefficient adjusting member may be a core material containing glass cloth. This makes it possible to suppress warping of the electronic component-embedded substrate while increasing its mechanical strength. In this case, the electronic component-embedded substrate may further include via conductors that penetrate the first insulating layer and the core material, or may further include via conductors that penetrate the first insulating layer, with the core material being positioned to avoid the positions where the via conductors are provided. The former can improve the connection reliability of the via conductors, while the latter makes it easier to form vias for embedding the via conductors.

[0011] In the present invention, the thickness of the thermal expansion coefficient adjusting member may be thinner than the thickness of the first electronic component, so that the thermal expansion coefficient adjusting member does not increase the overall thickness.

[0012] In the present invention, the thermal expansion coefficients of the first and second insulating layers may be different from each other, and the difference in the thermal expansion coefficients between the first and second insulating layers makes it possible to suppress warpage caused by the difference in the total volume of the first electronic component and the second electronic component.

[0013] In the present invention, the multiple insulating layers further include a third insulating layer covering the first insulating layer from the side opposite the second insulating layer, and a fourth insulating layer covering the second insulating layer from the side opposite the first insulating layer, and the thermal expansion coefficients of the third insulating layer and the fourth insulating layer may be different from each other. This makes it possible to suppress warping caused by the difference in the total volume of the first electronic component and the total volume of the second electronic component due to the difference in the thermal expansion coefficients of the third and fourth insulating layers. [Effects of the Invention]

[0014] As described above, according to the present invention, it is possible to suppress the occurrence of warpage in an electronic component built-in substrate having a structure in which electronic components are embedded in a plurality of insulating layers. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 1 according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 2 according to a second embodiment of the present invention. [Figure 3] FIG. 3 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 3 according to a third embodiment of the present invention. [Figure 4]FIG. 4 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 4 according to a fourth embodiment of the present invention. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 5 according to a fifth embodiment of the present invention. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 6 according to a sixth embodiment of the present invention. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 7 according to a seventh embodiment of the present invention. [Figure 8] FIG. 8 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 8 according to an eighth embodiment of the present invention. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 9 according to a ninth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0017] First Embodiment FIG. 1 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 1 according to a first embodiment of the present invention.

[0018] 1, the electronic component built-in substrate 1 according to the first embodiment has a structure in which five conductor layers L1 to L5 and four insulating layers 11 to 14 are alternately stacked in the stacking direction. Here, insulating layer 11 is located between conductor layers L1 and L2, insulating layer 12 is located between conductor layers L2 and L3, insulating layer 13 is located between conductor layers L3 and L4, and insulating layer 14 is located between conductor layers L4 and L5. Each of insulating layers 11 to 14 is an interlayer film with conductor layers on both sides, and in that sense, solder resists 21 and 22 do not qualify as insulating layers.

[0019] The conductor layer L1 is located on the top layer, and a portion of it is covered with solder resist 21. The exposed portion of the conductor layer L1 that is not covered with solder resist 21 constitutes a terminal electrode E1 that is located on one surface 1a of the electronic component built-in substrate 1. The conductor layer L5 is located on the bottom layer, and a portion of it is covered with solder resist 22. The exposed portion of the conductor layer L5 that is not covered with solder resist 22 constitutes a terminal electrode E2 that is located on the other surface 1b of the electronic component built-in substrate 1. The surface 1a of the electronic component built-in substrate 1 may be mounted with electronic components such as semiconductor ICs and passive components (not shown), or may be used as a mounting surface for another circuit board (not shown). The surface 1b of the electronic component built-in substrate 1 may be used as a mounting surface for another circuit board (not shown), or may be mounted with electronic components such as semiconductor ICs and passive components (not shown).

[0020] As shown in Fig. 1, two conductor layers adjacent in the stacking direction are connected to each other by via conductors. For example, conductor pattern 31 located on conductor layer L1 and conductor pattern 32 located on conductor layer L2 are connected via via conductor 41 provided to penetrate insulating layer 11. conductor pattern 32 located on conductor layer L2 and conductor pattern 33 located on conductor layer L3 are connected via via conductor 42 provided to penetrate insulating layer 12. conductor pattern 33 located on conductor layer L3 and conductor pattern 34 located on conductor layer L4 are connected via via conductor 43 provided to penetrate insulating layer 13. conductor pattern 34 located on conductor layer L4 and conductor pattern 35 located on conductor layer L5 are connected via via conductor 44 provided to penetrate insulating layer 14.

[0021] The insulating layer 12 is composed of two insulating layers 12a and 12b, and an electronic component 51 is embedded between them. Similarly, the insulating layer 13 is composed of two insulating layers 13a and 13b, and an electronic component 52 is embedded between them. A terminal electrode provided on the electronic component 51 is connected to a conductor pattern 32 located on the conductor layer L2 through a via conductor 45. A terminal electrode provided on the electronic component 52 is connected to a conductor pattern 33 located on the conductor layer L3 through a via conductor 46. The insulating layers 12a and 13a function as adhesive layers when the electronic components 51 and 52 are mounted face-up in the manufacturing process of the electronic component-embedded substrate 1. Meanwhile, the insulating layers 12b and 13b function as embedding layers for embedding the electronic components 51 and 52 in the manufacturing process of the electronic component-embedded substrate 1. In this embodiment, the electronic components 51 and 52 overlap in the stacking direction, thereby reducing the planar size of the electronic component-embedded substrate 1.

[0022] The types of electronic components 51 and 52 are not particularly limited, and may be semiconductor ICs or passive components such as capacitors, inductors, and filters. If electronic components 51 and 52 are semiconductor ICs, the chip thickness may be reduced to 200 μm or less, for example, approximately 50 to 100 μm. Because electronic components 51 and 52 are mainly made of inorganic materials such as silicon, they have a smaller thermal expansion coefficient than insulating layers 11 to 14, which are mainly made of resin materials.

[0023] In this embodiment, the volume of electronic component 52 embedded in insulating layer 13 is smaller than the volume of electronic component 51 embedded in insulating layer 12. As a result, a difference in the thermal expansion coefficient between surface 1a and surface 1b of electronic component embedded substrate 1 occurs, which may cause warping of electronic component embedded substrate 1. To prevent this, electronic component embedded substrate 1 according to this embodiment has core material 60 including glass cloth embedded in insulating layer 13. Core material 60 has a smaller thermal expansion coefficient than the insulating material constituting insulating layer 13, and therefore functions as a thermal expansion coefficient adjusting member that reduces the thermal expansion coefficient of the entire insulating layer 13 including electronic component 52 and core material 60. In contrast, no core material with a low thermal expansion coefficient is embedded in insulating layer 12. This reduces the difference in the thermal expansion coefficient between the entire insulating layer 12 including electronic component 51 and the entire insulating layer 13 including electronic component 52 and core material 60, thereby preventing warping of electronic component embedded substrate 1. Furthermore, since the core material 60 is not present in the position overlapping with or around the electronic component 52, there is no interference between the electronic component 52 and the core material 60. Furthermore, if the thickness of the core material 60 is made thinner than the thickness of the electronic component 52, the core material 60 does not increase the overall thickness.

[0024] As described above, although there is a difference in volume between electronic components 51 and 52 in electronic component built-in substrate 1 according to this embodiment, because core material 60 with a small thermal expansion coefficient is embedded in insulating layer 13, it is possible to suppress warping of electronic component built-in substrate 1 caused by the difference in thermal expansion coefficient. Moreover, because core material 60 is provided on almost the entire surface of insulating layer 13, the mechanical strength of electronic component built-in substrate 1 is also increased. Furthermore, because via conductors 43 are provided so as to penetrate core material 60, the inner walls of the vias are roughened by the glass cloth. As a result, the adhesion between via conductors 43 and insulating layer 13 is improved, and the connection reliability of via conductors 43 is also improved.

[0025] Furthermore, if the warpage of the electronic component-embedded substrate 1 caused by the difference in thermal expansion coefficients cannot be eliminated by the core material 60 alone, the insulating material constituting the insulating layer 12 may have a higher thermal expansion coefficient than the insulating material constituting the insulating layer 13. As an example, if an inorganic filler with a low thermal expansion coefficient is added to the insulating layers 12 and 13, the content of the inorganic filler in the insulating layer 12 may be lower than the content of the inorganic filler in the insulating layer 13. Similarly, the insulating material constituting the insulating layer 11 may have a higher thermal expansion coefficient than the insulating material constituting the insulating layer 14. Even in this case, the thermal expansion coefficient on the surface 1a side increases, making it possible to ensure a balance between the thermal expansion coefficients on the surface 1a side and the surface 1b side.

[0026] <Second embodiment> FIG. 2 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 2 according to a second embodiment of the present invention.

[0027] 2, the electronic component built-in substrate 2 according to the second embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that the volume of the electronic component 51 embedded in the insulating layer 12 is smaller than the volume of the electronic component 52 embedded in the insulating layer 13, and that a core material 60 including glass cloth is embedded in the insulating layer 12. As the other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are designated by the same reference numerals and redundant explanations will be omitted.

[0028] As exemplified by the electronic component built-in substrate 2 according to the second embodiment, when the volume of electronic component 51 is smaller than the volume of electronic component 52, by embedding core material 60 in insulating layer 12 without embedding core material 60 in insulating layer 13, it is possible to suppress warping of electronic component built-in substrate 2 caused by the difference in thermal expansion coefficients.

[0029] <Third embodiment> FIG. 3 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 3 according to a third embodiment of the present invention.

[0030] 3, the electronic component built-in substrate 3 according to the third embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that a plurality of electronic components 51 are embedded in the insulating layer 12. As the other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0031] In this embodiment, there is not much difference in volume between the individual electronic components 51 and 52. However, because one electronic component 52 is embedded in the insulating layer 13, while two electronic components 51 are embedded in the insulating layer 12, the total volume of the electronic components 52 is smaller than the total volume of the electronic components 51. Even in such a case, if the core material 60 is embedded in the insulating layer 13 without being embedded in the insulating layer 12, it is possible to suppress warping of the electronic component-embedded substrate 3 caused by the difference in thermal expansion coefficients. As exemplified in this embodiment, when multiple electronic components are embedded in the insulating layer 12 or the insulating layer 13, the core material 60, which is a thermal expansion coefficient adjusting member, may be provided in the insulating layer with the smaller total volume of the embedded electronic components.

[0032] <Fourth embodiment> FIG. 4 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 4 according to a fourth embodiment of the present invention.

[0033] 4, the electronic component built-in substrate 4 according to the fourth embodiment differs from the electronic component built-in substrate 3 according to the third embodiment in that a dummy electronic component 53 is embedded in the insulating layer 13. As the other basic configurations are the same as those of the electronic component built-in substrate 3 according to the third embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0034] The electronic component 53 is a dummy electronic component that does not function as a circuit and serves solely to reduce the thermal expansion coefficient of the insulating layer 13. Therefore, the electronic component 53 may not be electrically connected to any conductor pattern, or a conductor pattern may be connected to the electronic component 53 for the purpose of heat dissipation. In the example shown in FIG. 4 , two electronic components 51 are embedded in the insulating layer 12, and one electronic component 52 and one dummy electronic component 53 are embedded in the insulating layer 13. Therefore, if the individual volumes of the electronic components 51 to 53 are approximately the same, warping of the electronic component-embedded substrate 4 due to differences in thermal expansion coefficients can be suppressed. As exemplified in this embodiment, the thermal expansion coefficient adjusting member does not necessarily have to be a core material 60 made of glass cloth or the like. Furthermore, using defective products that would otherwise be discarded as the dummy electronic components 53 can also reduce manufacturing costs.

[0035] <Fifth embodiment> FIG. 5 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 5 according to a fifth embodiment of the present invention.

[0036] 5, the electronic component built-in substrate 5 according to the fifth embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that the core material 60 is arranged so as to avoid the positions where the via conductors 43 are provided. As the other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0037] As exemplified in this embodiment, if the core material 60 is arranged so as to avoid the positions where the via conductors 43 are provided, when vias for embedding the via conductors 43 are formed by laser processing or the like, processing becomes easier.

[0038] Sixth Embodiment FIG. 6 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 6 according to a sixth embodiment of the present invention.

[0039] 6, the electronic component built-in substrate 6 according to the sixth embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that a core material 60 is disposed only around the electronic component 52. As the other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are denoted by the same reference numerals and redundant explanations will be omitted.

[0040] As exemplified in this embodiment, it is not necessary to arrange the core material 60 over almost the entire surface, and as long as the overall warpage is suppressed, the core material 60 may be arranged only around the electronic component 52. In this case, it is preferable to arrange the core material 60 so that it overlaps with the electronic component 51. This makes it possible to make the planar position where the thermal expansion coefficient of the insulating layer 13 is reduced approximately coincident with the electronic component 51. Furthermore, instead of the core material 60, a thermal expansion coefficient adjusting member made of an inorganic material such as silicon may be used.

[0041] Seventh Embodiment FIG. 7 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 7 according to a seventh embodiment of the present invention.

[0042] 7, the electronic component built-in substrate 7 according to the seventh embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that a plurality of dummy chips 61 are arranged on the insulating layer 13. As the other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0043] The dummy chips 61 are thermal expansion coefficient adjusting members made of an inorganic material such as silicon, and the number of dummy chips 61 is determined so that the thermal expansion coefficient of the insulating layer 13 is a desired value. As exemplified in this embodiment, it is also possible to reduce the thermal expansion coefficient of the insulating layer 13 by embedding multiple dummy chips 61 in the insulating layer 13. This makes it possible to finely adjust the thermal expansion coefficient of the insulating layer 13 by changing the number of dummy chips 61.

[0044] Eighth Embodiment FIG. 8 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 8 according to an eighth embodiment of the present invention.

[0045] 8, the electronic component built-in substrate 8 according to the eighth embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that a core material 62 including glass cloth is also embedded in the insulating layer 12. As the other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0046] The area of ​​the core material 62 embedded in the insulating layer 12 is smaller than the area of ​​the core material 60 embedded in the insulating layer 13. Therefore, the degree to which the core material 62 reduces the thermal expansion coefficient of the insulating layer 12 is smaller than the degree to which the core material 60 reduces the thermal expansion coefficient of the insulating layer 13. As exemplified in this embodiment, core materials may be embedded in both the insulating layers 12 and 13. In the example shown in FIG. 8 , the core material 62 is locally embedded in the insulating layer 12, but a core material 62 thinner than the core material 60 may be embedded over almost the entire surface.

[0047] <Ninth embodiment> FIG. 9 is a schematic cross-sectional view illustrating the structure of an electronic component built-in substrate 9 according to a ninth embodiment of the present invention.

[0048] 9, the electronic component built-in substrate 9 according to the ninth embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that a recess 60a having a locally thin thickness is provided in a core material 60, and an electronic component 52 is placed in the recess 60a. As the other basic configuration is the same as that of the electronic component built-in substrate 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0049] As exemplified in this embodiment, the core material 60 and the electronic component 52 may overlap. In this case, if a recess 60a is provided in the portion overlapping the electronic component 52, it is possible to suppress an increase in the overall thickness.

[0050] The above describes a preferred embodiment of the present invention, but the present invention is not limited to the above embodiment, and various modifications are possible within the scope of the present invention, and it goes without saying that these modifications are also included within the scope of the present invention.

[0051] For example, in the above embodiments, the thermal expansion coefficient of the electronic components 51, 52 is smaller than that of the insulating material constituting the insulating layers 12, 13. However, the thermal expansion coefficient of the electronic components 51, 52 may be larger than that of the insulating material constituting the insulating layers 12, 13. In this case, a material having a larger thermal expansion coefficient than that of the insulating material constituting the insulating layer 12 may be used as the thermal expansion coefficient adjusting member. [Explanation of symbols]

[0052] 1~9 Electronic component embedded board 1a One surface 1b Other surface 11 to 14, 12a, 12b, 13a, 13b Insulating layer 21,22 Solder resist 31~35 Conductor pattern 41~46 Via conductor 51~53 Electronic Components 60,62 Core material 60a recess 61 Dummy Chip E1,E2 terminal electrode L1~L5 conductor layers

Claims

1. An electronic component-embedded substrate having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately laminated, the plurality of insulating layers include a first insulating layer in which one or more first electronic components are embedded, and a second insulating layer in which one or more second electronic components are embedded; a total volume of the first electronic components is smaller than a total volume of the second electronic components; a thermal expansion coefficient adjusting member having a thermal expansion coefficient different from that of an insulating material constituting the first insulating layer is further embedded in the first insulating layer; The electronic component built-in substrate is characterized in that the thermal expansion coefficient adjusting member is not present in the position overlapping the first electronic component and in the surrounding area thereof.

2. the first electronic component has a thermal expansion coefficient smaller than that of an insulating material constituting the first insulating layer; the second electronic component has a thermal expansion coefficient smaller than that of an insulating material constituting the second insulating layer; 2. The electronic component built-in substrate according to claim 1, wherein the thermal expansion coefficient adjusting member has a thermal expansion coefficient smaller than that of the insulating material constituting the first insulating layer.

3. 3. The electronic component built-in substrate according to claim 1, wherein the first electronic component and the second electronic component overlap in the stacking direction.

4. 4. The electronic component built-in substrate according to claim 1, wherein the thermal expansion coefficient adjusting member is a core material containing glass cloth.

5. The electronic component built-in substrate according to claim 4 , further comprising a via conductor penetrating the first insulating layer and the core material.

6. a via conductor penetrating the first insulating layer; 5. The electronic component built-in substrate according to claim 4, wherein the core material is arranged so as to avoid positions where the via conductors are provided.

7. An electronic component-embedded substrate as described in any one of claims 1 to 3, characterized in that the thermal expansion coefficient adjustment member is a dummy electronic component or a dummy chip.

8. An electronic component-embedded substrate as described in any one of claims 1 to 7, characterized in that the thermal expansion coefficient adjusting member is not embedded in the second insulating layer.

9. 9. The electronic component built-in substrate according to claim 1, wherein the thickness of the thermal expansion coefficient adjusting member is thinner than the thickness of the first electronic component.

10. 10. The electronic component built-in substrate according to claim 1, wherein the first insulating layer and the second insulating layer have different thermal expansion coefficients.

11. the plurality of insulating layers further include a third insulating layer covering the first insulating layer from a side opposite to the second insulating layer, and a fourth insulating layer covering the second insulating layer from a side opposite to the first insulating layer; 11. The electronic component built-in substrate according to claim 1, wherein the third insulating layer and the fourth insulating layer have different thermal expansion coefficients.

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