Power module substrate, power module, and method for manufacturing power module

Abstract

The present disclosure relates to a substrate (200) for a power module (210) comprising a carrier sheet (201) having an insulating layer, the substrate (200) further comprising a first metallization layer (202) formed on a first surface of the carrier sheet (201), the first metallization layer (202) including a mounting area (207) for mounting at least one semiconductor die (204) of the power module (210), and the substrate (200) further comprises a second metallization layer (205) formed on a second surface of the carrier sheet (201) including an attachment area (206) for attaching the substrate (200) to a flat surface. At least a portion of the mounting area of ​​the first metallization layer (202) is structured with a plurality of first grooves (203), which extend from the outer surface of the first metallization layer (202) to the insulating layer and electrically divide the first metallization layer (202) into individual portions (202a, 202b, 202c). At least a portion of the mounting area of ​​the second metallization layer (205) is structured with at least one second groove (211), which extends from the outer surface of the second metallization layer (205) at least partially to the at least one insulating layer. The present disclosure further relates to a power module (210) including such a substrate (200) and a method for manufacturing the corresponding power module (210).

Description

[Technical Field]

[0001] The present disclosure relates to a power module substrate including a carrier sheet, a first metallization layer, and a second metallization layer. The present disclosure also relates to a power module including such a substrate and a manufacturing method for manufacturing such a power module. [Background technology]

[0002] JP 2002-344094 A relates to a circuit board for a power module, and more particularly to a circuit board for a power module, for example for an inverter device for an automobile, in which thermal cycling behavior is improved by forming grooves adjacent to the ends of the metallization pattern. Summary of the Invention [Problem to be solved by the invention]

[0003] The object of the present disclosure is to provide substrates and modules suitable for realizing power electronics, which are relatively easy to manufacture, can withstand thermal and / or mechanical stresses during manufacture and operation, and operate reliably even in the presence of high currents and / or voltages, as well as corresponding manufacturing methods. [Means for solving the problem]

[0004] According to one aspect of the present disclosure, a power module substrate is provided. The substrate includes a carrier sheet extending in a plane and including at least one insulating layer; and a first metallization layer formed on a first surface of the carrier sheet. The first metallization layer includes a mounting area for mounting at least one semiconductor die of the power module. The substrate further includes a second metallization layer formed on a second surface of the carrier sheet, the second surface being opposite the first surface, and the second metallization layer includes an attachment area for attaching the substrate to a flat surface. Projections of the mounting area and the attachment area onto the plane of the carrier sheet at least partially overlap. The mounting area is structured with at least one first groove, which extends from the outer surface of the first metallization layer to the at least one insulating layer to electrically divide the first metallization layer into individual portions. The attachment area is structured with at least one second groove, which extends from the outer surface of the second metallization layer at least partially to the at least one insulating layer.

[0005] Structuring at least a portion of the mounting and attachment areas on both sides can reduce bending or warping of the carrier sheet during thermal or mechanical stress cycles, e.g., during manufacturing, thereby reducing curvature of the finished substrate, which in turn reduces stress in the mechanical connections between the substrate and any carrier structures, increasing the reliability of assemblies such as power modules.

[0006] According to a further embodiment, a conductive material is disposed at the bottom of the at least one second groove, for example by disposing a conductive layer at the bottom of the trench or by filling at least the bottom of the trench with a resilient conductive material, and the conductive material interconnects ends of respective portions of the second metallization layer adjacent to the at least one second groove.

[0007] By forming an electrical connection between the side surfaces of the second groove, local high electric fields in the carrier sheet and the second groove, which mainly occur at the edges and corners of the metallization layer, can be avoided, thereby reducing electrical stress and avoiding partial discharge and insulation breakdown during operation.

[0008] According to a further embodiment, the carrier sheet further includes at least one first conductive layer disposed between the at least one insulating layer and the second metallization layer. The at least one second groove extends from an outer surface of the second metallization layer to a surface of the at least one first conductive layer. The at least one first conductive layer interconnects ends of respective portions of the second metallization layer adjacent to the at least one second groove. By maintaining the first conductive layer intact, electrical interconnections can be established, thereby mitigating adverse electrical effects associated with the second groove.

[0009] For example, the substrate may be an active metal brazing (AMB) substrate, and the at least one conductive layer may be a brazing layer formed on the surface of the at least one insulating layer. Such a structure is easy to manufacture. Dividing the second metallization layer by the second grooves balances the structuring of the first metallization layer. At the same time, an additional conductive layer, such as a brazing layer, may be used as a processing stop, for example, as an etch stop during etching, and may also be used to electrically connect adjacent ends of respective portions of the second metallization layer.

[0010] According to a further embodiment, the at least one second groove is formed as a trench extending from the outer surface of the second metallization layer to the at least one insulating layer. A conductive layer is disposed at the bottom of the trench, thereby interconnecting the ends of respective portions of the second metallization layer adjacent to the at least one second groove. Electrical interconnection can be established by, for example, covering at least the exposed portion of the insulating layer with a thin conductive layer or by, for example, filling at least the bottom of the at least one trench with a resilient conductive material, thereby mitigating adverse electrical effects associated with the second groove.

[0011] For example, the substrate may be one of a direct bond copper (DBC) substrate or a direct bond aluminum (DBA) substrate. Alternatively or additionally, the second metallization layer may be bonded directly to the surface of at least one insulating layer of the carrier sheet. Such substrates are widely available and offer a variety of advantageous effects, including favorable thermal properties for power electronics.

[0012] According to a further aspect, there is provided a power module including a substrate according to one of the embodiments and at least one semiconductor die mounted on a mounting area of ​​the first metallization layer.

[0013] Attaching the at least one semiconductor die to the mounting area of ​​the substrate, for example by soldering, sintering or a similar processing step, often requires heat treatment of the substrate or the at least one semiconductor die. The presence of the at least one second groove in the second metallization layer avoids or at least mitigates bending of the substrate, thereby avoiding or mitigating improper bonding connections of the power module when mounting the at least one semiconductor die on the substrate and / or when mounting the substrate to an underlying carrier structure such as a base plate, cooler, etc., which may involve application of heat to the substrate.

[0014] According to a further embodiment, the power module further includes a carrier structure, and the mounting area is mounted to a flat surface of the carrier structure. The carrier structure includes at least one of an electrically conductive carrier plate in electrical and / or thermal contact with the second metallization layer, a base plate in thermal contact with the second metallization layer, or a cooler in thermal contact with the second metallization layer. Reducing the curvature of the power module's substrate allows the substrate to be mounted to a larger flat surface area of ​​the carrier structure, including one or more of the base plate, the electrical carrier plate, and the cooler.

[0015] According to a further aspect, there is provided a method for manufacturing a power module, the method including providing a substrate including at least an insulating layer, a first metallization layer, and a second metallization layer, the first and second metallization layers being disposed on opposite sides of the insulating layer, the method further including structuring the first metallization layer to form at least one first groove, the first groove electrically dividing the first metallization layer into a plurality of individual portions, the method further including structuring the second metallization layer to form at least one second groove in a mounting region of the second metallization layer, the at least one second groove extending at least partially from an outer surface of the second metallization layer toward the insulating layer, the method further including mounting at least one semiconductor die in the mounting region of the first metallization layer and mounting at least the mounting region of the second metallization layer to a planar surface.

[0016] The above steps produce a power module with reduced bow, as detailed above with respect to other aspects of this disclosure.

[0017] According to a further embodiment, in the step of structuring the second metallization layer, the second metallization layer is etched, and the etching method, etching time, etching agent, and / or etching solution concentration are selected so that the at least one second groove does not extend completely to the insulating layer. By using appropriate etching parameters, partial etching of the second metallization layer can be achieved, which helps to mitigate undesirable electrical effects during operation of the power module.

[0018] The above manufacturing method is suitable for manufacturing, for example, the above power module substrate and the corresponding power module, and therefore the features and advantages described in relation to the substrate and the power module can be used for the manufacturing method and vice versa.

[0019] This disclosure includes several aspects of the invention, and all features described with respect to one aspect are also disclosed herein with respect to other aspects, even if each feature is not explicitly mentioned in the context of that particular aspect.

[0020] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily to scale. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a diagram illustrating a schematic of a surface metallization layer of a conventional substrate carrying a semiconductor die. [Figure 2] FIG. 2 is a diagram illustrating a schematic backside metallization layer of the substrate of FIG. 1. [Figure 3] FIG. 3 is a diagram schematically illustrating a cross section of the substrate of FIGS. 1 and 2. [Figure 4] FIG. 4 is a diagram illustrating a contact area between the substrate of FIGS. 1 to 3 and a flat surface. [Figure 5]FIG. 2 is a schematic diagram illustrating a surface metallization layer according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating a schematic backside metallization layer of the substrate of FIG. 5. [Figure 7] FIG. 7 is a diagram schematically illustrating a cross section of the substrate of FIGS. 5 and 6. [Figure 8] FIG. 8 is a diagram illustrating a contact area between the substrate and the flat surface of FIGS. 5 to 7. [Figure 9] FIG. 10 shows a simulation of the electric field strength in the region of a groove in a second metallization layer below an uninterrupted first metallization layer. [Figure 10] FIG. 10 shows a simulation of the electric field strength in the region of a groove in a second metallization layer below a discontinuous first metallization layer. [Figure 11] FIG. 10 is a diagram schematically illustrating a cross section of a substrate according to another embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a substrate according to another embodiment. [Figure 13] FIG. 10 shows a simulation of the electric field strength in the region of a groove in a second metallization layer below an uninterrupted first metallization layer. [Figure 14] FIG. 10 shows a simulation of the electric field strength in the region of a groove in a second metallization layer below a discontinuous first metallization layer. [Figure 15] FIG. 10 is a diagram schematically illustrating a cross section of a substrate according to another embodiment. [Figure 16] FIG. 10 is a diagram schematically illustrating a cross section of a substrate according to another embodiment. [Figure 17] 1A to 1C are diagrams schematically illustrating a method for manufacturing a power module. DETAILED DESCRIPTION OF THE INVENTION

[0022] While the invention is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that it is not intended to limit the invention to the particular embodiments described. On the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0023] Before describing various embodiments of the present disclosure in more detail, problems that may occur when manufacturing a power module using conventional techniques will first be described with reference to FIGS.

[0024] FIG. 1 shows a conventional insulating carrier sheet 101 of a substrate 100 having a first metallization layer 102 formed on a first side or surface thereof. In the illustrated example, the material of the first metallization layer 102 is divided into three individual portions 102a, 102b, and 102c by two grooves 103a and 103b. The grooves 103a and 103b extend from the outer surface of the first metallization layer 102 through the entire thickness of the first metallization layer 102 and into the carrier sheet 101. In the example shown in FIG. 3, the groove 103b extends from the top surfaces of the individual portions 102a and 102b all the way to the contact interface between the individual portions 102a, 102b, and 102c of the first metallization layer 102 and the underlying insulating carrier sheet 101. This top surface and contact interface are located on both major surfaces of the first metallization layer 102.

[0025] A total of four semiconductor dies 104a, 104b, 104c, and 104d are mounted on portions 102a-102c. In the embodiment shown in FIG. 1, each of semiconductor dies 104a-104d is mounted to one of portions 102a-102c of first metallization layer 102. Additional contacts may be provided from the top surfaces of semiconductor dies 104a-104d. In alternative embodiments not shown, one or more of semiconductor dies 104a-104d or other discrete elements, such as NTC resistors with two or more terminals, may span some of the portions of first metallization layer 102. Of course, the number of portions of first metallization layer 102, the number of insulating grooves 103 between them, and the number of components attached thereto are not limited in any way and will vary depending on the intended design and purpose of the module.

[0026] Figure 2 shows the second or back side of the substrate 100 of Figure 1, opposite the carrier sheet 101. As can be seen, most of the back side is covered with a single, uniform second metallization layer 105. The second metallization layer 105 essentially forms an attachment area 106 that is typically used to mount the carrier substrate 100 to a flat surface, such as a carrier plate made of a conductive material, such as a metallic material or a composite material, such as AlSiC or MgSiC, and provides a contact area for a common potential, typically an electrical ground, or a base plate or cooler that acts as a heat sink.

[0027] During manufacturing, the substrate 100, such as that shown in FIGS. 1 and 2, undergoes various processing steps. Some of these processing steps are performed at high temperatures and / or with mechanical forces. For example, the semiconductor dies 104a-104d may be soldered or sintered to the first metallization layer 102 using a heat treatment. Sintering also applies pressure to the substrate 100. Due to physical imbalances between the first metallization layer 102 and the second metallization layer 105, the substrate 100, including the carrier sheet 101, the first metallization layer 102, and the second metallization layer 105, may bend in response to thermal and / or mechanical stresses, resulting in the bowing shown in FIG. 3. This effect is relevant, for example, to the design of power electronics modules that use relatively large substrates with relatively large metallization features to accommodate their respective current, thermal, and reliability requirements. In the exemplary embodiment, the central portion 107 of the substrate 100 bends upward, i.e., away from the planar surface of the underlying baseplate 108, forming a gap 111 with this planar surface. This is undesirable for several reasons.

[0028] For example, as shown in FIG. 4 , if the second metallization layer 105 is attached to the underlying base plate 108 by soldering, the solder 109 connects the second metallization layer 105 and the base plate 108 only at the periphery 110 of the attachment area 106. In contrast, a gap 111 formed in the center 107 of the attachment area 106 would result in a weakened thermal, mechanical, and / or electrical connection between the base plate 108 and the substrate 100. Even if the gap 111 were not formed, the resulting solder layer would have an uneven thickness, which could result in reduced reliability with respect to thermomechanical stress. Therefore, such bowing poses challenges to properly and uniformly bonding the substrate 100 to the underlying base plate 108. Bowing can also cause thermal problems due to increased thermal resistance. Furthermore, a bent substrate 100 generally makes it more difficult to handle and process the substrate 100 in subsequent processing steps. The stresses caused by such bending of the substrate 100 can then also shorten the life of the completed device, such as a power module, with respect to thermal cycling.

[0029] In particular, the inventors have found that the above-mentioned adverse effects can be mitigated by providing at least one groove in the attachment area 106 of the second metallization layer 105. In doing so, this structuring of the first and second metallization layers 102 and 105 can at least partially balance and compensate for stresses, thereby reducing bowing of the substrate 100.

[0030] An improved embodiment of substrate 200 will be described with reference to Figures 5-8. The arrangement of surface metallization layer 202 and semiconductor dies 204a-204d shown in Figure 5 corresponds to the surface of substrate 100 shown in Figure 1. For brevity, reference is made to the corresponding parts above. However, to at least partially balance the two grooves 203a and 203b provided in first metallization layer 202, second metallization layer 205 shown in Figure 6 also includes several second grooves, which help to reduce mechanical stress and therefore curvature of substrate 200.

[0031] As detailed above with respect to the first groove 103, the second groove extends inward from the outer surface of the second metallization layer 205, i.e., toward the carrier sheet 201. The term "outer surface" refers to the surface of the second metallization layer 205 opposite the interface between the second metallization layer 205 and the carrier sheet 201, i.e., the surface facing the flat surface for mounting the substrate 200. In the described example, the outer surface of the second metallization layer 205 is attached to the flat surface of the base plate 208.

[0032] In the illustrated example, two horizontal grooves 211a and 211b and a vertical groove 211c are provided. The thicknesses of the metallization layers 202 and 205 may be 0.1 to 5 mm, e.g., 0.1 to 3 mm or 0.1 to 1 mm. In the described example, the first metallization layer 202 is 0.5 mm thick, and the second metallization layer 205 is slightly thinner, 0.4 mm. Alternatively, the thicknesses of the two metallization layers 202 and 205 may be the same. In general, the location of the upper grooves and the thickness ratio of the metallization layers should be taken into consideration for stress compensation.

[0033] In a first approximation, the second grooves 211 of the back metallization provided by the second metallization layer 205 are provided below the corresponding first grooves 203 of the top metallization provided by the first metallization layer 202. Nevertheless, as shown in Figures 5 and 6, this may deviate, for example due to different metallization thicknesses and / or individual stress situations caused by the mounted semiconductor die 204.

[0034] It should be noted that despite the presence of the second grooves 211a-211c, all portions of the second metallization layer 205 remain at the same potential, e.g., electrically connected. In the embodiment shown in FIG. 6, this is achieved by surrounding all grooves 211a-211c with material from the second metallization layer 205. This can also be achieved by attaching all portions of the second metallization layer 205 to a common conductive carrier plate, or by maintaining or providing conductive material at the bottom of the grooves 211a-211c, as described in more detail below. In contrast, the various portions 202a-202c of the first metallization layer 202 are electrically isolated from one another to enable desired operation and control of the semiconductor dies 204a-204d, such as high-power FET, diode, or IGBT structures.

[0035] The presence of second grooves 211a-211c approximately balances the presence of first grooves 203a and 203b in first metallization layer 202. Furthermore, if metallization layers 202 and 205 have different thicknesses, second grooves 211a-211c can also balance the effects caused by this imbalance. As a result, even after performing a heat treatment and attaching semiconductor dies 204a-204d to first metallization layer 202, substrate 200 remains essentially flat, as shown in FIG.

[0036] As a result, essentially all portions of second metallization layer 205 that form mounting region 206 are in direct contact with the underlying flat surface. For example, substrate 200 can be sintered or soldered to flat metal surface regions of base plate 208 and / or a cooler (not shown) used to cool semiconductor dies 204a-204d. This results in a more stable mechanical connection between substrate 200, semiconductor dies 204a-204d disposed on its surface, and any underlying carrier structure. Furthermore, it results in a lower thermal resistance R between the active semiconductor components and any attached cooling assemblies.

[0037] This situation is illustrated by the continuous solder 209 shown in Figure 8. As a result, a power module 210 can be formed that includes an essentially planar substrate 200, one or more semiconductor dies 204 disposed in a mounting area 207 on one side of the substrate 200, and optionally a base plate 208, conductive carrier plate, and / or cooler disposed in a mounting area 206 on the opposite side of the substrate 200. The mounting area 206 and mounting area 207 of the substrate at least partially overlap when projected onto the central plane of the substrate 200.

[0038] The first and second metallization layers 202 and 205 may be the same size, or may have different absolute sizes, as shown in FIG. 7 . Generally, grooves 203a and 203b divide the metal pattern onto which semiconductor dies 204a-204d, corresponding to the individual portions 202a-202c of the first metallization layer 202, are mounted. Thus, the grooves are typically found in the center of the substrate 200, and not just at the edges of the substrate 200. This is also true for the second grooves 211a-211c of the second metallization layer 205. Therefore, the terms attachment region 206 and mounting region 207 refer to the inner central portions of the respective metallization layers 202 and 205, respectively, rather than the outer peripheral regions near the edges of the carrier sheet 201. For example, these may be defined to cover 95, 90, or 80 percent of the interior surface area of ​​each side of the carrier sheet 201, or conversely, to exclude the outer 5, 10, or 20 percent, respectively, nearest the edge of the carrier sheet 201, which may be referred to as the peripheral region. In one example, the outer peripheral region may cover a border region having a width of less than 5 mm, e.g., 2 mm, measured from the edge of the substrate 200.

[0039] 7, second grooves 211a-211c extend completely from the outer surface of the lower portion of second metallization layer 205 that forms mounting region 206 to carrier sheet 201. In the described example, carrier sheet 201 is made entirely of an insulating material, such as a ceramic sheet for high voltage applications or a resin sheet for other applications. As mentioned above, such complete removal of the metal material of second metallization layer 205 in the region of second grooves 211a-211c can be used to mitigate curvature of substrate 200.

[0040] 9 and 10, the inventors have also discovered that complete removal of the conductive material of the second metallization layer 205 in the region of the second groove between the insulating material of the carrier sheet 201 and the underlying carrier structure can also have adverse effects during operation of a power module utilizing such a substrate 200. In particular, the open surface of the insulating carrier sheet 201 can result in high electric fields and partial discharges at the edges of the remaining portion of the second metallization layer 205.

[0041] FIG. 9 shows a simulation of the electric field strength in such a configuration. For simplicity, only a single groove 211 in the second metallization layer 205 is shown. An uninterrupted first metallization layer 202 is shown on top of the insulating carrier sheet 201. For the simulation, the solder 209, any underlying carrier structure (not shown in FIG. 9), and adjacent portions of the lower second metallization layer 205 are connected to a low potential, e.g., electrical ground. The upper first metallization layer 202 is connected to a high potential, e.g., a positive voltage. On the left and right sides of FIG. 9, i.e., away from the second groove 211, the electric field is nearly uniform within the insulating carrier sheet 201, with a constant potential gradient. However, as one approaches the groove 211, particularly at the corners 212a and 212b where the groove 211 meets the insulating carrier sheet 201, relatively large changes in the electric field can be observed, which can lead to partial discharges next to the edges and within the groove 211. Such partial discharges can be problematic when the resulting power module is operated at high voltages and / or frequencies, resulting in reduced module life and / or reduced manufacturing yields.

[0042] FIG. 10 shows a second simulation similar to that described above with respect to FIG. 9 . In contrast to the situation in FIG. 9 , in the situation shown in FIG. 10 , the first metallization layer 202 is also divided by a first groove 203, which is horizontally co-located with the second groove 211. Furthermore, the left portion 202a of the first metallization layer 202 is again connected to a high potential, while the right portion 202b of the first metallization layer 202 is connected to a low potential, e.g., electrical ground, corresponding to the potential of the second metallization layer 205, the solder 209, and any underlying carrier structures (not shown in FIG. 10 ). Thus, in the right portion of FIG. 10 , there is substantially no electric field between the two metallization layers 202 and 205. A uniform electric field intensity can be observed in the leftmost portion of FIG. 10 , which corresponds to the electric field intensity shown in the corresponding portion of FIG. 9 . In this example, a high electric field intensity can be observed at the left corner 212a of the second groove 211, but not at the right corner 212b of the second groove 211. Correspondingly, the area surrounding the corresponding corner 213a of the first groove 203 exhibits a locally very high electric field intensity. The electric field intensity in these areas of the first groove 203 can be reduced by coating critical locations with a polyimide layer and / or by embedding the module interior in a dielectric gel. Additionally, the gel and / or polyimide can improve the dielectric breakdown strength of the configuration. However, this approach cannot be easily applied to the second groove 211 of the second metallization layer 205 because it may interfere with the soldering process used to solder the mounting area 207 to the base plate 208 or other carrier structure.

[0043] FIG. 11 illustrates a further embodiment of a substrate according to an embodiment of the present disclosure. In the embodiment illustrated in FIG. 11, a so-called active metal brazing (AMB) substrate 214 is provided. The AMB substrate 14 includes an intermediate ceramic layer 215, which functions as an insulating layer for the substrate 214, coated on its upper and lower sides with brazing layers 216 and 217, respectively. An upper first metallization layer 202 and a lower second metallization layer 205 are provided on the outer surfaces of the brazing layers 216 and 217, respectively. In the described embodiment, the first metallization layer 202 is provided by an upper copper layer 218, and the lower second metallization layer 205 is provided by a lower copper layer 219. Alternatively, aluminum may be used to provide the metallization layers 202 and / or 205. The electrically insulating ceramic layer 215 and the electrically conductive upper and lower brazing layers 216 and 217 together correspond to the carrier sheet 201 of the substrate 200, as described in detail above with respect to FIG. 7.

[0044] 11 , both the upper copper layer 218 and the lower copper layer 219 are structured using grooves 203 and 211, respectively, for example by selectively etching the copper layers 218 and 219. The mounting area provided on the upper surface of the upper copper layer 218, which has a width C1, is divided into two portions 202a and 202b, each having a width A. These two portions 202a and 202b are separated by a separating trench in the form of a first groove 203, which has a width B. It should be noted that the lower brazing layer 216 is also absent in the region of the first groove 203 and has been etched away, for example. Between the upper surface of each of the portions 202a and 202b of the upper copper layer 218 and the lower ceramic layer 215, a transition zone having a width D is provided, in which the upper copper layer 218 is only partially missing and the upper brazing layer 216 remains intact. Instead of etching, other structuring methods are also possible, including stacking metal pieces onto a carrier sheet 201 to form the substrate 200, or manufacturing the substrate 200 by an additive manufacturing method, for example by selective coating with a metal material.

[0045] Correspondingly, the second metallization layer 205 below the AMB substrate 214 is also structured, for example by etching, to balance the presence of the structuring of the first metallization layer 202. However, unlike the structuring of the top surface of the AMB substrate 214, the trenches in the lower copper layer 219 of the AMB substrate 214 do not penetrate the lower braze layer 217. Instead, when the second grooves 211 of the attachment region 206 with width C2 are formed, for example by etching, the lower braze layer 217, which typically comprises a material other than the second metallization layer 205, such as titanium nitride (TiN), silver (Ag) and / or a silver / copper alloy (Ag / Cu), is used as a processing stop, for example as an etch stop in the etching process, and remains essentially intact, as shown in FIG. 11 . As a result, the left and right adjacent portions 205 a and 205 b of the second metallization layer 205 remain electrically connected by the lower braze layer 217. This increases manufacturing yield, improves process stability, and is relatively easy to achieve with conventional semiconductor processing equipment. Maintaining electrical connectivity prevents high electric field strength and partial discharges in the second grooves 211.

[0046] It should be noted that the single groove 211 shown in FIG. 11 is used merely as an example to illustrate the formation of an individual groove 211. In practice, the second metallization layer 205 of the substrate 200 used in a given power module may be provided with a more complex groove structure. For example, one or more closed and / or intersecting second grooves 211 of various thicknesses and lengths may be provided. The exact number, orientation, connections, and widths of the second grooves 211 provided in the second metallization layer generally depend on the structuring of the first metallization layer 202 and, optionally, the occupancy of this structuring with the semiconductor die 204 and other components (not shown), as well as the relative thicknesses of the first and second metallization layers 202 and 205. A suitable structure for the grooves 211 in the second metallization layer 205 can be obtained by experiment or simulation.

[0047] As a general rule, the amount of material remaining above the carrier sheet 201 should correspond to the amount of material remaining below the carrier sheet. As an approximation, the amount of material in the first metallization layer 202 should correspond to the amount of material in the second metallization layer. Conversely, if the first and second metallization layers are similarly sized, the volume of metal removed or omitted from the second metallization layer 205 during structuring should be approximately equal to the amount of metal removed from the first metallization layer 202. Thus, if the thicknesses of the metallization layers 202 and 205 are equal, the surface areas of the first grooves 203 and the second grooves 211 should be comparable. If the first metallization layer 202 is thicker, more material must be removed or omitted from the second metallization layer 205, or more second grooves 211 must be incorporated into the second metallization layer 205. Additionally, the semiconductor die 204 or other components mounted on the first metallization layer 202 may also have an impact and may be considered in determining the size and location of the one or more second grooves 211. Furthermore, it may be beneficial for the groove structure of the second metallization layer 205 to at least partially overlap the groove structure of the first metallization layer 202 when projected onto the plane of the substrate 200. For example, if the thickness of the first metallization layer 202 corresponds to the thickness of the second metallization layer, the at least one first groove 203 and the at least one second groove may be congruent. Alternatively, if the thickness of the first metallization layer 202 differs from the thickness of the second metallization layer 205 and / or if a semiconductor die is bonded to the first metallization layer 202, at least a portion of the at least one first groove 203 and the at least one second groove 211 may not be congruent. For example, the positions of the at least one first groove 203 and the at least one second groove 211 may be co-located, but the at least one first groove 203 may have a larger or smaller width than the at least one second groove 211.

[0048] Figure 12 shows a further embodiment according to the present disclosure. In contrast to Figure 11, the embodiment shown in Figure 15 shows a direct-bonded aluminum (DBA) substrate 220. Similarly, direct-bonded copper (DBC) may be used. In the described embodiment, an upper aluminum layer 221 is bonded directly to a ceramic substrate 222, which acts as an insulating layer. Similarly, a lower aluminum layer 223 is bonded directly to the underside of the ceramic substrate 222.

[0049] Except for the metallic material and the absence of brazing layers 216 and 217, the overall structure of DBA substrate 220 corresponds to that of AMB substrate 214 of FIG. 11 . However, due to the absence of lower brazing layer 217, structuring lower aluminum 223 by an etching or other removal process stopped by the additional metallic layer completely divides lower aluminum layer 223 into adjacent portions 205 a and 205 b during fabrication. To avoid undesirable spikes in electric field strength as detailed above, the exposed portion of the underside of ceramic substrate 222 at the bottom of trench 224 forming second groove 211 is coated with a thin conductive layer 225. For example, after trench 224 is formed, a thin copper, silver, or other metal film can be applied to this area. This can be achieved using a variety of techniques, such as thick- or thin-film coating by chemical vapor deposition (CVD) or sputtering. In this way, a direct electrical connection between adjacent portions 205a and 205b of second metallization layer 205 is re-established, thereby improving the electric field distribution as will be described in more detail below with respect to FIGS. 13 and 14.

[0050] Figures 13 and 14 show electrical simulations of the electric field strength in a substrate 200 having a groove 211 in the second metallization layer 205, as described above with respect to Figure 12. Unlike the situation shown in Figures 9 and 10, the exposed area at the bottom of the groove 211 in the second metallization layer 205 was coated with a thin conductive layer 225 to avoid high electric field strength and partial discharge in the second groove 211. Similar to Figures 9 and 10, in Figure 13 the top metallization layer 202 is uninterrupted and connected to a high potential, while in Figure 14 it is interrupted in the region of the second groove 211 by a first groove 203 and connected to a high potential (left) and a low potential (right), respectively.

[0051] As can be seen in Figures 13 and 14, due to the electrical connection through the conductive layer 225 in the region of the second groove 211, no locally increased electric field occurs near the corners 212a and 212b. Instead, only a uniform electric field exists within the insulating carrier sheet 201. Therefore, the corners 212a and 212b do not experience a high voltage drop. In fact, in Figure 13, the electric field strength in the second groove 211 is relatively low and constant, thereby improving the lifespan of the manufactured substrate 200 and the power module incorporating it. With respect to Figure 14, the locally increased electric field strength occurs only at the groove ends 213a of the first metallization layer 202, which are necessary for electrical isolation between metal patterns at different potentials.

[0052] Figure 15 illustrates a further embodiment according to the present disclosure. In contrast to Figure 12, the embodiment illustrated in Figure 15 shows a resin sheet 228 that serves as substrate 200. In the described embodiment, different portions 202a and 202b of first metallization layer 202 are deposited directly on the top surface of substrate 200, for example by any suitable additive manufacturing method. Similarly, different portions 205a and 205b of second metallization layer 202 are deposited directly on the bottom surface of substrate 200.

[0053] The overall structure of substrate 200 corresponds to that shown in Figure 12. However, instead of coating the exposed portions of the underside of resin sheet 228, the bottoms of trenches 224 forming second grooves 211 are filled with a conductive material 229. For example, trenches 224 can be partially or completely filled with a conductive adhesive or other conductive elastic material. In this way, a direct electrical connection between adjacent portions 205a and 205b of second metallization layer 205 is re-established, resulting in the same electric field distribution as shown in Figures 13 and 14.

[0054] 16 illustrates a further embodiment according to the present disclosure, showing a direct bonded copper (DBC) substrate 226 in which an upper copper layer 218 and a lower copper layer 219 are directly bonded to a ceramic substrate 222.

[0055] Similar to the embodiments shown in FIGS. 11 , 12 , and 15 , the second trench 211 in the lower metallization layer 205 does not extend completely to the ceramic substrate 222. In the described example, the second trench 211 in the lower copper layer 219 is formed by etching, and the etching method, etching time, etchant, and / or etchant concentration are selected so that the resulting trench 224 does not extend completely to the ceramic substrate 222. This can be achieved, for example, by etching the peripheral areas 227 of the trench 224 and the DBC substrate 226, respectively, using a different process or etch mask. Alternatively, other structuring methods, such as selective laser cutting, can be used to remove only a portion of the metal material of the second metallization layer 205. As described above, the resulting structure has an improved electric field distribution, as shown in FIGS. 13 and 14 , respectively.

[0056] While the above examples describe coating trench 224 in DBA substrate 220 with a thin conductive layer 225, filling trench 224 in substrate 200, and partially etching DBC substrate, respectively, this is not intended to be limiting. In particular, it is also possible to provide a thin conductive layer at the bottom of trench 224 in substrate 200 shown in FIG. 15 , partially or completely fill trench 224 in DBA substrate 220 or DBC substrate 226, etc.

[0057] 17 shows a schematic diagram of a method for manufacturing a power module 210 using steps S1 to S5. It should be noted that steps S1 to S5 may be performed in different orders and / or in parallel. For example, the rear surface of the substrate 200 may be structured before the front surface. Alternatively, the structuring of the front and rear surfaces may be performed in parallel, for example in a single etching step.

[0058] In step S1, a substrate 200 is provided, which includes at least one insulating layer, a first metallization layer 202, and a second metallization layer 205. The first and second metallization layers 202 and 205 are disposed on opposite sides of the insulating layer. For example, as described above, a DBC substrate 226, a DBA substrate 220, or an AMB substrate 214 may be provided.

[0059] In step S2, the first metallization layer 202 is structured to form a plurality of first grooves 203 that electrically divide the first metallization layer 202 into a plurality of individual portions. For example, in the case of a DBC substrate 226 or a DBA substrate 220, it is sufficient to divide the first metallization layer 203, for example by etching. In the case of an AMB substrate 214, it is necessary to also divide the upper braze layer 216, for example by etching with a long etching time or etchant concentration, or by performing a separate etching step with an etchant suitable for removing the chemically difficult to etch braze layer 216.

[0060] In step S3, the second metallization layer 205 is structured to form at least one second groove 211 in the attachment region 206 of the second metallization layer 205, the second groove 211 extending at least partially from the outer surface of the second metallization layer 205 toward the insulating layer. For example, as described above, the trench 224 may be etched to extend only to an etch stop, such as the lower braze layer 217, or all the way to the insulating layer, such as the ceramic substrate 222. If the initial structuring step completely divides the second metallization layer 205, then in at least some embodiments, the trench 224 may be partially filled with a conductive material 225 to re-establish electrical connection between corresponding ends of the trench 224.

[0061] In step S4, at least one semiconductor die 204 is mounted to the mounting area of ​​the first metallization layer 202. This may be accomplished, for example, by soldering, sintering, diffusion soldering, or gluing metal contact areas of one or more semiconductor die 204 to corresponding portions of the first metallization layer 202. Soldering or sintering imposes a thermal and / or mechanical load on the substrate 200.

[0062] In step S5, at least the attachment region 206 of the second metallization layer 205 is attached to a flat surface of a suitable carrier structure. Again, this may be done by soldering, sintering, or other suitable methods such as bonding with a conductive adhesive. For example, the flat surface of the base plate 208, a conductive carrier plate, and / or a cooler may be used as the carrier structure for the power module 210. Again, soldering or sintering subjects the substrate 200 to a thermal and / or mechanical load.

[0063] The embodiments illustrated in Figures 1-17 above represent exemplary embodiments of the improved substrates and power modules and methods for their manufacture. As such, they do not constitute an exhaustive list of all embodiments of the improved apparatus and methods. Actual apparatus and methods may differ from the illustrated embodiments in terms of, for example, layout, equipment, method steps, and materials. [Explanation of symbols]

[0064] Reference sign 100 boards 101 Career Sheet 102 first metallization layer Portions 102a-c (of the first metallization layer) 103, 103a~b (first) groove 104a~d Semiconductor die 105 Second Metallization Layer 106 Mounting area 107 (mounting area) center 108 base plate 109 Solder 110 (mounting area) periphery 111 Gap 200 boards 201 Career Sheet 202 First Metallization Layer 202a-c (first metallization layer) portions 203, 203a~b (first) groove 204, 204a~d Semiconductor die 205 Second Metallization Layer 205a, 205b (Second metallization layer) portions 206 Mounting Area 207 Implementation Area 208 base plate 209 Solder 210 Power Module 211, 211a-c (second) groove 212a, 212b (Second groove) corner 213a, 213b (first groove) corner 214 AMB board 215 (middle) ceramic layer 216 (Top) Brazing layer 217 (bottom) brazing layer 218 (top) copper layer 219 (bottom) copper layer 220 DBA board 221 (top) aluminum layer 222 Ceramic Substrate 223 (bottom) aluminum layer 224 Trench 225 Conductive Layer 226 DBC board 227 Surrounding Area 228 Resin Sheet 229 Conductive Materials S1~S5 method steps

Claims

1. A substrate (200) for a power module (210), a carrier sheet (201) extending in a plane and comprising at least one insulating layer; a first metallization layer (202) formed directly on the first surface of said carrier sheet (201), said first metallization layer (202) comprising a mounting area (207) for mounting at least one semiconductor die (204) of a power module (210), said substrate (200) further comprising: a second metallization layer (205) formed directly on a second surface of said carrier sheet (201), said second surface being opposite said first surface, said second metallization layer (205) including an attachment area (206) for attaching said substrate (200) to a flat surface; - the projections of the mounting area (207) and the attachment area (206) onto the plane of the carrier sheet (201) at least partially overlap; - said mounting area (207) is structured with at least one first groove (203), said first groove (203) extending from the outer surface of said first metallization layer (202) to said at least one insulating layer and electrically dividing said first metallization layer (202) into individual parts (202a, 202b, 202c); - said attachment area (206) is structured with at least one second groove (211), said second groove (211) extending from the outer surface of said second metallization layer (205) at least partially to said at least one insulating layer; a substrate (200) in which a conductive material (229) arranged at the bottom of said at least one second groove (211) interconnects ends of respective portions of said second metallization layer (205) adjacent to said at least one second groove (211) and exposes at least a portion of said second metallization layer (205).

2. - said carrier sheet (201) further comprises at least one first conductive layer arranged between said at least one insulating layer and said second metallization layer (205); - said at least one second groove (211) extends from said outer surface of said second metallization layer (205) to the surface of said at least one first conductive layer; The substrate (200) of claim 1, wherein the at least one first conductive layer interconnects the ends of the respective portions of the second metallization layer (205) adjacent to the at least one second groove (211).

3. 3. The substrate (200) of claim 2, wherein the substrate (200) is an active metal brazing substrate (214), and the at least one first conductive layer is a brazing layer (217) formed on a surface of the at least one insulating layer.

4. said at least one second groove (211) comprises a trench (224) extending from said outer surface of said second metallization layer (205) to said at least one insulating layer; The substrate (200) of claim 1, wherein at least one of a conductive layer (225) and an elastic conductive material (229) is disposed at least at the bottom of the trench (224), thereby interconnecting the ends of the respective portions of the second metallization layer (205) adjacent to the at least one second groove (211).

5. - said substrate (200) is one of a direct bonded copper substrate (226) or a direct bonded aluminum substrate (220); and - said second metallization layer (205) is bonded directly to the surface of said at least one insulating layer of said carrier sheet (201); The substrate (200) of claim 4, wherein the substrate (200) is at least one of:

6. 2. The substrate (200) of claim 1, wherein the at least one second groove (211) includes a trench (224) extending only partially from the outer surface of the second metallization layer (205) toward the insulating layer, whereby remaining material of the second metallization layer (205) below the trench (224) interconnects the ends of the respective portions of the second metallization layer (205) adjacent to the at least one second groove (211).

7. The substrate (200) of claim 1, wherein the first metallization layer (202) comprises an upper copper layer (218) and the second metallization layer (205) comprises a lower copper layer (219).

8. A power module (210), a substrate (200) according to any one of claims 1 to 7, - at least one semiconductor die (204) mounted on said mounting area (207) of said first metallization layer (202), a power module (210).

9. The mounting area (206) is attached to a flat surface of the carrier structure, the carrier structure further comprising: an electrically conductive carrier plate in electrical and / or thermal contact with said second metallization layer (205); a base plate (208) in thermal contact with said second metallization layer (205), or a cooler in thermal contact with said second metallization layer (205); The power module (210) of claim 8, comprising at least one of:

10. the patterns of the at least one first groove (203) and the at least one second groove (211) are balanced so that the attachment area (206) of the second metallization layer (205) of the substrate (200) carrying the at least one semiconductor die (204) remains essentially flat during a thermal treatment of the substrate (200); the amount of material in said first metallization layer (202) corresponds to the amount of material in said second metallization layer (205); - said at least one first groove (203) and said at least one second groove (211) cover corresponding surface areas of said carrier sheet (201); - said at least one first groove (203) and said at least one second groove (211) have corresponding volumes; the thickness of said first metallization layer (202) corresponds to the thickness of said second metallization layer (205), said at least one first groove (203) and said at least one second groove (211) being congruent, or the thickness of said first metallization layer (202) is different from the thickness of said second metallization layer (205), and at least a portion of said at least one first groove (203) and said at least one second groove (211) are not congruent; The power module (210) according to claim 8 or 9, wherein the power module (210) is at least one of:

11. A method of manufacturing a power module (210), comprising: - providing a substrate (200) comprising at least one insulating layer, a first metallization layer (202) and a second metallization layer (205), said first and second metallization layers (202, 205) being located directly on either side of said insulating layer, said method further comprising: - structuring said first metallization layer (202) to form at least one first groove (203) extending from an outer surface of said first metallization layer (202) to said at least one insulating layer, said first groove (203) electrically dividing said first metallization layer (202) into a plurality of individual portions (202a, 202b, 202c), said method further comprising: - structuring the second metallization layer (205) to form at least one second groove (211) in an attachment area (206) of the second metallization layer (205), the at least one second groove (211) extending at least partially from an outer surface of the second metallization layer (205) towards the insulating layer, a conductive material (229) arranged at the bottom of the at least one second groove (211) interconnecting ends of respective portions of the second metallization layer (205) adjacent to the at least one second groove (211) and exposing at least a part of the second metallization layer (205), the method further comprising: - mounting at least one semiconductor die (204) on a mounting area (207) of said first metallization layer (202); - attaching at least said attachment area (206) of said second metallization layer (205) to a flat surface.

12. - in the step of providing the substrate (200), a multilayer substrate (200) is provided which comprises at least one further metal layer arranged between the insulating layer and the second metallization layer (205); 12. The method of claim 11, wherein in the step of structuring the second metallization layer (205), the at least one further metal layer serves as at least one of an etch stop in an etching process or a processing stop in a structuring process.

13. The method of claim 11, further comprising the step of coating or filling at least a bottom of said at least one second groove (211) with a conductive material (225) to form an electrical interconnection between respective portions of said second metallization layer (205) adjacent said at least one second groove (211).

14. - in a step of structuring said second metallization layer (205), said second metallization layer (205) is etched, The method of claim 11, wherein the etching method, etching time, etching agent and / or etching solution concentration are selected such that the at least one second trench (211) does not extend completely to the insulating layer.

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