Semiconductor integrated circuits, substrates and electronic devices

Abstract

To increase the number of bits that can be read from one terminal and enable rapid reading.SOLUTION: A semiconductor integrated circuit 100 includes an IO buffer 110 connected through a signal line 101 to one of a pull-up resistor and a pull-down resistor and one of a first capacitor and a second capacitor, and an IO buffer control unit 130 that controls the IO buffer 110 to cause the IO buffer 110 to output a high or low signal to the signal line 101. The IO buffer control unit 130 specifies a set value to be set to the semiconductor integrated circuit 100 by a first value, which is determined based on the high or low state of the voltage of the signal line 101 when the power of the semiconductor integrated circuit 100 is turned on, and a second value, which is determined based on the high or low state of the voltage of the signal line 101 when a predetermined period has passed after the output of the IO buffer 110 is controlled to make a state different from the state corresponding to the first value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit, a substrate, and an electronic device. [Background technology]

[0002] Conventionally, it has been common for semiconductor integrated circuits to make a terminal that is originally used as an output high impedance when powered on, read the potential (1 or 0) of the terminal due to a pull-up or pull-down connected to that terminal, and use the read value as a setting value inside the chip (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-221112 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor integrated circuits, depending on the circuit configuration, there are cases where a sufficient number of terminals that can be used to take in information cannot be secured. However, even in such cases, conventional semiconductor integrated circuits cannot secure a sufficient number of setting values ​​because they can only take in one bit of information per terminal.

[0005] Therefore, one or more aspects of the present disclosure aim to increase the number of bits that can be read from one terminal and enable reading to be performed quickly. [Means for solving the problem]

[0006] A semiconductor integrated circuit according to a first aspect of the present disclosure includes either a pull-up resistor or a pull-down resistor, either a first capacitor or a second capacitor having a capacitance larger than that of the first capacitor, an input / output buffer connected by a signal line, and an input / output buffer control unit that controls the input / output buffer to output a high or low signal from the input / output buffer to the signal line, wherein the input / output buffer control unit controls the output of the input / output buffer so that the voltage of the signal line is in a state different from a first value determined by a high or low state of the voltage of the signal line when the semiconductor integrated circuit is powered on, and a state corresponding to the first value, and a second value determined by a high or low state, and the predetermined period is, when the state corresponding to the first value is high, a period until the state of the signal line is changed to low by a first RC circuit formed by a drive resistor and the first capacitor provided at the output end of the input / output buffer, and a period during which the state of the signal line is maintained high by a second RC circuit formed by the drive resistor and the second capacitor; and, when the state corresponding to the first value is low, a period is a period between a period until the state of the signal line is changed to high by the first RC circuit and a period during which the state of the signal line is maintained low by the second RC circuit.

[0007] a first input / output buffer that can switch an output terminal connected to a signal line between a first output terminal having a first drive resistance and a second output terminal having a second drive resistance that is greater in resistance than the first drive resistance; and an input / output buffer control unit that controls the input / output buffer to output a high or low signal from the first output terminal or the second output terminal to the signal line, wherein the input / output buffer control unit controls the output terminal to be switched to the first output terminal, and outputs a high or low signal from the first output terminal or the second output terminal to the signal line, the input / output buffer control unit controlling the output terminal to be switched to the first output terminal ... a setting value to be set in the semiconductor integrated circuit is specified by a third value determined by a high or low state of the voltage of the signal line when a predetermined second period has elapsed since the output terminal is switched to the second output terminal and the output of the input / output buffer is controlled to be in a state different from the state corresponding to the first value, wherein the first period is, when the state corresponding to the first value is high, a period until the state of the signal line is changed to low by a first RC circuit formed by the first drive resistor and the second capacitor, and a period during which the state of the signal line is maintained high by a second RC circuit formed by the first drive resistor and the third capacitor; when the state corresponding to the first value is low, a period until the state of the signal line is changed to high by the first RC circuit and a period during which the state of the signal line is maintained low by the second RC circuit; and the second period is, when the state corresponding to the first value is high, a period until the state of the signal line is changed to low by a third RC circuit formed by the second drive resistor and the first capacitor.and a period during which the state of the signal line is maintained high by a fourth RC circuit formed by the second drive resistor and the second capacitor, and when the state corresponding to the first value is low, the period is between a period until the state of the signal line is made high by the third RC circuit and a period during which the state of the signal line is maintained low by the fourth RC circuit.

[0008] A substrate according to a first aspect of the present disclosure is characterized by comprising the semiconductor integrated circuit according to the first aspect described above, either the pull-up resistor or the pull-down resistor, either the first capacitor or the second capacitor, and the signal line.

[0009] A substrate according to a second aspect of the present disclosure is characterized by comprising the semiconductor integrated circuit according to the second aspect described above, either the pull-up resistor or the pull-down resistor, either the first capacitor, the second capacitor, or the third capacitor, and the signal line.

[0010] An electronic device according to one aspect of the present disclosure is characterized by including the substrate according to the first aspect or the substrate according to the second aspect. [Effects of the Invention]

[0011] According to one or more aspects of the present disclosure, the number of bits that can be read from one terminal can be increased and reading can be performed quickly. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram schematically showing a configuration of a semiconductor integrated circuit according to a first embodiment. [Figure 2] 3 is a circuit diagram showing a circuit at an output end inside the IO buffer according to the first embodiment. FIG. [Figure 3] 1A and 1B are block diagrams illustrating first and second application examples of the semiconductor integrated circuit according to the first embodiment. [Figure 4] 10A and 10B are block diagrams illustrating third and fourth application examples of the semiconductor integrated circuit according to the first embodiment. [Figure 5] 10 is a graph showing a potential change of an L signal when an IO buffer is set to a High output state, using a step response calculation formula of an RC circuit, in a case where a pull-down resistor is provided in the first embodiment. [Figure 6] 10 is a graph showing a change in potential of an L signal when an IO buffer is set to a Low output state, using a step response calculation formula of an RC circuit, in a case where a pull-up resistor is provided in the first embodiment. [Figure 7] 10 is a flowchart illustrating the operation of an IO buffer control unit according to the first embodiment. [Figure 8] 3 is a first time chart according to the first embodiment. [Figure 9] 10 is a second time chart according to the first embodiment. [Figure 10] 10 is a third time chart according to the first embodiment. [Figure 11] 10 is a fourth time chart according to the first embodiment. [Figure 12] FIG. 10 is a block diagram schematically showing a configuration of a semiconductor integrated circuit according to a second embodiment. [Figure 13] FIG. 11 is a circuit diagram showing a circuit at an output end inside an IO buffer according to a second embodiment. [Figure 14] 10(A) to 10(C) are block diagrams illustrating first to third application examples of the semiconductor integrated circuit according to the second embodiment. [Figure 15] 10(A) to 10(C) are block diagrams illustrating fourth to sixth application examples of the semiconductor integrated circuit according to the second embodiment. [Figure 16] 10 is a graph showing a first potential change of an L signal when an IO buffer is set to a High output state, using a step response calculation formula of an RC circuit in a case where a pull-down resistor is provided in the second embodiment. [Figure 17]10 is a graph showing a second potential change of an L signal when an IO buffer is set to a High output state, using a step response calculation formula of an RC circuit in a case where a pull-down resistor is provided in the second embodiment. [Figure 18] 10 is a graph showing a first potential change of an L signal when an IO buffer is set to a Low output state, using a step response calculation formula of an RC circuit, in a case where a pull-up resistor is provided in the second embodiment. [Figure 19] 10 is a graph showing a second potential change of an L signal when an IO buffer is set to a Low output state, using a step response calculation formula of an RC circuit, in a case where a pull-up resistor is provided in the second embodiment. [Figure 20] 10 is a flowchart illustrating the operation of an IO buffer control unit according to the second embodiment. [Figure 21] 10 is a first time chart according to the second embodiment. [Figure 22] 10 is a second time chart in the second embodiment. [Figure 23] 10 is a third time chart in the second embodiment. [Figure 24] 10 is a fourth time chart in the second embodiment. [Figure 25] 10 is a fifth time chart in the second embodiment. [Figure 26] 6 is a sixth time chart in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Embodiment 1 FIG. 1 is a block diagram schematically showing a configuration of a semiconductor integrated circuit 100 according to the first embodiment. The semiconductor integrated circuit 100 includes an IO buffer 110, an IO buffer control unit 130, and a transmission unit 140.

[0014] The IO buffer 110 is an input / output buffer that complies with LVTTL (Low Voltage Transistor Logic). The input potential thresholds of LVTTL are Vil=0.8V, which is a low level, and Vih=2.0V, which is a high level.

[0015] The IO buffer 110 is connected to a signal line 101 from which an L signal is read.

[0016] The IO buffer control unit 130 is an input / output buffer control unit that controls the IO buffer 110. The IO buffer control unit 130 is a logic circuit (controller). The IO buffer control unit 130 is connected to the IO buffer 110 via three signal lines 102 , 103 , and 104 . The IO buffer control unit 130 provides the oe signal to the IO buffer 110 via the signal line 102 . The IO buffer control unit 130 provides an out signal to the IO buffer 110 via the signal line 103. As a result, the IO buffer control unit 130 controls the IO buffer 110 via the signal line 103, causing the IO buffer 110 to output a high or low signal to the signal line 101. The IO buffer control unit 130 receives the in signal from the IO buffer 110 via the signal line 104 .

[0017] Here, the IO buffer control unit 130 receives a clock from an OSC (OSCillator) 150 . The OSC 150 is an oscillator or resonator, and supplies a clock to the semiconductor integrated circuit 100. The clock frequency is set to 30 MHz (period: 0.033 us).

[0018] The transmitter 140 is a logic circuit that transmits a tx signal, which is an output signal to a counterpart device 163 (described later), when the semiconductor integrated circuit 100 is used as intended. For example, the transmitting unit 140 is connected to the IO buffer control unit 130 by a signal line 105, and provides a tx signal to the IO buffer control unit 130 via the signal line 105. In this case, the IO buffer control unit 130 sets the oe signal to High (1) and outputs the tx signal as an out signal using the signal line 103.

[0019] FIG. 2 is a circuit diagram showing a circuit at the output end inside the IO buffer 110 according to the first embodiment. The output terminal of the IO buffer 110 is provided with transistors 111A and 111B and resistors 112A and 112B as drive resistors.

[0020] When the oe signal is "0", the IO buffer 110 turns off the transistor 111A and the transistor 111B, thereby putting the output of the IO buffer 110 into a high impedance state. Furthermore, when the oe signal is "1", the IO buffer 110 changes the L signal of the signal line 101 between High and Low by turning on or off the transistors 111A and 111B. For example, the IO buffer 110 outputs High (1) by turning on the transistor 111A and turning off the transistor 111B, which causes the terminal 107 (see FIG. 1) of the semiconductor integrated circuit 100 to output High (1). Furthermore, the IO buffer 110 outputs Low (0) by turning off the transistor 111A and turning on the transistor 111B, which causes the terminal 107 (see FIG. 1) of the semiconductor integrated circuit 100 to output Low (0).

[0021] The resistance values ​​of the resistors 112A and 112B determine the drive strength of the output of the IO buffer 110. Here, the resistors 112A and 112B each have a resistance of 50Ω.

[0022] FIGS. 3A and 3B and FIGS. 4A and 4B are block diagrams for explaining examples of use of the semiconductor integrated circuit 100 according to the first embodiment. Figure 3(A) is a block diagram of a substrate 160A carrying a semiconductor integrated circuit 100, Figure 3(B) is a block diagram of a substrate 160B carrying a semiconductor integrated circuit 100, Figure 4(A) is a block diagram of a substrate 160C carrying a semiconductor integrated circuit 100, and Figure 4(B) is a block diagram of a substrate 160D carrying a semiconductor integrated circuit 100. These substrates are mounted in electronic devices such as image forming devices.

[0023] As shown in FIG. 3A, the substrate 160A includes the semiconductor integrated circuit 100, a resistor 161U, a capacitor 162A, and a counter device 163. As shown in FIG. 3B, the substrate 160B includes the semiconductor integrated circuit 100, a resistor 161U, a capacitor 162B, and a counter device 163. As shown in FIG. 4A, the substrate 160C includes the semiconductor integrated circuit 100, a resistor 161L, a capacitor 162A, and a counter device 163. As shown in FIG. 4B, the substrate 160D includes the semiconductor integrated circuit 100, a resistor 161L, a capacitor 162B, and a counter device 163.

[0024] In other words, the IO buffer 110 is connected to either a resistor 161U which is a pull-up resistor or a resistor 161L which is a pull-down resistor, and either a capacitor 162A which is a first capacitor or a capacitor 162B which is a second capacitor, by a signal line 101. The signal line 101 is also connected to an opposing device 163.

[0025] In the first embodiment, the set value set in the semiconductor integrated circuit 100 can be changed by using resistors 161U or 161L arranged at different positions and capacitors 162A and 162B with different capacitances. For example, the set value set in the semiconductor integrated circuit 100 can be changed depending on the type of substrates 160A to 160D. Here, four types of set values ​​can be set in the semiconductor integrated circuit 100.

[0026] The resistors 161U and 161L are both resistive elements, and the resistance values ​​thereof are both set to 10 kΩ. In the boards 160A and 160B shown in FIGS. 3A and 3B, the resistor 161U is connected between the 3.3V power supply 164 and the signal line 101, and functions as a pull-up resistor. On the other hand, in the boards 160C and 160D shown in FIGS. 4A and 4B, the resistor 161L is connected between the signal line 101 and GND 165 of 0V, and functions as a pull-down resistor.

[0027] The capacitors 162A and 162B are capacitance components between the signal line 101 and the GND 165 of 0V. The capacitor 162A has a capacitance Cs, and the capacitor 162B has a capacitance Cl. Here, the capacitance Cs is 50 pF (Small), and the capacitance Cl is 0.01 uF (Large).

[0028] The opposite device 163 is a device that receives data from the transmitter 140 in response to the tx signal output by the semiconductor integrated circuit 100 . Here, the counterpart device 163 is connected to the semiconductor integrated circuit 100 via a signal line 101 .

[0029] In the first embodiment, the combination of the resistor 161U and the capacitor 162A shown in FIG. 3(A) allows the semiconductor integrated circuit 100 to read the set value "3." The combination of the resistor 161U and the capacitor 162B shown in FIG. 3B allows the semiconductor integrated circuit 100 to read the set value "2." The combination of the resistor 161L and the capacitor 162A shown in FIG. 4A allows the semiconductor integrated circuit 100 to read the set value "1." The combination of the resistor 161L and the capacitor 162B shown in FIG. 4B allows the semiconductor integrated circuit 100 to read the set value "0."

[0030] FIG. 5 is a graph showing the potential change of the L signal when the IO buffer 110 is in a high output state (oe=1, out=1) using the step response calculation formula of the RC circuit in the case where the resistor 161L is provided as shown in FIGS. 4(A) and (B). Here, the RC circuit is composed of the resistor 112A and the capacitor 162A or 162B shown in FIG.

[0031] Here, the capacitance of the capacitor 162A is Cs=50 pF, and the capacitance of the capacitor 162B is Cl=0.01 uF. Figure 5 shows the potential changes in these two cases.

[0032] The potential Vc (V) of the L signal is expressed by the following equation (1) using the time t (seconds) from the start.

number

[0033] When the capacitance element constant is Cs=50pF, the value of τ is expressed by the following formula (2), and when the capacitance element constant is Cl=0.01uF, the value of τ is expressed by the following formula (3). Note that R is the value of resistor 112A as the drive resistance, which is 50Ω.

[0034] τ=Cs×R=50×10 -12 ×50=2.5×10 -9 =2.5ns (2) τ = Cl × R = 0.01 × 10 -6 ×50=500×10 -9 =500ns (3)

[0035] Curve 10 shown in FIG. 5 shows the case where capacitor 162A (Cs=50 pF) is used, and curve 11 shows the case where capacitor 162B (Cl=0.001 uF) is used.

[0036] 5, when capacitor 162A is used, the potential of the L signal exceeds Vih (2.0 V) after 2.4 ns, as shown in curve 10. This means that if the IO buffer 110 is put into a high impedance state (oe=0) after 2.4 ns, the IO buffer 110 will read "1."

[0037] On the other hand, when capacitor 162B is used, the potential of the L signal does not exceed Vil (0.8V) until 140ns. This means that if the IO buffer 110 is put into a high impedance state (oe=0) before 140ns, the IO buffer 110 will read "0". In this case, the RC circuit is in a transient state and has not yet reached a steady state.

[0038] In other words, if the IO buffer 110 is put into a high impedance state (oe=0) a predetermined period of time (e.g., 33 ns) after the IO buffer 110 starts a high output state (oe=1, out=1), when the constant of the capacitance element is Cs (50 pF), the IO buffer 110 reads "1", and when the constant of the capacitance element is Cl (0.01 uF), the IO buffer 110 reads "0". The predetermined period here may be the period between 2.4 ns when the L signal exceeds Vih (2.0 V) when capacitor 162A is used and 140 ns when the L signal exceeds Vil (0.8 V) when capacitor 162B is used.

[0039] FIG. 6 is a graph showing the potential change of the L signal when the IO buffer 110 is set to a Low output state (oe=1, out=0) using the step response calculation formula of the RC circuit in the case where the resistor 161U is provided as shown in FIGS. 3(A) and (B). Here, the RC circuit is composed of the resistor 112B and the capacitor 162A or 162B shown in FIG.

[0040] Here, the capacitance of the capacitance element that can be implemented as capacitor 162A is Cs=50 pF, and the capacitance of the capacitance element that can be implemented as capacitor 162B is Cl=0.01 uF. Figure 6 shows the potential changes in these two cases.

[0041] The potential Vc (V) of the L signal is expressed by the following equation (4) using the time t (seconds) from the start.

number

[0042] Curve 12 shown in FIG. 6 shows the case where capacitor 162A (Cs=50 pF) is used, and curve 13 shows the case where capacitor 162B (Cl=0.001 uF) is used.

[0043] 6, when capacitor 162A is used, the potential of the L signal falls below Vil (0.8 V) at 3.6 ns. This means that if the IO buffer 110 is put into a high impedance state (oe=0) after 3.6 ns, the IO buffer 110 will read "0."

[0044] On the other hand, when capacitor 162B is used, the potential of the L signal does not fall below Vih (2.0 V) until 250 ns. This means that if the IO buffer 110 is put into a high-impedance state (oe=0) before 250 ns, the IO buffer 110 will read "1." In this case, the RC circuit is in a transient state and has not yet reached a steady state.

[0045] In other words, if the IO buffer 110 is put into a high impedance state (oe=0) a predetermined period of time (e.g., 33 ns) after the IO buffer 110 starts a low output state (oe=1, out=0), the IO buffer 110 will read "0" if the capacitance constant is Cs=50 pF, and will read "1" if the capacitance constant is Cl=0.01 uF. The predetermined period here may be the period between 3.6 ns when the L signal falls below Vil (0.8 V) when capacitor 162A is used and 250 ns when the L signal falls below Vih (2.0 V) when capacitor 162B is used.

[0046] FIG. 7 is a flowchart showing the operation of the IO buffer control unit 130 according to the first embodiment. When the power supply of the semiconductor integrated circuit 100 is turned on, the IO buffer control unit 130 sets the out signal to 0 and the oe signal to 0, putting the IO buffer 110 in a high impedance state, and reads the value of the in signal after a certain time has passed (S10). Note that although the out signal is set to 0 here, the out signal may also be set to 1.

[0047] Next, the IO buffer control unit 130 determines whether the value of the read in signal is "1" (S11). If the value of the in signal is "1" (Yes in S11), the process proceeds to step S12, and if the value of the in signal is "0" (No in S11), the process proceeds to step S14.

[0048] In step S12, in order to change the state of the L signal, the IO buffer control unit 130 sets the out signal to 0 and the oe signal to 1.

[0049] Next, after a predetermined period of time, here 33 ns, has elapsed, the IO buffer control unit 130 sets the out signal to 0 and the oe signal to 0, puts the IO buffer 110 into a high impedance state, and reads the value of the in signal (S13).Then, the process proceeds to step S16.

[0050] On the other hand, in step S11, if the in signal is "0" (No in S11), the process proceeds to step S14, and in order to change the state of the L signal, the IO buffer control unit 130 sets the out signal=1 and the oe signal=1.

[0051] Next, after a predetermined period of time, here 33 ns, has elapsed, the IO buffer control unit 130 sets the out signal to 1 and the oe signal to 0, puts the IO buffer 110 into a high impedance state, and reads the value of the in signal (S15).Then, the process proceeds to step S16.

[0052] In step S16, the IO buffer control unit 130 identifies the setting value. For example, the IO buffer control unit 130 identifies the setting value by combining the in signal read in step S10 with the in signal read in step S13 or the in signal read in step S15.

[0053] Specifically, if the value a read in step S10 is "1" (Yes in S11), the process proceeds to step S12, and the IO buffer control unit 130 uses the value b read in step S13. Then, the IO buffer control unit 130 identifies the set value by the value ab. Specifically, if a=1 and b=0, the value "10" becomes "2" in binary, and therefore the set value becomes "2." On the other hand, if a=1 and b=1, the value "11" becomes "3" in binary, and therefore the set value becomes "3."

[0054] On the other hand, if the value a read in step S10 is "0" (No in S11), the process proceeds to step S14, and the IO buffer control unit 130 uses the value c read in step S15. Then, the IO buffer control unit 130 identifies the setting value by the value ac. Specifically, if a=0 and c=0, the value "00" becomes "0" in binary, and therefore the setting value becomes "0". On the other hand, if a=0 and b=1, the value "01" becomes "1" in binary, and therefore the setting value becomes "1".

[0055] Then, the IO buffer control unit 130 transfers the signal control right of the IO buffer 110 to the transmission unit 140 with the out signal = tx and the oe signal = 1 (S17).

[0056] As described above, the IO buffer control unit 130 can specify the set value according to the configurations of the substrates 160A and 160B on which the semiconductor integrated circuit 100 is mounted.

[0057] Hereinafter, a specific description will be given using a time chart. Note that the in signal is the result of the IO buffer 110, which is an LVTTL buffer, reading "0" or "1" from the potential Vc (V) of the L signal as follows. When Vc > Vih (2.0V), the in signal becomes "1". When Vil (0.8V) < Vc < Vih (2.0V), the in signal is indeterminate and cannot be determined as "0" or "1". When Vc < Vil (0.8V), the in signal becomes "0".

[0058] FIG. 8 is a time chart when the resistor 161U and the capacitor 162B are used as shown in FIG. 3(B). First, the IO buffer control unit 130 sets the out signal = 0 and the oe signal = 0 at power-on, sets the IO buffer 110 in a high-impedance state, and reads the value of the in signal at time T0 after a certain time has elapsed. Here, since the resistor 161U is used, it is pulled up to 3.3V. Therefore, the in signal = "1".

[0059] Next, since the in signal read at time T0 is "1", the IO buffer control unit 130 sets the out signal = "0" and the oe signal "1" at time T1, and sets the IO buffer 110 in the "0" output state.

[0060] Then, at time T4, 33 ns after time T1, the IO buffer control unit 130 again sets the out signal to "0" and the oe signal to "0", puts the IO buffer 110 into a high impedance state, and reads the value of the in signal at time T4. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T4 occurs one clock after time T1.

[0061] Here, since the capacitance of capacitor 162B is Cl, Vc>Vih (2.0 V) remains true until 250 ns have elapsed from time T1, as shown by curve 13 in Fig. 6. Therefore, at time T4, 33 ns after time T1, the in signal becomes "1".

[0062] Then, since the value of the in signal read by the IO buffer control unit 130 at time T0 was "1" and the value of the in signal read at time T4 was "1", the IO buffer control unit 130 obtains a setting value of "3" (2'b11 in binary).

[0063] Furthermore, at time T5, the IO buffer control unit 130 transfers the signal control right of the IO buffer 110 to the transmitting unit 140 by setting the out signal to "tx" and the oe signal to "1".

[0064] FIG. 9 is a time chart when the resistor 161U and the capacitor 162A are used as shown in FIG. 3(A). The hatched areas in FIG. 9 indicate a state in which the in signal is indefinite. First, when powered on, the IO buffer control unit 130 sets the out signal to 0 and the oe signal to 0, putting the IO buffer 110 into a high impedance state, and then reads the value of the in signal at time T0 after a certain time has passed. Here, since resistor 161U is used, it is pulled up to 3.3V. Therefore, the in signal becomes "1".

[0065] Next, since the in signal read at time T0 by the IO buffer control unit 130 is "1", at time T1, the out signal is set to "0" and the oe signal to "1", putting the IO buffer 110 in the "0" output state.

[0066] Then, at time T4, 33 ns after time T1, the IO buffer control unit 130 sets the out signal to "0" and the oe signal to "0" again, putting the IO buffer 110 in the high-impedance state and reading the value of the in signal at that time T4. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T4 is reached after one clock from time T1.

[0067] Here, since the capacitance of capacitor 162A is Cs, as shown by curve 12 in FIG. 6, at time T2, 3.6 ns after time T1, Vc < Vil(0.8), so the in signal is also "0" at time T4.

[0068] Then, since the value of the in signal read at time T0 by the IO buffer control unit 130 is "1" and the value of the in signal read at time T4 is "0", the set value "2" (2'b10 in binary representation) is obtained.

[0069] Furthermore, at time T5, the IO buffer control unit 130 transfers the signal control right of the IO buffer 110 to the transmission unit 140 by setting the out signal to "tx" and the oe signal to "i".

[0070] FIG. 10 is a time chart when the resistor 161L and the capacitor 162B are used as shown in FIG. 4(B). First, when power is turned on, the IO buffer control unit 130 sets the out signal to 0 and the oe signal to i, puts the IO buffer 110 in the high-impedance state, and reads the value of the in signal at time T0 after a certain time has elapsed. Here, since the resistor 161L is used, it is pulled down to 0V. Therefore, the in signal becomes "0".

[0071] Next, since the in signal read at time T0 is "0", at time T1, the IO buffer control unit 130 sets the out signal = "1" and the oe signal = "1" to put the IO buffer 110 in the "1" output state.

[0072] Then, at time T4 when 33 ns has elapsed from time T1, the IO buffer control unit 130 sets the out signal = "1" and the oe signal = "0", puts the IO buffer 110 in the high-impedance state, and reads the value of the in signal at that time T4. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T4 is reached after one clock from time T1.

[0073] Here, since the capacitance of capacitor 162B is Cl, as shown by curve 11 in FIG. 5, Vc < Vil (0.8V) from time T1 to 140 ns. Therefore, the in signal = "0" also at time T4.

[0074] Then, since the value of the in signal read at time T0 is "0" and the value of the in signal read at time T4 is "0", the IO buffer control unit 130 obtains the set value "0" (2'b00 in binary representation).

[0075] Furthermore, at time T5, the IO buffer control unit 130 transfers the signal control right of the IO buffer 110 to the transmission unit 140 by setting the out signal = "tx" and the oe signal = "1".

[0076] FIG. 11 is a time chart when the resistor 161U and the capacitor 162A are used as shown in FIG. 4(B). Note that the shaded portion shown in FIG. 11 indicates a state where the in signal is indeterminate. First, when powered on, the IO buffer control unit 130 sets the out signal to 0 and the oe signal to 0, putting the IO buffer 110 in a high impedance state, and then reads the value of the in signal at time T0 after a certain time has passed. Here, since resistor 161L is used, it is pulled down by V. Therefore, the in signal becomes "0".

[0077] Next, since the in signal read at time T0 was "0", the IO buffer control unit 130 sets the out signal to "1" and the oe signal to "1" at time T1, putting the IO buffer 110 into a "1" output state.

[0078] Then, at time T4, 33 ns after time T1, the IO buffer control unit 130 sets the out signal to "1" and the oe signal to "0," putting the IO buffer 110 into a high impedance state, and reads the value of the in signal at time T4. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T4 occurs one clock after time T1.

[0079] In this case, since the capacitance of capacitor 162A is Cs, Vc>Vih (2.0 V) is already established at time T3, which is 2.4 ns after time T1, as shown by curve 10 in Fig. 5. Therefore, the in signal is also "1" at time T4.

[0080] Then, since the value of the in signal read by the IO buffer control unit 130 at time T0 was "0" and the value of the in signal read at time T4 was "1", the IO buffer control unit 130 obtains a setting value of "1" (0'b01 in binary notation).

[0081] Furthermore, at time T5, the IO buffer control unit 130 transfers the signal control right of the IO buffer 110 to the transmitting unit 140 by setting the out signal to "tx" and the oe signal to "1".

[0082] As described above, in the first embodiment, the IO buffer control unit 130 specifies a setting value for performing the initial setting based on a first value determined by the high or low state of the voltage of the signal line 101 when the semiconductor integrated circuit 100 is initially set, and a second value determined by the high or low state of the voltage of the signal line 101 after a predetermined period of time has elapsed after controlling the output of the IO buffer 110 so that the output is in a state different from the state corresponding to the first value.

[0083] For example, the first value indicates either 1 or 0 when the state of the signal line 101 is high, and indicates the other of 1 or 0 when the state of the signal line 101 is low. The second value indicates either 1 or 0 when the state of the signal line 101 is high, and indicates the other of 1 or 0 when the state of the signal line 101 is low. The set value is a value indicated by a binary number that combines the first value and the second value.

[0084] Furthermore, when the state corresponding to the first value is high, the predetermined period is the period between the period until the state of the signal line 101 becomes low due to a first RC circuit consisting of a drive resistor, which is resistor 112A or 112B, provided at the output end of the IO buffer 110, and a first capacitor, which is capacitor 162A, and the period during which the state of the signal line 101 is maintained high due to a second RC circuit consisting of the drive resistor and a second capacitor, which is capacitor 162B. On the other hand, when the state corresponding to the first value is low, it is the period between the time when the first RC circuit causes the state of the signal line 101 to become high and the time when the second RC circuit maintains the state of the signal line 101 low.

[0085] As described above, according to the first embodiment, in addition to the 1-bit setting value that is read in a high impedance state by the conventional pull-up and pull-down, it is possible to acquire a 1-bit setting value. Therefore, according to the first embodiment, it is possible to acquire 2-bit information per terminal.

[0086] Embodiment 2 FIG. 12 is a block diagram schematically showing a configuration of a semiconductor integrated circuit 200 according to the second embodiment. The semiconductor integrated circuit 200 includes an IO buffer 210, an IO buffer control unit 230, and a transmission unit 140.

[0087] The transmitting section 140 of the semiconductor integrated circuit 200 according to the second embodiment is similar to the transmitting section 140 of the semiconductor integrated circuit 100 according to the first embodiment.

[0088] The IO buffer 210 is an input / output buffer that complies with the LVTTL standard. The input potential thresholds of the LVTTL standard are Vil=0.8V, which is the low level, and Vih=2.0V, which is the high level.

[0089] The IO buffer 210 is connected to a signal line 101, and an L signal is read from the signal line 101.

[0090] The IO buffer control unit 230 is a logic circuit that controls the IO buffer 210 . The IO buffer control unit 230 is connected to the IO buffer 210 via four signal lines 102 , 103 , 104 , and 206 . The IO buffer control unit 230 provides the oe signal to the IO buffer 210 via the signal line 102 . The IO buffer control unit 230 provides an out signal to the IO buffer 210 via the signal line 103 . The IO buffer control unit 230 receives the in signal from the IO buffer 210 via the signal line 104 . The IO buffer control unit 230 provides the sel signal to the IO buffer 210 via the signal line 206 .

[0091] Here, the IO buffer control unit 230 receives a clock from the OSC 150 . The OSC 150 is the same as in the first embodiment, and its clock frequency is 30 MHz (period 0.033 us).

[0092] FIG. 13 is a circuit diagram showing a circuit at the output end inside the IO buffer 210 according to the second embodiment. The output terminal of the IO buffer 210 is provided with transistors 211A, 211B, 211C, and 211D, resistors 212A, 212B, 212C, and 212D as drive resistors, and a selector 213 as a switching unit.

[0093] In the second embodiment, when the oe signal is "1", the selector 213 can switch between the output from the first output terminal 214A having the transistors 211A, 211B and the resistors 212A, 212B and the output from the second output terminal 214B having the transistors 211C, 211D and the resistors 212C, 212D, and when the oe signal is "0", the transistors 211A, 211B, 211C, 211D are turned OFF, thereby putting the output into a high impedance state. In other words, the IO buffer 210 can switch the output terminal connected to the signal line 101 between a first output terminal 214A having a first drive resistance which is resistor 212A or resistor 212B, and a second output terminal 214B having a second drive resistance which is resistor 212C or resistor 212D having a resistance value greater than the first drive resistance. Therefore, the IO buffer control unit 230 controls the IO buffer 210 to output a high or low signal to the signal line 101 from the first output terminal 214A or the second output terminal 214B.

[0094] First, a case where the output of the first output terminal 214A is selected by the selector 213 will be described. The IO buffer 210 changes the L signal on the signal line 101 between High and Low by turning on or off the transistors 211A and 211B. For example, the IO buffer 210 outputs High (1) by turning on the transistor 211A and turning off the transistor 211B, which causes the terminal 107 (see FIG. 12) of the semiconductor integrated circuit 200 to output High (1). Furthermore, the IO buffer 210 outputs Low (0) by turning off the transistor 211A and turning on the transistor 211B. As a result, Low (0) is output from the terminal 107 of the semiconductor integrated circuit 200.

[0095] The resistance values ​​of the resistors 212A and 212B determine the drive strength of the output of the IO buffer 210. The resistance values ​​of the resistors 212A and 212B are each set to 50Ω.

[0096] Next, a case where the output of the second output terminal 214B is selected by the selector 213 will be described. The IO buffer 210 changes the L signal on the signal line 101 between High and Low by turning on or off the transistors 211C and 211D. For example, the IO buffer 210 outputs High (1) by turning on the transistor 211C and turning off the transistor 211D. As a result, the terminal 107 of the semiconductor integrated circuit 200 outputs High (1). Furthermore, the IO buffer 210 outputs Low (0) by turning off the transistor 211C and turning on the transistor 211D, so that the terminal 107 of the semiconductor integrated circuit 200 outputs Low (0).

[0097] The resistance values ​​of the resistors 212C and 212D determine the drive strength of the output of the IO buffer 210. The resistance values ​​of the resistors 212C and 212D are each set to 350Ω. The resistances 212A, 212B at the first output 214A are 50 Ω, so the first output 214A has a higher drive strength than the second output 214B. In the following description, when the first output terminal 214A is selected, it is also referred to as high drive strength, and when the second output terminal 214B is selected it is also referred to as low drive strength.

[0098] FIGS. 14(A) to 14(C) and FIGS. 15(A) to 15(C) are block diagrams for explaining examples of use of the semiconductor integrated circuit 200 according to the second embodiment. Figure 14(A) is a block diagram of a substrate 260A carrying a semiconductor integrated circuit 200, Figure 14(B) is a block diagram of a substrate 260B carrying a semiconductor integrated circuit 200, Figure 14(C) is a block diagram of a substrate 260C carrying a semiconductor integrated circuit 200, Figure 15(A) is a block diagram of a substrate 260D carrying a semiconductor integrated circuit 200, Figure 15(B) is a block diagram of a substrate 260E carrying a semiconductor integrated circuit 200, and Figure 15(C) is a block diagram of a substrate 260F carrying a semiconductor integrated circuit 200. These substrates are mounted in electronic devices such as image forming devices.

[0099] As shown in FIG. 14(A), the substrate 260A includes the semiconductor integrated circuit 200, a resistor 261U, a capacitor 262A, and a counter device 163. As shown in FIG. 14(B), the substrate 260B includes the semiconductor integrated circuit 200, a resistor 261U, a capacitor 262B, and a counter device 163. As shown in FIG. 14(C), the substrate 260C includes the semiconductor integrated circuit 200, a resistor 261U, a capacitor 262C, and a counter device 163.

[0100] As shown in FIG. 15(A), the substrate 260D includes the semiconductor integrated circuit 200, a resistor 261L, a capacitor 262A, and a counter device 163. As shown in FIG. 15B, the substrate 260E includes the semiconductor integrated circuit 200, a resistor 261L, a capacitor 262B, and a counter device 163. As shown in FIG. 15(C), the substrate 260F includes the semiconductor integrated circuit 200, a resistor 261L, a capacitor 262C, and a counter device 163. In other words, the IO buffer 210 is connected to either the resistor 261U which is a pull-up resistor or the resistor 261L which is a pull-down resistor, and either the capacitor 262A which is a first capacitor, the capacitor 262B which is a second capacitor having a larger capacitance than the first capacitor, or the capacitor 262C which is a third capacitor having a larger capacitance than the second capacitor, by the signal line 101. As described above, the IO buffer 210 can switch the output terminal connected to the signal line 101 between the first output terminal 214A and the second output terminal 214B.

[0101] In the second embodiment, the set value set in the semiconductor integrated circuit 200 can be changed by using resistors 261U or 261L arranged at different positions and capacitors 262A, 262B, and 262C with different capacitances. For example, the set value set in the semiconductor integrated circuit 200 can be changed depending on the type of substrates 260A to 260F. Here, six types of set values ​​can be set in the semiconductor integrated circuit 200.

[0102] The resistor 261U and the resistor 161L are both resistive elements, and the resistance value thereof is set to 10 kΩ. In the substrates 260A to 260C shown in FIGS. 14(A) to 14(C), the resistor 261U is connected between the 3.3V power supply 164 and the signal line 101, and functions as a pull-up resistor. On the other hand, in the substrates 260D to 260F shown in FIGS. 15(A) to 15(C), the resistor 261L is connected between the signal line 101 and the GND 165 of 0V, and functions as a pull-down resistor.

[0103] The capacitors 262A to 262C are capacitance components between the signal line 101 and the GND 165 of 0V. Capacitor 262A has a capacitance Cs, capacitor 262B has a capacitance Cm, and capacitor 262C has a capacitance Cl. Here, it is assumed that capacitance Cs is 50 pF (Small), capacitance Cm is 400 pF (Middle), and capacitance Cl is 0.01 uF (Large).

[0104] The counterpart device 163 in the second embodiment is the same as the counterpart device 163 in the first embodiment.

[0105] In the second embodiment, the combination of the resistor 261U and the capacitor 262A shown in FIG. 14(A) allows the semiconductor integrated circuit 200 to read the set value "4." The combination of the resistor 261U and the capacitor 262B shown in FIG. 14(B) allows the semiconductor integrated circuit 200 to read the set value "5." The combination of the resistor 261U and the capacitor 262C shown in FIG. 14(C) allows the semiconductor integrated circuit 200 to read the set value "7."

[0106] The combination of the resistor 261L and the capacitor 262A shown in FIG. 15(A) allows the semiconductor integrated circuit 200 to read the set value "3." The combination of the resistor 261L and the capacitor 262B shown in FIG. 15(B) allows the semiconductor integrated circuit 200 to read the set value "2." The combination of the resistor 261L and the capacitor 262C shown in FIG. 15(C) allows the semiconductor integrated circuit 200 to read the set value "0."

[0107] 16 and 17 are graphs showing the potential change of the L signal when the IO buffer 110 is in a High output state (oe=1, out=1) using the step response calculation formula of an RC circuit in the case where a resistor 261L is provided as shown in FIGS. 15(A) to 15(C). Here, the RC circuit is configured by resistor 212A or resistor 212C and any one of capacitors 262A to 262C shown in FIG.

[0108] Here, the capacitance of the capacitor 262A is Cs=50 pF, the capacitance of the capacitor 262B is Cm=400 pF, and the capacitance of the capacitor 262C is Cl=0.01 uF. Figures 16 and 17 show the potential changes in these three cases.

[0109] The potential Vc (V) of the L signal is expressed by the above formula (1) using the time t (seconds) from the start.

[0110] First, a case where the selector 213 selects the first output terminal 214A will be described. When the capacitance element constant is Cs=50pF, the value of τ is given by the following equation (5), when Cm=400pF, the value of τ is given by the following equation (6), and when the capacitance element constant is Cl=0.01uF, the value of τ is given by the following equation (7). For R, the value of resistor 212A as a drive resistor = 50Ω is applied.

[0111] τ=Cs×R=50×10 -12 ×50=2.5×10 -9 =2.5ns (5) τ=Cm×R=400×10 -12 ×50=20×10 -9 =20ns (6) τ = Cl × R = 0.01 × 10 -6 ×50=500×10 -9 =500ns (7)

[0112] Curve 20 shown in FIG. 16 shows the case where capacitor 262A (Cs=50 pF) is used, curve 21 shows the case where capacitor 262B (Cm=400 pF) is used, and curve 22 shows the case where capacitor 262B (Cl=0.001 uF) is used.

[0113] 16, when capacitor 262A is used, the potential of the L signal exceeds Vih (2.0 V) after 2.4 ns, as shown in curve 20. This means that if the IO buffer 210 is put into a high impedance state (oe=0) after 2.4 ns, the IO buffer 210 will read "1."

[0114] Furthermore, when capacitor 262B is used, the potential of the L signal exceeds Vih (2.0 V) after 20 ns, as shown in curve 21. This means that if the IO buffer 210 is put into a high impedance state (oe=0) after 20 ns, the IO buffer 210 will read "1."

[0115] On the other hand, when capacitor 262C is used, the potential of the L signal does not exceed Vil (0.8 V) until 140 ns. This means that if the IO buffer 210 is put into a high impedance state (oe=0) before 140 ns, the IO buffer 210 will read "0." In this case, the RC circuit is in a transient state and has not yet reached a steady state.

[0116] In other words, if the IO buffer 210 is set to a high impedance state (oe=0) a predetermined period (e.g., 33 ns) after the IO buffer 210 starts a high output state (oe=1, out=1), when the capacitance constants are Cs (50 pF) and Cm (400 pF), the IO buffer 210 reads "1," and when the capacitance constant is Cl (0.01 uF), the IO buffer 210 reads "0." The predetermined period here may be the period between 20 ns when the L signal exceeds Vih (2.0 V) when capacitor 262A or capacitor 262B is used and 140 ns when the L signal exceeds Vil (0.8 V) when capacitor 262C is used.

[0117] Next, a case where the selector 213 selects the second output terminal 214B will be described. When the capacitance element constant is Cs=50pF, the value of τ is given by the following equation (8), when Cm=400pF, the value of τ is given by the following equation (9), and when the capacitance element constant is Cl=0.01uF, the value of τ is given by the following equation (10). For R, the value of resistor 212C as a drive resistor = 350Ω is applied.

[0118] τ=Cs×R=50×10 -12 ×350=17.5×10 -9 =17.5ns (8) τ=Cm×R=400×10 -12 ×50=140×10 -9 =140ns (9) τ = Cl × R = 0.01 × 10 -6 ×50=3500×10 -9 =3500ns (10)

[0119] Curve 23 shown in FIG. 17 shows the case where capacitor 262A (Cs=50 pF) is used, curve 24 shows the case where capacitor 262B (Cm=400 pF) is used, and curve 25 shows the case where capacitor 262C (Cl=0.001 uF) is used.

[0120] 17, when capacitor 262A is used, the potential of the L signal exceeds Vih (2.0 V) after 16 ns, as shown in curve 23. This means that if the IO buffer 210 is put into a high impedance state (oe=0) after 16 ns, the IO buffer 210 reads "1."

[0121] On the other hand, when capacitor 262B is used, the potential of the L signal does not exceed Vil (0.8 V) until 39 ns, as shown in curve 24. This means that if the IO buffer 210 is put into a high impedance state (oe=0) before 39 ns, the IO buffer 210 will read "0." In this case, the RC circuit is in a transient state and has not yet reached a steady state.

[0122] In other words, if the IO buffer 210 is put into a high impedance state (oe=0) a predetermined period of time (e.g., 33 ns) after the IO buffer 210 starts a high output state (oe=1, out=1), the IO buffer 210 will read "1" if the capacitance constant is Cs (50 pF), and will read "0" if the capacitance constant is Cm (400 pF). The predetermined period here may be the period between 16 ns when the L signal exceeds Vih (2.0 V) when capacitor 262A is used and 39 ns when the L signal exceeds Vil (0.8 V) when capacitor 262B is used. Even when the capacitor 262C is used, the IO buffer 210 reads "0" for this predetermined period, as shown by the curve 25 in FIG.

[0123] 18 and 19 are graphs showing the potential change of the L signal when the IO buffer 210 is set to a Low output state (oe=1, out=0) using the step response calculation formula of an RC circuit in the case where a resistor 261U is provided as shown in FIGS. 14(A) to 14(C). Here, the RC circuit is composed of resistor 212B or resistor 212D shown in FIG. 13 and any one of capacitors 262A to 262C.

[0124] Here, the capacitance of the capacitor 262A is Cs=50 pF, the capacitance of the capacitor 262B is Cm=400 pF, and the capacitance of the capacitor 262C is Cl=0.01 uF. Figure 18 shows the potential changes in these three cases.

[0125] The potential Vc (V) of the L signal is expressed by the above equation (4) using the time t (seconds) from the start. Here, e is the same as in equation (1).

[0126] First, a case where the selector 213 selects the first output terminal 214A will be described. In this case, τ is the same as in the above equations (5) to (7). Curve 26 shown in FIG. 18 shows the case where capacitor 262A (Cs=50 pF) is used, curve 27 shows the case where capacitor 262B (Cm=400 pF) is used, and curve 28 shows the case where capacitor 262B (Cl=0.001 uF) is used.

[0127] 18, when capacitor 262A is used, the potential of the L signal falls below Vil (0.8 V) at 3.6 ns, as shown by curve 26. This means that if the IO buffer 210 is put into a high impedance state (oe=0) after 3.6 ns, the IO buffer 210 will read "0."

[0128] Furthermore, when capacitor 262B is used, the potential of the L signal falls below Vil (0.8 V) at 29 ns, as shown by curve 27. This means that if the IO buffer 210 is put into a high impedance state (oe=0) after 29 ns, the IO buffer 210 will read "0."

[0129] On the other hand, when capacitor 262C is used, the potential of the L signal does not fall below Vih (2.0 V) until 250 ns, as shown by curve 28. This means that if the IO buffer 110 is put into a high impedance state (oe=0) before 250 ns, the IO buffer 210 will read "1."

[0130] In other words, if the IO buffer 210 is put into a high impedance state (oe=0) a predetermined period (e.g., 33 ns) after the IO buffer 210 starts a low output state (oe=1, out=0), the IO buffer 210 will read "0" if the capacitance constant is Cs=50 pF or Cm=400 pF, and the IO buffer 110 will read "1" if the capacitance constant is Cl=0.01 uF. The predetermined period here may be the period between 29 ns when the L signal falls below Vil (0.8 V) when capacitor 262B is used and 250 ns when the L signal falls below Vih (2.0 V) when capacitor 262C is used.

[0131] Next, a case where the selector 213 selects the second output terminal 214B will be described. In this case, τ is the same as in the above equations (8) to (10).

[0132] Curve 29 shown in FIG. 19 shows the case where capacitor 262A (Cs=50 pF) is used, curve 30 shows the case where capacitor 262B (Cm=400 pF) is used, and curve 31 shows the case where capacitor 262C (Cl=0.001 uF) is used.

[0133] 19, when capacitor 262A is used, the potential of the L signal falls below Vil (0.8 V) after 26 ns, as shown by curve 29. This means that if the IO buffer 210 is put into a high impedance state (oe=0) after 26 ns, the IO buffer 210 will read "0."

[0134] On the other hand, when capacitor 262B is used, the potential of the L signal does not fall below Vih (2.0 V) until 70 ns, as shown in curve 30. This means that if the IO buffer 210 is put into a high impedance state (oe=0) before 70 ns, the IO buffer 210 will read "1." In this case, the RC circuit is in a transient state and has not yet reached a steady state.

[0135] In other words, if the IO buffer 210 is put into a high impedance state (oe=0) a predetermined period of time (e.g., 33 ns) after the IO buffer 210 starts a low output state (oe=1, out=0), the IO buffer 210 will read "0" if the capacitance constant is Cs (50 pF), and will read "1" if the capacitance constant is Cm (400 pF). The predetermined period here may be the period between 26 ns when the L signal falls below Vil (0.8 V) when capacitor 262A is used and 70 ns when the L signal falls below Vih (2.0 V) when capacitor 262B is used. During this period, as shown by curve 31 in FIG. 19, the IO buffer 210 reads out "1" even if the capacitor 262C is used.

[0136] FIG. 20 is a flowchart showing the operation of the IO buffer control unit 230 according to the second embodiment. First, when the power supply of the semiconductor integrated circuit 200 is turned on, the IO buffer control unit 230 sets the sel signal to 1, thereby causing the selector 213 of the IO buffer 210 to select the output of the first output terminal 214A (S20).

[0137] Next, the IO buffer control unit 230 sets the out signal to 0 and the oe signal to 0, putting the IO buffer 210 into a high impedance state, and reads the value of the in signal after a certain time has passed (S21). Note that although the out signal is set to 0 here, the out signal may also be set to 1.

[0138] Next, the IO buffer control unit 230 determines whether the value of the read in signal is "1" (S22). If the value of the in signal is "1" (Yes in S22), the process proceeds to step S23, and if the value of the in signal is "0" (No in S22), the process proceeds to step S28.

[0139] In step S23, in order to change the state of the L signal, the IO buffer control unit 230 sets the out signal to 0 and the oe signal to 1.

[0140] Next, after a predetermined period of time, here 33 ns, has elapsed, the IO buffer control unit 230 sets the out signal to 0 and the oe signal to 0, puts the IO buffer 210 into a high impedance state, and reads the value of the in signal (S24).

[0141] Next, the IO buffer control unit 230 sets the sel signal to 0, thereby causing the selector 213 of the IO buffer 210 to select the output of the second output terminal 214B (S25).

[0142] Next, the IO buffer control unit 230 waits for a certain period of time until the values ​​become stable, and then sets the out signal to 0 and the oe signal to 1 (S26).

[0143] Next, after a predetermined period, here 33 ns, has elapsed, the IO buffer control unit 230 sets the out signal to 0 and the oe signal to 0, puts the IO buffer 210 into a high impedance state, and reads the value of the in signal (S27).Then, the process proceeds to step S33.

[0144] On the other hand, in step S22, if the in signal is "0" (No in S22), the process proceeds to step S28, and in order to change the state of the L signal, the IO buffer control unit 230 sets the out signal=1 and the oe signal=1.

[0145] Next, after a predetermined period, here 33 ns, has elapsed, the IO buffer control unit 230 sets the out signal to 1 and the oe signal to 0, puts the IO buffer 110 into a high impedance state, and reads the value of the in signal (S29).

[0146] Next, the IO buffer control unit 230 sets the sel signal to 0, thereby causing the selector 213 of the IO buffer 210 to select the output of the second output terminal 214B (S30).

[0147] Next, the IO buffer control unit 230 waits for a certain period of time until the values ​​stabilize, and then sets the out signal to 1 and the oe signal to 1 (S31).

[0148] Next, after a predetermined period of time, here 33 ns, has elapsed, the IO buffer control unit 230 sets the out signal to 1 and the oe signal to 0, puts the IO buffer 210 into a high impedance state, and reads the value of the in signal (S32).Then, the process proceeds to step S33.

[0149] In step S33, the IO buffer control unit 230 identifies the setting value. For example, the IO buffer control unit 230 identifies the setting value by combining the in signal read in step S21, the in signal read in step S24, and the in signal read in step S27, or the in signal read in step S29 and the in signal read in step S32.

[0150] For example, if the value a read in step S21 is "1" (Yes in S22), the process proceeds to step S23, and the IO buffer control unit 230 uses the value b read in step S24 and the value c read in step S27. Then, the IO buffer control unit 230 specifies the setting value by the values ​​abc. Specifically, if a=1, b=1, and c=1, the value "111" is "7" in binary, and the setting value is "7." If a=1, b=0, and c=1, the value "101" is "5" in binary, and the setting value is "5." Furthermore, if a=1, b=0, and c=0, the value "100" is "4" in binary, and the setting value is "4."

[0151] On the other hand, if the value a read in step S21 is "0" (No in S22), the process proceeds to step S28, and the IO buffer control unit 230 uses the value d read in step S29 and the value e read in step S32. Then, the IO buffer control unit 230 specifies the setting value by the value ade. Specifically, if a=0, d=1, and e=1, the value "011" becomes "3" in binary, and the setting value becomes "3." If a=0, d=1, and e=0, the value "010" becomes "2" in binary, and the setting value becomes "2." If a=0, d=0, and e=0, the value "000" becomes "0" in binary, and the setting value becomes "0."

[0152] Then, the IO buffer control unit 230 transfers the signal control right of the IO buffer 110 to the transmitting unit 140 by setting the out signal to tx and the oe signal to 1 (S34).

[0153] In this way, the IO buffer control unit 230 can identify the setting value according to the configuration of the boards 260A to 260F on which the semiconductor integrated circuit 200 is mounted.

[0154] A specific explanation will be given below using a time chart. The in signal is the result of the IO buffer 210, which is an LVTTL buffer, reading "0" or "1" from the potential Vc (V) of the L signal, as described below. When Vc > Vih (2.0V), the in signal becomes "1". When Vil (0.8V) < Vc < Vih (2.0V), the in signal is indeterminate and it is impossible to determine whether it is "0" or "1". When Vc < Vil (0.8V), the in signal becomes "0".

[0155] FIG. 21 is a time chart when the resistor 261U and the capacitor 262C are used, as shown in FIG. 14(C). First, at power-on, the IO buffer control unit 23 set the sel signal = 1, the out signal = 0, and the oe signal = 0, put the IO buffer 210 in a high drive strength and high impedance state, and read the value of the in signal at time T0 after a certain time has elapsed. Here, since the resistor 261U is used, it is pulled up at 3.3V. Therefore, the in signal = "1".

[0156] Next, since the in signal read at time T0 was "1", at time T1, the out signal = "0" and the oe signal = "1" were set, and the IO buffer 210 was put in the "0" output state.

[0157] Then, at time T4 when 33 ns has elapsed from time T1, the IO buffer control unit 230 set the out signal = "0" and the oe signal = "0", put the IO buffer 210 in a high impedance state, and read the value of the in signal at that time T4. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T4 is reached after one clock from time T1.

[0158] Here, since the capacitance of capacitor 262C is Cl, Vc>Vih (2.0 V) remains true until 250 ns have elapsed from time T1, as shown by curve 28 in Fig. 18. Therefore, at time T4, 33 ns after time T1, the in signal becomes "1".

[0159] Next, the IO buffer control unit 230 sets the sel signal to 0, thereby setting the IO buffer 210 to low drive strength. Then, at time T5 after waiting for a certain period of time, the IO buffer control unit 230 sets the out signal to 0 and the oe signal to 1, putting the IO buffer 210 into a "0" output state.

[0160] Then, at time T6, 33 ns after time T5, the IO buffer control unit 230 sets the out signal to "0" and the oe signal to "0", puts the IO buffer 210 into a high impedance state, and reads the value of the in signal at time T6. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T6 occurs one clock after time T5.

[0161] Here, since the capacitance of capacitor 262C is Cl, Vc>Vih (2.0V) as shown in curve 31 in FIG. 19, the in signal becomes "1" at time T6, 33 ns after time T5. Then, since the value of the in signal read by the IO buffer control unit 230 at time T0 was "1," the value of the in signal read at time T4 was "1," and the value of the in signal read at time T5 was "1," the IO buffer control unit 230 obtains a setting value of "7" (2'b111 in binary).

[0162] Furthermore, at time T7, the IO buffer control unit 230 transfers the signal control right of the IO buffer 210 to the transmitting unit 140 by setting the out signal to "tx" and the oe signal to "1".

[0163] FIG. 22 is a time chart when resistor 261U and capacitor 262B are used, as shown in FIG. 14(B). First, at power-on, the IO buffer control unit 230 sets the sel signal = 1, out signal = 0, and oe signal = 0, puts the IO buffer 210 in a high drive strength and high impedance state, and reads the value of the in signal at time T0 after a certain time has elapsed. Here, since resistor 261U is used, it is pulled up to 3.3V. Therefore, the in signal = "1".

[0164] Next, since the in signal read at time T0 by the IO buffer control unit 230 is "1", at time T1, the out signal = "0" and oe signal "1" are set, and the IO buffer 210 is put in the "0" output state.

[0165] Then, at time T4 when 33 ns has elapsed from time T1, the IO buffer control unit 230 sets the out signal = "0" and oe signal = "0", puts the IO buffer 210 in a high impedance state, and reads the value of the in signal at that time T4. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T4 is reached after one clock from time T1.

[0166] Here, since the capacitance of capacitor 262C is Cm, as shown by curve 27 in FIG. 18, when 29 ns has elapsed from time T1, Vc < Vil (0.8V). Therefore, at time T4, 33 ns after time T1, the in signal = "0".

[0167] Next, the IO buffer control unit 230 sets the sel signal = 0 and reduces the drive strength of the IO buffer 210. Then, at time T5 after a certain period has elapsed, the IO buffer control unit 230 sets the out signal = 0 and oe signal = 1, and puts the IO buffer 210 in the "0" output state.

[0168] Then, at time T6, 33 ns after time T5, the IO buffer control unit 230 sets the out signal to "0" and the oe signal to "0", puts the IO buffer 210 into a high impedance state, and reads the value of the in signal at time T6. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T6 occurs one clock after time T5.

[0169] Here, since the capacitance of capacitor 262C is Cm, Vc>Vih (2.0 V) remains true until 70 ns have elapsed from time T5, as shown by curve 30 in Fig. 19. Therefore, at time T6, 33 ns after time T5, the in signal becomes "1." Then, since the value of the in signal read by the IO buffer control unit 230 at time T0 was "1", the value of the in signal read at time T4 was "0", and the value of the in signal read at time T5 was "1", the IO buffer control unit 230 obtains a setting value of "5" (2'b101 in binary).

[0170] Furthermore, at time T7, the IO buffer control unit 230 transfers the signal control right of the IO buffer 210 to the transmitting unit 140 by setting the out signal to "tx" and the oe signal to "1".

[0171] FIG. 23 is a time chart when a resistor 261U and a capacitor 262A are used as shown in FIG. 14(A). First, when powered on, the IO buffer control unit 230 sets the sel signal to 1, the out signal to 0, and the oe signal to 0, putting the IO buffer 210 in a high drive strength and high impedance state, and then reads the value of the in signal at time T0 after a certain time has passed. Here, since resistor 261U is used, it is pulled up to 3.3V. Therefore, the in signal becomes "1".

[0172] Next, since the in signal read at time T0 by the IO buffer control unit 230 is "1", at time T1, the out signal is set to "0" and the oe signal is set to "1", and the IO buffer 210 is set to the "0" output state.

[0173] Then, at time T4 when 33 ns has elapsed from time T1, the IO buffer control unit 230 sets the out signal = "0" and the oe signal = "0", puts the IO buffer 210 in the high-impedance state, and reads the value of the in signal at that time T4. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T4 is reached after 1 clock from time T1.

[0174] Here, since the capacitance of the capacitor 262C is Cs, as shown by the curve 26 in FIG. 18, when 3.6 ns has elapsed from time T1, Vc < Vil (0.8 V). Therefore, at time T4, 33 ns after time T1, the in signal = "0".

[0175] Next, the IO buffer control unit 230 sets the sel signal = 0 and reduces the drive strength of the IO buffer 210. Then, at time T5 after waiting for a certain period, the IO buffer control unit 230 sets the out signal = 0 and the oe signal = 1, and sets the IO buffer 210 to the "0" output state.

[0176] Then, at time T6 when 33 ns has elapsed from time T5, the IO buffer control unit 230 sets the out signal = "0" and the oe signal = "0", puts the IO buffer 210 in the high-impedance state, and reads the value of the in signal at that time T6. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T6 is reached after 1 clock from time T5.

[0177] Here, since the capacitance of capacitor 262C is Cs, as shown by curve 29 in FIG. 19, when 26 ns have elapsed from time T5, Vc < Vil (0.8 V). Therefore, at time T6, 33 ns after time T5, in signal = "0". And since the value of the in signal read at time T0 was "1", the value of the in signal read at time T4 was "0", and the value of the in signal read at time T5 was "0", the IO buffer control unit 230 obtains the set value "4" (2'b100 in binary representation).

[0178] Furthermore, at time T7, the IO buffer control unit 230 transfers the signal control right of the IO buffer 210 to the transmission unit 140 with out signal = "tx" and oe signal = "1".

[0179] FIG. 24 is a time chart when resistor 261L and capacitor 262C are used, as shown in FIG. 15(C). First, when power is turned on, the IO buffer control unit 230 sets sel signal = 1, out signal = 0, and oe signal = 0, sets the IO buffer 210 to high drive strength and high impedance state, and reads the value of the in signal at time T0 after a certain period of time. Here, since resistor 261L is used, it is pulled down to 0V. Therefore, in signal = "0".

[0180] Next, since the in signal read at time T0 was "0", at time T1, the IO buffer control unit 230 sets out signal = "1" and oe signal "1" to put the IO buffer 210 in the "1" output state.

[0181] Then, at time T4, 33 ns after time T1, the IO buffer control unit 230 sets out signal = "0" and oe signal = "0", puts the IO buffer 210 in the high impedance state, and reads the value of the in signal at that time T4. Note that since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T4 is reached after one clock from time T1.

[0182] Here, since the capacitance of capacitor 262C is C1, until 140 ns has elapsed from time T1 as shown by curve 22 in FIG. 16, Vc < Vil (0.8 V). Therefore, at time T4, 33 ns after time T1, in signal = "0".

[0183] Next, the IO buffer control unit 230 sets sel signal = 0 to reduce the drive strength of the IO buffer 210. Then, at time T5 after waiting for a certain period, the IO buffer control unit 230 sets out signal = 1 and oe signal = 1 to put the IO buffer 210 in the "1" output state.

[0184] Then, at time T6, 33 ns after time T5, the IO buffer control unit 230 sets out signal = "0" and oe signal = "0", puts the IO buffer 210 in the high-impedance state, and reads the value of the in signal at that time T6. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T6 is reached after one clock from time T5.

[0185] Here, since the capacitance of capacitor 262C is C1, as shown by curve 25 in FIG. 17, Vc < Vih (0.8 V). Therefore, at time T6, 33 ns after time T5, in signal = "0". Then, since the value of the in signal read at time T0 is "0", the value of the in signal read at time T4 is "0", and the value of the in signal read at time T5 is "0", the IO buffer control unit 230 obtains the set value "0" (2'b000 in binary representation).

[0186] Furthermore, at time T7, the IO buffer control unit 130 sets out signal = "tx" and oe signal = "1" to transfer the signal control right of the IO buffer 210 to the transmission unit 140.

[0187] FIG. 25 is a time chart when a resistor 261L and a capacitor 262B are used as shown in FIG. 15(B). First, when powered on, the IO buffer control unit 230 sets the sel signal to 1, the out signal to 0, and the oe signal to 0, putting the IO buffer 210 in a high drive strength and high impedance state, and then reads the value of the in signal at time T0 after a certain time has passed. Here, since resistor 261L is used, it is pulled down to 0V. Therefore, the in signal becomes "0".

[0188] Next, since the in signal read at time T0 was "0", the IO buffer control unit 230 sets the out signal to "1" and the oe signal to "1" at time T1, putting the IO buffer 210 into a "1" output state.

[0189] Then, at time T4, 33 ns after time T1, the IO buffer control unit 230 sets the out signal to "0" and the oe signal to "0", puts the IO buffer 210 into a high impedance state, and reads the value of the in signal at time T4. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T4 occurs one clock after time T1.

[0190] Here, since the capacitance of capacitor 262B is Cm, Vc>Vih (2.0 V) occurs 20 ns after time T1, as shown by curve 21 in Fig. 16. Therefore, at time T4, 33 ns after time T1, the in signal becomes "1".

[0191] Next, the IO buffer control unit 230 sets the sel signal to 0, thereby setting the IO buffer 210 to low drive strength. Then, at time T5 after waiting for a certain period of time, the IO buffer control unit 230 sets the out signal=1 and the oe signal=1, putting the IO buffer 210 into a "1" output state.

[0192] Then, at time T6 when 33 ns has elapsed since time T5, the IO buffer control unit 230 sets the out signal = "0" and the oe signal = "0", puts the IO buffer 210 in a high-impedance state, and reads the value of the in signal at that time T6. Since the clock frequency of OSC150 is 30 MHz (period 33 ns), time T6 is reached after one clock from time T5.

[0193] Here, since the capacitance of capacitor 262B is Cm, until 39 ns has elapsed since time T5, Vc < Vil (0.8 V) as shown by curve 24 in FIG. 17. Therefore, at time T6, 33 ns after time T5, the in signal = "0". Then, since the value of the in signal read at time T0 was "0", the value of the in signal read at time T4 was "1", and the value of the in signal read at time T5 was "0", the IO buffer control unit 230 obtains the set value "2" (2'b010 in binary representation).

[0194] Furthermore, at time T7, the IO buffer control unit 230 transfers the signal control right of the IO buffer 210 to the transmission unit 140 with the out signal = "tx" and the oe signal = "1".

[0195] FIG. 26 is a time chart when the resistor 261L and the capacitor 262A are used as shown in FIG. 15(A). First, when power is turned on, the IO buffer control unit 230 sets the sel signal = 1, the out signal = 0, and the oe signal = 0, puts the IO buffer 210 in a high drive strength and high-impedance state, and reads the value of the in signal at time T0 after a certain time has elapsed. Here, since the resistor 261L is used, it is pulled down to 0V. Therefore, the in signal = "0".

[0196] Next, since the in signal read at time T0 was "0", the IO buffer control unit 230 sets the out signal to "1" and the oe signal to "1" at time T1, putting the IO buffer 210 into a "1" output state.

[0197] Then, at time T4, 33 ns after time T1, the IO buffer control unit 230 sets the out signal to "0" and the oe signal to "0", puts the IO buffer 210 into a high impedance state, and reads the value of the in signal at time T4. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T4 occurs one clock after time T1.

[0198] Here, since the capacitance of capacitor 262A is Cs, Vc>Vih (2.0 V) occurs 2.4 ns after time T1, as shown in curve 20 in Fig. 16. Therefore, at time T4, 33 ns after time T1, the in signal becomes "1".

[0199] Next, the IO buffer control unit 230 sets the sel signal to 0, thereby setting the IO buffer 210 to low drive strength. Then, at time T5 after waiting for a certain period of time, the IO buffer control unit 230 sets the out signal=1 and the oe signal=1, putting the IO buffer 210 into a "1" output state.

[0200] Then, at time T6, 33 ns after time T5, the IO buffer control unit 230 sets the out signal to "0" and the oe signal to "0", puts the IO buffer 210 into a high impedance state, and reads the value of the in signal at time T6. Since the clock frequency of the OSC 150 is 30 MHz (period of 33 ns), time T6 occurs one clock after time T5.

[0201] Here, since the capacitance of capacitor 262C is Cm, Vc>Vih (2.0 V) after 16 ns from time T5, as shown by curve 23 in Fig. 17. Therefore, at time T6, 33 ns after time T5, the in signal becomes "1". Then, since the value of the in signal read by the IO buffer control unit 230 at time T0 was "0", the value of the in signal read at time T4 was "1", and the value of the in signal read at time T5 was "1", the IO buffer control unit 230 obtains a setting value of "3" (2'b011 in binary).

[0202] Furthermore, at time T7, the IO buffer control unit 230 transfers the signal control right of the IO buffer 210 to the transmitting unit 140 by setting the out signal to "tx" and the oe signal to "1".

[0203] As described above, in the second embodiment, the IO buffer control unit 230 specifies the setting values ​​for performing the initial setup based on: a first value determined by the high or low state of the voltage of the signal line 101 when performing the initial setup of the semiconductor integrated circuit 100 with the output terminal connected to the signal line 101 switched to the first output terminal 214A; a second value determined by the high or low state of the voltage of the signal line 101 when a predetermined first period has elapsed after controlling the output of the IO buffer 210 so that the voltage becomes a state different from the state corresponding to the first value; and a third value determined by the high or low state of the voltage of the signal line 101 when a predetermined second period has elapsed after switching the output terminal to the second output terminal 214B and controlling the output of the IO buffer 210 so that the voltage becomes a state different from the state corresponding to the first value.

[0204] For example, the first value indicates either 1 or 0 when the state of the signal line 101 is high, and indicates the other of 1 or 0 when the state of the signal line 101 is low. The second value indicates either 1 or 0 when the state of the signal line 101 is high, and indicates the other of 1 or 0 when the state of the signal line 101 is low. The third value indicates either 1 or 0 when the state of the signal line 101 is high, and indicates the other of 1 or 0 when the state of the signal line 101 is low. The set value is a value indicated by a binary number obtained by concatenating the first value, the second value, and the third value.

[0205] In the second embodiment, the first period is the period between when the state corresponding to the first value is high and when the state of the signal line 101 becomes low due to a first RC circuit formed by a first drive resistor, which is resistor 212A or resistor 212B, and a second capacitor, 262B, and when the state of the signal line 101 is maintained high due to a second RC circuit formed by the first drive resistor and a third capacitor, capacitor 262C. On the other hand, if the state corresponding to the first value is low, it is the period between the time when the first RC circuit causes the state of signal line 101 to become high and the time when the second RC circuit maintains the state of signal line 101 low.

[0206] In the second embodiment, the second period is the period between when the state corresponding to the first value is high and when the state of the signal line 101 becomes low due to the third RC circuit formed by the second drive resistor, which is resistor 212C or resistor 212D, and the first capacitor, capacitor 262A, and when the state of the signal line 101 is maintained high due to the fourth RC circuit formed by the second drive resistor and the second capacitor, capacitor 262B. On the other hand, when the state corresponding to the first value is low, it is the period between the time when the third RC circuit causes the state of signal line 101 to become high and the time when the fourth RC circuit maintains the state of signal line 101 low.

[0207] As described above, according to the second embodiment, in addition to the conventional one-bit setting value that is read in a high-impedance state by pull-up or pull-down, a two-bit setting value can be acquired, making it possible to acquire three bits of information per terminal.

[0208] In the first and second embodiments, an example is shown in which LVTTL is used as the IO buffers 110 and 210, but the first embodiment is not limited to such an example. The IO buffer 110 can also be realized by other types of buffers, such as LVCMOS (Low Voltage Complementary Metal-Oxide Semiconductor).

[0209] Furthermore, in the first and second embodiments, the voltage of the IO buffers 110 and 210 is 3.3V, but other voltages are also possible.

[0210] In the first embodiment described above, the IO buffers 110 and 210 are set to a high impedance state and the value of the in signal is read after 33 ns has elapsed, but this is not limited to 33 ns.

[0211] Furthermore, if the in signal can be read even when the IO buffers 110 and 210 are in the output state, the value of the in signal may be read without changing the IO buffer 110 to a high impedance state.

[0212] In the first and second embodiments, examples of the constants of the resistance elements, the electrostatic capacitance, the drive resistance, the clock frequency of the OSC, etc. are shown, but it is also possible to realize the invention when these values ​​are different. [Explanation of symbols]

[0213] 100,200 semiconductor integrated circuit, 101 signal line, 110,210 IO buffer, 111A,111B,211A,211B,211C,211D transistor, 112A,112B,212A,212B,212C,212D resistor, 130,230 IO buffer control unit, 140 transmission unit, 160A,160B,160C,160D,260A,260B,260C,260D,260E,260F substrate, 161U,161L,261U,261L resistor, 162A,162B,262A,262B,262C capacitor, 163 opposing device.

Claims

1. one of a pull-up resistor and a pull-down resistor, one of a first capacitor and a second capacitor having a capacitance larger than that of the first capacitor, and an input / output buffer connected by a signal line; an input / output buffer control unit that controls the input / output buffer to output a high or low signal from the input / output buffer to the signal line, the input / output buffer control unit specifies a setting value to be set in the semiconductor integrated circuit based on a first value determined by a high or low state of the voltage of the signal line when the power supply of the semiconductor integrated circuit is turned on, and a second value determined by a high or low state of the voltage of the signal line when a predetermined period has elapsed since the output of the input / output buffer is controlled to be in a state different from the state corresponding to the first value; The predetermined period is, when the state corresponding to the first value is high, between a period until the state of the signal line is made low by a first RC circuit constituted by a drive resistor and the first capacitor provided at the output end of the input / output buffer, and a period during which the state of the signal line is maintained high by a second RC circuit constituted by the drive resistor and the second capacitor; and, when the state corresponding to the first value is low, between a period until the state of the signal line is made high by the first RC circuit and a period during which the state of the signal line is maintained low by the second RC circuit. A semiconductor integrated circuit characterized by:

2. the first value indicates one of 1 and 0 when the state of the signal line is high, and indicates the other of 1 and 0 when the state of the signal line is low; the second value indicates either 1 or 0 when the state of the signal line is high, and indicates the other of 1 or 0 when the state of the signal line is low; The set value is a value represented by a binary number obtained by concatenating the first value and the second value.

2. The semiconductor integrated circuit according to claim 1,

3. one of a pull-up resistor and a pull-down resistor, one of a first capacitor, a second capacitor having a capacitance larger than that of the first capacitor, and a third capacitor having a capacitance larger than that of the second capacitor, and an input / output buffer capable of switching an output terminal connected by a signal line between a first output terminal having a first drive resistance and a second output terminal having a second drive resistance having a resistance value larger than that of the first drive resistance; an input / output buffer control unit that controls the input / output buffer to output a high or low signal from the first output terminal or the second output terminal to the signal line, the input / output buffer control unit specifies a setting value to be set in the semiconductor integrated circuit based on: a first value determined by a high or low state of the voltage of the signal line when the semiconductor integrated circuit is powered on with the output terminal switched to the first output terminal; a second value determined by a high or low state of the voltage of the signal line when a predetermined first period has elapsed after controlling the output of the input / output buffer to be in a state different from the state corresponding to the first value; and a third value determined by a high or low state of the voltage of the signal line when a predetermined second period has elapsed after switching the output terminal to the second output terminal and controlling the output of the input / output buffer to be in a state different from the state corresponding to the first value after the first period has elapsed; the first period is, when the state corresponding to the first value is high, a period until the state of the signal line is changed to low by a first RC circuit constituted by the first drive resistor and the second capacitor, and a period during which the state of the signal line is maintained high by a second RC circuit constituted by the first drive resistor and the third capacitor; and, when the state corresponding to the first value is low, a period is between a period until the state of the signal line is changed to high by the first RC circuit and a period during which the state of the signal line is maintained low by the second RC circuit; The second period is, when the state corresponding to the first value is high, between a period until the state of the signal line is made low by a third RC circuit formed by the second drive resistor and the first capacitor, and a period during which the state of the signal line is maintained high by a fourth RC circuit formed by the second drive resistor and the second capacitor; and, when the state corresponding to the first value is low, between a period until the state of the signal line is made high by the third RC circuit and a period during which the state of the signal line is maintained low by the fourth RC circuit. A semiconductor integrated circuit characterized by:

4. the first value indicates one of 1 and 0 when the state of the signal line is high, and indicates the other of 1 and 0 when the state of the signal line is low; the second value indicates either 1 or 0 when the state of the signal line is high, and indicates the other of 1 or 0 when the state of the signal line is low; the third value indicates either 1 or 0 when the state of the signal line is high, and indicates the other of 1 or 0 when the state of the signal line is low; The set value is a value represented by a binary number obtained by concatenating the first value, the second value, and the third value.

4. The semiconductor integrated circuit according to claim 3,

5. A semiconductor integrated circuit according to claim 1 or 2; one of the pull-up resistor and the pull-down resistor; one of the first capacitor and the second capacitor; the signal line; A substrate characterized by:

6. a semiconductor integrated circuit according to claim 3 or 4; one of the pull-up resistor and the pull-down resistor; any one of the first capacitor, the second capacitor, and the third capacitor; the signal line; A substrate characterized by:

7. An electronic device comprising the substrate according to claim 5 or 6.

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