Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device which can increase an output while achieving a superior high-frequency characteristic, and a manufacturing method thereof.SOLUTION: A semiconductor device comprises: a substrate; a channel layer provided on the substrate and containing Ga and N; and a barrier layer provided on the channel layer, having a first face on a side of the channel layer, and a second face on a side opposite to the first face, and containing at least one of Al, Ga and In, and N. In the semiconductor device, the average value of Al composition in the barrier layer is 30% or more. In a profile of the Al composition in the barrier layer, the tilt of a first straight line that connects between a first point where the Al composition first reaches 10% in a direction from the first face toward the second face and a second point where the Al composition first reaches 30% in the direction from the first face toward the second face is 20% / nm or more and 65% / nm or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] There has been a demand for high-power and high-frequency characteristics improvements in high-electron mobility transistors (HEMTs) with channel and barrier layers. For example, output can be improved by increasing the Al composition in the barrier layer. A method for forming a heterostructure has also been proposed, which involves temporarily stopping the supply of Ga precursors while supplying only Al precursors into a deposition chamber during barrier layer formation. The precursor here refers to a substance in a stage before a substance is produced, such as through a chemical reaction. The Al composition refers to the ratio of the number of Al atoms to the total number of atoms of Group III elements contained in a III-V semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 155794 Summary of the Invention [Problem to be solved by the invention]

[0004] The inventors of the present application investigated a method for forming a barrier layer with a high Al composition, which includes a step of temporarily stopping the supply of the Ga precursor and supplying only the Al precursor into the deposition chamber. However, it became clear that this method could not simultaneously achieve high output power and improved high-frequency characteristics of the HEMT.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve output while obtaining excellent high-frequency characteristics. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a substrate, a channel layer provided on the substrate and containing Ga and N, and a barrier layer provided on the channel layer and having a first surface on the channel layer side and a second surface opposite to the first surface, the barrier layer containing Al, at least one of Ga and In, and N, wherein the average Al composition in the barrier layer is 30% or more, and in an Al composition profile in the barrier layer, the gradient of a first line connecting a first point at which the Al composition first reaches 10% from the first surface toward the second surface and a second point at which the Al composition first reaches 30% from the first surface toward the second surface is 20% or more and 65% / nm or less. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to improve the output of a HEMT while obtaining excellent high-frequency characteristics. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of an Al composition profile in the barrier layer. [Figure 3] FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9]FIG. 9 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a timing chart showing a method for forming a barrier layer. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a diagram showing the Al composition profile in the barrier layer of sample No. 2. [Figure 14] FIG. 14 shows the Al composition profile in the barrier layer of sample No. 3. [Figure 15] FIG. 15 is a diagram showing the Al composition profile in the barrier layer of sample No. 4. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a substrate; a channel layer provided on the substrate and containing Ga and N; and a barrier layer provided on the channel layer and having a first surface on the channel layer side and a second surface opposite to the first surface, the barrier layer containing Al, at least one of Ga and In, and N, wherein an average Al composition in the barrier layer is 30% or more, and in an Al composition profile in the barrier layer, the first line connecting a first point at which the Al composition first reaches 10% moving from the first surface to the second surface and a second point at which the Al composition first reaches 30% moving from the first surface to the second surface has a slope of 20% / nm or more and 65% / nm or less.

[0011] The average Al composition in the barrier layer is 30% or more, resulting in high output. Furthermore, the gradient of the first line in the Al composition profile in the barrier layer is 20% / nm or more and 65% / nm or less, meaning that two-dimensional electron gas (2DEG) generated near the barrier layer in the channel layer is less likely to migrate to the barrier layer. This results in high electron mobility and excellent high-frequency characteristics.

[0012] [2] In [1], in the Al composition profile, a second line connecting the first point and a third point where the Al composition reaches 40% for the first time from the first surface toward the second surface may have a gradient of 20% / nm or more and 65% / nm or less. In this case, migration of 2DEG to the barrier layer can be further suppressed.

[0013] [3] In [1] or [2], the channel layer may be a GaN layer, and the barrier layer may be an AlGaN layer, an InAlN layer, or an InAlGaN layer. In this case, the channel layer and the barrier layer are easily formed.

[0014] [4] In any of [1] to [3], the average Al composition in the barrier layer may be 35% or more, which makes it easier to improve output.

[0015] [5] In any of [1] to [4], the channel layer has a third surface on the barrier layer side, and the channel layer constitutes the third surface, and the concentration of C is 1×10 16 cm -3 The following first layer may be included: In this case, scattering of electrons in the channel layer can be made less likely to occur, and better electron mobility can be obtained.

[0016] [6] A method for manufacturing a semiconductor device according to another embodiment of the present disclosure includes the steps of: forming a channel layer containing Ga and N on a substrate; and forming a barrier layer on the channel layer, the barrier layer having a first surface on the channel layer side and a second surface opposite to the first surface, the barrier layer containing Al, at least one of Ga and In, and N; wherein an average Al composition in the barrier layer is 30% or more; and in an Al composition profile in the barrier layer, the gradient of a first line connecting a first point at which the Al composition first reaches 10% from the first surface toward the second surface and a second point at which the Al composition first reaches 30% from the first surface toward the second surface is 20% / nm or more and 65% / nm or less.

[0017] By setting the average Al composition in the barrier layer to 30% or more, high output can be obtained. Also, by setting the slope of the first line in the Al composition profile in the barrier layer to 20% / nm or more and 65% / nm or less, it is possible to make it difficult for the 2DEG to move to the barrier layer. This results in high electron mobility and excellent high-frequency characteristics.

[0018] [7] In [6], the step of forming the barrier layer includes the steps of: under first conditions, supplying ammonia and an Al precursor into a deposition chamber for a time insufficient to form a single layer, without supplying a Ga precursor and an In precursor, and under second conditions, supplying ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor into the deposition chamber to form a first semiconductor layer on the channel layer; and under third conditions, supplying ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor into the deposition chamber to form a second semiconductor layer on the first semiconductor layer, wherein a first pressure in the deposition chamber under the first conditions and a second pressure in the deposition chamber under the second conditions may be higher than a third pressure in the deposition chamber under the third conditions, or a first flow rate of ammonia under the first conditions and a second flow rate of ammonia under the second conditions may be higher than a third flow rate of ammonia under the third conditions. In this case, it is easy to set the gradient of the first straight line L1 to 20% / nm or more and 65% / nm or less.

[0019] [8] In [7], the first pressure may be equal to the second pressure, and the first flow rate may be equal to the second flow rate. In this case, the second pressure and the second flow rate can be easily adjusted.

[0020] [9] In [7] or [8], the second pressure and the third pressure may be equal, and the third flow rate may be smaller than the second flow rate. In this case, good crystallinity is easily obtained in the second semiconductor layer.

[0021]

[10] In any of [7] to [9], under the second condition, when ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor are supplied into the deposition chamber, the flow rates of the ammonia, the Al precursor, and at least one of a Ga precursor and an In precursor may be adjusted so that the Al composition in the first semiconductor layer is 30% or less, and under the third condition, when ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor are supplied into the deposition chamber, the flow rates of the ammonia, the Al precursor, and at least one of a Ga precursor and an In precursor may be adjusted so that the Al composition in the second semiconductor layer is more than 30%. In this case, it is easy to obtain excellent high-frequency characteristics while obtaining a high output.

[0022]

[11] In any of [7] to

[10] , the supply under the second condition may be performed for a time period during which the thickness of the first semiconductor layer is 0.5 nm or more and 3.0 nm or less, which makes it easier to obtain high output and excellent high-frequency characteristics.

[0023]

[12] In

[11] , the supply under the second condition may be performed for a time period during which the thickness of the first semiconductor layer is 0.5 nm or more and 1.5 nm or less. In this case, even better high-frequency characteristics are likely to be obtained.

[0024]

[13] In any of [6] to

[12] , the channel layer has a third surface on the barrier layer side, and the step of forming the channel layer includes forming the third surface and forming a C concentration of 1×10 16 cm -3The following step of forming the first layer may be included. In this case, it is easy to obtain even higher electron mobility.

[0025] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0026] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based HEMT. Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0027] 1, the semiconductor device 1 according to the first embodiment includes a substrate 10 and a stacked structure 20. The substrate 10 is, for example, a SiC substrate having a (0001) plane, and the stacking direction of the stacked structure 20 is, for example, the

[0001] direction. The stacked structure 20 is provided on the substrate 10. The stacked structure 20 includes a nucleation layer 12, a channel layer 14, a barrier layer 16, and a cap layer 18.

[0028] The nucleation layer 12 is formed on the substrate 10. For example, the nucleation layer 12 is an AlN layer, and the thickness of the nucleation layer 12 is 5 nm to 20 nm. The nucleation layer 12 functions as a seed layer for the channel layer 14.

[0029] The channel layer 14 is formed on the nucleation layer 12 by epitaxial growth. The channel layer 14 contains Ga and N. For example, the channel layer 14 is an undoped GaN layer, and the thickness of the channel layer 14 is 500 nm. The channel layer 14 functions as an electron transit layer.

[0030] The barrier layer 16 is formed on the channel layer 14 by epitaxial growth. The barrier layer 16 contains Al, at least one of Ga and In, and N. For example, the barrier layer 16 is Al X Ga1-X N layer (0.00≦X≦1.00), In 1-X Al X N layer (0.00≦X≦1.00) or In Y Al X Ga (1-X-Y) The barrier layer 16 is an N layer (0.00≦X≦1.00, 0.00≦Y≦1.00), and the thickness of the barrier layer 16 is 5 nm to 30 nm. The band gap of the barrier layer 16 is larger than that of the channel layer 14. The average value of the Al composition (X) in the barrier layer is 30% or more (X≧0.30). The conductivity type of the barrier layer 16 is n-type or undoped. The barrier layer 16 and the channel layer 14 may be in contact with each other, or a spacer layer (not shown) may be interposed between the barrier layer 16 and the channel layer 14. Strain occurs between the barrier layer 16 and the channel layer 14 due to the difference in lattice constants between them. As a result, a 2DEG due to piezoelectric charges is generated in a region on the channel layer 14 side near the interface between the barrier layer 16 and the channel layer 14, forming a channel region. The barrier layer 16 functions as an electron supply layer.

[0031] The cap layer 18 is formed on the barrier layer 16 by epitaxial growth. For example, the cap layer 18 is a GaN layer, and the thickness of the cap layer 18 is 5 nm. For example, the conductivity type of the cap layer 18 is n-type. Note that the cap layer 18 does not necessarily have to be provided.

[0032] The semiconductor device 1 has a passivation film 26. For example, the passivation film is a nitride film such as a silicon nitride film, and the thickness of the passivation film 26 is 10 nm to 100 nm. A source opening 26S, a drain opening 26D, and a gate opening 26G are formed in the passivation film 26. The stacked structure 20 is exposed from the passivation film 26 in the source opening 26S, the drain opening 26D, and the gate opening 26G. Specifically, the cap layer 18 is removed in the source opening 26S and the drain opening 26D, exposing the barrier layer 16. The cap layer 18 is exposed in the gate opening 26G.

[0033] The semiconductor device 1 has a source electrode 22, a drain electrode 24, and a gate electrode 28. The source electrode 22 and the drain electrode 24 are arranged in order along the surface of the substrate 10.

[0034] The source electrode 22 covers a source opening 26S of the passivation film 26 and is in ohmic contact with the barrier layer 16 via the source opening 26S. The drain electrode 24 covers a drain opening 26D of the passivation film 26 and is in ohmic contact with the barrier layer 16 via the drain opening 26D. The source electrode 22 and the drain electrode 24 are formed by heat treating a titanium (Ti) layer and an aluminum (Al) layer provided in this order from the stacked structure 20 side.

[0035] The gate electrode 28 is provided on the stacked structure 20 between the source electrode 22 and the drain electrode 24. The gate electrode 28 covers the gate opening 26G of the passivation film 26 and is in Schottky contact with the cap layer 18 via the gate opening 26G. The gate electrode 28 has, for example, a nickel (Ni) layer, a gold (Au) layer, and a tantalum (Ta) layer provided in this order from the stacked structure 20 side.

[0036] The semiconductor device 1 has an insulating film 30 that covers the source electrode 22, the gate electrode 28, and the drain electrode 24. The insulating film 30 is in contact with and continuous with the passivation film 26. The insulating film 30 is made of an insulating material containing Si, and is, for example, a SiN film, a SiO2 film, or a SiON film.

[0037] Here, the Al composition profile in the barrier layer 16 will be described. FIG. 2 is a diagram showing an example of the Al composition profile in the barrier layer 16. The horizontal axis in FIG. 2 represents the distance from the first surface toward the second surface. The vertical axis in FIG. 2 represents the Al composition. The barrier layer 16 has a first surface 16A on the channel layer 14 side and a second surface 16B opposite the first surface 16A. In the Al composition profile in the barrier layer 16, a first line L1 connecting a first point 41, which is the first point reached at 10% (X=0.10) from the first surface 16A toward the second surface 16B, and a second point 42, which is the first point reached at 30% (X=0.30) from the first surface 16A toward the second surface 16B, has a slope of 20% / nm or more and 65% / nm or less.

[0038] In the semiconductor device 1 according to the first embodiment, the average Al composition in the barrier layer 16 is 30% or more (X≧0.30). Therefore, a high output can be obtained. Furthermore, in the Al composition profile in the barrier layer 16, the slope of the first line L1 is 20% / nm or more and 65% / nm or less. Therefore, the 2DEG generated in the channel layer 14 near the barrier layer 16 is less likely to migrate to the barrier layer 16. Because electrons are more likely to scatter in the barrier layer 16 than in the channel layer 14, the migration of the 2DEG to the barrier layer 16 reduces the electron mobility. According to this embodiment, the migration of the 2DEG to the barrier layer 16 can be suppressed, resulting in high electron mobility and excellent high-frequency characteristics of the HEMT. Thus, according to the first embodiment, the output of the HEMT can be improved while maintaining excellent high-frequency characteristics.

[0039] The Al composition profile in the barrier layer 16 can be obtained by energy dispersive X-ray spectroscopy (EDX). The measurement interval in the thickness direction of the barrier layer 16 is 0.155 nm. Because the channel layer 14 does not contain Al, the first point 41 and the second point 42 can be identified without strictly identifying the interface (first surface 16A) between the channel layer 14 and the barrier layer 16. The slope of the first line L1 is preferably 25% / nm or more and 65% / nm or less, more preferably 30% / nm or more and 65% / nm or less, and even more preferably 40% / nm or more and 65% / nm or less. The greater the slope of the first line L1, the higher the 2DEG concentration. However, it is difficult to make the slope of the first line L1 greater than 65% / nm. This is because Al inevitably diffuses from the barrier layer 16 to the channel layer 14.

[0040] In the Al composition profile in the barrier layer 16, the slope of the second line L2 connecting the first point 41 and the third point 43, which is the first point reaching 40% (X=0.40) from the first surface 16A toward the second surface 16B, is preferably 20% / nm or more and 65% / nm or less, more preferably 25% / nm or more and 65% / nm or less, and even more preferably 30% / nm or more and 65% / nm or less. The greater the slope of the second line L2, the higher the 2DEG concentration. However, it is difficult to make the slope of the second line L2 exceed 65% / nm. This is because, as described above, Al inevitably diffuses from the barrier layer 16 to the channel layer 14.

[0041] In the first embodiment, the average Al composition in the barrier layer 16 is preferably 35% or more (X≧0.35), more preferably 38% or more (X≧0.38), and even more preferably 40% or more (X≧0.40). The higher the average Al composition in the barrier layer 16, the easier it is to improve output. Here, the first surface 16A of the barrier layer 16 on the channel layer 14 side is assumed to be located at a position in the Al composition profile where the Al composition finally reaches 5% from the position where the Al composition in the barrier layer 16 is maximized toward the substrate 10. The second surface 16B on the opposite side of the barrier layer 16 is assumed to be located at a position in the Al composition profile where the Al composition finally reaches 5% from the position where the Al composition in the barrier layer 16 is maximized toward the opposite side of the substrate 10. The average Al composition in the barrier layer 16 is the average value of the Al composition between the first surface 16A and the second surface 16B thus determined.

[0042] When the channel layer 14 is a GaN layer and the barrier layer 16 is an AlGaN layer, an InAlN layer, or an InAlGaN layer, the channel layer 14 and the barrier layer 16 are easily formed.

[0043] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. Figures 3 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. In the following description, an AlGaN layer is formed as the barrier layer 16. When an InAlN layer is formed as the barrier layer 16, an In precursor, for example, TMI (trimethylindium), may be used instead of a Ga precursor, and when an InAlGaN layer is formed as the barrier layer 16, an In precursor may be used in addition to a Ga precursor.

[0044] First, as shown in FIG. 3, a stacked structure 20 including a plurality of nitride semiconductor layers is formed on a substrate 10 by metal organic chemical vapor deposition (MOCVD).

[0045] Specifically, first, the nucleation layer 12 is grown on the substrate 10. When the nucleation layer 12 is an AlN layer, the source gases are, for example, TMA (trimethylaluminum) and NH3 (ammonia). TMA is an example of an Al precursor.

[0046] Next, the channel layer 14 is grown on the nucleation layer 12. When the channel layer 14 is a GaN layer, the source gas is, for example, TMG (trimethylgallium) and NH3. TMG is an example of a Ga precursor. At this time, for example, the temperature of the substrate 10 is set to 1015°C, and the pressure in the film formation chamber is set to 100 Torr (1.33 × 10 2 Pa) and the growth rate is 250 pm / s.

[0047] Next, the barrier layer 16 is grown on the channel layer 14. When the barrier layer 16 is an AlGaN layer, the source gases are, for example, TMA, TMG, and NH. Here, a method for forming the barrier layer 16 will be described in detail. Figure 11 is a timing chart showing the method for forming the barrier layer 16.

[0048] When forming the barrier layer 16, first, as a first condition, from time t0 to time t1, NH3 and TMA are supplied into the deposition chamber without supplying TMG for a time insufficient to form a monolayer, for example, 6 seconds. At this time, for example, the temperature of the substrate 10 is 1035°C, the pressure in the deposition chamber is 100 Torr, the flow rate of TMA is 120 sccm, and the flow rate of NH3 is 20,000 sccm. Calculations show that the thickness of the film formed when the precursors are supplied for 6 seconds is 0.25 nm, and although island-like deposits may form, a monolayer is not formed.

[0049] Next, from time t1 to time t2, as a second condition, TMG is supplied into the deposition chamber while continuing to supply NH3 and TMA, to form a first semiconductor layer 71 on the channel layer 14 (see FIG. 3). At this time, for example, the temperature of the substrate 10 is 1035°C, the pressure in the deposition chamber is 100 Torr, the flow rates of TMA, TMG, and NH3 are 120 sccm, 25 sccm, and 20,000 sccm. The flow rates of NH3, TMA, and TMG are adjusted so that the Al composition in the first semiconductor layer 71 is, for example, 30% or less (X≦0.30). This is because it is easy to form the first semiconductor layer 71 while maintaining the deposits that formed on the surface of the channel layer 14 from time t0 to time t1.

[0050] Next, from time t2 to time t3, while continuing to supply NH3, the supply of TMA and TMG is temporarily stopped and the set value of the NH3 flow rate of the film forming apparatus is changed to 8800 sccm, resulting in a decrease in the NH3 flow rate to 8800 sccm.

[0051] Subsequently, from time t3 to time t4, as a third condition, the supply of TMA and TMG into the deposition chamber is resumed while the supply of NH3 is continued at a reduced flow rate, thereby forming a second semiconductor layer 72 on the first semiconductor layer 71 (see FIG. 3). At this time, for example, the temperature of the substrate 10 is 1035°C, the pressure in the deposition chamber is 100 Torr, the flow rates of TMA, TMG, and NH3 are 90 sccm, 20 sccm, and 8800 sccm. The flow rates of NH3, TMA, and TMG are adjusted so that the Al composition in the second semiconductor layer 72 is, for example, greater than 30% (X>0.30). The flow rates of NH3, TMA, and TMG are adjusted so that the Al composition in the second semiconductor layer 72 is preferably greater than 35% (X>0.35), more preferably greater than 38% (X>0.38), and even more preferably greater than 40% (X>0.40). This is to obtain high output from the HEMT.

[0052] In this way, the barrier layer 16 having the Al composition profile shown in FIG. 2 is formed.

[0053] After the barrier layer 16 is formed, a cap layer 18 is formed on the barrier layer 16. When the cap layer 18 is a GaN layer, the source gases are, for example, TMG and NH3.

[0054] Next, as shown in FIG. 4, a passivation film 26 in contact with the upper surface of the stacked structure 20 is formed using low-pressure CVD or plasma CVD. For example, when low-pressure CVD is used, the film formation temperature is 600°C to 850°C, and the growth pressure is, for example, 10 Pa to 50 Pa. The passivation film 26 formed by low-pressure CVD is denser and harder than when formed by plasma CVD. After forming a portion (lower layer) of the passivation film 26 by low-pressure CVD, the remaining portion (upper layer) of the passivation film 26 may be formed by plasma CVD. When forming the passivation film 26 by low-pressure CVD, ammonia gas and dichlorosilane (SiH2Cl2) are used as raw material gases.

[0055] 5, photoresist 52 and photoresist 54 are applied in this order on the passivation film 26. For example, the material of the photoresist 54 is polymethylglutarimide (PMGI), and the photoresist 54 is an i-line resist. Next, by photolithography, an opening 54S for the source and an opening 54D for the drain are formed in the photoresist 54, and an opening 52S for the source and an opening 52D for the drain are formed in the photoresist 52. A portion of the passivation film 26 is exposed through the openings 54S and 52S, and another portion of the passivation film 26 is exposed through the openings 54D and 52D.

[0056] 6, using the photoresists 52 and 54 as masks, reactive ion etching (RIE) is performed to form a source opening 26S and a drain opening 26D in the passivation film 26 and the stacked structure 20. For example, a reactive gas containing fluorine (F) is used to etch the passivation film 26, and a reactive gas containing chlorine (Cl) is used to etch the stacked structure 20.

[0057] Next, as shown in FIG. 7, a metal layer 62 is formed by vapor deposition inside the source opening 26S and the drain opening 26D. The metal layer 62 is formed so as to protrude upward from the source opening 26S and the drain opening 26D. The metal layer 62 also adheres to the upper surface of the photoresist 54 and the sidewall surfaces of the opening 54S and the opening 54D. The metal layer 62 includes, for example, a Ti layer and an Al layer formed in this order from the substrate 10 side. For example, the Ti layer has a thickness of 30 nm, and the Al layer has a thickness of 300 nm.

[0058] Next, as shown in FIG. 8, the photoresists 52 and 54 are removed. As the photoresist 54 is removed, the portion of the metal layer 62 that is attached to the photoresist 54 is also removed. Meanwhile, the metal layer 62 remains inside the source opening 26S and the drain opening 26D. In other words, lift-off is performed. As a result, the source electrode 22 is formed in the source opening 26S, and the drain electrode 24 is formed in the drain opening 26D.

[0059] Next, the source electrode 22 and the drain electrode 24 are alloyed by heat treatment. The alloying temperature is, for example, 600° C. As a result, the source opening 26S and the drain electrode 24 come into ohmic contact with the stacked structure 20.

[0060] Next, as shown in FIG. 9, a gate opening 26G is formed in the passivation film 26. To form the gate opening 26G, a resist mask having an opening corresponding to the gate opening 26G is formed on the passivation film 26, and the passivation film 26 is etched through the resist mask. For example, a reactive gas containing fluorine is used to etch the passivation film 26. Thereafter, the resist mask is removed. Next, a gate electrode 28 is formed in Schottky contact with the stacked structure 20 through the gate opening 26G. The gate electrode 28 includes, for example, a Ni layer, an Au layer, and a Ta layer, which are formed in this order from the substrate 10 side.

[0061] 10, an insulating film 30 that covers the gate electrode 28 is formed on the passivation film 26. The insulating film 30 is formed by, for example, a plasma CVD method.

[0062] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 1 according to the first embodiment can be manufactured.

[0063] In this manufacturing method, when forming the barrier layer 16, TMG is not supplied into the deposition chamber from time t0 to time t1, and NH3 and TMA are supplied for a time insufficient to form a single layer. This makes it easy to set the slope of the first line L1 to 20% / nm or more and 65% / nm or less. If the second semiconductor layer 72 is formed after time t1 without forming the first semiconductor layer 71, the surface condition of the channel layer 14 is likely to change in the early stages of formation of the second semiconductor layer 72, and the crystallinity of the second semiconductor layer 72 is likely to deteriorate. In contrast, by forming the first semiconductor layer 71 before forming the second semiconductor layer 72, the first semiconductor layer 71 with good crystallinity can be formed without changing the surface condition of the channel layer 14, and the second semiconductor layer 72 with good crystallinity can be formed on the first semiconductor layer 71. Therefore, a barrier layer 16 with good crystallinity can be formed, including the first semiconductor layer 71 and the second semiconductor layer 72.

[0064] The first pressure, second pressure, third pressure, first flow rate, second flow rate, and third flow rate are not particularly limited as long as the first pressure and second pressure are higher than the third pressure or the first flow rate and second flow rate are higher than the third flow rate. However, from the viewpoint of ease of adjustment, it is preferable that the first pressure and the second pressure are equal and the first flow rate and the second flow rate are equal. It is also preferable that the second pressure and the third pressure are equal and the third flow rate is smaller than the second flow rate. This is because it is easier to obtain good crystallinity in the second semiconductor layer 72.

[0065] The supply under the second condition is performed for a time period during which the thickness of the first semiconductor layer 71 becomes preferably 0.5 nm or more and 3.0 nm or less, and more preferably 0.5 nm or more and 1.5 nm or less. If the first semiconductor layer 71 is too thick, the slope of the second line L2 becomes small, which may cause the 2DEG to easily move to the barrier layer 16. If the first semiconductor layer 71 is too thin, the surface state of the channel layer 14 may easily change in the early stages of forming the second semiconductor layer 72.

[0066] The source opening 26S and the drain opening 26D may be formed in the passivation film 26, and the source opening 26S and the drain opening 26D may not be formed in the stacked structure 20.

[0067] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the channel layer. Fig. 12 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0068] 12, in the semiconductor device 2 according to the second embodiment, the channel layer 14 has a third surface 14A on the barrier layer 16 side, and the channel layer 14 has a first layer 61 that forms the third surface 14A. The concentration of C in the first layer 61 is 1×10 16 cm -3 The thickness of the first layer 61 is, for example, 50 nm or more and 150 nm or less, preferably 60 nm or more and 140 nm or less, more preferably 70 nm or more and 130 nm or less, and even more preferably 80 nm or more and 120 nm or less. The C concentration in the portion of the channel layer 14 closer to the substrate 10 than the first layer 61 is 1×10 16 cm -3 It may be super.

[0069] The other configurations are the same as those in the first embodiment.

[0070] The second embodiment also provides the same effects as the first embodiment. Furthermore, since the channel layer 14 has the first layer 61, scattering of electrons in the channel layer 14 can be made less likely to occur. Therefore, better electron mobility can be obtained.

[0071] Next, a method for manufacturing the semiconductor device 2 according to the second embodiment will be described. When manufacturing the semiconductor device 2, for example, the temperature and growth rate of the substrate 10 are changed during the formation of the channel layer 14. In the initial stage, as in the first embodiment, the temperature of the substrate 10 is set to 1015°C, the pressure in the film formation chamber is set to 100 Torr, and the growth rate is set to 250 pm / s. Thereafter, the temperature of the substrate 10 is set to 1035°C, the pressure in the film formation chamber remains at 100 Torr, and the growth rate is set to 100 pm / s. In this way, the temperature of the substrate 10 is increased and the growth rate is decreased.

[0072] Other configurations are the same as those of the first embodiment. In this manner, the semiconductor device 2 according to the second embodiment can be manufactured.

[0073] The entire channel layer 14 may be the first layer 61, but in that case, it takes a longer time to form the channel layer 14, and the throughput decreases.

[0074] Here, we will explain the measurement results of the characteristics of semiconductor devices manufactured by the present inventors according to the first and second embodiments. Table 1 shows the conditions for forming the barrier layer. The thicknesses in Table 1 are thicknesses converted from the film formation time, and the Al compositions are compositions converted from the flow rates of the source gases. Also, the "First layer 61 present" in the remarks column for sample No. 5 indicates that the channel layer contains a layer equivalent to the first layer 61 of the second embodiment, with a thickness of 100 nm.

[0075] [Table 1]

[0076] The other conditions for the five types of samples (samples No. 1 to No. 5) are the same. For each sample, the electron density Ns (cm-2 ), mobility μ(cm 2 The SiO2 / Vs and sheet resistance Rsh (Ω / □) were measured by Hall spectroscopy at room temperature. The results are shown in Table 2. Furthermore, for samples No. 2 to No. 4, the Al composition profile in the barrier layer was measured by EDX. FIG. 13 shows the Al composition profile in the barrier layer of sample No. 2. FIG. 14 shows the Al composition profile in the barrier layer of sample No. 3. FIG. 15 shows the Al composition profile in the barrier layer of sample No. 4. The horizontal axes in FIGS. 13 to 15 represent the distance from the first surface to the second surface. The vertical axes in FIGS. 13 to 15 represent the Al composition and the Ga composition. Table 2 also shows the slopes of the first line L1 and the second line L2 obtained from FIGS. 13 to 15. The Ga composition refers to the ratio of the number of Ga atoms to the total number of atoms of group III elements contained in the III-V semiconductor.

[0077] [Table 2]

[0078] 13 to 15, high mobility μ was obtained in Samples No. 3 to No. 5. This indicates that good high frequency characteristics of HEMT can be obtained in Samples No. 3 to No. 5.

[0079] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0080] 1, 2: Semiconductor device 10: Circuit board 12: Nucleation layer 14: Channel layer 14A: Third Side 16: Barrier layer 16A: 1st page 16B: 2nd side 18: Cap layer 20:Laminated structure 22: Source electrode 24: Drain electrode 26: Passivation film 26D: Drain opening 26G: Gate opening 26S: Source opening 28: Gate electrode 30: insulating film 41:1st point 42:Second point 43: 3rd point 52, 54: Photoresist 52D, 52S, 54D, 54S: Opening 61: 1st layer 62: Metal layer 71: First semiconductor layer 72: Second semiconductor layer L1: 1st straight line L2: Second straight line

Claims

1. A substrate; a channel layer provided on the substrate and containing Ga and N; a barrier layer provided on the channel layer, the barrier layer having a first surface on the channel layer side and a second surface opposite to the first surface, the barrier layer including Al, at least one of Ga and In, and N; and the average Al composition in the barrier layer is 30% or more; a first line connecting a first point at which the Al composition first reaches 10% from the first surface toward the second surface and a second point at which the Al composition first reaches 30% from the first surface toward the second surface in an Al composition profile in the barrier layer, the first line having a slope of 20% / nm or more and 65% / nm or less.

2. 2. The semiconductor device according to claim 1, wherein in the Al composition profile, a second line connecting the first point and a third point at which the Al composition first reaches 40% from the first surface toward the second surface has a gradient of 20% / nm or more and 65% / nm or less.

3. the channel layer is a GaN layer; 3. The semiconductor device according to claim 1, wherein the barrier layer is an AlGaN layer, an InAlN layer, or an InAlGaN layer.

4. 4. The semiconductor device according to claim 1, wherein an average value of the Al composition in the barrier layer is 35% or more.

5. the channel layer has a third surface on the barrier layer side; The channel layer constitutes the third surface, and the concentration of C is 1×10 １６ cm －３ 5. The semiconductor device according to claim 1, further comprising a first layer:

6. forming a channel layer containing Ga and N on a substrate; forming a barrier layer on the channel layer, the barrier layer having a first surface on the channel layer side and a second surface opposite to the first surface, the barrier layer containing Al, at least one of Ga and In, and N; and the average Al composition in the barrier layer is 30% or more; a first line connecting a first point at which the Al composition first reaches 10% from the first surface toward the second surface and a second point at which the Al composition first reaches 30% from the first surface toward the second surface in an Al composition profile in the barrier layer, the first line having a slope of 20% / nm or more and 65% / nm or less.

7. The step of forming the barrier layer includes: supplying ammonia and an Al precursor into a deposition chamber under a first condition, without supplying a Ga precursor and an In precursor, for a time insufficient to form a single layer; supplying ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor into the deposition chamber under second conditions to form a first semiconductor layer on the channel layer; supplying ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor into the deposition chamber under third conditions to form a second semiconductor layer on the first semiconductor layer; and 7. The method for manufacturing a semiconductor device according to claim 6, wherein at least one of a first pressure in the film formation chamber under the first condition and a second pressure in the film formation chamber under the second condition is higher than a third pressure in the film formation chamber under the third condition, and a first flow rate of ammonia under the first condition and a second flow rate of ammonia under the second condition is higher than a third flow rate of ammonia under the third condition.

8. the first pressure and the second pressure are equal; 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first flow rate is equal to the second flow rate.

9. the second pressure and the third pressure are equal; 9. The method for manufacturing a semiconductor device according to claim 7, wherein the third flow rate is smaller than the second flow rate.

10. under the second condition, when ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor are supplied into the film formation chamber, the flow rates of the ammonia, the Al precursor, and at least one of a Ga precursor and an In precursor are adjusted so that the Al composition in the first semiconductor layer is 30% or less; 10. The method for manufacturing a semiconductor device according to claim 7, wherein when ammonia, an Al precursor, and at least one of a Ga precursor and an In precursor are supplied into the film formation chamber under the third condition, flow rates of the ammonia, the Al precursor, and at least one of a Ga precursor and an In precursor are adjusted so that an Al composition in the second semiconductor layer is more than 30%.

11. 11. The method for manufacturing a semiconductor device according to claim 7, wherein the supply under the second condition is performed for a time period during which the thickness of the first semiconductor layer becomes 0.5 nm or more and 3.0 nm or less.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the supply under the second condition is performed for a time period during which the thickness of the first semiconductor layer becomes 0.5 nm or more and 1.5 nm or less.

13. the channel layer has a third surface on the barrier layer side; The step of forming the channel layer includes forming the third surface and forming a C layer having a concentration of 1×10 １６ cm －３ 13. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of forming a first layer as follows:

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