Design program, design method, and design device

Abstract

To shorten a design period in hierarchical design.SOLUTION: A processing part 12 reads the highest hierarchy design information 11a from a storage part 11, divides the highest hierarchy into a plurality of division regions (division regions 15a to 17a, or the like) on the basis of the highest hierarchy design information 11a, detects overlapping regions (optimum arrangement regions 15c to 17c) where all division regions existing at a corresponding position overlap between instances 15 and 16 when instances 15 to 17 of the lowest hierarchy included in the highest hierarchy are overlapped, sets a temporary arrangement position for temporarily arranging an inspection cell to be used for inspection of manufacturing variation of minimum line width in the overlapping region of each of the instances 15 to 17, and outputs information showing the overlapping region and the temporary arrangement position.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a design program, a design method, and a design apparatus. [Background technology]

[0002] As semiconductor integrated circuits continue to become increasingly miniaturized, one method for improving manufacturing variations in critical dimensions (CD) is to monitor variations in the manufacturing process on a die (hereinafter referred to as a chip).

[0003] Specifically, a structure called a TCD (Test-Key Critical Dimension) structure, which has a bulk layer and a metal layer inside, is placed on a chip, and by checking the finished product, it becomes possible to monitor fluctuations in the manufacturing process. The bulk layer is the layer where elements such as transistors, capacitors, and resistors are patterned on the semiconductor substrate during the substrate process. The metal layer is the layer where the wiring connected to each of the above elements is formed during the wiring process. The TCD structure is built into a dedicated cell called a TCD cell.

[0004] The placement rules of the DRC (Design Rule Check) stipulate that tape-out requires that TCD cells be placed in a specified percentage or more of the multiple divided areas (also called check windows) obtained by dividing the entire chip at regular intervals. Note that there are cases where the placement of TCD cells is invalid depending on the placement location (see Figure 2 below).

[0005] In the design of large-scale semiconductor integrated circuits, hierarchical design is generally performed (see, for example, Patent Document 1). TCD cells are placed in a site area, an area for cell placement that takes power supply into consideration. When hierarchical design is performed, the site area exists in the lowest layer. In other words, TCD cells are placed in the lowest layer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-203906 Summary of the Invention [Problem to be solved by the invention]

[0007] Verification based on DRC placement rules is performed at the top level. Therefore, if there are many invalid TCD cells, or if the TCD cells are not placed at the specified ratio in multiple divided areas, they are rearranged at the bottom level, assembled at the top level, and then re-verified at the top level. This can sometimes extend the design period.

[0008] In one aspect, the present invention aims to provide a design program, a design method, and a design device that can shorten the design period in hierarchical design. [Means for solving the problem]

[0009] In one embodiment, there is provided a design program that causes a computer to execute a process for performing hierarchical design, the design program reading first design information for a top layer from a storage unit, dividing the top layer into a plurality of divided areas based on the first design information, detecting overlapping areas where all divided areas at corresponding positions between a plurality of instances of a bottom layer included in the top layer overlap when the instances are overlapped, setting temporary placement positions for the overlapping areas of each of the plurality of instances to temporarily place inspection cells used to inspect manufacturing variations in minimum line widths, and outputting information indicating the overlapping areas and the temporary placement positions.

[0010] Also, in one embodiment, a design method is provided. Also, in one embodiment, a design device is provided. [Effects of the Invention]

[0011] In one aspect, the present invention can shorten the design period in hierarchical design. [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates an example of a design apparatus and a design method according to a first embodiment; [Figure 2] FIG. 10 is a diagram for explaining an example of verification of the placement rules of TCD cells. [Figure 3] FIG. 1 is a diagram illustrating an overview of a hierarchical design. [Figure 4] 10 is a flowchart showing the flow of a TCD cell placement process when determining a placement area for a TCD cell and placing the TCD cell in the lowest layer. [Figure 5] FIG. 10 is a diagram illustrating an example of a case where a verification error occurs. [Figure 6] 10A and 10B are diagrams illustrating examples of cases in which excessive placement occurs and cases in which excessive placement does not occur. [Figure 7] 10 is a flowchart showing a flow of an example of a placement process of a TCD cell by the design device of the first embodiment. [Figure 8] FIG. 2 is a block diagram illustrating an example of hardware of the design apparatus. [Figure 9] FIG. 2 is a block diagram illustrating an example of functions of the design apparatus. [Figure 10] FIG. 10 is a diagram showing an outline of a flow of a placement process of a TCD cell by the design device according to the second embodiment. [Figure 11] FIG. 10 is a diagram illustrating an example of setting information on the highest layer side. [Figure 12] FIG. 10 is a diagram illustrating an example of setting information on the lowest layer side. [Figure 13] FIG. 10 is a diagram illustrating an example of generating setting information using an interactive editor. [Figure 14] 10A and 10B are diagrams illustrating an example of a top layer setting screen and a bottom layer setting screen. [Figure 15] FIG. 10 is a diagram showing a first example of designation of a placement prohibition area using the interactive editor. [Figure 16] FIG. 10 is a diagram showing a second example of designating a placement prohibition area using the interactive editor. [Figure 17] FIG. 10 is a diagram showing a third example of designating a placement prohibition area using the interactive editor. [Figure 18] FIG. 10 is a diagram illustrating an example of creating a reserved area. [Figure 19] FIG. 10 is a diagram illustrating a design example of the lowest layer. [Figure 20] FIG. 10 is a diagram showing an example of generating a setting file including setting information on the lowest layer side using an interactive editor. [Figure 21] FIG. 10 is a diagram illustrating an example of check area information. [Figure 22] 10 is a flowchart showing the flow of an example of an automatic placement process of dummy TCD cells (part 1); [Figure 23] 10 is a flowchart showing the flow of an example of an automatic placement process of dummy TCD cells (part 2). [Figure 24] 10 is a flowchart showing the flow of an example of an automatic placement process of dummy TCD cells (part 3). [Figure 25] FIG. 10 is a diagram illustrating an example of a process for detecting an optimum placement area (part 1). [Figure 26] FIG. 10 is a diagram illustrating an example of the process of detecting an optimum placement area (part 2). [Figure 27] FIG. 10 is a diagram showing an example of the process of detecting an optimum placement area (part 3). [Figure 28] FIG. 10 is a diagram showing an example of the process of detecting an optimum placement area (part 4). [Figure 29] FIG. 10 is a diagram showing an example of the process of detecting an optimum placement area (part 5). [Figure 30] FIG. 10 is a diagram illustrating an example of a placement process of dummy TCD cells. [Figure 31] 10 is a flowchart showing the flow of an example of a process for placing dummy TCD cells using an interactive editor (part 1); [Figure 32] 10 is a flowchart showing the flow of an example of a process for placing dummy TCD cells using an interactive editor (part 2). [Figure 33] 10 is a flowchart showing the flow of an example of a process for placing dummy TCD cells using an interactive editor (part 3). [Figure 34] FIG. 10 is a diagram showing an example of a placement operation of a dummy TCD cell using an interactive editor. [Figure 35] FIG. 10 is a diagram illustrating an example of the deployment function of a dummy TCD cell. [Figure 36] 10 is a flowchart showing a flow of an example of automatic placement verification of dummy TCD cells (part 1); [Figure 37] 10 is a flowchart showing the flow of an example of automatic placement verification of dummy TCD cells (part 2); [Figure 38] FIG. 10 is a diagram illustrating an example of an output verification result. [Figure 39] 10 is a flowchart showing a flow of an example of placement verification of dummy TCD cells using an interactive editor. [Figure 40] FIG. 10 is a diagram showing an example of a display of verification results of placement verification using an interactive editor. [Figure 41] 10 is a flowchart showing the flow of an example of automatic placement processing of TCD cells in the lowest layer (part 1). [Figure 42] 10 is a flowchart showing the flow of an example of automatic placement processing of TCD cells in the lowest layer (part 2). [Figure 43] 10 is a flowchart showing the flow of an example of a TCD cell placement process using an interactive editor (part 1). [Figure 44] 10 is a flowchart showing the flow of an example of a TCD cell placement process using an interactive editor (part 2). [Figure 45] 10 is a flowchart showing the flow of an example of a TCD cell placement process using an interactive editor (part 3). [Figure 46] FIG. 10 is a diagram showing an example of a TCD cell placement operation using an interactive editor (part 1). [Figure 47] FIG. 10 is a diagram showing an example of a TCD cell placement operation using an interactive editor (part 2). [Figure 48] FIG. 10 is a diagram illustrating an example of a placement correction of a TCD cell. [Figure 49]10 is a flowchart showing a flow of an example of automatic placement verification of TCD cells. [Figure 50] FIG. 10 is a diagram illustrating an example of an output verification result. [Figure 51] 10 is a flowchart showing the flow of an example of TCD cell placement verification using an interactive editor. [Figure 52] FIG. 10 is a diagram showing an example of a display of verification results of placement verification using an interactive editor. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 illustrates an example of a design apparatus and a design method according to the first embodiment.

[0014] The design device 10 of the first embodiment performs hierarchical design. The design device 10 includes a storage unit 11 and a processing unit 12 . The storage unit 11 is, for example, a volatile storage device such as a RAM (Random Access Memory), or a non-volatile storage device such as an HDD (Hard Disk Drive) or a flash memory.

[0015] The storage unit 11 stores top-level hierarchical design information 11a and bottom-level hierarchical design information 11b. The top-level hierarchical design information 11a includes design information for the top level hierarchical layer that includes multiple instances of the bottom level hierarchical layer. The multiple instances of the bottom level hierarchical layer may include, for example, instances that are vertically or horizontally inverted relative to a given instance. The top level hierarchical layer may also include multiple instances of the bottom level hierarchical layer. The multiple bottom levels may, for example, have different sizes or different functions.

[0016] The lowest level hierarchical design information 11b includes design information for the lowest level hierarchical level used in the highest level hierarchical level, and may include design information for multiple lowest levels.

[0017] The top-level hierarchical design information 11a and the bottom-level hierarchical design information 11b may be generated by the design device 10 based on input from a designer, or may be generated by another design device, acquired by the design device 10, and stored in the storage unit 11.

[0018] The processing unit 12 can be realized by a hardware processor such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor). However, the processing unit 12 may also include electronic circuits such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The processor executes a program stored in a memory such as a RAM. For example, a design program is executed to cause the design device 10 to perform the following processes. A set of multiple processors may be referred to as a "multiprocessor" or simply as a "processor."

[0019] The processing unit 12 sets the provisional placement positions of the above-mentioned TCD cells, which are an example of inspection cells used to inspect manufacturing variations in minimum line widths, in the highest hierarchy. The temporary placement position is set, for example, as follows.

[0020] The processing unit 12 reads the top-level hierarchical design information 11a from the storage unit 11, and divides the top level into a plurality of divided areas based on the top-level hierarchical design information 11a. Then, when a plurality of instances of the lowest level hierarchical level (or the same lowest level if there are a plurality of lowest levels; the same applies below) included in the top level are overlapped, the processing unit 12 detects an overlapping area where all divided areas at corresponding positions among the plurality of instances overlap.

[0021] 1 shows multiple instances 15, 16, and 17 at the lowest level of the highest level. In the instances 15 to 17, the dashed lines indicate the boundaries of the divided areas when the highest level is divided. The number and size of the divided areas included in the instances 15 to 17 vary depending on the position and orientation of the instances in the highest level.

[0022] For example, instance 15 includes four divided areas including divided area 15a, instance 16 includes nine divided areas including divided area 16a, and instance 17 includes nine divided areas including divided area 17a.

[0023] In the instances 15 to 17, the diagonal line and the line perpendicular to the diagonal line are lines that represent the orientation of the instances 15 to 17. When detecting an overlapping area, the instances 15 to 17 extracted from the top layer are arranged in the same orientation (without flipping).

[0024] The processing unit 12 determines the instance 15, whose lower left divided region has the largest area among the instances 15 to 17, as the reference instance. Then, the processing unit 12 determines the divided regions of the other instances that are located at positions corresponding to the divided region of the reference instance, for example, as follows.

[0025] The processing unit 12 sets the divided area as the reference area from among the four divided areas of the instance 15 that is set as the reference instance, for example, in ascending order of x coordinate and y coordinate (the lower left corner of each of the instances 15 to 17 is x=y=0). In Fig. 1, an example is shown in which the divided area 15a is set as the reference area.

[0026] Then, the processing unit 12 detects, for each of the instances 16 and 17, one or more divided areas (hereinafter referred to as contact areas) that contact the divided area 15a, which is the reference area, when the instances 15 to 17 are superimposed.

[0027] 1, a contact area 16b formed by four divided areas that contact the divided area 15a is detected in the instance 16. Also, a contact area 17b formed by four divided areas that contact the divided area 15a is detected in the instance 17.

[0028] Then, the processing unit 12 determines, in each of the contact regions 16b and 17b, the divided region that has the largest overlapping area with the divided region 15a, which is the reference region, as the divided region located at a position corresponding to the divided region 15a. In the example of Fig. 1, the divided region 16a in the instance 16 and the divided region 17a in the instance 17 are determined as the divided regions located at a position corresponding to the divided region 15a.

[0029] Then, the processing unit 12 detects an overlapping area (AND area) where all divided areas at corresponding positions overlap between the instances 15 to 17. This overlapping area may be the optimal placement area for the TCD cell, and therefore, hereinafter, the overlapping area is referred to as the optimal placement area.

[0030] 1, optimal placement regions 15c, 16c, and 17c are obtained for instances 15 to 17. The optimal placement regions 15c to 17c are regions that are the same size as the divided region 16a of instance 16 and are located in the same position.

[0031] Then, the processing unit 12 sets temporary placement positions for temporarily placing the TCD cells in the optimal placement regions 15c to 17c of the instances 15 to 17. The temporary placement positions can be set by placing pseudo cells (hereinafter referred to as dummy TCD cells) 15d, 16d, and 17d having the same size as the TCD cells, one by one, in each of the optimal placement regions 15c to 17c, as shown in FIG.

[0032] The physical definition of a TCD cell includes information such as size, bulk, and wiring, but the physical definition of a dummy TCD cell requires only size. Also, while TCD cells are restricted to being placed in a site area, dummy TCD cells do not have such placement restrictions. Furthermore, dummy TCD cells do not require a library and can be defined by anyone other than the TCD cell designer. Therefore, as will be described later, placement verification can be performed in advance using dummy TCD cells before the TCD cells are officially released. Another difference between dummy TCD cells and TCD cells is that they do not require registration in a database.

[0033] The placement of the dummy TCD cells 15d to 17d in the optimum placement regions 15c to 17c may be performed based on a user input, or the processing unit 12 may place the dummy TCD cells 15d to 17d in each of the optimum placement regions 15c to 17c (for example, in the center).

[0034] The processing unit 12 performs the above-described processing using each divided region of the reference instance as the reference region. Furthermore, the processing unit 12 performs placement verification to determine whether the placement rules are satisfied for the top layer including the instances 15 to 17 in which the dummy TCD cells are placed. As described above, the DRC placement rules stipulate that the tape-out is performed by placing TCD cells in at least a specified percentage of the divided regions obtained by dividing the entire chip at regular intervals. In the design method of this embodiment, placement verification to determine whether the placement rules are satisfied can be performed for the top layer including the instances 15 to 17 in which the dummy TCD cells are placed, instead of the top layer in which the TCD cells are placed.

[0035] If it is determined that the placement rules are not satisfied, for example, the processing unit 12 adjusts various parameters for placing dummy TCD cells, which will be described later. If it is determined that the placement rules are satisfied, the processing unit 12 outputs information indicating each optimum placement area and tentative placement position (placement position of the dummy TCD cell). The processing unit 12 may output the information indicating each optimum placement area and tentative placement position to a display device (not shown) for display, or may output the information to the storage unit 11 for storage. The processing unit 12 may also output (or transmit) the information to a device external to the design device 10.

[0036] Although the details will be described later, for example, the processing unit 12 performs processing to place the TCD cell at a tentative placement position in the lowest hierarchical level based on the lowest hierarchical level design information 11b and information indicating each optimum placement area and tentative placement position (the position where the dummy TCD cell is placed). If another cell is placed at the tentative placement position in the lowest hierarchical level, the processing unit 12 may shift the placement area of ​​the TCD cell from the tentative placement position within the optimum placement area.

[0037] The process of placing the TCD cells in the lowest layer may be performed by a design device other than the design device 10. According to the design apparatus 10 and design method of the first embodiment described above, the tentative placement positions of TCD cells are set for multiple instances in the lowest layer included in the highest layer based on the divided areas in the highest layer. This reduces the occurrence of TCD cells that are invalidated in the highest layer, and reduces the number of rearrangements in the lowest layer, the number of assembly steps in the highest layer, and the number of re-verifications in the highest layer. This makes it possible to shorten the design period (design TAT (Turn Around Time)) in hierarchical design.

[0038] The reason why many invalid TCD cells occur when the placement area of ​​the TCD cells is determined in the lowest hierarchy as in the conventional case will be explained below. (Why many invalid TCD cells occur when determining the placement area of ​​TCD cells at the lowest level) FIG. 2 is a diagram for explaining an example of verification of the placement rules of TCD cells.

[0039] The chip is divided into regions at regular intervals, starting from the lower left corner. For example, if a chip that is 11,500 μm long in the x direction and 9,500 μm long in the y direction is divided at 1,000 μm intervals in both the x and y directions, 11 divided regions will be generated in the x direction and 9 divided regions will be generated in the y direction, as shown in Figure 2. Regions 20a and 20b, which are spaced apart by less than 1,000 μm, will not be considered divided regions.

[0040] When verifying the TCD cell placement rules, if the TCD cells are placed in a specified percentage or more of the divided regions, the placement rules are determined to be satisfied. For example, if the specified percentage is 50% and there are 99 divided regions, as shown in Figure 2, if the TCD cells are placed in 50 or more divided regions, the placement rules are determined to be satisfied.

[0041] A TCD cell is determined to be valid or invalid depending on its location. A TCD cell located within a divided region (e.g., TCD cell 21) is determined to be valid. On the other hand, a TCD cell that spans multiple divided regions (e.g., TCD cell 22a) or a TCD cell located in regions 20a and 20b that are not divided regions (e.g., TCD cell 22b) is determined to be invalid.

[0042] When a hierarchical design is performed, there is a possibility that many such invalid TCD cells will occur. FIG. 3 is a diagram showing an outline of the hierarchical design. 3 shows an example in which an intermediate hierarchical level 31 is designed from three lowest hierarchical levels 30a, 30b, and 30c, and a top hierarchical level 32 (representing the entire chip) is designed from the intermediate hierarchical level 31 and three intermediate hierarchical levels 31a, 31b, and 31c that are the inverses of the intermediate hierarchical level 31. Using such an intermediate hierarchical level 31 simplifies the design of the top hierarchical level 32, since it is only necessary to arrange the intermediate hierarchical level 31 and the three intermediate hierarchical levels 31a, 31b, and 31c that are the inverses of the intermediate hierarchical level 31.

[0043] TCD cells are placed in cell placement areas called site areas. Site areas are areas for placing cells to which power is supplied. Since site areas exist on the lowest hierarchical levels 30a, 30b, and 30c, TCD cells are placed on the lowest hierarchical levels 30a, 30b, and 30c.

[0044] FIG. 4 is a flowchart showing the flow of the TCD cell placement process when determining the placement area of ​​the TCD cell and placing the TCD cell in the lowest layer. Step S1: In the lowest layer, TCD cells are placed so that placement rules are satisfied. When the highest layer includes multiple instances of the lowest layer, the size and position of the partitioned regions are unknown when the lowest layer is designed. Therefore, partitioned regions are assumed by dividing the region at regular intervals, for example, starting from the lower left corner. Hereinafter, the assumed partitioned regions are referred to as assumed partitioned regions. After the assumed partitioned regions are obtained, TCD cells are placed in each assumed partitioned region so that placement rules (for example, a rule that TCD cells should be placed in at least 50% of all assumed partitioned regions in each lowest layer) are satisfied.

[0045] In the example of Figure 4, TCD cells are placed in the three lowest hierarchical levels so as to satisfy the placement rules. All TCD cells placed in each lowest hierarchical level are placed within the assumed partition area, and are all valid TCD cells.

[0046] Step S2: It is determined whether or not the placement of TCD cells has been completed in all of the lowest hierarchical layers. If it is determined that the placement of TCD cells has not been completed in all of the lowest hierarchical layers, the process from step S1 is repeated. If it is determined that the placement of TCD cells has been completed in all of the lowest hierarchical layers, the process of step S3 is performed.

[0047] Step S3: The multiple lowest hierarchies are assembled into the highest hierarchical level. At this time, intermediate hierarchies such as those shown in Figure 3 can also be used. In the example of Figure 4, the highest hierarchical level is assembled, containing four instances each of the three lowest hierarchical levels.

[0048] Step S4: Placement verification is performed to determine whether the TCD cells in the highest layer satisfy the DRC placement rules. In placement verification in the highest layer, as shown in Figure 2, the chip is divided into regions at regular intervals, starting from the lower left corner of the chip as the starting point for region division. At this time, there may be a discrepancy (offset) between the divided regions obtained by region division in the highest layer and the assumed divided regions obtained in the lowest layer. For this reason, as shown in Figure 4, there may be many TCD cells that are invalidated because they span multiple divided regions, or TCD cells that are placed in regions that are not considered divided regions and are therefore invalidated.

[0049] Step S5: It is determined whether the TCD cell does not satisfy the DRC placement rules and a verification error has occurred. If it is determined that a verification error has occurred, the process from step S1 is repeated. In this case, the process of step S1 involves correcting the placement area of ​​the TCD cell.

[0050] If it is determined that no verification error has occurred, the TCD cell placement process ends. FIG. 5 is a diagram illustrating an example of a case where a verification error occurs. Figure 5 shows an example in which TCD cells are placed in a hypothetical partition area in the lowest layer, and then assembled in the highest layer, and the partition area is set. As shown in Figure 5, in the lowest layer, the offset lines extending in the x and y directions from the starting point of the partitioning area coincide with the boundaries in two directions of the lowest layer, and there is no offset.

[0051] However, after assembly on the top layer, the offset lines are misaligned with the boundaries on two sides of the bottom layer, causing offsets. Therefore, TCD cells 35a and 35b, which were validated in placement verification at the lowest hierarchical level as shown in Figure 5, are invalidated in placement verification at the highest hierarchical level because they span multiple division regions. Furthermore, TCD cell 36a, which was validated in placement verification at the lowest hierarchical level as shown in Figure 5, is placed in a single division region with other TCD cells in the highest hierarchical level, resulting in an excessively placed TCD cell. The same is true for TCD cell 36b.

[0052] This reduces the partitioned area containing valid TCD cells, which may lead to verification errors. Below, several examples of cases where over-allocation occurs will be explained.

[0053] FIG. 6 shows examples of cases where over-allocation occurs and cases where over-allocation does not occur. In the first case of excessive placement (NG case 1), one TCD cell is placed in each of the four assumed division regions, but the top layer contains only one division region. In this case, three TCD cells are excessive.

[0054] In the second case (NG case 2) and the third case (NG case 3) where excessive placement occurs, one TCD cell is placed in each of the four assumed division regions, but two division regions in the highest hierarchy contain two TCD cells each. In this case, one TCD cell is an excessive TCD cell in each of the two division regions.

[0055] In the first case (OK case 1) and the second case (OK case 2), where no over-placement occurs, one TCD cell is placed in each of the four assumed division areas, and one TCD cell is placed in each of the four division areas at the highest level.

[0056] When the highest hierarchy level includes multiple instances of the lowest hierarchy level, it is difficult to determine the optimal placement area for TCD cells that does not result in the above-mentioned over-placement because the offsets differ between the multiple instances.

[0057] TCD cells are relatively large cells with internal bulk and metal layers, which can become obstacles when placing and routing other cells. If the number of TCD cells is excessively increased in order to increase the number of partitioned regions containing valid TCD cells and satisfy the placement rules, this will affect the placement and routing of other cells.

[0058] In contrast to the flow of the TCD cell placement process shown in FIG. 4, the flow of the TCD cell placement process by the design device 10 of the first embodiment is, for example, as follows. (Flow of TCD Cell Placement Processing by the Design Apparatus 10 of the First Embodiment) FIG. 7 is a flowchart showing an example of the flow of a TCD cell placement process performed by the design apparatus according to the first embodiment.

[0059] Step S10: The processing unit 12 sets parameters for placing dummy TCD cells. The parameters for placing dummy TCD cells include, for example, parameters that represent rules for placing dummy TCD cells in the highest layer.

[0060] Step S11: The processing unit 12 detects an optimum placement area from a plurality of instances in the lowest layer by the process shown in FIG. Step S12: The processing unit 12 places the dummy TCD cells in the optimum placement area based on the parameters for placing the dummy TCD cells, thereby setting the tentative placement positions of the TCD cells.

[0061] Step S13: The processing unit 12 verifies the placement of TCD cells in the highest layer. In the process of step S13, it is verified whether dummy TCD cells are placed in a specified proportion or more of the divided regions out of all the divided regions.

[0062] Step S14: The processing unit 12 determines whether or not a verification error has occurred in the placement verification. If the processing unit 12 determines that a verification error has occurred, the processing returns to the processing of step S10. In this case, in the processing of step S10, for example, parameters for the placement of dummy TCD cells are adjusted so that a verification error does not occur in the placement verification. If the processing unit 12 determines that a verification error has not occurred, the processing unit 12 performs the processing of step S15.

[0063] Step S15: The processing unit 12 outputs information indicating each optimum placement area and the provisional placement position (the position where the dummy TCD cell is placed). If there are multiple lowest hierarchical layers, this information is generated and output for each lowest hierarchical layer.

[0064] In the following description, it is assumed that the processing unit 12 processes the TCD cell at the lowest layer based on this information. Step S16: The processing unit 12 performs processing to place the TCD cells in the lowest hierarchy, for example, in the tentative placement positions of each optimal placement area, based on the lowest hierarchy design information 11b and information indicating each optimal placement area and tentative placement position.

[0065] Step S17: The processing unit 12 determines whether or not the placement of TCD cells has been completed in all of the lowest hierarchical layers. If the processing unit 12 determines that the placement of TCD cells has not been completed in all of the lowest hierarchical layers, it returns to the processing of step S16. If the processing unit 12 determines that the placement of TCD cells has been completed in all of the lowest hierarchical layers, it performs the processing of step S18.

[0066] Step S18: The processing unit 12 verifies the placement of the TCD cell within the optimal placement area. For example, it verifies whether the TCD cell overlaps with other cells, whether it is placed in a position where it can be correctly wired, and so on.

[0067] Step S19: The processing unit 12 determines whether or not a verification error has occurred in the placement verification of the TCD cell in the lowest layer. If the processing unit 12 determines that a verification error has occurred, the processing returns to step S16. In this case, in the processing of step S16, adjustments are made, such as shifting the placement position of the TCD cell, so that a verification error does not occur in the placement verification. If the processing unit 12 determines that no verification error has occurred, the processing of the TCD cell placement ends.

[0068] As is clear from a comparison of the TCD cell placement process shown in Fig. 7 with the TCD cell placement process shown in Fig. 4, the TCD cell placement process shown in Fig. 7 does not require repeated assembly to the top layer or re-verification at the top layer, which makes it possible to shorten the design TAT.

[0069] Furthermore, even if the top layer contains multiple instances of the lowest layer, the design device 10 detects the overlapping area as an optimal placement area and sets the tentative placement position of the TCD cell in the overlapping area. This allows the top layer to optimize the placement area so that the TCD cell is not invalid. This minimizes the number of TCD cells placed. This eliminates the need to place excessive TCD cells in the bottom layer to prevent verification errors during placement verification in the top layer, thereby improving placement and wiring.

[0070] Furthermore, even if a TCD cell overlaps with the placement area of ​​another cell in the lowest layer, as long as its placement position is adjusted within the optimal placement area, the TCD cell will not be invalidated even after assembly in the highest layer. This makes it easier to correct the placement position and prevents the correction of the placement position from lengthening the design turnaround time. Furthermore, since the placement of the TCD cell can be corrected even in the later phases of implementation design (after the TCD cell has been placed) (see Figure 48 below), it is possible to improve placement and wiring.

[0071] (Second embodiment) Next, a second embodiment will be described. FIG. 8 is a block diagram illustrating an example of hardware of the design apparatus.

[0072] The design device 40 can be realized by a computer as shown in Fig. 8. The design device 40 has a CPU 41, a RAM 42, an HDD 43, a GPU 44, an input interface 45, a media reader 46, and a communication interface 47. The above units are connected to a bus.

[0073] The CPU 41 is a processor including an arithmetic circuit that executes program instructions. The CPU 41 loads at least a portion of the program and data stored in the HDD 43 into the RAM 42 and executes the program. The CPU 41 may have multiple processor cores, and the design device 40 may have multiple processors, and the processes described below may be executed in parallel using multiple processors or processor cores. A collection of multiple processors (a multiprocessor) may also be called a "processor."

[0074] The RAM 42 is a volatile semiconductor memory that temporarily stores programs executed by the CPU 41 and data used in calculations by the CPU 41. Note that the design device 40 may be provided with a type of memory other than RAM, or may be provided with multiple memories.

[0075] The HDD 43 is a nonvolatile storage device that stores software programs such as an OS (Operating System), middleware, and application software, as well as data. The programs include, for example, a design program that causes the design device 40 to execute a process for performing hierarchical design. Note that the design device 40 may also be equipped with other types of storage devices, such as a flash memory or an SSD (Solid State Drive), or may be equipped with multiple nonvolatile storage devices.

[0076] The GPU 44 outputs an image to a display 44a connected to the design device 40 in accordance with an instruction from the CPU 41. The display 44a may be a CRT (Cathode Ray Tube) display, a liquid crystal display (LCD: Liquid Crystal Display), a plasma display (PDP: Plasma Display Panel), an organic EL (OEL: Organic Electro-Luminescence) display, or the like.

[0077] The input interface 45 receives input signals from an input device 45a connected to the design apparatus 40 and outputs them to the CPU 41. The input device 45a may be a pointing device such as a mouse, touch panel, touch pad, or trackball, a keyboard, a remote controller, or a button switch. Multiple types of input devices may be connected to the design apparatus 40.

[0078] The medium reader 46 is a reading device that reads programs and data recorded on a recording medium 46a. For example, a magnetic disk, an optical disk, a magneto-optical disk (MO: Magneto-Optical disk), or a semiconductor memory can be used as the recording medium 46a. Magnetic disks include flexible disks (FD: Flexible Disks) and HDDs. Optical disks include compact discs (CDs) and digital versatile discs (DVDs).

[0079] The medium reader 46 copies programs and data read from the recording medium 46a to another recording medium such as the RAM 42 or the HDD 43. The read programs are executed by the CPU 41, for example. The recording medium 46a may be a portable recording medium and may be used to distribute programs and data. The recording medium 46a and the HDD 43 may also be referred to as computer-readable recording media.

[0080] The communication interface 47 is connected to a network 47a and communicates with other information processing devices via the network 47a. The communication interface 47 may be a wired communication interface connected to a communication device such as a switch via a cable, or may be a wireless communication interface connected to a base station via a wireless link.

[0081] Next, the function of the design device 40 will be described. FIG. 9 is a block diagram illustrating an example of functions of the design apparatus. The design device 40 has an input unit 51, a dummy TCD cell placement unit 52, a top-level hierarchy DB (DataBase) 53, modules 54a, 54b, 54c, and an output unit 55. The modules 54a, 54b, 54c have TCD cell placement units 54a1, 54b1, 54c1, lower-level DBs 54a2, 54b2, 54c2, and setting information generation units 54a3, 54b3, 54c3.

[0082] The top-level DB 53 and the lower-level DBs 54a2, 54b2, and 54c2 can be implemented, for example, using storage areas secured in the RAM 42 or the HDD 43. The input unit 51, the dummy TCD cell placement unit 52, the TCD cell placement units 54a1, 54b1, and 54c1, the setting information generation units 54a3, 54b3, and 54c3, and the output unit 55 can be implemented, for example, using program modules executed by the CPU 41. The input unit 51, the dummy TCD cell placement unit 52, the TCD cell placement units 54a1, 54b1, and 54c1, the setting information generation units 54a3, 54b3, and 54c3, and the output unit 55 are examples of functions executed by the processing unit 12 shown in FIG. 1 .

[0083] The input unit 51 acquires information input by a user operating the input device 45a. The input unit 51 acquires, for example, setting information on the highest hierarchical level. The input unit 51 may acquire information input using an interactive editor or the like.

[0084] The dummy TCD cell placement unit 52 places and verifies the placement of dummy TCD cells based on the setting information for the highest layer, the setting information for the lowest layer output from the modules 54a, 54b, and 54c, and the design information for the highest layer stored in the highest layer DB 53. The placement of dummy TCD cells is performed for each lowest layer corresponding to each of the modules 54a, 54b, and 54c. The dummy TCD cell placement unit 52 may place the dummy TCD cells based on information input by the user.

[0085] Information (hereinafter referred to as check area information) including the placement results of the dummy TCD cells (optimal placement area and provisional placement positions of the TCD cells (positions where the dummy TCD cells are placed)) is also output for each lowest hierarchy (each module). An example of generating check area information will be described later (see FIG. 21).

[0086] The top layer DB 53 stores design information and the like for the top layer. The modules 54a, 54b, and 54c each perform a TCD cell placement process in a different lowest hierarchy. In other words, in this embodiment, three lowest hierarchy levels are used, but the number of applicable lowest hierarchy levels is not limited to three. The number of modules can be changed depending on the number of lowest hierarchy levels.

[0087] The TCD cell placement unit 54a1 places TCD cells based on the check area information for module 54a output by the dummy TCD cell placement unit 52 and the design information for the lowest hierarchical level stored in the lower hierarchical level DB 54a2. The TCD cell placement unit 54a1 may place TCD cells based on information input by the user. The TCD cell placement results may be stored in the lower hierarchical level DB 54a2. The TCD cell placement units 54b1 and 54c1 of modules 54b and 54c have the same functions as the TCD cell placement unit 54a1.

[0088] The lower hierarchy DB 54a2 stores design information of the lowest hierarchy for which the module 54a is responsible for processing, etc. The lower hierarchy DBs 54b2 and 54c2 of the modules 54b and 54c have the same functions as the lower hierarchy DB 54a2.

[0089] The setting information generator 54a3 generates setting information based on design information for the lowest hierarchical level stored in the lower hierarchical level DB 54a2. The setting information includes information on areas where dummy TCD cells are prohibited from being placed (such as areas where cells other than TCD cells are already placed). The setting information generator 54a3 may generate setting information based on information input by the user. An example of generating setting information will be described later (see FIG. 12). The setting information generators 54b3 and 54c3 of the modules 54b and 54c have the same functions as the setting information generator 54a3.

[0090] The output unit 55 outputs the placement results of the dummy TCD cells, the placement results of the TCD cells, the verification results of the placement verification, error information, etc. The output unit 55 may output the placement results of the dummy TCD cells, the placement results of the TCD cells, the verification results of the placement verification, error information, etc. to the display 44a for display, or may output them to the HDD 43 for storage. Furthermore, the output unit 55 may output (or transmit) the placement results of the dummy TCD cells, the placement results of the TCD cells, the verification results of the placement verification, error information, etc. to a device external to the design device 40.

[0091] The setting information on the top layer and bottom layer and the check area information may be stored as files in a storage unit (not shown). The storage unit may also be implemented using a storage area secured in the RAM 42 or the HDD 43, for example.

[0092] FIG. 10 is a diagram showing an outline of the flow of the TCD cell placement process performed by the design device according to the second embodiment. The design device 40 of the second embodiment performs the following processes at the highest level: placement of dummy TCD cells (step S20), placement verification of the dummy TCD cells (step S21), and output of check area information (step S22). The output of the check area information is performed for each of the modules 54a, 54b, and 54c.

[0093] Furthermore, as processing at the lowest hierarchy level, the design device 40 performs TCD cell placement processing (step S23) and TCD cell placement verification (step S24) for each lowest hierarchy level (each module).

[0094] These processes may be performed automatically by a batch processing program, or a part of the processes may be performed based on input from a user (such as a designer) using an interactive editor or the like.

[0095] The user can select whether to perform some of the processing based on user input depending on the design progress (e.g., whether it is in the early stages of design or the final stages of design) and the purpose (e.g., for trial purposes, for status confirmation purposes, for actual operation purposes). For example, if the purpose is a trial in the early stages of design, the design system 40 automatically places dummy TCD cells using a batch processing program. In the middle stages of design, the design system 40 automatically places dummy TCD cells, and then the user adjusts the placement position using an interactive editor or the like. In the final stages of design, manual placement is the main method, and in cases where partial automatic placement is to be performed, it is possible to select to perform manual placement using the interactive editor and then continue with automatic placement using the interactive editor.

[0096] (Example of top-level configuration information) FIG. 11 is a diagram showing an example of setting information on the highest layer side. The setting information is input to the design device 40 as a setting file on the top layer side, for example.

[0097] The setting items included in the setting information are the following (a) to (d): Note that the lower layer shown in Fig. 12 means the lowest layer. (a) Placement rule for dummy TCD cells in the top layer “RULE” (b) Dummy TCD cell placement prohibition area “INHIBIT_AREA” (defined in the top layer and in the bottom layer) (c) The lower limit “PLACE_RATIO_LOWER_LIMIT” and upper limit “PLACE_RATIO_UPPER_LIMIT” of the placement ratio of dummy TCD cells in the lowest layer (d) "PLACE_AREA_LOWER_LIMIT": the lower limit size (area) of the optimal placement area to be notified to the modules 54a, 54b, and 54c (e) Reserve area creation ratio for the lowest layer “RESERVE_RATIO” (f) The name of the file containing the configuration information on the lowest level: “CONST_FILE” Each setting item will be described in detail later.

[0098] (Example of setting information on the lowest layer) FIG. 12 is a diagram showing an example of setting information on the lowest layer side. The setting information on the lowest hierarchical level side is generated by setting information generating units 54a3, 54b3, and 54c3 of the modules 54a, 54b, and 54c.

[0099] The setting items included in the setting information are the following (a) to (d): Note that the lower layer shown in Fig. 12 means the lowest layer. (a) Dummy TCD cell placement prohibition area “INHIBIT_AREA” (defined at the lowest level) (b) The lower limit “PLACE_RATIO_LOWER_LIMIT” and upper limit “PLACE_RATIO_UPPER_LIMIT” of the placement ratio of dummy TCD cells in the lowest layer (c) “PLACE_AREA_LOWER_LIMIT” is the lower limit size of the optimal placement area to be notified to the modules 54a, 54b, and 54c. (d) Reserve area creation ratio for the lowest layer “RESERVE_RATIO” The file name of the setting file containing such setting information on the lowest layer side is specified as "CONST_FILE" in FIG.

[0100] Each setting item will be described in detail later. (Example of creating configuration information using the interactive editor) An example of generating the above setting information using an interactive editor will be described below.

[0101] FIG. 13 is a diagram showing an example of generating setting information using an interactive editor. First, a "Dummy TCD Window" such as that shown in Fig. 13 is displayed on the screen of the display 44a. When the user operates the input device 45a to select "ParameterSet" and press "EXEC," the "Dummy TCD Setting Window" is displayed.

[0102] When "IN" in the "Dummy TCD Setting Window" is selected and "OK" is pressed, a file selection screen (not shown) is displayed. When a setting file containing setting information such as that shown in Figure 11 or Figure 12 is selected, the setting information can be displayed on the screen. It is also possible to create a new setting file on the file selection screen.

[0103] In the "Dummy TCD Setting Window", the user can adjust the "RULE" parameters by operating the input device 45a. The prohibited areas for placement of dummy TCD cells in the highest hierarchy can be set on the screen that appears when "CHIP" is selected in "Module Select" of the "Dummy TCD Setting Window" and "OK" is pressed. The various parameters in the lowest hierarchy can be set on the screen that appears when "MODULE_A" or the like is selected in "Module Select" of the "Dummy TCD Setting Window" and "OK" is pressed.

[0104] When "OUT" is selected in the "Dummy TCD Setting Window" and "OK" is pressed, a setting file reflecting the entered parameter values ​​is output.

[0105] FIG. 14 shows an example of the top layer setting screen and the bottom layer setting screen. In the top layer setting screen "Top Layer Window," pressing "EDIT" displays a setting screen for the prohibited area for placing dummy TCD cells.

[0106] The "Lower Layer Window" setting screen for the lowest layer allows you to set the upper and lower limits of the placement rate of dummy TCD cells in the lowest layer, the lower limit size of the optimal placement area notified to modules 54a, 54b, and 54c, and the creation rate of the reserved area. Furthermore, by pressing "EDIT," a setting screen for areas where dummy TCD cells are prohibited from being placed is displayed.

[0107] Furthermore, when "IN" is selected on the screen and "OK" is pressed, a file selection screen (not shown) is displayed. When a setting file containing setting information such as that shown in FIG. 12 is selected, the setting information can be displayed on the screen. It is also possible to create a new setting file on the file selection screen. When "OUT" is selected on the screen and "OK" is pressed, a setting file reflecting the input parameter values ​​is output.

[0108] (Explanation of each setting item in the setting information) (a) Regarding the “RULE” The placement rule "RULE" for the dummy TCD cells in the highest layer shown in Figure 11 includes the size of the check window, which means the divided region described in the first embodiment, and the placement rate of the TCD cells. The check window size and the placement rate of the TCD cells are based on the DRC placement rule, but may be changed based on user input. For example, the placement rate may be changed to a value stricter than the DRC placement rule based on user input.

[0109] The "RULE" can be specified or changed in the configuration file shown in Figure 11 or in the interactive editor shown in Figure 13, in the "Check_Window" section that specifies the size of the check window and the "Check_Ratio" section that specifies the placement ratio.

[0110] The placement verification of the dummy TCD cells, which will be described later, is performed based on the specified size of the check window and the placement rate. (b) Regarding “INHIBIT_AREA” When dummy TCD cells are placed in the top layer, there may be areas where the dummy TCD cells cannot be placed due to the top layer's constraints. In this case, an "INHIBIT_AREA" is set as an area where dummy TCD cells cannot be placed based on the top or bottom layer.

[0111] The prohibited placement areas can be specified or changed in a setting file such as that shown in Fig. 11. The prohibited placement areas can also be specified or changed on the prohibited placement area setting screen for dummy TCD cells that is displayed by pressing "EDIT" in the "Top Layer Window" or "Lower Layer Window" of the interactive editor shown in Fig. 14.

[0112] FIG. 15 shows a first example of specifying a placement prohibition area using the interactive editor. On the setting screen for the prohibited area of ​​the dummy TCD cell, the prohibited area is specified by "Pos", which is the bottom left coordinate of the prohibited area, and "Size", which is the length in the x-axis direction and the length in the y-axis direction. In addition, the prohibited area can be copied, moved, or deleted by pressing "Copy", "Move", or "Delete".

[0113] FIG. 16 is a diagram showing a second example of specifying a placement prohibition area using the interactive editor. On the setting screen for the prohibited area of ​​dummy TCD cells, the user can specify the prohibited area by operating the mouse, with two points designated by the mouse pointer (the two arrows in Figure 16) as the lower left and upper right coordinates.

[0114] FIG. 17 shows a third example of specifying a placement prohibition area using the interactive editor. On the setting screen for the prohibited area of ​​dummy TCD cells, the user operates the mouse to specify the prohibited area with the point specified by the mouse pointer (arrow in Figure 17) as the bottom left coordinate, and the length in the x-axis direction and the length in the y-axis direction represented by "Size".

[0115] "INHIBIT_AREA" in the setting information on the lowest hierarchical level shown in FIG. 12 can also be specified in the setting file or using the interactive editor, just like "INHIBIT_AREA" in the setting information on the highest hierarchical level.

[0116] (c) Regarding “PLACE_RATIO_LOWER_LIMIT” and “PLACE_RATIO_UPPER_LIMIT” When there are multiple lowest hierarchical levels, the lowest hierarchical levels have different logical functions and therefore different logical scales, and may differ from one another in physical size and cell usage rate.

[0117] Therefore, it is desirable to place TCD cells at different placement rates for each lowest hierarchy level, rather than placing TCD cells at a uniform placement rate for each lowest hierarchy level. For this reason, the design device 40 of this embodiment allows the lower limit "PLACE_RATIO_LOWER_LIMIT" and upper limit "PLACE_RATIO_UPPER_LIMIT" of the placement rate of dummy TCD cells to be freely specified for each lowest hierarchy level.

[0118] The upper and lower limits of the placement rate of dummy TCD cells can be specified or changed in the setting file shown in Figure 11 or Figure 12. The upper and lower limits of the placement rate of dummy TCD cells can also be specified or changed in the "Lower Layer Window" of the interactive editor shown in Figure 14.

[0119] The placement verification of the dummy TCD cells, which will be described later, is performed based on the specified "PLACE_RATIO_LOWER_LIMIT" and "PLACE_RATIO_UPPER_LIMIT".

[0120] (d) “PLACE_AREA_LOWER_LIMIT” If the optimum placement area notified to the lowest layer side (modules 54a, 54b, 54c) is extremely narrow for the TCD cell, it may become difficult to adjust the placement of the TCD cell on the lowest layer side.

[0121] To prevent such a situation from occurring, the design device 40 of this embodiment allows specification of a lower limit size (area) "PLACE_AREA_LOWER_LIMIT" of the optimum placement area notified to the modules 54a, 54b, and 54c.

[0122] The lower limit size can be specified or changed in the setting file as shown in FIG. 11 or 12, or in the "lower layer window" of the interactive editor as shown in FIG. 14.

[0123] An optimal placement area that is smaller than the lower limit size is invalid and is not notified to the lowest layer side. (e) Regarding “RESERVE_RATIO” In the lowest layer, TCD cells are placed according to the optimal placement area notified from the highest layer. However, depending on the design situation of the lowest layer, other logic cells may become obstacles, making it impossible to place the TCD cells.

[0124] To avoid this situation, the design device 40 designates an optimized area with a predetermined creation ratio "RESERVE_RATIO" among multiple optimal placement areas as a reserved area where no dummy TCD cells are placed (no tentative placement position is set).The design device 40 then outputs information indicating the reserved area (notifies the lowest layer side).

[0125] FIG. 18 is a diagram showing an example of creating a reserved area. In the lowest hierarchical layer 60, an optimum allocation area (for example, optimum allocation area 61) and reserve areas 62a, 62b, and 62c are set based on information notified from the highest hierarchical layer side.

[0126] In the optimum placement area 61, if there are fixed placement logic cells 63a, 63b, and 63c, they will get in the way and prevent the placement of the TCD cell 64. On the other hand, the reserved area 62a contains fixed-placement logic cells 63d, 63e, 63f, and 63g, but has space for arranging the TCD cell 64. Therefore, during the placement process for the TCD cell 64 in the lowest hierarchical level 60, for example, the optimal placement area 61 is replaced with the reserved area 62a, and the TCD cell 64 is placed therein.

[0127] The reserve area creation ratio can be specified or changed in the setting file shown in Figure 11 or Figure 12, or in the "lower layer window" of the interactive editor shown in Figure 14.

[0128] (f) Regarding “CONST_FILE” "CONST_FILE" is a setting item that indicates the file name of the setting file that includes the setting information on the lowest hierarchical level as shown in Fig. 11. In the example of Fig. 11, the file name " / xxx / yyy / zzz / tcd_moduleA.cnst.txt" is specified.

[0129] Generally, when the chip floor plan is decided in the early stages of design, the size of the top layer, the placement position of the bottom layer included in the top layer, the number of instances, and the logical size and physical size of the bottom layer are often already determined.

[0130] In such cases, it is difficult to determine detailed constraints at the lowest level, so it is desirable to specify the constraints (the various setting items mentioned above) at the highest level as appropriate, as in the configuration file shown in Figure 11.

[0131] On the other hand, as the design of the lowest level advances, the area in which TCD cells can be placed becomes limited. For example, if cells with large physical sizes, such as RAM or custom macros, or macros that greatly affect performance, such as clock macros or flip-flops, are placed preferentially, TCD cells cannot be placed in the locations where these are placed.

[0132] Therefore, even in the highest hierarchy, it is necessary to prohibit the placement of dummy TCD cells in the positions where these are placed, and therefore, the above-mentioned prohibited areas for placing dummy TCD cells are set.

[0133] However, since it is difficult for the highest hierarchical level to grasp the placement status of cells, macros, etc. on the lowest hierarchical level due to reasons such as different designers, it is desirable to specify constraints on the lowest hierarchical level. For this reason, for example, the setting information generators 54a3, 54b3, and 54c3 shown in Fig. 9 generate setting information for the lowest hierarchical level based on the design information for the lowest hierarchical level stored in the lower hierarchical DBs 54a2, 54b2, and 54c2, and output a setting file including the setting information.

[0134] FIG. 19 is a diagram illustrating a design example of the lowest layer. In the lowest layer 70, a RAM 71 and a custom macro 72 are arranged. Next, an example of automatically generating a setting file using an interactive editor based on the design information of the lowest hierarchy will be described.

[0135] FIG. 20 shows an example of generating a setting file containing setting information on the lowest hierarchical level using the interactive editor. The "Lower Layer Window" of the interactive editor shown in Fig. 20 differs from that shown in Fig. 14 in that "AUTO" is displayed in "TCD_AREA_IN_FILE" and "INHIBIT_AREA." The file name of the check area information acquired by the modules 54a, 54b, and 54c is input in "TCD_AREA_IN_FILE."

[0136] When "AUTO" is pressed on the "Lower Layer Window" screen, a prohibited placement area is automatically specified based on the design information of the lowest layer as shown in Fig. 19. When "EDIT" is pressed, it is possible to specify a prohibited placement area as shown in Figs. 15 to 17 above.

[0137] After that, "OUT" is pressed, a file name is entered, and then "OK" is pressed, and the setting file is created. In the configuration file of Figure 20, two prohibited placement areas are specified by the bottom left coordinates "0 1000" and top right coordinates "3300 2600" of RAM 71 in Figure 19, and the bottom left coordinates "3500 3300" and top right coordinates "4700 4300" of custom macro 72.

[0138] The file name of the setting file on the lowest layer side created in this way is specified by "CONST_FILE" shown in Fig. 11 so that it can be referenced when placing dummy TCD cells on the highest layer side. Alternatively, by pressing "IN" on the "Lower Layer Window" screen shown in Fig. 14, entering the file name of the setting file, and pressing "OK", the setting file can be referenced on the highest layer side.

[0139] (Example of check area information) FIG. 21 is a diagram illustrating an example of check area information. The check area information is generated by the dummy TCD cell placement unit 52.

[0140] The check area information includes the following information (1) to (6): Note that the lower layer shown in Fig. 21 means the lowest layer. (1) Module name to which the check area information is applied (output destination) In the example of Fig. 21, "MODULE_A" is specified as the module name. The information in the brackets "MODULE_A{}" is applied to the module "MODULE_A" (one of the modules 54a, 54b, and 54c shown in Fig. 9).

[0141] (2) Creation date The creation date is the date when the check area information file was created by the dummy TCD cell placement unit 52, and is expressed as "DATE ​​year, month, day, hour, minute, second."

[0142] The creation date is used, for example, in the modules 54a, 54b, and 54c to check whether check area information created on the same date is used. The creation date may also be used, for example, to check the version number of the check area information file read by the modules 54a, 54b, and 54c.

[0143] (3) Coordinate unit system The coordinate unit system is a numerical unit that indicates the coordinates of the optimum placement area, tentative placement position, placement prohibition area, and reserved area, and is expressed in "UNIT units." In the example of Fig. 21, the unit is nm.

[0144] (4) Optimal placement area, provisional placement position The optimum placement area and the tentative placement positions of the TCD cells (placement positions of the dummy TCD cells) within the optimum placement area are expressed as "TCD_GEN Num AREA MinX MinY MaxX MaxY POS XY."

[0145] "Num" represents an additional number, and the maximum value of Num is the number of TCD cells requested at the lowest layer. "AREA" is a keyword that will be used to represent the optimal placement area.

[0146] "MinX" is the bottom left X coordinate of the optimal placement area, "MinY" is the bottom left Y coordinate of the optimal placement area, "MaxX" is the top right X coordinate of the optimal placement area, and "MaxY" is the top right Y coordinate of the optimal placement area.

[0147] "POS" is a keyword that will represent the provisional placement position. "X" is the X coordinate of the temporary placement position, and "Y" is the Y coordinate of the temporary placement position. (5) Reserve Area The reserved area shown in FIG. 18 and the like is expressed as "RESERVE_AREA Num MinX MinY MaxX MaxY."

[0148] "Num" represents the serial number. "MinX" is the lower left X coordinate of the reserved area, "MinY" is the lower left Y coordinate of the reserved area, "MaxX" is the upper right X coordinate of the reserved area, and "MaxY" is the upper right Y coordinate of the reserved area.

[0149] (6) Placement prohibited area The prohibited area for placing TCD cells shown in the above-mentioned FIGS. 15 to 17 is expressed as "INHIBIT_AREA MinX MinY MaxX MaxY."

[0150] "MinX" is the lower left X coordinate of the prohibited area, "MinY" is the lower left Y coordinate of the prohibited area, "MaxX" is the upper right X coordinate of the prohibited area, and "MaxY" is the upper right Y coordinate of the prohibited area.

[0151] The modules 54a, 54b, and 54c place TCD cells in accordance with the check area information as described above, thereby satisfying the DRC placement rules for the placement of TCD cells across the entire chip.

[0152] The check area information file is output and stored under a directory specified by an argument in a storage unit (not shown) when a program that executes the function of the dummy TCD cell placement unit 52 is executed.

[0153] The check area information file can also be output using an interactive editor. When the function of the dummy TCD cell placement unit 52 is executed, for example, "PLACE" in the "Dummy TCD Window" in Fig. 13 is selected and "EXEC" is pressed. At this time, the check area information file is output and stored in a storage unit (not shown) under the directory having the directory name entered in "Const.FileOutDir."

[0154] For example, when a program that executes the functions of the TCD cell placement units 54a1, 54b1, and 54c1 is executed, the modules 54a, 54b, and 54c can acquire the check area information from the storage unit by specifying the file name of the check area information as an argument.

[0155] The check area information file can also be obtained using the interactive editor. When the file name of the check area information is entered in the "TCD_AREA_IN_FILE" of the "Lower Layer Window" shown in Figure 20 and "OK" is pressed, the modules 54a, 54b, and 54c obtain the check area information file with that file name.

[0156] Next, the details of the placement process of the dummy TCD cells in the highest layer shown in Fig. 10 will be explained. Below, the explanation will be divided into two cases: when the dummy TCD cell placement unit 52 automatically places the dummy TCD cells, and when the interactive editor is used to place the dummy TCD cells.

[0157] (Automatic placement of dummy TCD cells) 22, 23 and 24 are flowcharts showing an example of the flow of automatic placement processing of dummy TCD cells.

[0158] Step S30: The dummy TCD cell placement unit 52 reads the design information of the highest hierarchy from the highest hierarchy DB 53. Step S31: The dummy TCD cell placement unit 52 reads the setting file (see FIG. 11) on the top layer side described above.

[0159] Step S32: The dummy TCD cell placement unit 52 determines whether the generation mode of the dummy TCD cell is the addition generation mode. If it is determined to be the addition generation mode, the dummy TCD cell placement unit 52 keeps the information in the internal database related to the dummy TCD cell placement status created in the highest hierarchical DB 53, and performs the process of step S33. If it is determined not to be the addition generation mode (if it is determined to be the new generation mode), the dummy TCD cell placement unit 52 clears the information in the internal database of the dummy TCD cell stored in the highest hierarchical DB 53, and performs the process of step S34.

[0160] Step S33: The dummy TCD cell placement unit 52 calculates the number of dummy TCD cells already placed for all the lowest layers from the placement status of the existing dummy TCD cells, and re-registers this in the internal database. Thereafter, the process of step S34 is performed.

[0161] Step S34: The dummy TCD cell placement unit 52 divides the top layer into a plurality of check windows in accordance with the above-mentioned dummy TCD cell placement rules. Step S35: The dummy TCD cell placement unit 52 calculates the required number of TCD cells based on the placement rate specified by the above-mentioned dummy TCD cell placement rule and the number of check windows.

[0162] Step S36: If a dummy TCD cell placement prohibition area is set for the top layer, the dummy TCD cell placement unit 52 registers the placement prohibition area in the internal database.

[0163] Step S37: The dummy TCD cell placement unit 52 detects an optimum placement area for each instance in the lowest hierarchy level included in the highest hierarchy level. The detection of the optimum placement area will be described in detail later.

[0164] Step S38: The dummy TCD cell placement unit 52 deletes the optimum placement area that overlaps with the placement prohibition area. Step S39: The dummy TCD cell placement unit 52 determines whether the optimum placement area satisfies the above-mentioned lower limit size. If the dummy TCD cell placement unit 52 determines that the optimum placement area satisfies the lower limit size, it performs the process of step S40. If the dummy TCD cell placement unit 52 determines that the optimum placement area does not satisfy the lower limit size, it performs the process of step S41.

[0165] Step S40: The dummy TCD cell placement unit 52 registers the optimum placement area in the internal database. The dummy TCD cell placement unit 52 also registers the optimum placement area in which the existing dummy TCD cell is placed as a TCD cell placement area in the internal database.

[0166] Step S41: The dummy TCD cell placement unit 52 determines whether or not the detection of the optimum placement area for all the lowest hierarchical layers has been completed. If the dummy TCD cell placement unit 52 determines that the detection of the optimum placement area for all the lowest hierarchical layers has been completed, it performs the process of step S42. If the dummy TCD cell placement unit 52 determines that the detection of the optimum placement area for all the lowest hierarchical layers has not been completed, it repeats the process from step S37.

[0167] Step S42: The dummy TCD cell placement unit 52 acquires parameters defined for a certain lowest layer. Step S43: The dummy TCD cell placement unit 52 acquires the number of optimal placement areas in the lowest hierarchy.

[0168] Step S44: The dummy TCD cell placement unit 52 obtains the upper and lower limits of the placement rate of dummy TCD cells specified as described above for the lowest hierarchy level, and calculates the upper and lower limits of the number of dummy TCD cells.

[0169] Step S45: The dummy TCD cell placement unit 52 registers the optimum placement regions detected for the lowest layer in the internal database in descending order of area. Step S46: The dummy TCD cell placement unit 52 determines whether the number of optimal placement areas detected for the lowest hierarchical level is less than the lower limit of the number of dummy TCD cells. If the dummy TCD cell placement unit 52 determines that the number of optimal placement areas detected for the lowest hierarchical level is less than the lower limit of the number of dummy TCD cells, it performs the process of step S47. If the dummy TCD cell placement unit 52 determines that the number of optimal placement areas detected for the lowest hierarchical level is equal to or greater than the lower limit of the number of dummy TCD cells, it performs the process of step S48.

[0170] Step S47: The dummy TCD cell placement unit 52 sets a lower limit error flag indicating the occurrence of an error. Step S48: The dummy TCD cell placement unit 52 places dummy TCD cells one by one in the optimum placement area starting from the largest area until the number of placed dummy TCD cells reaches the lower limit of the number of dummy TCD cells. The dummy TCD cell placement unit 52 places the dummy TCD cells and registers the optimum placement area where the dummy TCD cells have been placed in the internal database as a TCD cell placement area.

[0171] The placement position of the dummy TCD cell is, for example, the center of the optimum placement region. Step S49: The dummy TCD cell placement unit 52 determines whether placement of dummy TCD cells has been completed for all the lowest hierarchical layers. If the dummy TCD cell placement unit 52 determines that placement of dummy TCD cells has been completed for all the lowest hierarchical layers, it performs the process of step S50. If the dummy TCD cell placement unit 52 determines that placement of dummy TCD cells has not been completed for all the lowest hierarchical layers, it repeats the process from step S42.

[0172] Step S50: The dummy TCD cell placement unit 52 determines whether the placement rule for the dummy TCD cells is satisfied. If the dummy TCD cell placement unit 52 determines that the placement rule for the dummy TCD cells is satisfied, it sets a placement rule OK flag and performs the process of step S56. If the dummy TCD cell placement unit 52 determines that the placement rule for the dummy TCD cells is not satisfied, it performs the process of step S51.

[0173] Step S51: The dummy TCD cell placement unit 52 selects an arbitrary lowest layer. Step S52: The dummy TCD cell placement unit 52 determines whether the number of placed dummy TCD cells is the upper limit of the number of dummy TCD cells. If the dummy TCD cell placement unit 52 determines that the number of TCD cells placed in the selected lowest layer is the upper limit of the number of dummy TCD cells, it repeats the processing from step S51. If the dummy TCD cell placement unit 52 determines that the number of placed dummy TCD cells is not the upper limit of the number of dummy TCD cells, it performs the processing of step S53.

[0174] If the lower limit error flag is set for the selected lowest hierarchy level, or if there is no optimum placement area in which dummy TCD cells have not yet been placed, the process of step S51 is carried out regardless of the result of the above determination.

[0175] Step S53: The dummy TCD cell placement unit 52 places the dummy TCD cell in the optimum placement area having the largest area where the dummy TCD cell is not placed. The dummy TCD cell placement unit 52 places the dummy TCD cell and registers the optimum placement area where the dummy TCD cell has been placed in the top-level DB 53 as a TCD cell placement area.

[0176] The placement position of the dummy TCD cell is, for example, the center of the optimum placement region. Step S54: The dummy TCD cell placement unit 52 determines whether the placement rule for the dummy TCD cells is satisfied. If the dummy TCD cell placement unit 52 determines that the placement rule for the dummy TCD cells is satisfied, it sets a placement rule OK flag and performs the process of step S56. If the dummy TCD cell placement unit 52 determines that the placement rule for the dummy TCD cells is not satisfied, it performs the process of step S55.

[0177] Step S55: The dummy TCD cell placement unit 52 determines whether or not all the lowest hierarchical layers have been selected. If the dummy TCD cell placement unit 52 determines that all the lowest hierarchical layers have been selected, it performs the process of step S56. If it determines that all the lowest hierarchical layers have not been selected, it repeats the process from step S51.

[0178] Step S56: The dummy TCD cell placement unit 52 selects an arbitrary lowest layer. Step S57: The dummy TCD cell placement unit 52 acquires parameters related to the reserved area for the selected lowest hierarchy level.

[0179] Step S58: The dummy TCD cell placement unit 52 calculates the required number of reserved areas in the selected lowest hierarchy. Step S59: The dummy TCD cell placement unit 52 registers the optimum placement regions where dummy TCD cells have not yet been placed in the internal database as reserved regions in the selected lowest hierarchy in descending order of area until the required number is reached.

[0180] Step S60: The dummy TCD cell placement unit 52 determines whether the required number of reserved areas has been secured in the selected lowest layer. If the dummy TCD cell placement unit 52 determines that the required number of reserved areas has been secured, it performs the process of step S62. If it determines that the required number of reserved areas has not been secured, it performs the process of step S61.

[0181] Step S61: The dummy TCD cell placement unit 52 sets a reserve error flag indicating the occurrence of an error. Step S62: The dummy TCD cell placement unit 52 determines whether or not all the lowest hierarchical layers have been selected. If the dummy TCD cell placement unit 52 determines that all the lowest hierarchical layers have been selected, it performs the process of step S63. If it determines that all the lowest hierarchical layers have not been selected, it repeats the process from step S56.

[0182] Step S63: If the lower limit error flag or the reserve error flag is set as described above, the dummy TCD cell placement unit 52 causes the output unit 55 to output error information indicating that a lower limit error or a reserve error has occurred.

[0183] Step S64: The dummy TCD cell placement unit 52 outputs the check area information (see FIG. 21) obtained by the above process to all the lowest layer sides (modules 54a, 54b, 54c).

[0184] This completes the placement of the dummy TCD cells in the highest hierarchy. The above processing order is an example, and the processing order may be changed as appropriate. (Example of optimal placement area detection process and dummy TCD cell placement process) An example of the process of detecting the optimum placement area and the process of placing the dummy TCD cells, which are the processes in step S37, will be described below.

[0185] 25 to 29 are diagrams showing an example of the optimum placement area detection process. 25 shows multiple instances a, b, and c in the lowest hierarchical level of the highest hierarchical level. In instances a to c, the dashed lines indicate the boundaries of the divided areas when the highest hierarchical level is divided. The number and size of the divided areas included in instances a to c vary depending on the positions where they are placed in the highest hierarchical level.

[0186] In the instances a to c, the diagonal line and the line perpendicular to the diagonal line are lines that indicate the directions of the instances a to c. (1) As shown in FIG. 25, the dummy TCD cell placement unit 52 first places multiple instances (instances a to c) in a non-flip orientation.

[0187] (2) Then, the dummy TCD cell placement unit 52 determines a reference instance. The reference instance is, for example, an instance whose lower left divided region has the largest area among the instances a to c. In the example of FIG. 25, the instance a is determined as the reference instance.

[0188] (3) The dummy TCD cell placement unit 52 determines the processing order. The dummy TCD cell placement unit 52 sets the divided areas as the reference areas, for example, in ascending order of x and y coordinates (the lower left corner of each of instances a to c is x=y=0) among the four divided areas of instance a, which is the reference instance. In the example of FIG. 25, the order (processing order) of the reference areas is determined as follows: the lower left divided area, the lower right divided area, the upper left divided area, and the upper right divided area. Hereinafter, the divided areas set as the reference area first are referred to as reference area No. 1, reference area No. 2, reference area No. 3, and reference area No. 4.

[0189] FIG. 26 is a diagram showing the processing for reference region No. 1 of the reference instance. (4) When the instances a to c are superimposed, the dummy TCD cell placement unit 52 detects areas (contact areas) of the divided areas that contact the reference area No. 1 for each of the instances b and c.

[0190] (5) The dummy TCD cell placement unit 52 determines, in each contact region, the divided region that has the largest overlapping area with reference region No. 1 as the divided region (maximum overlapping region) located at the position corresponding to reference region No. 1. Then, the dummy TCD cell placement unit 52 detects, as the optimal placement region, the AND region, which is the region where all of the maximum overlapping regions located at the position corresponding to reference region No. 1 overlap.

[0191] FIG. 27 is a diagram showing the processing for reference region No. 2 of the reference instance. (6) When the instances a to c are superimposed, the dummy TCD cell placement unit 52 detects, for each of the instances b and c, a divided area (contact area) that contacts the reference area No. 2. Note that the dummy TCD cell placement unit 52 does not include, in the contact area, a divided area for which an optimal placement area has already been detected.

[0192] (7) The dummy TCD cell placement unit 52 determines, in each contact region, the divided region that has the largest overlapping area with reference region No. 2 as the divided region (maximum overlapping region) located at the position corresponding to reference region No. 2. Then, the dummy TCD cell placement unit 52 detects, as the optimal placement region, the AND region, which is the region where all of the maximum overlapping regions located at the position corresponding to reference region No. 2 overlap.

[0193] FIG. 28 shows the processing for reference area No. 3 of the reference instance, and FIG. 29 shows the processing for reference area No. 4 of the reference instance. The optimal placement area is detected by the same processes (8) to (11) as above.

[0194] FIG. 30 is a diagram showing an example of a placement process of dummy TCD cells. For each of the instances a to c, an example is shown in which dummy TCD cells are placed in the four optimum placement areas detected by the processes of Figures 25 to 29. The dummy TCD cell placement unit 52 places one dummy TCD cell in the center of each optimum placement area, for example.

[0195] (Placement of dummy TCD cells using an interactive editor) 31, 32 and 33 are flowcharts showing an example of the flow of a dummy TCD cell placement process using an interactive editor.

[0196] Step S70: The dummy TCD cell placement unit 52 reads the design information of the highest hierarchy from the highest hierarchy DB 53. Step S71: The dummy TCD cell placement unit 52 reads the setting file (see FIG. 11) on the top layer side described above. Alternatively, the setting information is input using, for example, an interactive editor as described above, and the dummy TCD cell placement unit 52 acquires the input setting information.

[0197] Step S72: The dummy TCD cell placement unit 52 retrieves the generation mode. The generation mode is specified by the user using, for example, an interactive editor. The generation mode includes, for example, an additional generation mode, a new generation mode, an automatic placement mode, and a manual placement mode.

[0198] Step S73: The dummy TCD cell placement unit 52 determines whether the generation mode of the dummy TCD cells is the automatic placement mode. If the dummy TCD cell placement unit 52 determines that the generation mode is the automatic placement mode, it performs the process of step S74, and if it determines that the generation mode is not the automatic placement mode, it performs the process of step S76.

[0199] Step S74: The dummy TCD cell placement unit 52 executes a program for performing batch processing, and performs the automatic placement processing of dummy TCD cells as shown in FIGS. 22 to 24 above. Step S75: The dummy TCD cell placement unit 52 receives a user instruction input using, for example, an interactive editor and determines whether or not to execute manual placement. If it determines to execute manual placement, the dummy TCD cell placement unit 52 resets the generation mode and performs the process of step S76. If it determines not to execute manual placement, it performs the process of step S97 in FIG. 33.

[0200] Step S76: The dummy TCD cell placement unit 52 acquires the optimum placement area. If the optimum placement area has not yet been detected, the dummy TCD cell placement unit 52 detects the optimum placement area by the processes shown in FIGS. 25 to 29.

[0201] Step S77: The dummy TCD cell placement unit 52 determines whether the generation mode of the dummy TCD cell is the addition generation mode. If it is determined to be the addition generation mode, the dummy TCD cell placement unit 52 keeps the internal database information related to the dummy TCD cell placement status created in the highest hierarchical DB 53, and performs the process of step S78. If it is determined not to be the addition generation mode (if it is determined to be the new generation mode), the dummy TCD cell placement unit 52 clears the internal data information stored in the highest hierarchical DB 53, and performs the process of step S79.

[0202] Step S78: The dummy TCD cell placement unit 52 checks whether or not a dummy TCD cell has already been placed in the optimum placement area. Step S79: The dummy TCD cell placement unit 52 displays the optimum placement areas on the map of the interactive editor (see FIG. 34, which will be described later). For example, the optimum placement areas where dummy TCD cells have already been placed, the optimum placement areas where dummy TCD cells have not yet been placed, and the reserved areas are displayed in different colors.

[0203] Step S80: The dummy TCD cell placement unit 52 determines whether the placement position of the dummy TCD cell has been deleted by manual work using the interactive editor. If the dummy TCD cell placement unit 52 determines that the placement position of the dummy TCD cell has been deleted, it performs the process of step S81. If the dummy TCD cell placement unit 52 determines that the placement position of the dummy TCD cell has not been deleted, it performs the process of step S83.

[0204] Step S81: The dummy TCD cell placement unit 52 keeps the information (pre-edit information) before the deletion of the placement positions of the dummy TCD cells, and then performs the process of step S82.

[0205] Step S82: The dummy TCD cell placement unit 52 performs a process of deleting the placement position of the dummy TCD cell and keeps the deletion information (post-edit information). After that, the process of step S93 in FIG.

[0206] Step S83: The dummy TCD cell placement unit 52 determines whether the dummy TCD cell has been moved manually using the interactive editor. If the dummy TCD cell placement unit 52 determines that the dummy TCD cell has been moved, it performs the process of step S84. If the dummy TCD cell placement unit 52 determines that the dummy TCD cell has not been moved, it performs the process of step S86.

[0207] Step S84: The dummy TCD cell placement unit 52 keeps the information before the dummy TCD cell is moved (pre-edit information), and then the process of step S85 is performed. Step S85: The dummy TCD cell placement unit 52 moves the dummy TCD cells and keeps information (post-edit information) about the placement positions after the movement. After that, the process of step S93 in FIG.

[0208] Step S86: The dummy TCD cell placement unit 52 determines whether or not a dummy TCD cell placement has been assigned (the placement position of the dummy TCD cell has been determined) by manual work using the interactive editor. If the dummy TCD cell placement unit 52 determines that a dummy TCD cell placement has been assigned, it performs the process of step S87, and if it determines that a dummy TCD cell placement has not been assigned, it performs the process of step S89.

[0209] Step S87: The dummy TCD cell placement unit 52 keeps the information before the dummy TCD cell placement is assigned (pre-edit information), and then the process of step S88 is performed. Step S88: The dummy TCD cell placement unit 52 performs an assignment process for dummy TCD cell placement, and keeps information (post-edit information) related to the placement position after assignment. Thereafter, the process of step S93 in FIG.

[0210] Step S89: The dummy TCD cell placement unit 52 determines whether the reserved area has been deleted manually using the interactive editor. If the dummy TCD cell placement unit 52 determines that the reserved area has been deleted, it performs the process of step S90. If the dummy TCD cell placement unit 52 determines that the reserved area has not been deleted, it performs the process of step S91.

[0211] Step S90: The dummy TCD cell placement unit 52 keeps the information (pre-edit information) of the selected reserved area before deletion, and then performs the process of step S93 in FIG. Step S91: The dummy TCD cell placement unit 52 determines whether or not a reserved area has been registered by manual work using an interactive editor. If the dummy TCD cell placement unit 52 determines that a reserved area has been registered, it performs the process of step S92. If the dummy TCD cell placement unit 52 determines that a reserved area has not been registered, it performs the process of step S96 in FIG. 33.

[0212] Step S92: The dummy TCD cell placement unit 52 performs a registration process for the reserved area and keeps the registered information (post-edit information). After that, the process of step S93 in FIG. 33 is performed.

[0213] Step S93: The dummy TCD cell placement unit 52 determines whether the edit target is a dummy TCD cell. If the determination results of the above-mentioned steps S80, S83, and S86 are "YES," it is determined that the edit target is a dummy TCD cell. If the dummy TCD cell placement unit 52 determines that the edit target is a dummy TCD cell, it performs the process of step S94, and if it determines that the edit target is not a dummy TCD cell, it performs the process of step S95.

[0214] Step S94: The dummy TCD cell placement unit 52 updates the dummy TCD cell information of the lowest hierarchy (information on the temporary placement position of the TCD cell (placement position of the dummy TCD cell) included in the check area information mentioned above) based on the pre-edit information and post-edit information.

[0215] Step S95: The dummy TCD cell placement unit 52 updates the information on the reserved area included in the check area information for the lowest layer in which the reserved area has been changed, and then performs the process of step S96.

[0216] Step S96: The dummy TCD cell placement unit 52 receives a user instruction input using, for example, an interactive editor, and determines whether or not to end the manual placement process. If the dummy TCD cell placement unit 52 determines that the manual placement process should be ended, it performs the process of step S97. If the dummy TCD cell placement unit 52 determines that the manual placement process should not be ended, it repeats the process from step S80.

[0217] Step S97: The dummy TCD cell placement unit 52 receives a user instruction input using, for example, an interactive editor, and determines whether or not to execute automatic placement of dummy TCD cells. If the dummy TCD cell placement unit 52 determines to execute automatic placement, the generation mode (additional generation mode, new generation mode, automatic placement mode) is reset, and the processing from step S73 is repeated. If the dummy TCD cell placement unit 52 determines not to execute automatic placement, the processing of step S98 is performed.

[0218] Step S98: The dummy TCD cell placement unit 52 determines whether the final change to the dummy TCD cell placement and the reserved area was made by manual placement. If the dummy TCD cell placement unit 52 determines that the final change was made by manual placement, it performs the process of step S99. If it determines that the final change was not made by manual placement, it ends the process.

[0219] Step S99: The dummy TCD cell placement unit 52 outputs the updated dummy TCD cell information or the check area information file including the information on the reserved area, and then the process ends.

[0220] The above processing order is an example, and the processing order may be changed as appropriate. FIG. 34 shows an example of the placement operation of a dummy TCD cell using the interactive editor.

[0221] First, a "Dummy TCD Window" such as that shown in Fig. 34 is displayed on the screen of the display 44a. When the user operates the input device 45a to select "PLACE" and press "EXEC," the "Dummy TCD PLACE Window" and "Dummy TCD MAP" are displayed.

[0222] When "New" (new generation mode) or "Add" (additional generation mode) is selected in the "Dummy TCD PLACE Window" and "OK" is pressed, a selection screen for unplaced dummy TCD cells is displayed. Here, any unplaced dummy TCD cell is selected, and "Asign" is pressed. The dummy TCD cell is placed in the optimal placement area, and the placement position of that dummy TCD cell is confirmed.

[0223] 34, "MODULE_A" and "MODULE_B," which represent the two lowest hierarchical levels, are placed in the highest hierarchical level using two instances each. For example, if a dummy TCD cell is placed in the optimal placement area of ​​the "MODULE_B" instance at the bottom left, the dummy TCD cell placement unit 52 also reflects the placement of the dummy TCD cell in other instances (bottom right instances) of "MODULE_B" in the same library.

[0224] An example of such a function (dummy TCD cell expansion function) will be further described below. FIG. 35 is a diagram showing an example of the development function of a dummy TCD cell. 35 shows an example of four instances in the lowest hierarchy. The nine dummy TCD cells placed in the bottom-left instance are deployed as deployed dummy TCD cells at corresponding positions in the other three instances by the function of the dummy TCD cell placement unit 52.

[0225] This eliminates the need for the user to place dummy TCD cells for all instances when verifying placement of dummy TCD cells in the highest hierarchy. Next, a detailed description will be given of the placement verification of the dummy TCD cells in the highest layer shown in Fig. 10. Below, the description will be divided into a case where the dummy TCD cell placement unit 52 automatically performs the placement verification of the dummy TCD cells and a case where the placement verification is performed using an interactive editor.

[0226] (Automatic placement verification of dummy TCD cells) 36 and 37 are flowcharts showing an example of the flow of automatic placement verification of dummy TCD cells.

[0227] Step S100: The dummy TCD cell placement unit 52 reads the design information of the highest hierarchy from the highest hierarchy DB 53. Step S101: The dummy TCD cell placement unit 52 reads the setting file (see FIG. 11) on the top layer side described above.

[0228] Step S102: The dummy TCD cell placement unit 52 sets the dummy TCD cell placement prohibition area specified in the setting file for the top layer. Step S103: If the top layer includes a plurality of bottom layers (modules), the dummy TCD cell placement unit 52 selects one of the bottom layers.

[0229] Step S104: The dummy TCD cell placement unit 52 selects one optimum placement area (dummy TCD cell placement area) in which a dummy TCD cell is placed in the selected lowest hierarchy. Step S105: The dummy TCD cell placement unit 52 determines whether the selected dummy TCD cell placement area satisfies the lower limit size of the aforementioned optimal placement area. If the dummy TCD cell placement unit 52 determines that the dummy TCD cell placement area satisfies the lower limit size of the optimal placement area, it performs the process of step S107. If it determines that the dummy TCD cell placement area does not satisfy the lower limit size of the optimal placement area, it performs the process of step S106.

[0230] Step S106: The dummy TCD cell placement unit 52 sets an error flag indicating the occurrence of an error. Step S107: The dummy TCD cell placement unit 52 determines whether the dummy TCD cell placed in the selected dummy TCD cell placement area overlaps the boundary of the check window (divided area). If the dummy TCD cell placement unit 52 determines that the dummy TCD cell overlaps the boundary of the check window, it performs the process of step S108, and if it determines that the dummy TCD cell does not overlap, it performs the process of step S109.

[0231] Step S108: The dummy TCD cell placement unit 52 sets an error flag indicating the occurrence of an error, invalidates the optimal placement area that is the selected dummy TCD cell placement area, and further invalidates the dummy TCD cells placed in that dummy TCD cell placement area.

[0232] Step S109: The dummy TCD cell placement unit 52 determines whether the dummy TCD cell placed in the selected dummy TCD cell placement area overlaps with the placement prohibition area. If the dummy TCD cell placement unit 52 determines that the dummy TCD cell overlaps with the placement prohibition area, it performs the process of step S110. If it determines that the dummy TCD cell does not overlap with the placement prohibition area, it performs the process of step S111.

[0233] Step S110: The dummy TCD cell placement unit 52 sets an error flag indicating the occurrence of an error, invalidates the optimal placement area that is the selected dummy TCD cell placement area, and further invalidates the dummy TCD cells placed in that dummy TCD cell placement area.

[0234] Step S111: The dummy TCD cell placement unit 52 determines whether or not all dummy TCD cell placement areas have been selected in the selected lowest hierarchy. If the dummy TCD cell placement unit 52 determines that all dummy TCD cell placement areas have been selected, it performs the process of step S112 in Fig. 37, and if it determines that all dummy TCD cell placement areas have not been selected, it repeats the process from step S104.

[0235] Step S112: The dummy TCD cell placement unit 52 calculates the placement rate of the dummy TCD cells. Step S113: The dummy TCD cell placement unit 52 determines whether the calculated placement rate of the dummy TCD cells satisfies the upper limit of the placement rate specified in the setting file. If the dummy TCD cell placement unit 52 determines that the placement rate satisfies the upper limit, it performs the process of step S115. If the dummy TCD cell placement unit 52 determines that the placement rate does not satisfy the upper limit, it performs the process of step S114.

[0236] Step S114: The dummy TCD cell placement unit 52 sets an error flag indicating the occurrence of an error that the upper limit of the placement rate is not satisfied. Step S115: The dummy TCD cell placement unit 52 determines whether the calculated placement rate of the dummy TCD cells satisfies the lower limit of the placement rate specified in the setting file. If the dummy TCD cell placement unit 52 determines that the placement rate satisfies the lower limit, it performs the process of step S117. If the dummy TCD cell placement unit 52 determines that the placement rate does not satisfy the lower limit, it performs the process of step S116.

[0237] Step S116: The dummy TCD cell placement unit 52 sets an error flag indicating the occurrence of an error that the lower limit of the placement rate is not satisfied. Step S117: The dummy TCD cell placement unit 52 calculates the creation rate of the reserved area.

[0238] Step S118: The dummy TCD cell placement unit 52 determines whether the calculated reserve area creation rate satisfies the creation rate specified in the setting file. If the dummy TCD cell placement unit 52 determines that the calculated reserve area creation rate satisfies the specified creation rate, it performs the process of step S120. If it determines that the calculated reserve area creation rate does not satisfy the specified creation rate, it performs the process of step S119.

[0239] Step S119: The dummy TCD cell placement unit 52 sets an error flag indicating the occurrence of an error that the designated creation ratio is not met. Step S120: The dummy TCD cell placement unit 52 determines whether or not all of the lowest hierarchical layers have been selected. If the dummy TCD cell placement unit 52 determines that all of the lowest hierarchical layers have been selected, it performs the process of step S121. If it determines that all of the lowest hierarchical layers have not been selected, it repeats the process from step S103.

[0240] Step S121: The dummy TCD cell placement unit 52 checks whether the placement rules for the dummy TCD cells in the highest hierarchy are satisfied. Step S122: The dummy TCD cell placement unit 52 outputs the result of placement verification to the output unit 55. Then, the verification process ends.

[0241] The above processing order is an example, and the processing order may be changed as appropriate. FIG. 38 is a diagram illustrating an example of the verification result to be output. The verification results include the "TCD placement rule check results" (circle (indicating no errors) or cross (indicating errors)) checked in the processing of step S121, their details, and information about the verification results for each lowest hierarchy.

[0242] (Verification of placement of dummy TCD cells using an interactive editor) FIG. 39 is a flowchart showing an example of the flow of placement verification of dummy TCD cells using an interactive editor.

[0243] Step S 130 : The dummy TCD cell placement unit 52 reads the design information of the highest hierarchy from the highest hierarchy DB 53 . Step S131: When parameter setting is selected on the screen of the interactive editor, the dummy TCD cell placement unit 52 recognizes it.

[0244] Step S132: The dummy TCD cell placement unit 52 reads the setting file on the top layer side described above. Alternatively, the setting information is input using, for example, an interactive editor as described above, and the dummy TCD cell placement unit 52 acquires the input setting information.

[0245] Step S133: When the check mode is selected on the screen of the interactive editor, the dummy TCD cell placement unit 52 recognizes this. For example, when "CHECK" is selected and "EXEC" is pressed in the "Dummy TCD Window" shown in Fig. 34, the selection of check mode is recognized. Alternatively, when "EXEC" is pressed in the "Dummy TCD Check" column of the "Dummy TCD PLACE Window" shown in Fig. 34, the selection of check mode is also recognized.

[0246] Step S134: The dummy TCD cell placement unit 52 executes the automatic placement verification process as shown in FIGS. 36 and 37 above, using a program for performing batch processing. Step S135: The dummy TCD cell placement unit 52 causes the output unit 55 to emphasize (highlight, etc.) the dummy TCD cells that have been invalidated by placement verification, and then the process ends.

[0247] The above processing order is an example, and the processing order may be changed as appropriate. FIG. 40 is a diagram showing an example of a display of the verification result of the placement verification using the interactive editor. The "Dummy TCD MAP" shows examples of invalid dummy TCD cells that overlap the boundaries of check windows (division areas) and invalid dummy TCD cells that overlap prohibited placement areas. These invalid dummy TCD cells are highlighted by color to distinguish them from valid dummy TCD cells.

[0248] Next, the details of the TCD cell placement process in the lowest hierarchical layer shown in Fig. 10 will be explained. Below, the explanation will be divided into two cases: when the TCD cell placement unit 54a1 of the module 54a shown in Fig. 9 automatically places the TCD cell, and when the TCD cell is placed using an interactive editor. The placement process performed by the TCD cell placement unit 54b1 of the module 54b and the TCD cell placement unit 54c1 of the module 54c is the same as the placement process performed by the TCD cell placement unit 54a1.

[0249] (Automatic placement of TCD cells) 41 and 42 are flowcharts showing an example of the flow of automatic placement processing of TCD cells in the lowest hierarchy.

[0250] Step S140: The TCD cell placement unit 54a1 reads the design information of the lowest hierarchy from the lower hierarchy DB 54a2. Step S141: The TCD cell placement unit 54a1 reads the file of check area information (see FIG. 21) output from the highest layer side.

[0251] Step S142: The TCD cell placement unit 54a1 acquires a preset or input overlap cancellation parameter. The overlap cancellation parameter indicates whether or not the movement of another cell is permitted. The overlap cancellation parameter may be set for each cell.

[0252] Step S143: The TCD cell placement unit 54a1 acquires a placement mode that has been set in advance or input. The placement mode includes a repair mode and a new placement mode. Step S144: If an internal database related to TCD cells has been created in the lower-level DB 54a2, the TCD cell placement unit 54a1 refers to the internal database and determines whether the TCD cells have been placed according to the check area information. If the TCD cell placement unit 54a1 determines that the TCD cells have been placed according to the check area information, it performs the process of step S145. If it determines that the TCD cells have not been placed according to the check area information, it performs the process of step S146.

[0253] Step S145: The TCD cell placement unit 54a1 determines whether the placement mode is the new placement mode. If the TCD cell placement unit 54a1 determines that the placement mode is the new placement mode, it performs the process of step S146. If the TCD cell placement unit 54a1 determines that the placement mode is not the new placement mode, it performs the process of step S148.

[0254] Step S146: If there is an existing TCD cell, the TCD cell placement unit 54a1 deletes the existing TCD cell from the internal database. Step S147: The TCD cell placement unit 54a1 creates an internal database relating to the TCD cells based on the check area information.

[0255] Step S148: The TCD cell placement unit 54a1 selects one TCD cell from the plurality of TCD cells to be placed, based on the check area information. Step S149: The TCD cell placement unit 54a1 determines whether the selected TCD cell has not yet been placed. If the TCD cell placement unit 54a1 determines that the selected TCD cell has not yet been placed, it performs the process of step S150. If the TCD cell placement unit 54a1 determines that the selected TCD cell has already been placed, it performs the process of step S151.

[0256] Step S150: The TCD cell placement unit 54a1 automatically places the selected TCD cell in a site area near the center of one of the optimum placement areas based on the check area information. Step S151: The TCD cell placement unit 54a1 determines whether the placement position of the TCD cell is within the optimal placement area. If the TCD cell placement unit 54a1 determines that the placement position of the TCD cell is within the optimal placement area, it performs the process of step S152 in Fig. 42, and if it determines that the placement position is not within the optimal placement area, it performs the process of step S150.

[0257] Step S152: The TCD cell placement unit 54a1 determines whether the placed TCD cell overlaps with another cell. If the TCD cell placement unit 54a1 determines that the placed TCD cell overlaps with another cell, it turns on the overlap error flag and performs the process of step S153. If the TCD cell placement unit 54a1 determines that the placed TCD cell does not overlap with another cell, it turns off the overlap error flag and performs the process of step S161.

[0258] Step S153: The TCD cell placement unit 54a1 searches for an empty space in which a TCD cell can be placed within the optimum placement area, and performs a process to remove the overlap. Step S154: The TCD cell placement unit 54a1 determines whether the overlap has been removed. If the TCD cell placement unit 54a1 determines that the overlap has been removed, it turns off the overlap error flag and performs the process of step S161. If the TCD cell placement unit 54a1 determines that the overlap has not been removed, it leaves the overlap error flag on and performs the process of step S155.

[0259] Step S155: The TCD cell placement unit 54a1 checks the overlap cancellation parameters and determines whether the movement of the other cell is permitted. If the TCD cell placement unit 54a1 determines that the movement of the other cell is permitted, it performs the process of step S156, and if it determines that the movement of the other cell is not permitted, it performs the process of step S159.

[0260] Step S156: The TCD cell placement unit 54a1 moves cells other than those required to have fixed placement positions, and performs a process to remove overlaps, in order to create free space in which a TCD cell can be placed within the optimal placement area.

[0261] Step S157: The TCD cell placement unit 54a1 determines whether the overlap has been removed. If the TCD cell placement unit 54a1 determines that the overlap has been removed, it turns off the overlap error flag and performs the process of step S161. If the TCD cell placement unit 54a1 determines that the overlap has not been removed, it leaves the overlap error flag on and performs the process of step S158.

[0262] Step S158: The TCD cell placement unit 54a1 checks the check area information and determines whether or not there is a reserved area. If it determines that there is a reserved area, the TCD cell placement unit 54a1 performs the process of step S159. If it determines that there is no reserved area, the TCD cell placement unit 54a1 performs the process of step S161.

[0263] Step S159: The TCD cell placement unit 54a1 registers the unused reserve area with the largest area as the optimum placement area. Step S160: The TCD cell placement unit 54a1 sets a use flag indicating that the reserved area registered as the optimum placement area is already in use, and then repeats the process from step S149 in FIG.

[0264] Step S161: The TCD cell placement unit 54a1 registers the TCD cell, the optimum placement area where the TCD cell has been placed, the placement position of the TCD cell, and the overlap error flag. Step S162: The TCD cell placement unit 54a1 determines whether all TCD cells have been selected. If the TCD cell placement unit 54a1 determines that all TCD cells have been selected, it performs the process of step S163. If the TCD cell placement unit 54a1 determines that all TCD cells have not been selected, it repeats the process from step S148 in FIG. 41.

[0265] Step S163: If the overlap error flag is on, the TCD cell placement unit 54a1 outputs overlap error information indicating that an overlap error has occurred.

[0266] Step S164: The TCD cell placement unit 54a1 stores the TCD cell, the optimum placement area where the TCD cell was placed, the placement position of the TCD cell, and other TCD placement results in an internal database related to the TCD cell, after which the TCD cell placement process is completed.

[0267] The above processing order is an example, and the processing order may be changed as appropriate. (TCD cell placement process using an interactive editor) 43, 44 and 45 are flowcharts showing an example of the flow of a TCD cell placement process using an interactive editor.

[0268] The processing in steps S170 to S173 is the same as the processing in steps S140 to S143 shown in FIG. Step S174: The TCD cell placement unit 54a1 acquires a placement method that has been set in advance or input. The placement method includes automatic placement and manual placement.

[0269] Step S175: The TCD cell placement unit 54a1 determines whether the placement method is automatic placement. If the TCD cell placement unit 54a1 determines that the placement method is automatic placement, it performs the process of step S176, and if it determines that the placement method is not automatic placement, it performs the process of step S178.

[0270] Step S176: The TCD cell placement unit 54a1 executes a program for performing batch processing, and performs the automatic placement processing of TCD cells as shown in FIGS. 41 and 42 above. Step S177: The TCD cell placement unit 54a1 receives the input user instruction and determines whether or not to execute manual placement. If it determines to execute manual placement, the TCD cell placement unit 54a1 resets the generation mode and performs the process of step S178. If it determines not to execute manual placement, it performs the process of step S193 in FIG. 44.

[0271] Step S178: If an internal database related to TCD cells has been created in the lower-level DB 54a2, the TCD cell placement unit 54a1 refers to the internal database and determines whether the TCD cells have been placed according to the check area information. If the TCD cell placement unit 54a1 determines that the TCD cells have been placed according to the check area information, it performs the process of step S179. If the TCD cell placement unit 54a1 determines that the TCD cells have not been placed according to the check area information, it performs the process of step S180.

[0272] Step S179: The TCD cell placement unit 54a1 determines whether the placement mode is the new placement mode. If the TCD cell placement unit 54a1 determines that the placement mode is the new placement mode, it performs the process of step S180. If the TCD cell placement unit 54a1 determines that the placement mode is not the new placement mode, it performs the process of step S182.

[0273] Step S180: If there is an existing TCD cell, the TCD cell placement unit 54a1 deletes the existing TCD cell from the internal database. Step S181: The TCD cell placement unit 54a1 creates an internal database relating to the TCD cells based on the check area information.

[0274] Step S182: The TCD cell placement unit 54a1 executes placement verification of the TCD cell. Details of the placement verification will be described later. After that, the process of step S183 in FIG. 44 is performed. Step S183: The TCD cell placement unit 54a1 selects one TCD cell from the plurality of TCD cells to be placed, based on the check area information.

[0275] Step S184: The TCD cell placement unit 54a1 determines whether the selected TCD cell has not yet been placed. If the TCD cell placement unit 54a1 determines that the selected TCD cell has not yet been placed, it performs the process of step S185. If the TCD cell placement unit 54a1 determines that the selected TCD cell has already been placed, it performs the process of step S186.

[0276] Step S185: Using the interactive editor, the TCD cells are manually placed. The TCD cell placement unit 54a1 acquires information such as the placement positions of the manually placed TCD cells.

[0277] Step S186: The TCD cell placement unit 54a1 determines whether the placed TCD cell overlaps with another cell. If the TCD cell placement unit 54a1 determines that the placed TCD cell overlaps with another cell, it turns on the overlap error flag and performs the process of step S187. If the TCD cell placement unit 54a1 determines that the placed TCD cell does not overlap with another cell, it turns off the overlap error flag and performs the process of step S191.

[0278] Step S187: The TCD cell placement unit 54a1 determines whether there is free space in the optimum placement area where a TCD cell can be placed. If the TCD cell placement unit 54a1 determines that there is free space in the optimum placement area where a TCD cell can be placed, it turns off the overlap error flag and performs the process of step S191. If the TCD cell placement unit 54a1 determines that there is no free space in the optimum placement area where a TCD cell can be placed, it leaves the overlap error flag on and performs the process of step S188.

[0279] Step S188: The TCD cell placement unit 54a1 checks the overlap cancellation parameters and determines whether the movement of the other cell is permitted. If the TCD cell placement unit 54a1 determines that the movement of the other cell is permitted, it performs the process of step S189, and if it determines that the movement of the other cell is not permitted, it performs the process of step S192.

[0280] Step S189: The TCD cell placement unit 54a1 moves cells other than those required to have fixed placement positions, and performs a process to remove overlaps, in order to create free space in which a TCD cell can be placed within the optimal placement area.

[0281] Step S190: The TCD cell placement unit 54a1 determines whether the overlap has been removed. If the TCD cell placement unit 54a1 determines that the overlap has been removed, it turns off the overlap error flag and performs the process of step S191. If the TCD cell placement unit 54a1 determines that the overlap has not been removed, it leaves the overlap error flag on and performs the process of step S192.

[0282] Step S191: The TCD cell placement unit 54a1 determines the placement position of the TCD cell in accordance with the user's instructions input using the interactive editor, and then performs the process of step S195 in FIG.

[0283] Step S192: The TCD cell placement unit 54a1 checks the check area information and determines whether or not there is a reserved area. If it determines that there is a reserved area, the TCD cell placement unit 54a1 performs the process of step S193, and if it determines that there is no reserved area, the TCD cell placement unit 54a1 performs the process of step S195.

[0284] Step S193: The TCD cell placement unit 54a1 registers the unused reserve area with the largest area as the optimum placement area. Step S194: The TCD cell placement unit 54a1 sets a use flag indicating that the reserved area registered as the optimum placement area is already in use, and then repeats the process from step S184.

[0285] Step S195: The TCD cell placement unit 54a1 registers the TCD cell, the optimum placement area where the TCD cell has been placed, the placement position of the TCD cell, and the overlap error flag. Step S196: The TCD cell placement unit 54a1 receives a user instruction input using, for example, an interactive editor, and determines whether to execute automatic placement of TCD cells. If the TCD cell placement unit 54a1 determines to execute automatic placement, it returns to the processing of step S176 in Fig. 43, and if it determines not to execute automatic placement, it performs the processing of step S197.

[0286] Step S197: The TCD cell placement unit 54a1 determines whether all TCD cells have been selected. If the TCD cell placement unit 54a1 determines that all TCD cells have been selected, it performs the process of step S198. If the TCD cell placement unit 54a1 determines that all TCD cells have not been selected, it repeats the process from step S183 in FIG. 44.

[0287] Step S198: If the overlap error flag is on, the TCD cell placement unit 54a1 outputs overlap error information indicating that an overlap error has occurred.

[0288] Step S199: The TCD cell placement unit 54a1 stores the TCD cell, the optimum placement area where the TCD cell was placed, the placement position of the TCD cell, and other TCD placement results in an internal database related to the TCD cell, after which the TCD cell placement process is completed.

[0289] The above processing order is an example, and the processing order may be changed as appropriate. 46 and 47 are diagrams showing an example of the placement operation of a TCD cell using the interactive editor.

[0290] First, the "TCD Window" as shown in Fig. 46 is displayed on the screen of the display 44a. When the user operates the input device 45a to select "Parameter Set" and press "EXEC," the "TCD Module Setting Window" is displayed.

[0291] When the file name of the check area information is entered in the "TCD_AREA_IN_FILE" field of the "TCD Module Setting Window" and "OK" is pressed, the check area information is displayed on the screen.

[0292] Next, when "PLACE" is selected in the "TCD Window" and "EXEC" is pressed as shown in FIG. 47, the "TCD PLACE Window" and "TCD MAP" are displayed.

[0293] When "New" (new generation mode) or "Add" (additional generation mode) is selected in the "TCD PLACE Window" and "OK" is pressed, a selection screen for unplaced TCD cells is displayed. Here, any unplaced TCD cell can be selected and "Asign" pressed. The TCD cell is placed in the optimal placement area, and the placement position of that TCD cell is confirmed.

[0294] For example, when an optimum placement area is selected, the selected optimum placement area is expanded as shown in Fig. 47. The example in Fig. 47 shows an example in which a TCD cell (TCD cell with the TCD cell name "TCD_00001") is placed between two logic cells whose placement is fixed.

[0295] Incidentally, the TCD cell placement unit 54a1 can carry out the following placement corrections, including the above-mentioned overlap cancellation process. FIG. 48 is a diagram showing an example of correcting the placement of TCD cells.

[0296] Case 1 shows an example of a placement correction that aligns a TCD cell properly with the grid of the site area when the TCD cell is placed off the grid of the site area. This placement correction is called "sucking into the site area" (or "legalizing").

[0297] Case 2 shows an example of placement modification in which, when a logic cell exists at the placement position of a TCD cell, the TCD cell is moved to an empty space within the optimal placement area. This placement modification is the aforementioned overlap elimination process.

[0298] Case 3 is, for example, when, in the latter phase of packaging design (after TCD cells have been placed), you want to move a logic cell closer to another logic cell to satisfy timing constraints, but there is no space available because the TCD cell has already been placed. In this case, you can move the TCD cell's placement position to an empty space within the optimal placement area and move the logic cell to the area where the TCD cell was placed, thereby achieving routing that satisfies the timing constraints.

[0299] Next, details of the placement verification of the TCD cell in the lowest layer shown in Fig. 10 will be explained. Below, the explanation will be divided into a case where the TCD cell placement unit 54a1 performs the TCD cell placement verification automatically and a case where the placement verification is performed using an interactive editor. Note that the placement verification performed by the TCD cell placement unit 54b1 of module 54b and the TCD cell placement unit 54c1 of module 54c is the same as the placement verification performed by the TCD cell placement unit 54a1.

[0300] (Automatic placement verification of TCD cells) FIG. 49 is a flowchart showing an example of the flow of automatic placement verification of TCD cells. Step S200: The TCD cell placement unit 54a1 reads the design information of the lowest hierarchy from the lower hierarchy DB 54a2.

[0301] Step S201: The TCD cell placement unit 54a1 reads the file of check area information output from the highest layer side. Step S202: The TCD cell placement unit 54a1 determines whether the number of TCD cells is placed according to the check area information. If the TCD cell placement unit 54a1 determines that the number of TCD cells is placed according to the check area information, it performs the process of step S204. If the number of TCD cells is not placed according to the check area information, it performs the process of step S203.

[0302] Step S203: The TCD cell placement unit 54a1 sets a number error flag indicating that an error has occurred regarding the number of TCD cells, and calculates the number of shortages, excesses, etc. Step S204: The TCD cell placement unit 54a1 selects one TCD cell registered in the internal database related to the TCD cell generated in the process of step S181 in FIG.

[0303] Step S205: The TCD cell placement unit 54a1 determines whether the selected TCD cell is unplaced. If the TCD cell placement unit 54a1 determines that the selected TCD cell is unplaced, it performs the process of step S206. If the TCD cell placement unit 54a1 determines that the selected TCD cell is not unplaced, it performs the process of step S207.

[0304] Step S206: The TCD cell placement unit 54a1 sets an unplaced error flag indicating that a TCD cell has not been placed, and counts the number of unplaced TCD cells. Step S207: The TCD cell placement unit 54a1 determines whether the selected TCD cell is placed within the optimal placement area. If the TCD cell placement unit 54a1 determines that the selected TCD cell is placed within the optimal placement area, it performs the process of step S209. If the TCD cell placement unit 54a1 determines that the selected TCD cell is not placed within the optimal placement area, it performs the process of step S208.

[0305] Step S208: The TCD cell placement unit 54a1 sets an out-of-area placement error flag indicating that the TCD cell is not placed within the optimum placement area, and counts the number of TCD cells that are not placed within the optimum placement area.

[0306] Step S209: The TCD cell placement unit 54a1 determines whether all TCD cells have been selected. If the TCD cell placement unit 54a1 determines that all TCD cells have been selected, it performs the process of step S210. If the TCD cell placement unit 54a1 determines that all TCD cells have not been selected, it repeats the process from step S204.

[0307] Step S210: The TCD cell placement unit 54a1 outputs the placement verification result to the output unit 55. After that, the verification process ends. The above processing order is an example, and the processing order may be changed as appropriate.

[0308] FIG. 50 is a diagram showing an example of the verification result to be output. The verification results include information such as the "TOTAL check result" (a circle (indicating no errors) or an X (indicating errors)) and its details.

[0309] (TCD cell placement verification using an interactive editor) FIG. 51 is a flowchart showing an example of the flow of TCD cell placement verification using an interactive editor.

[0310] Step S220: The TCD cell placement unit 54a1 reads the design information of the lowest hierarchy from the lower hierarchy DB 54a2. Step S221: The TCD cell placement unit 54a1 reads the file of check area information output from the highest layer side.

[0311] Step S222: The TCD cell placement unit 54a1 determines whether or not a placement check mode for the TCD cell has been selected using the interactive editor. When the placement check mode has been selected on the screen of the interactive editor, the TCD cell placement unit 54a1 recognizes this.

[0312] For example, when "CHECK" is selected and "EXEC" is pressed in the "TCD Window" shown in Fig. 46, the selection of the placement check mode is recognized. Alternatively, when "EXEC" is pressed in the "TCD Check" column of the "TCD PLACE Window" shown in Fig. 47, the selection of the placement check mode is also recognized.

[0313] If the TCD cell placement unit 54a1 determines that the TCD cell placement check mode has been selected, it performs the process of step S223, and if it determines that the TCD cell placement check mode has not been selected, it ends the process.

[0314] Step S223: The TCD cell placement unit 54a1 executes the automatic placement verification process as shown in FIG. 49 above, using a program for performing batch processing. Step S224: The TCD cell placement unit 54a1 causes the output unit 55 to highlight (e.g., highlight) error TCD cells (TCD cells that are not within the optimal placement area or TCD cells that overlap other cells) and the optimal placement area. Then, the process ends.

[0315] The above processing order is an example, and the processing order may be changed as appropriate. FIG. 52 is a diagram showing an example of a display of the verification result of the placement verification using the interactive editor. In the "TCD MAP," TCD cells that are not within the optimal placement area or that overlap other cells (RAM in the example of FIG. 52) are highlighted as error TCD cells.

[0316] The design device 40 and design method of the second embodiment described above also achieve the same effects as those of the design device 40 and design method of the first embodiment. That is, the occurrence of TCD cells that are invalidated in the highest layer is suppressed, and the number of rearrangements in the lowest layer, the number of assembly operations in the highest layer, and the number of re-verifications in the highest layer can be suppressed. This makes it possible to shorten the design period (design TAT) in hierarchical design.

[0317] Furthermore, by optimizing the placement area so that TCD cells are not invalid at the top level, the number of TCD cells can be minimized. This eliminates the need to place excessive TCD cells at the bottom level to prevent verification errors during placement verification at the top level, improving placement and routing.

[0318] Furthermore, even if a TCD cell overlaps with the placement area of ​​another cell in the lowest layer, as long as the placement position is adjusted within the optimal placement area, the TCD cell will not be invalidated even after assembly in the highest layer. This makes it easier to correct the placement position and prevents the correction of the placement position from lengthening the design TAT. Furthermore, as shown in Figure 48, the placement of the TCD cell can be corrected even in the later phases of implementation design (after the TCD cell has been placed), which improves placement and wiring.

[0319] As mentioned above, the above processing contents can be realized by causing the design device 40 to execute a program. The program can be recorded on a computer-readable recording medium (e.g., recording medium 46a). Examples of recording media that can be used include magnetic disks, optical disks, magneto-optical disks, and semiconductor memories. Magnetic disks include FDs and HDDs. Optical disks include CDs, CD-R (Recordable) / RW (Rewritable), DVDs, and DVD-R / RWs. The program may be recorded on a portable recording medium and distributed. In this case, the program may be copied from the portable recording medium to another recording medium (e.g., HDD 43) and executed.

[0320] While one aspect of the design program, design method, and design apparatus of the present invention has been described above based on the embodiment, these are merely examples and the present invention is not limited to the above description. [Explanation of symbols]

[0321] 10 Design equipment 11 Storage section 11a Top layer design information 11b Bottom layer design information 12 Processing section 15-17 instances 15a~17a divided area 16b,17b contact area 15c~17c Optimal placement area 15d~17d Dummy TCD cell

Claims

1. A design program that causes a computer to execute a process for performing hierarchical design, reading first design information of the top layer from a storage unit, and dividing the top layer into a plurality of division regions based on the first design information; detecting an overlapping area where all divided areas at corresponding positions among the plurality of instances overlap when the plurality of instances at the lowest layer included in the highest layer are overlapped; setting a temporary placement position for temporarily placing an inspection cell used to inspect manufacturing variations in minimum line widths for the overlapping region of each of the plurality of instances; outputting information indicating the overlapping area and the temporary placement position; A design program that causes the computer to execute the process.

2. determining one of the instances as a reference instance; detecting, in each of the instances other than the reference instance among the plurality of instances, a contact area consisting of one or more divided areas that contacts a first divided area included in the reference instance among the plurality of divided areas when the plurality of instances arranged in the same orientation are superimposed on one another; causing the computer to execute a process; the divided areas at corresponding positions among the plurality of instances are a second divided area that has the largest overlapping area with the first divided area among the one or more divided areas included in the contact area, and the first divided area; The design program according to claim 1 .

3. placing a pseudo cell having the same size as the inspection cell in the overlapping region of each of the instances; performing placement verification of the test cell in the top layer including the plurality of instances after placement of the pseudo cell; 3. The design program according to claim 1, wherein the program causes the computer to execute processing.

4. When the pseudo cell is placed in the overlapping area of ​​a first instance among the plurality of instances based on a user input, the pseudo cell is also placed in the overlapping areas of instances other than the first instance among the plurality of instances.

4. The design program according to claim 3, which causes the computer to execute processing.

5. placing the inspection cell at the temporary placement position based on information indicating the overlapping region and the temporary placement position; 5. The design program according to claim 1, which causes the computer to execute processing.

6. If a cell has already been placed at the temporary placement position in the lowest layer based on information indicating the overlapping region and the temporary placement position, the inspection cell is placed in an empty space in the overlapping region.

5. The design program according to claim 1, which causes the computer to execute processing.

7. correcting the placement position of the inspection cell when the temporary placement position in the lowest layer is displaced from a site area, which is a cell placement area, based on information indicating the overlapping area and the temporary placement position; 5. The design program according to claim 1, which causes the computer to execute processing.

8. acquiring information representing a placement prohibition area in which placement of the inspection cell is prohibited; deleting the overlapping area that overlaps with the placement prohibition area; The design program according to any one of claims 1 to 7, which causes the computer to execute processing.

9. When a plurality of overlapping areas including the overlapping area are detected in the lowest layer, information indicating that a predetermined proportion of the overlapping areas among the plurality of overlapping areas are reserve areas for which the temporary placement position is not set is output. The design program according to any one of claims 1 to 8, which causes the computer to execute processing.

10. A design method for performing hierarchical design, comprising: The computer reading first design information of the highest hierarchy from a memory, and dividing the highest hierarchy into a plurality of division regions based on the first design information; detecting an overlapping area where all divided areas at corresponding positions among the plurality of instances overlap when the plurality of instances at the lowest layer included in the highest layer are overlapped; setting a temporary placement position for temporarily placing an inspection cell used to inspect manufacturing variations in minimum line widths for the overlapping region of each of the plurality of instances; outputting information indicating the overlapping area and the temporary placement position; How to design the process.

11. A design device for performing hierarchical design, a storage unit that stores first design information of the highest hierarchy; a processing unit that reads the first design information from a storage unit, divides the top layer into a plurality of divided regions based on the first design information, detects overlapping regions where all divided regions at corresponding positions between a plurality of instances of a bottom layer included in the top layer overlap when the plurality of instances are overlapped, sets temporary placement positions for temporarily placing inspection cells used to inspect manufacturing variations in minimum line widths for the overlapping regions of the plurality of instances, and outputs information indicating the overlapping regions and the temporary placement positions; A design device having:

Images