Nitride semiconductor device manufacturing method and nitride semiconductor device

Abstract

To provide a method for manufacturing a nitride semiconductor device capable of forming a highly concentrated P-type region, and a nitride semiconductor device.SOLUTION: A method for manufacturing a nitride semiconductor device includes: a step of forming N-type regions in a nitride semiconductor layer; a step of implanting ions of an acceptor element into a region under the N-type regions in the nitride semiconductor layer; and a step of forming a first P-type region under the N-type regions by subjecting the nitride semiconductor layer in which the N-type regions are formed and into which ions of the acceptor element are implanted to heat treatment and activating the acceptor element. In the step of forming the N-type regions, ions of a donor element are implanted to the nitride semiconductor layer at a high concentration in such a way that concentration of the donor element in the N-type regions has a value equal to or greater than concentration of the acceptor element in the first P-type region. In the step of implanting ions of the acceptor element into a region under the N-type regions, ions of the acceptor element are implanted in such a way that concentration of the acceptor element in the first P-type region is 1×1019 cm-3 or more and 1×1021 cm-3 or less.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device. [Background technology]

[0002] Nitride semiconductor devices having a vertical MOS (Metal Oxide Semiconductor) structure are known (see, for example, Patent Document 1). In addition, in nitride semiconductor devices, it is possible to control the P-type conductivity by using magnesium (Mg) as a dopant (see, for example, Patent Document 2).

[0003] To achieve good ohmic contact in nitride semiconductor devices, it is necessary to selectively form a high-concentration P-type region in the nitride semiconductor. Ion implantation is a desirable method for selectively forming a P-type region from the viewpoints of cost, productivity, and reliability. However, when high-concentration Mg ions are implanted into a nitride semiconductor and heat treatment is performed at a high temperature exceeding 1300°C to activate the Mg, the Mg segregates into rod-like structures at high density. When Mg segregates into rod-like structures at high density, the Mg concentration decreases in regions other than the segregated regions (see, for example, Non-Patent Document 1). Furthermore, when heat treatment is performed at a high temperature exceeding 1400°C under an ultra-high pressure atmosphere, the Mg diffuses deeply, resulting in a decrease in concentration (see, for example, Non-Patent Document 2). For this reason, it has been difficult to form a high-concentration P-type region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-096744 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-086698 [Non-patent literature]

[0005] [Non-Patent Document 1] Kumar et.al.,J.Appl.Phys.126(2019)235704. [Non-patent document 2] H.Sakurai et.al.,Appl.Phys.Lett. 115,142104(2019). [Non-patent document 3] G. Miceli, A. Pasquarello PRB (2016). Summary of the Invention [Problem to be solved by the invention]

[0006] When Mg is activated by heat treatment to form a P-type region, the Fermi level of the P-type region approaches the valence band. When the Fermi level approaches the valence band, the formation energy of Mg acceptors (i.e., the energy required to insert Mg into the Ga site of GaN) increases, making the activation of Mg unstable (see, for example, Non-Patent Document 3). The high-density segregation of Mg described above is thought to occur when the activation of Mg becomes unstable, making it easier for Mg to segregate through defects.

[0007] The present invention was made through extensive research by the inventors based on this idea, and aims to provide a method for manufacturing a nitride semiconductor device that is capable of forming a highly-doped P-type region, and a nitride semiconductor device. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, a method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes the steps of: forming an N-type region in a nitride semiconductor layer; ion-implanting an acceptor element into a region of the nitride semiconductor layer located below the N-type region; and forming a first P-type region located below the N-type region by performing a heat treatment on the nitride semiconductor layer in which the N-type region has been formed and into which the acceptor element has been ion-implanted to activate the acceptor element. In the step of forming the N-type region, the donor element is ion-implanted into the nitride semiconductor layer at a high concentration so that the concentration of the donor element in the N-type region is equal to or greater than the concentration of the acceptor element in the first P-type region. In the step of ion-implanting the acceptor element into the region located below the N-type region, the concentration of the acceptor element in the first P-type region is 1×10 19 cm -3 More than 1×10 21 cm -3 The acceptor element is ion-implanted so as to satisfy the following conditions.

[0009] A nitride semiconductor device according to one aspect of the present invention includes a nitride semiconductor layer, an N-type region provided on one surface of the nitride semiconductor layer, and a first P-type region provided on the one surface of the nitride semiconductor layer and located below the N-type region. The concentration of the donor element in the N-type region is equal to or greater than the concentration of the acceptor element in the first P-type region. The concentration of the acceptor element in the first P-type region is 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a nitride semiconductor device manufacturing method capable of forming a highly doped P-type region, and a nitride semiconductor device. [Brief explanation of the drawings]

[0011] [Figure 1]FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a plan view showing a configuration example of the vertical MOSFET according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a cross-sectional view showing an example of the configuration of a vertical MOSFET according to the first embodiment of the present invention. [Figure 3B] FIG. 3B is an enlarged cross-sectional view of the first P+ type region and its surrounding region in the cross-sectional view of FIG. 3A. [Figure 4A] FIG. 4A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4B] FIG. 4B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4C] 4A to 4C are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4D] 4A to 4D are cross-sectional views showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4E] FIG. 4E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 4F] 4F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the first embodiment of the present invention in the order of steps. [Figure 5] FIG. 5 is a band diagram of the contact portion between N-type GaN and P-type GaN and its vicinity, showing the valence band Ev, the conduction band Ec, and the Fermi level Ef before and after heat treatment for activating the acceptor element (e.g., Mg) ion-implanted into the P-type GaN. [Figure 6] FIG. 6 is a band diagram of P-type GaN in the absence of N-type GaN, showing the valence band Ev, conduction band Ec, and Fermi level Ef before and after heat treatment for activating the acceptor element. [Figure 7] FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. [Figure 8] FIG. 8 is a graph showing the relationship between the acceptor concentration of P-type GaN and the width of the depletion layer formed in P-type GaN due to contact with N-type GaN. [Figure 9] FIG. 9 is a graph showing an example of Mg and Si profiles in the depth direction of GaN. [Figure 10A] FIG. 10A is a plan view showing a configuration example of a GaN semiconductor device according to embodiment 2 of the present invention. [Figure 10B] FIG. 10B is a plan view showing a further enlarged view of the area surrounded by the two-dot chain line in the plan view of FIG. 10A. [Figure 11A] FIG. 11A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a second embodiment of the present invention. [Figure 11B] FIG. 11B is an enlarged cross-sectional view of the second P+ type region and its surrounding region in the cross-sectional view of FIG. 11A. [Figure 12A] FIG. 12A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 12B] FIG. 12B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 12C] FIG. 12C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 12D] FIG. 12D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 12E] FIG. 12E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 12F] FIG. 12F is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the second embodiment of the present invention in the order of steps. [Figure 13] FIG. 13 is a graph showing an example of the Mg and Si profiles in the X-axis direction of GaN. [Figure 14] FIG. 14 is a plan view showing a configuration example of a GaN semiconductor device according to the third embodiment of the present invention. [Figure 15]FIG. 15 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the third embodiment of the present invention. [Figure 16A] FIG. 16A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to the third embodiment of the present invention in the order of steps. [Figure 16B] FIG. 16B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment of the present invention in the order of steps. [Figure 16C] FIG. 16C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the third embodiment of the present invention in the order of steps. [Figure 16D] FIG. 16D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to the third embodiment of the present invention in the order of steps. [Figure 17] FIG. 17 is a plan view showing a configuration example of a GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 18A] FIG. 18A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 4 of the present invention. [Figure 18B] FIG. 18B is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 4 of the present invention. [Figure 19] FIG. 19 is a plan view showing a configuration example of a GaN semiconductor device according to the fifth embodiment of the present invention. [Figure 20A] FIG. 20A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 5 of the present invention. [Figure 20B] FIG. 20B is a cross-sectional view showing a configuration example of a GaN semiconductor device according to embodiment 5 of the present invention. [Figure 21] FIG. 21 is a plan view showing a configuration example of a GaN semiconductor device according to a sixth embodiment of the present invention. [Figure 22] FIG. 22 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device 100E according to the sixth embodiment of the present invention. [Figure 23] FIG. 23 is a plan view showing a configuration example of a GaN semiconductor device according to the seventh embodiment of the present invention. [Figure 24A] FIG. 24A is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a seventh embodiment of the present invention. [Figure 24B] FIG. 24B is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the seventh embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to an eighth embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a ninth embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a tenth embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to an eleventh embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a twelfth embodiment of the present invention. [Figure 30] FIG. 30 is a plan view showing a configuration example of a GaN semiconductor device according to a thirteenth embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a thirteenth embodiment of the present invention. [Figure 32A] FIG. 32A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to a thirteenth embodiment of the present invention in the order of steps. [Figure 32B] FIG. 32B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the thirteenth embodiment of the present invention in the order of steps. [Figure 32C] FIG. 32C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to embodiment 13 of the present invention in the order of steps. [Figure 33] FIG. 33 is an enlarged cross-sectional view showing the N+ type source region, the first P+ type region, and the P type well region in FIG. 32A. [Figure 34] FIG. 34 is a graph schematically showing the impurity concentration distribution in the depth direction of the N+ type source region, the first P+ type region, and the P type well region after heat treatment for activating Mg. [Figure 35] FIG. 35 is a plan view showing a configuration example of a GaN semiconductor device according to a fourteenth embodiment of the present invention. [Figure 36] FIG. 36 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a fourteenth embodiment of the present invention. [Figure 37] FIG. 37 is a plan view showing a configuration example of a GaN semiconductor device according to a fifteenth embodiment of the present invention. [Figure 38] FIG. 38 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a fifteenth embodiment of the present invention. [Figure 39] FIG. 39 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a sixteenth embodiment of the present invention. [Figure 40] FIG. 40 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to a seventeenth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0013] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10, which will be described later. The X-axis and Y-axis directions are also referred to as horizontal directions. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10 (i.e., the thickness direction of the GaN substrate 10). The X-axis, Y-axis, and Z-axis directions are orthogonal to one another. In the following description, the term "planar view" means, for example, a view from a direction (for example, the Z-axis direction) perpendicular to a surface 10a of a GaN substrate 10 described below.

[0014] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship between regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up." In the following description, + or - attached to P or N indicating the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same P and P (or N and N) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0015] <Embodiment 1> (Configuration example) FIG. 1 is a plan view showing an example configuration of a gallium nitride semiconductor device 100 according to a first embodiment of the present invention (an example of the "nitride semiconductor device" of the present invention; hereinafter, referred to as a GaN semiconductor device). FIG. 1 is an XY plan view. As shown in FIG. 1, the GaN semiconductor device 100 has an active region 110 and an edge termination region 130. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to a gate electrode 23 and a source electrode 25, respectively, which will be described later.

[0016] In a plan view from the Z-axis direction, edge termination region 130 surrounds the periphery of active region 110. Edge termination region 130 may have one or more of a guard ring structure and a JTE (Junction Termination Extension) structure. Edge termination region 130 may have the function of preventing electric field concentration in active region 110 by extending a depletion layer generated in active region 110 to edge termination region 130.

[0017] Fig. 2 is a plan view showing a configuration example of the vertical MOSFET 1 according to the first embodiment of the present invention. Fig. 2 shows an enlarged view of a part of the active region 110 shown in Fig. 1, and omits the gate pad 112, the source pad 114, the gate electrode 23, and the source electrode 25 in order to show the shape of the N+ type source region 18 and the like in a plan view from the Z-axis direction.

[0018] 3A is a cross-sectional view showing a configuration example of the vertical MOSFET 1 according to the first embodiment of the present invention. FIG. 3A shows a cross section taken along line X1-X'1 in the plan view of FIG. 2. FIG. 3B is a cross-sectional view showing an enlarged view of the first P+ type region and its surrounding region in the cross-sectional view of FIG. 3A. FIG. 3B shows a cross section taken along line X2-X'2 in the plan view of FIG. 2B.

[0019] GaN semiconductor device 100 shown in FIGS. 2 and 3A includes a gallium nitride substrate 10 (an example of a "nitride semiconductor layer" of the present invention; hereinafter, referred to as a GaN substrate) and a plurality of vertical MOSFETs 1 (an example of a "field-effect transistor" of the present invention) provided on GaN substrate 10. In GaN semiconductor device 100, vertical MOSFETs 1 are repeatedly provided in one direction (e.g., the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction (e.g., the X-axis direction).

[0020] As shown in FIGS. 2 and 3A , the vertical MOSFET 1 includes an N− type drift region 12, a P type well region 14, an N+ type source region 18 (an example of an “N-type region” according to the present invention), and a first P+ type region 30 (an example of a “first P-type region” according to the present invention) provided in a GaN substrate 10, a gate insulating film 21 provided on a front surface 10 a (an example of a “one surface” according to the present invention) of the GaN substrate 10, a gate electrode 23 provided on the gate insulating film 21, a source electrode 25 (an example of an “electrode” according to the present invention) provided on the front surface 10 a side of the GaN substrate 10 and electrically connected to the N+ type source region 18, and a drain electrode 27 provided on the back surface 10 b side of the GaN substrate 10 and electrically connected to the drift region 12.

[0021] The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a front surface 10a and a back surface 10b located opposite the front surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1×10 7 cm -2 It is a free-standing GaN substrate with low dislocation density. The donor element (N-type impurity) contained in the GaN substrate 10 may be one or more of Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

[0022] Because the GaN substrate 10 is a freestanding GaN substrate with low dislocations, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. Furthermore, during the heat treatment included in the manufacturing process of the vertical MOSFET 1, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations. The GaN substrate 10 may be N-type instead of N-type. The GaN substrate 10 may also include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N-type, and the GaN layer may be N type or N-type. The GaN single crystal substrate may also be a low-dislocation freestanding GaN substrate.

[0023] In the vertical MOSFET 1, the GaN substrate 10 may contain one or more elements of aluminum (Al) and indium (In). The GaN substrate 10 may be an alloy semiconductor containing trace amounts of Al and In in GaN, i.e., AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN. A drift region 12, a P-type well region 14, an N+ type source region 18, and a first P+ type region 30 are provided on a GaN substrate 10. The well region 14, the N+ type source region 18, and the first P+ type region 30 are each formed by ion-implanting impurities to a predetermined depth from the surface 10a of the GaN substrate 10 and activating the impurities by heat treatment.

[0024] For example, a first P+ type region 30 is provided in the P type well region 14 below the N+ type source region 18. As shown in FIGS. 3A and 3B , the first P+ type region 30 is sandwiched between the N+ type source region 18 and the P type well region 14 from above and below, and is in contact with the N+ type source region 18 and the well region 14, respectively. The first P+ type region 30 has a higher P type impurity concentration than the well region 14. The well region 14 and the first P+ type region 30 contain at least one of Mg and Be as an acceptor element. For example, the well region 14 and the first P+ type region 30 contain Mg as an acceptor element. The Mg concentration in the well region 14 is 1×10 16 cm -3 3x10 or more 18 cm -3 The Mg concentration in the first P+ type region 30 is 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0025] The drift region 12 is an N-type region. The N+ type source region 18 has a higher N-type impurity concentration than the N- type drift region 12. The drift region 12 and the N+ type source region 18 contain, for example, Si as an N-type impurity. For example, the N-type impurity concentration of the drift region 12 is the same as the N-type impurity concentration of the GaN substrate 10. In this case, the drift region 12 does not need to be ion-implanted with N-type impurities. The Si concentration in the drift region 12 is 1×10 15 cm -3 More than 1×10 17 cm -3 The following is the result.

[0026] The N+ type source region 18 is provided on the surface side of the well region 14 (i.e., on the surface 10a of the GaN substrate 10 within the well region 14). The N+ type source region 18 is formed by ion-implanting Si into the surface side of the well region 14 and activating the Si by heat treatment. The Si concentration in the N+ type source region 18 is 1×10 19 cm -3 More than 1×10 22 cm -3 The following is the result.

[0027] An upper portion of the N+ type source region 18 is exposed on the surface 10a of the GaN substrate 10. The N+ type source region 18 has one side in the X-axis direction and another side located opposite the one in the X-axis direction. One side and the other side of the N+ type source region 18 are in contact with the well region 14, respectively. A part or all of the bottom of the N+ type source region 18 is in contact with the first P+ type region 30. The channel of the vertical MOSFET 1 is formed in a region of the well region 14 adjacent to one side or the other side of the N+ type source region 18. In the following description, the region of the well region 14 where the channel of the vertical MOSFET 1 is formed is referred to as the channel region.

[0028] As shown in FIG. 2, the well region 14, the first P+ type region 30, and the N+ type source region 18 have, for example, a stripe shape extending in the Y-axis direction. An upper portion (hereinafter referred to as the upper region) 121 of the drift region 12 is exposed on the surface 10a of the GaN substrate 10. The upper region 121 is in contact with the gate insulating film 21 on the surface 10a. The upper region 121 is located between a pair of well regions 14 facing each other in the Y-axis direction. The upper region 121 may also be called a JFET region. The upper region 121 may be N-type instead of N-type. This allows the on-resistance of the vertical MOSFET 1 to be reduced.

[0029] A lower portion (hereinafter referred to as the lower portion) 122 of the drift region 12 contacts the bottom of the well region 14. The lower portion 122 is located between the upper portion 121 and the drain electrode 27, and between the well region 14 and the drain electrode 27. The lower portion 122 is provided continuously in the X-axis direction between a plurality of vertical MOSFETs 1 (i.e., a plurality of unit structures) repeated in the X-axis direction. The drift region 12 functions as a current path between the drain electrode 27 and the channel region. The first P+ type region 30 is a region for establishing an ohmic connection with excellent ohmic properties between the source electrode 25 and the P type well region 14.

[0030] That is, the first P+ type region 30 realizes an ohmic connection between the N+ type source region 18 and the P type well region 14 through a tunnel junction. Because there is an ohmic contact between the source electrode 25 and the N+ type source region 18, and between the N+ type source region 18 and the P type well region 14, there is also an ohmic connection between the source electrode 25 and the P type well region 14. The source electrode 25 can be in ohmic contact with the P type well region 14 via the N+ type source region 18 and the first P+ type region 30. The N+ type source region 18 and the first P+ type region 30 also function as a hole extraction path when the gate is off.

[0031] The gate insulating film 21 is, for example, a silicon oxide film (SiO2 film). The gate insulating film 21 is provided on, for example, the flat surface 10a. The gate electrode 23 is provided above the channel region via the gate insulating film 21. For example, the gate electrode 23 is a planar type provided on the flat gate insulating film 21. The gate electrode 23 is formed of a material different from that of the gate pad 112. The gate electrode 23 is formed of polysilicon doped with impurities, and the gate pad 112 is formed of Al or an Al-Si alloy.

[0032] The source electrode 25 is provided on the surface 10a of the GaN substrate 10. The source electrode 25 is in contact with a part of the N+ type source region 18. The source electrode 25 may also be provided on the gate electrode 23 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 23 so that the gate electrode 23 and the source electrode 25 are not electrically connected to each other.

[0033] The source electrode 25 is made of a material that can make ohmic contact with the N+ type source region 18, and is made of, for example, the same material as the source pad 114. As an example, the source electrode 25 is made of Al or an Al-Si alloy and also serves as the source pad 114. The source electrode 25 may have a barrier metal layer between the surface 10a of the GaN substrate 10 and the Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer. The drain electrode 27 is provided on the back surface 10b side of the GaN substrate 10 and is in contact with the back surface 10b. The drain electrode 27 is made of a material that can make ohmic contact with the back surface 10b of the GaN substrate 10, and is made of, for example, the same material as the source electrode 25.

[0034] In FIG. 3A , the gate terminal, the source terminal, and the drain terminal are indicated by G, D, and S, respectively. For example, when a potential equal to or greater than the threshold voltage is applied to the gate electrode 23 via the gate terminal G, an inversion layer is formed in the channel region. With the inversion layer formed in the channel region, when a predetermined high potential is applied to the drain electrode 27 and a low potential (e.g., ground potential) is applied to the source electrode 25, a current flows from the drain terminal D to the source terminal S. On the other hand, when a potential lower than the threshold voltage is applied to the gate electrode 23, no inversion layer is formed in the channel region and the current is blocked. This allows the vertical MOSFET 1 to switch the current between the source terminal S and the drain terminal D.

[0035] In the first P+ type region 30, Mg segregation is suppressed. For example, Mg segregation is classified into rod-shaped Mg segregation and non-rod-shaped Mg segregation. Rod-shaped Mg segregation has a length of 30 nm or more in one direction and a Mg concentration of 5×10 20 cm -3 The non-rod-shaped Mg segregation is a type of segregation with a length of less than 30 nm in one direction and a Mg concentration of 5×10 20 cm -3 The density of the rod-shaped acceptor segregation in the first P+ type region 30 is 1×10 14 cm -3 and the density of non-rod-shaped acceptor segregation is 1×10 15 cm -3 It is less than.

[0036] As will be described later, this is achieved by forming an N+ type source region 18 adjacent to the first P+ type formation region 30′ beforehand when activating Mg ions implanted into the first P+ type formation region 30′ (see FIG. 4D ). Contacting the N+ type source region 18 with the first P+ type formation region 30′ generates a depletion layer in the first P+ type formation region 30′, preventing the Fermi level in the depletion layer from approaching the valence band (more preferably, the conduction band). This prevents Mg segregation in the first P+ type region 30. By preventing Mg segregation, a high concentration of P+ type with small concentration variations is achieved.

[0037] Furthermore, the concentration of the donor element (for example, Si) in the N+ type source region 18 is equal to or greater than the Mg concentration in the first P+ type region 30. This makes it easier for the depletion layer to spread widely from the N+ type source region 18 toward the first P+ type region 30, and makes it easier for the first P+ type region 30 with a high Mg concentration to be formed widely. The first P+ type region 30 has a high Mg concentration and small variation in the Mg concentration, so a tunnel junction can be formed between the N+ type source region 18 and the P type well region 14, and an ohmic connection can be achieved between the source electrode and the well region 14. 3B, the depth d18 of the N+ type source region 18 is, for example, 1 nm or more and 500 nm or less, for example, in the range of several nm to several tens of nm. The thickness t30 of the first P+ type region 30 is, for example, 1 nm or more and 25 nm or less.

[0038] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 100 according to embodiment 1 of the present invention will be described. Figures 4A to 4F are cross-sectional views showing the manufacturing method for GaN semiconductor device 100 according to embodiment 1 of the present invention in the order of steps. GaN semiconductor device 100 is manufactured using various types of equipment, such as a film formation apparatus, an exposure apparatus, an etching apparatus, an ion implantation apparatus, and a heat treatment apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing equipment.

[0039] First, the manufacturing equipment performs ion implantation to form well region 14 (see FIG. 3A). For example, the manufacturing equipment forms a mask (not shown) on GaN substrate 10 that opens above a region (hereinafter referred to as well formation region) 14' where well region 14 will be formed and covers above other regions, and then ions of Mg as an acceptor element are implanted into GaN substrate 10 on which this mask has been formed. The mask is, for example, a resist pattern. After the ion implantation, the manufacturing equipment removes the mask from GaN substrate 10.

[0040] In the ion implantation step for forming the well region 14, the Mg implantation energy (acceleration voltage) is set so that the well region 14 is formed deeper from the surface 10a of the GaN substrate 10 than the N+ type source region 18 and the first P+ type region 30 (see FIG. 3A). This ion implantation step may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. In addition, in this ion implantation step, the Mg concentration in the well region 14 is set to 1×10 16 cm -3 3x10 or more 18 cm -3 The dose of Mg is set as follows:

[0041] Next, the manufacturing equipment performs ion implantation to form N+ type source region 18 (see FIG. 3A). For example, the manufacturing equipment forms a mask (not shown) on GaN substrate 10 that opens above a region where N+ type source region 18 is to be formed (hereinafter referred to as source formation region 18') and covers above other regions, and then ions of Si as a donor element are implanted into GaN substrate 10 with this mask formed. The mask is, for example, a resist pattern. After the ion implantation, the manufacturing equipment removes the mask from GaN substrate 10.

[0042] In the ion implantation step for forming the N+ type source region 18, the Si implantation energy (acceleration voltage) is set so that the depth d18 (see FIG. 3B) of the N+ type source region 18 is 1 nm or more and 500 nm or less. In the ion implantation step for forming the N+ type source region 18, the dose of Si is set so that the Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the first P+ type region 30. For example, when the Si concentration in the N+ type source region 18 is 1×10 19 cm -3 More than 1×10 22 cm -3 The dose of Si is set as follows:

[0043] Next, the manufacturing equipment subjects the GaN substrate 10 to a heat treatment at a maximum temperature of 1200°C or less. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg and Si ions implanted into the GaN substrate 10, and as shown in FIG. 4B, a P-type well region 14 and an N+-type source region 18 are formed in the GaN substrate 10, and the drift region 12 is defined. This heat treatment also allows defects caused by the Mg and Si ion implantation in the GaN substrate 10 to be repaired to some extent. Note that this heat treatment may be performed with a protective film (not shown) formed on the GaN substrate 10. The protective film may be, for example, aluminum nitride (AlN) or silicon nitride (SiN). This protective film is removed after the heat treatment.

[0044] 4C, the manufacturing equipment forms a mask 52 on the GaN substrate 10, which opens an area above a region 30′ where the first P+ type region 30 (see FIG. 3A) will be formed (hereinafter referred to as a first P+ type formation region) and covers the other areas. The mask 52 is, for example, a resist pattern. 4C, the first P+ type formation region 30′ may be set to partially overlap with the N+ type source region 18. In this case, a depletion layer is formed in the region of the first P+ type formation region 30′ located below the N+ type source region 18 (i.e., the region that does not overlap with the N+ type source region 18), and the first P+ type region 30 is formed in the region where this depletion layer is formed.

[0045] Next, the manufacturing equipment ions-implants Mg as an acceptor element into the GaN substrate 10 on which the mask 52 has been formed. After the ion implantation, the manufacturing equipment removes the mask 52 from the GaN substrate 10. In the ion implantation step for forming the first P+ type region 30, the implantation energy (acceleration voltage) of Mg is set so that the first P+ type region 30 is formed below the N+ type source region 18. That is, in the ion implantation step for forming the first P+ type region 30, the implantation energy (acceleration voltage) of Mg is set so that Mg is implanted into a region that is deeper from the surface 10a of the GaN substrate 10 than the bottom of the N+ type source region 18 and where a depletion layer is formed by contact with the N+ type source region 18.

[0046] In the ion implantation step for forming the first P+ type region 30, the dose of Mg is set so that the Mg concentration in the first P+ type region 30 is equal to or lower than the Si concentration in the N+ type source region 18. For example, if the Mg concentration in the first P+ type region 30 is 1×10 19 cm -3 More than 1×10 21 cm -3 The dose of Mg is set as follows:

[0047] 4D, the manufacturing equipment then forms a protective film 53 on the GaN substrate 10. The protective film 53 is, for example, AlN or SiN. Next, the manufacturing equipment subjects GaN substrate 10 covered with protective film 53 to a heat treatment at a maximum temperature of 1300°C to 2000°C. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg ions implanted into GaN substrate 10, and as shown in FIG. 4E, first P+ type regions 30 are formed in GaN substrate 10. This heat treatment also makes it possible to recover, to a certain extent, defects in GaN substrate 10 that have occurred due to the Mg ion implantation. After the heat treatment, the manufacturing equipment removes protective film 53 from surface 10a of GaN substrate 10.

[0048] Next, as shown in FIG. 4F, the manufacturing equipment forms a gate insulating film 21 on the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 23 and a source electrode 25. Next, the manufacturing equipment forms an interlayer insulating film (not shown) on the front surface 10a of the GaN substrate 10 so as to cover the gate electrode 23 and the source electrode 25. Next, the manufacturing equipment forms a gate pad 112 (see FIG. 1) electrically connected to the gate electrode 23 and a source pad 114 (see FIG. 1) electrically connected to the source electrode 25. Thereafter, the manufacturing equipment forms a drain electrode 27 on the back surface 10b of the GaN substrate 10. Through these steps, a GaN semiconductor device 100 (see FIG. 3A) including a vertical MOSFET 1 is completed.

[0049] (Fermi level of the depletion layer in GaN) 5 is a band diagram of the contact portion between the N-type GaN and the P-type GaN and its vicinity, showing the valence band Ev, the conduction band Ec, and the Fermi level Ef before and after heat treatment for activating the acceptor element (e.g., Mg) ion-implanted into the P-type GaN. The N-type GaN before and after heat treatment in FIG. 5 corresponds to the N+ type source region 18 of this embodiment. The P-type GaN before heat treatment in FIG. 5 corresponds to the first P+ type formation region 30' of this embodiment, and the P-type GaN after heat treatment corresponds to the first P+ type region 30 of this embodiment.

[0050] As shown in Figure 5, a depletion layer occurs at the contact point between n-type GaN and p-type GaN. The depletion layer bends the band structure, and the Fermi level Ef of n-type GaN coincides with the Fermi level Ef of p-type GaN. When heat treatment is performed in this state, Mg is activated in p-type GaN, and the Fermi level approaches the valence band, but the band structure is bent in the depletion layer. Therefore, in the region where the depletion layer occurs in p-type GaN, the approach of the Fermi level Ef to the valence band is suppressed compared to regions where the depletion layer does not occur.

[0051] Figure 6 is a band diagram of p-type GaN in the absence of n-type GaN, showing the valence band Ev, conduction band Ec, and Fermi level Ef before and after heat treatment to activate the acceptor element. When there is no n-type GaN in the vicinity, no depletion layer is formed in the p-type GaN, as shown in Figure 6, and no bending of the band structure occurs in the depletion layer. When p-type GaN covered with an insulating film is subjected to heat treatment, the acceptor element (e.g., Mg) ion-implanted into the p-type GaN is activated, and the Fermi level of the p-type GaN approaches the valence band.

[0052] (Suppression of Mg segregation by controlling the Fermi level) FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. This graph shows data calculated using first-principles calculations. The horizontal axis of FIG. 7 represents the Fermi level Ef (eV), and the vertical axis of FIG. 7 represents energy (eV). The solid line (a) in FIG. 7 shows the relationship between the formation energy of Mg acceptors (i.e., the energy required to insert Mg into the Ga site of GaN) and the Fermi level Ef of GaN. The dashed line (b) in FIG. 7 shows the relationship between the energy required to insert Ga into the GaN interstitial space and the Fermi level Ef of GaN.

[0053] In Figure 7, the closer the Fermi level Ef is to 0 (eV) (i.e., the closer the Fermi level Ef is to the valence band and the closer the conductivity type of GaN is to P-type), the higher the formation energy of Mg acceptors. Also, the closer the Fermi level is to 0 (eV), the lower the energy required for Ga to enter the GaN interstitial space. 7, it can be seen that the closer the Fermi level of GaN is to the valence band and the closer the conductivity type of GaN is to P-type, the more difficult it is for Mg to be activated and the less likely it is to function as an acceptor. In other words, the closer the Fermi level of GaN is to the conduction band and the closer the conductivity type of GaN is to N-type, the more easily Mg is activated and the more easily it can function as an acceptor.

[0054] In the embodiment of the present invention, a depletion layer is formed in the region of the first P+ type formation region 30′ located below the N+ type source region 18 (i.e., a region that does not overlap with the N+ type source region 18) due to contact with the N+ type source region 18, and the Fermi level Ef of the depletion layer is prevented from approaching the valence band Ev. Since the Fermi level Ef of the region of the first P+ type formation region 30′ located below the N+ type source region 18 is controlled so as not to approach the valence band, Mg is easily activated in this region and easily functions as an acceptor.

[0055] (depletion layer width) Figure 8 is a graph showing the relationship between the acceptor concentration of p-type GaN and the width of the depletion layer formed in p-type GaN due to contact with n-type GaN. The horizontal axis of Figure 8 is the acceptor concentration (cm -3 ) and the vertical axis of FIG. 8 represents the width (nm) of the depletion layer formed in the P-type GaN. As shown in Figure 8, when the acceptor concentration in p-type GaN is 1×10 18 cm -3 More than 1×10 21 cm -3 Below, the donor concentration in N-type GaN is 1×10 19 cm -3 More than 1×10 22 cm -3 In the following cases, the width (depth) of the depletion layer formed in P-type GaN due to contact with N-type GaN is approximately several nm to 60 nm. The higher the donor concentration in N-type GaN, the wider the depletion layer formed in P-type GaN tends to be. Also, the higher the acceptor concentration in P-type GaN, the narrower the depletion layer formed in P-type GaN tends to be.

[0056] For example, the acceptor concentration in p-type GaN is 1×10 19 cm -3 More than 1×10 21 cm -3 Below, the donor concentration in N-type GaN is 1×10 19 cm -3 More than 1×10 22 cm -3 In the following cases, the width (depth) of the depletion layer formed in the P-type GaN due to contact with the N-type GaN is 1 nm or more and 25 nm or less. 19 cm -3 When the donor concentration is 1×10 19 cm -3 More than 1×10 22 cm -3 The width of the depletion layer formed in the P-type GaN due to contact with the N-type GaN below is substantially about 25 nm. 4D, at least a portion of the first P+ type formation region 30′ is located under the N+ type source region 18. Therefore, the acceptor concentration (for example, Mg concentration) of the first P+ type formation region 30′ is 1×10 19 cm -3 At this stage, a depletion layer of about 25 nm is formed in the first P+ type formation region 30' located below the N+ type source region 18.

[0057] (Mg, Si profile) FIG. 9 is a graph showing an example of Mg and Si profiles in the depth direction of GaN. The horizontal axis of FIG. 9 indicates the depth direction of GaN, and the vertical axis of FIG. 9 indicates the concentration of Mg or Si. In FIG. 9, for example, the N+ implanted region corresponds to the source formation region 18′ (see FIG. 4A), and the P+ implanted region corresponds to the first P+ type formation region 30′ (see FIG. 4C). The N+, P+ overlapping region corresponds to the overlapping region between the source formation region 18′ and the first P+ type formation region 30′. Because the Si implanted into the N+ implanted region has a higher concentration than the Mg implanted into the P+ implanted region, the conductivity type of the overlapping region between the source formation region 18′ and the first P+ type formation region 30′ becomes N type. The Mg concentration maintaining region is depleted by contact with an activated N+ implantation region (e.g., N+ type source region 18), and the Fermi level Ef is controlled so as not to approach the valence band. As a result, Mg activation is stabilized in the Mg concentration maintaining region, and Mg segregation is suppressed, so that a high Mg concentration is maintained after activation.

[0058] The first P+ type region 30 (see FIGS. 3A and 3B) is preferably composed of only an Mg concentration maintaining region. The thickness of the Mg concentration maintaining region (the length in the horizontal direction in FIG. 9) is 1 nm to 25 nm, preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. To realize a tunnel junction between the N+ type source region 18 (see FIGS. 3A and 3B) and the P type well region 14 (see FIGS. 3A and 3B) via the first P+ type region 30, the first P+ type region 30 preferably has a high Mg concentration and is thin. By constituting the first P+ type region 30 only from an Mg concentration maintaining region and not forming a reduced Mg concentration region, it is easy to further increase the concentration of the first P+ type region 30.

[0059] The Mg concentration reduced region is not depleted because it is far from the N+ implanted region (e.g., N+ type source region 18), and the Fermi level Ef approaches the valence band. In the Mg concentration reduced region, Mg activation is less stable than in the Mg concentration maintained region, and Mg is more likely to segregate, resulting in a reduced Mg concentration. For example, in the Mg concentration reduced region, even if Mg ions are implanted at the same concentration as in the Mg concentration maintained region, the Mg concentration after activation will be 3×10 due to Mg precipitation. 18 cm -3 It drops to near

[0060] To prevent the formation of a low-Mg concentration region, the Mg ion implantation energy should be set so that the Mg implanted region is contained within the depletion layer below the N+ type source region 18. For example, if a depletion layer is formed within a depth range of 25 nm from the junction interface between the N+ type source region 18 and the P type well region 14, the Mg ion implantation energy should be set so that the implanted Mg ions are contained within this range. This ensures that almost all of the Mg ions implanted below the N+ type source region 18 are activated within the depletion layer. A Mg concentration maintaining region having a thickness of 1 nm to 25 nm is formed as the first P+ type region 30 below the N+ type source region 18, thereby suppressing the formation of a low-Mg concentration region.

[0061] (Effects of the First Embodiment) As described above, the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of forming the N+ type source region 18 in the GaN substrate 10, ion-implanting an acceptor element (e.g., Mg) into a region of the GaN substrate 10 located below the N+ type source region 18, and activating the Mg by heat-treating the GaN substrate 10 in which the N+ type source region 18 has been formed and into which the Mg has been ion-implanted, thereby forming the first P+ type region 30 located below the N+ type source region 18. In the step of forming the N+ type source region 18, Si is ion-implanted into the GaN substrate 10 at a high concentration so that the concentration of the donor element (e.g., Si) in the N+ type source region 18 is equal to or greater than the concentration of Mg in the first P+ type region 30. In the step of ion-implanting Mg into the region located below the N+ type source region 18, the Mg concentration in the first P+ type region 30 is increased to 1×10. 19 cm -3 More than 1×10 21 cm -3 Mg ions are implanted as follows:

[0062] According to this, contact between the N+ type source region 18 and the first P+ type formation region 30′ generates a depletion layer in the first P+ type formation region 30′, and the Fermi level of the depletion layer coincides with the Fermi level of the N+ type source region 18. Because the N+ type source region 18 is N+ type, the Fermi level of the depletion layer generated in the first P+ type formation region 30′ can be prevented from approaching the valence band. As a result, in the first P+ type formation region 30′, the formation energy of Mg acceptors can be maintained low, making it easier to activate Mg, thereby suppressing Mg segregation due to heat treatment and preventing a decrease in the Mg concentration due to Mg segregation.

[0063] Furthermore, the Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the first P+ type formation region 30'. This allows a wide depletion layer to be formed in the first P+ type formation region 30', suppressing a decrease in the Mg concentration due to Mg segregation and forming a high-concentration first P+ type region 30. The high-concentration first P+ type region 30 establishes an ohmic connection between the N+ type source region 18 and the P type well region 14 via a tunnel junction.

[0064] A GaN semiconductor device 100 according to a first embodiment of the present invention includes a GaN substrate 10, an N+ type source region 18 provided on the surface 10a side of the GaN substrate 10, and a first P+ type region 30 provided on the surface 10a side of the GaN substrate 10 and located below the N+ type source region 18. The Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the first P+ type region 30. The Mg concentration in the first P+ type region 30 is 1×10 19 cm -3 More than 1×10 21 cm -3 The GaN semiconductor device 100 having such a configuration can be manufactured by the manufacturing method described in the first embodiment.

[0065] <Embodiment 2> (Configuration example) Fig. 10A is a plan view showing a configuration example of a GaN semiconductor device 100A according to embodiment 2 of the present invention. As with Fig. 2 described in embodiment 1, Fig. 10A shows the shape of N+ type source region 18 and the like in a plan view from the Z-axis direction, and therefore does not show gate pad 112, source pad 114 (see Fig. 1), gate electrode 23, and source electrode 25 (see Fig. 11A). Fig. 10B is a plan view showing a further enlarged view of the region surrounded by a two-dot chain line in the plan view of Fig. 10A. FIG. 11A is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to embodiment 2 of the present invention. FIG. 11A shows a cross-section of the plan view of FIG. 10A taken along line X1-X'1. FIG. 11B is a cross-sectional view showing an enlarged view of second P+ type region 20 and its surrounding region in the cross-sectional view of FIG. 11A. FIG. 11B shows a cross-section of the plan view of FIG. 10B taken along line X3-X'3.

[0066] As shown in FIGS. 10A and 11A, the GaN semiconductor device 100A has, as components of a vertical MOSFET, an N-type drift region 12, a P-type well region 14, an N+ type source region 18, a first P+ type region 30, and a second P+ type region 20 (an example of the “second P-type region” of the present invention) provided in a GaN substrate 10, a gate insulating film 21 provided on a front surface 10a of the GaN substrate 10, a gate electrode 23 provided on the gate insulating film 21, a source electrode 25 provided on the front surface 10a side of the GaN substrate 10 and electrically connected to the N+ type source region 18 and the P+ type region 20, and a drain electrode 27 provided on the back surface 10b side of the GaN substrate 10 and electrically connected to the drift region 12.

[0067] The configurations of the N- type drift region 12, P-type well region 14, N+ type source region 18, first P+ type region 30, gate insulating film 21, gate electrode 23, source electrode 25, and drain electrode 27 are the same as those in the first embodiment. The second P+ type region 20 is provided in the GaN substrate 10. The second P+ type region 20 is a region in which impurities are ion-implanted to a predetermined depth from the surface 10a of the GaN substrate 10 and the impurities are activated by heat treatment.

[0068] For example, the second P+ type region 20 is provided on the surface side of the P-type well region 14 and is in contact with the well region 14. The second P+ type region 20 contains at least one of Mg and Be as an acceptor element. The second P+ type region 20 has a higher P-type impurity concentration than the well region 14. For example, the second P+ type region 20 contains Mg as an acceptor element. The Mg concentration in the well region 14 is 1×10 16 cm -3 3x10 or more 18 cm -3 The Mg concentration in at least a portion of the second P+ type region 20 (for example, the second region 202 described below) is 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0069] The N+ type source region 18 has one side in the X-axis direction and the other side located opposite the one side in the X-axis direction. One side of the N+ type source region 18 contacts the well region 14, and the other side of the N+ type source region 18 contacts the second P+ type region 20. One side of the N+ type source region 18 is located on the channel region side. In addition, a portion of the bottom of the N+ type source region 18 contacts the first P+ type region 30.

[0070] The second P+ type region 20 is exposed on the surface 10a of the GaN substrate 10. Both side portions of the second P+ type region 20 in the X-axis direction are in contact with the N+ type source region 18, and the bottom portion is in contact with the well region 14. The well region 14, the N+ type source region 18, the first P+ type region 30, and the second P+ type region 20 have, for example, a stripe shape extending in the Y-axis direction. The second P+ type region 20 is a region for making contact between the well region 14 and an electrode (for example, a source electrode 25). The second P+ type region 20 also functions as a hole extraction path when the gate is off.

[0071] As shown in FIGS. 10B and 11B, the second P+ type region 20 has a first region 201 and a second region 202 located on both sides of the first region 201 in the X-axis direction. The second region 202 is located between the first region 201 and the N+ type source region 18 and contacts both the first region 201 and the N+ type source region 18. Of the second P+ type region 20, the second region 202 contacts the N+ type source region 18. If the length (i.e., width) of the second P+ type region 20 in the X-axis direction is W, the width of the first region 201 is W1, and the width of the second region 202 is W2, then the relationship W=W1+W2×2 holds. W is, for example, 50 nm or more and 500 nm or less. W1 is, for example, 0 nm or more and 498 nm or less. W2 is, for example, 1 nm or more and 25 nm or less.

[0072] Since the second P+ type region 20 is sandwiched between the N+ type source regions 18 on both sides, the width W of the second P+ type region 20 can also be rephrased as the spacing between the N+ type source regions 18. In other words, the width W can also be rephrased as the spacing between the portions of the N+ type source region 18 that sandwich the second P+ type region 20 on both sides. In the second P+ type region 20, the density of Mg segregation in the second region 202 is lower than the density of Mg segregation in the first region 201. For example, the density of rod-shaped acceptor segregation in the second region 202 is 1×10 14 cm -3 and the density of non-rod-shaped acceptor segregation is 1×10 15 cm -3 The density of the rod-shaped acceptor segregation and the density of the non-rod-shaped acceptor segregation in the first region 201 are higher than the respective densities in the second region 202.

[0073] As will be described later, this is achieved by forming the N+ type source region 18 adjacent to the P+ type formation region 20′ beforehand when activating the Mg ions implanted into the P+ type formation region 20′ (see FIG. 12D ). By contacting the N+ type source region 18 with the P+ type formation region 20′, a depletion layer is generated on the side of the P+ type formation region 20′ (the region corresponding to the second region 202), preventing the Fermi level in the depletion layer from approaching the valence band (more preferably, the conduction band). This prevents Mg segregation in the second region 202.

[0074] By suppressing the segregation of Mg, a high concentration of P+ type with small concentration variations is realized. In the second P+ type region 20, the depletion layer extends from the N+ type source region 18, so that the segregation of Mg is suppressed in the second region 202 compared to the first region 201, resulting in a higher Mg concentration. For example, the Mg concentration in the second region 202 is 1×10 19 cm -3 More than 1×10 21 cm -3 The Mg concentration in the first region 201 is lower than the Mg concentration in the second region 202, and is 3×10 18 cm -3 It has dropped to nearby levels.

[0075] Furthermore, the concentration of the donor element (for example, Si) in the N+ type source region 18 is equal to or greater than the Mg concentration in the second region 202. This makes it easier for the depletion layer to spread widely from the N+ type source region 18 toward the second region 202, and makes it easier for the second region 202 with a high Mg concentration to be formed widely. The second region 202 has a high Mg concentration and small variations in the Mg concentration, so that ohmic contact can be achieved between the second P+ type region 20 and the source electrode 25.

[0076] 11B, the depth d18 of the N+ type source region 18 from the surface 10a and the depth d20 of the second P+ type region 20 from the surface 10a are preferably the same. For example, the depth d18 of the N+ type source region 18 and the depth d20 of the second P+ type region 20 are each 1 nm to 500 nm, e.g., in the range of several nm to several tens of nm. The difference between the depth d18 of the N+ type source region 18 and the depth d20 of the second P+ type region 20 is preferably 50 nm or less (|d18-d20|≦50 nm). This is because if the second P+ type region 20 is shallower than the N+ type source region 18, the lower part of the second P+ type region 20 will be depleted, increasing the connection resistance between the second P+ type region 20 and the P-type well region 14. Furthermore, if the second P+ type region 20 is deeper than the N+ type source region 18, this deeper portion is separated from the N+ type source region 18, making it difficult for the depletion layer to expand and for the Mg in the deeper portion to be activated.

[0077] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 100A according to embodiment 2 of the present invention will be described. Figures 12A to 12F are cross-sectional views showing the manufacturing method of GaN semiconductor device 100A according to embodiment 2 of the present invention in the order of steps. GaN semiconductor device 100A according to embodiment 2 is manufactured using various manufacturing equipment, such as a film formation equipment, an exposure equipment, an etching equipment, an ion implantation equipment, and a heat treatment equipment, just like GaN semiconductor device 100 according to embodiment 1.

[0078] First, the manufacturing equipment performs ion implantation to form well region 14 (see FIG. 11A). For example, as shown in FIG. 12A, the manufacturing equipment forms a mask (not shown) on GaN substrate 10 that opens above well formation region 14' and covers the tops of other regions, and then ions of Mg as an acceptor element are implanted into GaN substrate 10 with this mask formed. The mask is, for example, a resist pattern. After the ion implantation, the manufacturing equipment removes the mask from GaN substrate 10.

[0079] In the ion implantation step for forming the well region 14, the Mg implantation energy (acceleration voltage) is set so that the well region 14 is formed deeper from the surface 10a of the GaN substrate 10 than the N+ type source region 18, the first P+ type region 30, and the second P+ type region 20 shown in FIG. 11A. This ion implantation step may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. In addition, in this ion implantation step, the Mg concentration in the well region 14 is set to 1×10 16 cm -3 3x10 or more 18 cm -3 The dose of Mg is set as follows:

[0080] Next, the manufacturing equipment performs ion implantation to form the N+ type source region 18. For example, the manufacturing equipment forms a mask (not shown) on the GaN substrate 10 that opens above the source formation region 18' and covers above the other regions, and then ions of Si as a donor element are implanted into the GaN substrate 10 on which this mask has been formed. The mask is, for example, a resist pattern. After the ion implantation, the manufacturing equipment removes the mask from the GaN substrate 10.

[0081] In the ion implantation step for forming the N+ type source region 18, the implantation energy (acceleration voltage) of Si is set so that the depth d18 (see FIG. 11B) of the N+ type source region 18 is 1 nm or more and 500 nm or less. In this ion implantation step, it is preferable to set the implantation energy (acceleration voltage) of Si so that the depth d18 of the N+ type source region 18 is the same as the depth d20 of the second P+ type region 20.

[0082] In the ion implantation step for forming the N+ type source region 18, the dose of Si is set so that the Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in each of the first P+ type region 30 and the second P+ type region 20. For example, if the Si concentration in the N+ type source region 18 is 1×10 19 cm -3 More than 1×10 22 cm-3 The dose of Si is set as follows:

[0083] Next, the manufacturing equipment subjects the GaN substrate 10 to a heat treatment at a maximum temperature of 1200°C or less. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg and Si ions implanted into the GaN substrate 10, and as shown in FIG. 12B, a P-type well region 14 and an N+-type source region 18 are formed in the GaN substrate 10, and the drift region 12 is defined. This heat treatment also allows defects caused by the Mg and Si ion implantation in the GaN substrate 10 to be repaired to some extent. Note that this heat treatment may be performed with a protective film formed on the GaN substrate 10. For example, aluminum nitride (AlN) or silicon nitride (SiN) may be used as the protective film. This protective film is removed after the heat treatment.

[0084] Next, as shown in FIG. 12C, the manufacturing equipment forms a mask 51 on the GaN substrate 10, which opens an area above a region (hereinafter, referred to as a second P+ type formation region) 20′ where the second P+ type region 20 (see FIG. 11A) will be formed, and covers the area above the other regions. The mask 51 is, for example, a resist pattern. As shown in FIG. 12C, the second P+ type formation region 20′ may be set to partially overlap with the N+ type source region 18. Next, the manufacturing equipment ions implants Mg as an acceptor element into the GaN substrate 10 on which the mask 51 has been formed. After the ion implantation, the manufacturing equipment removes the mask 51 from the GaN substrate 10.

[0085] In the ion implantation step for forming the second P+ type region 20, the implantation energy (acceleration voltage) of Mg is set so that the depth d20 (see FIG. 11B) of the second P+ type region 20 is 1 nm or more and 500 nm or less. In this ion implantation step, it is preferable to set the implantation energy (acceleration voltage) of Mg so that the depth d20 of the second P+ type region 20 is the same as the depth d18 of the N+ type source region 18 (see FIG. 11B). In the ion implantation step for forming the second P+ type region 20, the dose of Mg is set so that the Mg concentration in the second P+ type region 20 is equal to or lower than the Si concentration in the N+ type source region 18. For example, if the Mg concentration in the second P+ type region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3 The dose of Mg is set as follows:

[0086] 12D, the manufacturing equipment forms a mask 52 on the GaN substrate 10, which opens an area above a region 30′ where the first P+ type region 30 (see FIG. 11A) will be formed (hereinafter referred to as a first P+ type formation region) and covers the other areas above. The mask 52 is, for example, a resist pattern. 4B, the first P+ type formation region 30′ may be set to partially overlap with the N+ type source region 18. In this case, a depletion layer is formed in the region of the first P+ type formation region 30′ located below the N+ type source region 18 (i.e., the region that does not overlap with the N+ type source region 18), and the first P+ type region 30 is formed in the region where this depletion layer is formed.

[0087] Next, the manufacturing equipment ions-implants Mg as an acceptor element into the GaN substrate 10 on which the mask 52 has been formed. After the ion implantation, the manufacturing equipment removes the mask 52 from the GaN substrate 10. In the ion implantation step for forming the first P+ type region 30, the implantation energy (acceleration voltage) of Mg is set so that the first P+ type region 30 is formed below the N+ type source region 18. That is, in the ion implantation step for forming the first P+ type region 30, the implantation energy (acceleration voltage) of Mg is set so that Mg is implanted into a region that is deeper from the surface 10a of the GaN substrate 10 than the bottom of the N+ type source region 18 and where a depletion layer is formed by contact with the N+ type source region 18.

[0088] In the ion implantation step for forming the first P+ type region 30, the dose of Mg is set so that the Mg concentration in the first P+ type region 30 is equal to or lower than the Si concentration in the N+ type source region 18. For example, if the Mg concentration in the first P+ type region 30 is 1×10 19 cm -3 More than 1×10 21 cm -3 The dose of Mg is set as follows: In the second embodiment, the order of the ion implantation step shown in Fig. 12C and the ion implantation step shown in Fig. 12D may be reversed. That is, the ion implantation step for forming the first P+ type region 30 may be performed first, and then the ion implantation step for forming the second P+ type region 20 may be performed.

[0089] 12D, the manufacturing equipment then forms a protective film 53 on the GaN substrate 10. The protective film 53 is, for example, AlN or SiN. Next, the manufacturing equipment subjects GaN substrate 10 covered with protective film 53 to a heat treatment at a maximum temperature of 1300°C to 2000°C. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg ions implanted into GaN substrate 10, and as shown in FIG. 12E, first P+ type regions 30 and second P+ type regions 20 are formed in GaN substrate 10. This heat treatment also makes it possible to repair, to a certain extent, defects in GaN substrate 10 that have occurred due to the Mg ion implantation. After the heat treatment, the manufacturing equipment removes protective film 53 from surface 10a of GaN substrate 10.

[0090] Next, as shown in FIG. 12F, the manufacturing equipment forms gate insulating film 21 on GaN substrate 10. Next, the manufacturing equipment forms gate electrode 23 and source electrode 25. Next, the manufacturing equipment forms an interlayer insulating film (not shown) on front surface 10a of GaN substrate 10 so as to cover gate electrode 23 and source electrode 25. Next, the manufacturing equipment forms gate pad 112 (see FIG. 1) electrically connected to gate electrode 23 and source pad 114 (see FIG. 1) electrically connected to source electrode 25. Thereafter, the manufacturing equipment forms drain electrode 27 on rear surface 10b of GaN substrate 10. Through these steps, a GaN semiconductor device 100A (see FIG. 11A) including a vertical MOSFET is completed.

[0091] (Mg, Si profile) FIG. 13 is a graph showing an example of Mg and Si profiles in the X-axis direction of GaN. The horizontal axis of FIG. 13 represents the X-axis direction, and the vertical axis of FIG. 13 represents the Mg or Si concentration. In FIG. 13, for example, the N+ implanted region corresponds to the source formation region 18′ (see FIG. 12A), and the P+ implanted region corresponds to the second P+ type formation region 20′ (see FIG. 12C). The N+, P+ overlapping region corresponds to the overlapping region between the source formation region 18′ and the second P+ type formation region 20′. Since the Si implanted into the N+ implanted region has a higher concentration than the Mg implanted into the P+ implanted region, the conductivity type of the overlapping region between the source formation region 18′ and the second P+ type formation region 20′ becomes N-type. In FIG. 13, for example, the Mg concentration decreasing region corresponds to the first region 201 (see FIG. 11B), and the Mg concentration maintaining region corresponds to the second region 202 (see FIG. 11B). The Mg concentration maintaining region is located on both sides of the Mg concentration decreasing region.

[0092] The Mg concentration maintaining region is depleted by contact with an activated N+ implantation region (e.g., N+ type source region 18), and the Fermi level Ef is controlled so as not to approach the valence band. As a result, Mg activation is stabilized in the Mg concentration maintaining region, and Mg segregation is suppressed, so that a high Mg concentration is maintained. As described above, the width of the Mg concentration maintaining region is 1 nm or more and 25 nm or less, for example, 25 nm. The width of the spacing between the N+ implanted regions (i.e., the P+ regions) is, for example, 50 nm or more and 500 nm or less, preferably 100 nm or less. Narrowing the spacing between the N+ implanted regions increases the area ratio of the Mg concentration maintaining region to the P+ region.

[0093] (Effects of the second embodiment) As described above, the manufacturing method of the GaN semiconductor device 100A according to the second embodiment of the present invention further includes the step of ion-implanting Mg into the region sandwiched between the N+ type source regions 18. In the step of forming the first P+ type region 30, the GaN substrate 10 in which the N+ type source regions 18 have been formed and in which Mg has been ion-implanted into the region below the N+ type source region 18 and the region sandwiched between the N+ type source regions 18 is heat-treated to activate the Mg, thereby forming the first P+ type region 30 below the N+ type source region 18 and the second P+ type region 20 sandwiched between the N+ type source regions 18. In the step of forming the N+ type source region 18, the donor element is ion-implanted at a high concentration into the GaN substrate 10 so that the concentration of the donor element in the N+ type source region 18 is equal to or greater than the concentration of Mg in each of the first P+ type region 30 and the second P+ type region 20. In the step of ion-implanting Mg into the regions sandwiched by the N+ type source regions 18, the Mg concentration in the second P+ type region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3 Mg ions are implanted as follows:

[0094] This makes it possible to form a high-concentration first P+ type region 30 in which a decrease in Mg concentration due to Mg segregation is suppressed, as in the first embodiment. The high-concentration first P+ type region 30 realizes an ohmic connection between the N+ type source region 18 and the P type well region 14 through a tunnel junction.

[0095] Furthermore, contact between the N+ type source region 18 and the second P+ type formation region 20′ generates depletion layers on both sides of the second P+ type formation region 20′, and the Fermi levels of these sides coincide with the Fermi level of the N+ type source region 18. Because the N+ type source region 18 is N+ type, the Fermi levels of the depletion layers generated on both sides of the second P+ type formation region 20′ can be prevented from approaching the valence band. This allows the formation energy of Mg acceptors to be maintained low on both sides of the second P+ type formation region 20′, making it easier to activate Mg. This suppresses Mg segregation due to heat treatment and the reduction in Mg concentration due to Mg segregation.

[0096] Furthermore, the Si concentration in the N+ type source region 18 is equal to or greater than the Mg concentration in the second P+ type formation region 20'. As a result, a wide depletion layer is formed on both sides of the second P+ type formation region 20', and a wide second region 202 is formed in which a decrease in the Mg concentration due to Mg segregation is suppressed. A high-concentration P+ type region 20 including the second region 202 can be formed. Furthermore, a source contact with excellent ohmic properties can be achieved by joining the source electrode 25 to such a second P+ type region 20. The high-concentration first P+ type region 30 and second P+ type region 20 can further improve the ohmic properties of the connection between the source electrode 25 and the P-type well region 14.

[0097] The GaN semiconductor device 100A according to the second embodiment of the present invention further includes a second P+ type region 20 provided on the surface 10a side of the GaN substrate 10 and sandwiched between the N+ type source regions 18 on both sides. The Mg concentration in at least a portion of the second P+ type region 20 (for example, the second region 202) is 1×10 19 cm -3 More than 1×10 21 cm -3 The GaN semiconductor device 100A having such a configuration can be manufactured by the manufacturing method described in the second embodiment.

[0098] <Embodiment 3> In the above-described second embodiment, the first P+ type region 30 is disposed below the N+ type source region 18, but is not disposed below the second P+ type region 20. However, in the embodiments of the present invention, the first P+ type region 30 may be disposed not only below the N+ type source region 18, but also below the second P+ type region 20.

[0099] Fig. 14 is a plan view showing a configuration example of a GaN semiconductor device 100B according to embodiment 3 of the present invention. Fig. 15 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100B according to embodiment 3 of the present invention. Fig. 15 shows a cross section taken along line X4-X'4 in the plan view of Fig. 14. 14 and 15 , in the GaN semiconductor device 100B according to the third embodiment, the first P+ type region 30 is disposed not only under the N+ type source region 18 but also under the second P+ type region 20. The first P+ type region 30 is provided continuously from under one N+ type source region 18 to under the other N+ type source region 18 within the P-type well region 14.

[0100] 16A to 16D are cross-sectional views showing the process steps of a manufacturing method for a GaN semiconductor device 100B according to Embodiment 3 of the present invention. As shown in Fig. 16A, the manufacturing equipment forms a P-type well region 14 and an N+-type source region 18 in a GaN substrate 10 using a method similar to that of Embodiment 2. 16B, the manufacturing equipment forms a mask 52 on the GaN substrate 10, which opens above the first P+ type formation region 30′ and covers above the other regions. In the second embodiment, the first P+ type region 30 is formed not only below the N+ type source region 18 but also below the second P+ type region 20, so the first P+ type formation region 30′ is set wide so as to overlap with the second P+ type formation region 20′. 16C, the manufacturing equipment ions-implants Mg as an acceptor element into GaN substrate 10 on which mask 52 has been formed. After the ion implantation, mask 52 is removed from GaN substrate 10 by the manufacturing equipment.

[0101] In the third embodiment, the Mg concentration is 1×10 from the surface 10a of the GaN substrate 10 to the position where the bottom of the first P+ type region 30 is formed (i.e., the position from the surface 10a of the GaN substrate 10 deeper than the N+ type source region 18 and where a depletion layer is formed by contact with the N+ type source region 18). 19 cm -3 More than 1×10 21 cm -3 The dose amount of Mg and the implantation energy (acceleration voltage) are set as follows: This Mg ion implantation process may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. When using multi-stage ion implantation, it is easy to maintain a constant Mg concentration in the depth direction even when Mg ions are implanted deep from the surface 10a of the GaN substrate 10.

[0102] 16C, the manufacturing equipment then forms a protective film 53 on the GaN substrate 10. The protective film 53 is, for example, AlN or SiN. Next, the manufacturing equipment subjects GaN substrate 10 covered with protective film 53 to a heat treatment at a maximum temperature of 1300°C to 2000°C. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the Mg ions implanted into GaN substrate 10, and as shown in FIG. 16D, first P+ type region 30 and second P+ type region 20 are formed in GaN substrate 10. After the heat treatment, the manufacturing equipment removes protective film 53 from surface 10a of GaN substrate 10. The subsequent steps are the same as those in Embodiments 1 and 2. The manufacturing equipment forms the gate insulating film 21, the gate electrode 23, the source electrode 25, the drain electrode 27, etc. Through these steps, a GaN semiconductor device 100B (see FIG. 15) including a vertical MOSFET 1 is completed.

[0103] Like the GaN semiconductor device 100A according to the second embodiment, the GaN semiconductor device 100B according to the third embodiment of the present invention includes a highly-doped first P+ type region 30 and a second P+ type region 20. The highly-doped first P+ type region 30 and the second P+ type region 20 can further improve the ohmic connection between the source electrode 25 and the P-type well region 14. Furthermore, in the third embodiment, the first P+ type region 30 and the second P+ type region 20 can be formed simultaneously using the same mask 52, which makes it possible to shorten the manufacturing process and reduce manufacturing costs. In the method of the third embodiment, an acceptor element (e.g., Mg) is ion-implanted also near the surface of the N+ type source region 18, but the concentration of the donor element (e.g., Si) in the N+ type source region 18 is higher than the concentration of the ion-implanted Mg. Therefore, also in the third embodiment, the N+ type source region 18 is maintained as a high-concentration N type.

[0104] <Embodiment 4> In the second embodiment described above, the second P+ type region 20 has a stripe shape extending in the Y-axis direction in plan view. However, in the present invention, the shape of the second P+ type region 20 in plan view is not limited to this. The second P+ type region 20 may have a portion extending in the X-axis direction.

[0105] Fig. 17 is a plan view showing a configuration example of a GaN semiconductor device 100C according to embodiment 4 of the present invention. Figs. 18A and 18B are cross-sectional views showing a configuration example of a GaN semiconductor device 100C according to embodiment 4 of the present invention. Fig. 18A shows a cross section of the plan view of Fig. 17 taken along line X5-X'5. Fig. 18B shows a cross section of the plan view of Fig. 17 taken along line X6-X'6. 17 to 18B, in the GaN semiconductor device 100C according to the fourth embodiment, the second P+ type region 20 has a first portion 20Y extending in the Y-axis direction and a second portion 20X extending in the X-axis direction in a plan view, and the first portion 20Y and the second portion 20X are connected to each other to form a comb-like shape. In a plan view, the first portion 20Y and the second portion 20X are each sandwiched by an N+ type source region 18 on both sides, and each has a first region 201 and second regions 202 located on both sides of the first region 201.

[0106] Like the GaN semiconductor device 100A according to the second embodiment, the GaN semiconductor device 100C according to the fourth embodiment includes a highly-doped first P+ type region 30 and a second P+ type region 20. The highly-doped first P+ type region 30 and the second P+ type region 20 can further improve the ohmic connection between the source electrode 25 and the P-type well region 14. Furthermore, in the GaN semiconductor device 100C, the second region 202 in which Mg segregation is suppressed and a decrease in the Mg concentration is suppressed is formed not only in the first portion 20Y but also in the second portion 20X, which allows the high-concentration second P+ type region 20 to be formed over a larger area.

[0107] <Embodiment 5> In an embodiment of the present invention, the second P+ type regions 20 may be arranged in a dot pattern in a plan view. FIG. 19 is a plan view showing a configuration example of a GaN semiconductor device 100D according to embodiment 5 of the present invention. FIGS. 20A and 20B are cross-sectional views showing a configuration example of a GaN semiconductor device 100D according to embodiment 5 of the present invention. FIG. 20A shows a cross section of the plan view of FIG. 19 taken along line X7-X'7. FIG. 20B shows a cross section of the plan view of FIG. 19 taken along line X8-X'8.

[0108] 19 to 20B, in the GaN semiconductor device 100D according to the fifth embodiment, the second P+ type regions 20 are arranged in a dotted pattern in a plan view. The second P+ type regions 20 arranged in a dotted pattern are surrounded by the N+ type source regions 18 in all directions in a plan view, and therefore the proportion of the activation range in one second P+ type region 20 (i.e., the proportion of the area of ​​the second region 202) can be increased. Like the GaN semiconductor device 100A according to the second embodiment, the GaN semiconductor device 100D according to the fifth embodiment includes a highly-doped first P+ type region 30 and a second P+ type region 20. The highly-doped first P+ type region 30 and the second P+ type region 20 can further improve the ohmic connection between the source electrode 25 and the P-type well region 14.

[0109] Furthermore, in the GaN semiconductor device 100D, the proportion of the activated range in the second P+ type region 20 (i.e., the proportion of the area of ​​the second region 202) can be increased, making it possible to further increase the concentration of the second P+ type region 20. The dot-shaped second P+ type regions 20 may be arranged arbitrarily as long as they are surrounded by the N+ type source regions 18 in a plan view. Also, while Fig. 19 shows a case where the dot-shaped second P+ type regions 20 are square in a plan view, this is merely an example. The dot-shaped second P+ type regions 20 may be rectangular or circular in a plan view.

[0110] <Embodiment 6> Fig. 21 is a plan view showing a configuration example of a GaN semiconductor device 100E according to embodiment 6 of the present invention. Fig. 22 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100E according to embodiment 6 of the present invention. Fig. 22 shows a cross section taken along line X9-X'9 in the plan view of Fig. 21.

[0111] As shown in FIGS. 21 and 22 , in the GaN semiconductor device 100E according to the sixth embodiment, two second P+ type regions 20 extending in the Y-axis direction are disposed below one source electrode 25. An N+ type region 28 is disposed between the two second P+ type regions 20. In the X-axis direction, the N+ type source region 18, the first second P+ type region 20, the N+ type region 28, the second second P+ type region 20, and the N+ type source region 18 are disposed side by side in this order. Each of the two second P+ type regions 20 is sandwiched between the N+ type source region 18 and the N+ type region 28. In the sixth embodiment, the N+ type source region 18 and the N+ type region 28 are examples of the “N-type region” of the present invention.

[0112] The concentration of the dopant element (e.g., Si concentration) in the N+ type region 28 may be the same as or different from the concentration of the dopant element (e.g., Si concentration) in the N+ type source region 18, but is equal to or greater than the concentration of the acceptor element (e.g., Mg concentration) in the second P+ type region 20. In addition, as shown in Fig. 22, the depth of the N+ type region 28 from the surface 10a is the same as the depth of the second P+ type region 20 from the surface 10a.

[0113] Like the GaN semiconductor device 100A according to the second embodiment, the GaN semiconductor device 100E according to the sixth embodiment includes a highly-doped first P+ type region 30 and a second P+ type region 20. The highly-doped first P+ type region 30 and the second P+ type region 20 can further improve the ohmic connection between the source electrode 25 and the P-type well region 14. Furthermore, in GaN semiconductor device 100E, Mg segregation and a decrease in the Mg concentration are suppressed not only in N+ type source region 18 but also in second region 202 adjacent to N+ type region 28. As a result, even when multiple second P+ type regions 20 are arranged below source electrode 25, second region 202 can be formed on both sides of each of the multiple second P+ type regions 20, making it possible to increase the concentration of each of the multiple second P+ type regions 20.

[0114] 21 shows an example in which the N+ type source region 18 and the N+ type region 28 are not connected in plan view, but this is merely an example. In the sixth embodiment of the present invention, the N+ type source region 18 and the N+ type region 28 may be connected in plan view. Furthermore, in the sixth embodiment, an example has been given in which two second P+ type regions 20 extending in the Y-axis direction are arranged under one source electrode 25, but this is merely an example. In the sixth embodiment, three or more second P+ type regions 20 extending in the Y-axis direction may be arranged under one source electrode 25. In such a case, too, by arranging an N+ type region 28 between one second P+ type region 20 and the other second P+ type region 20 adjacent to each other in the X-axis direction, it is possible to increase the concentration of each of the three or more second P+ type regions 20.

[0115] <Embodiment 7> Fig. 23 is a plan view showing a configuration example of a GaN semiconductor device 100F according to embodiment 7 of the present invention. Figs. 24A and 24B are cross-sectional views showing a configuration example of a GaN semiconductor device 100F according to embodiment 7 of the present invention. Fig. 24A shows a cross section of the plan view of Fig. 23 taken along line X10-X'10. Fig. 24B shows a cross section of the plan view of Fig. 23 taken along line X11-X'11.

[0116] 23, in the GaN semiconductor device 100F according to the seventh embodiment, N+ type regions 28 are scattered throughout the second P+ type region 20 in a plan view. As shown in FIGS. 23 to 24B, the second P+ type region 20 is sandwiched between N+ type source regions 18 on both sides in the X-axis direction. A portion of the second P+ type region 20 is in contact with the N+ type regions 28 scattered throughout the second P+ type region 20, and is sandwiched between the N+ type regions 28 (or the N+ type regions 28 and the N+ type source regions 18) on both sides. The distance between the N+ type source regions 18 and the N+ type regions 28 in the X-axis direction is the same as the distance W shown in FIG. 10B, and is, for example, 50 nm or more and 500 nm or less.

[0117] In the seventh embodiment, as in the sixth embodiment, the concentration of the dopant element (e.g., Si concentration) in the N+ type region 28 may be the same as or different from the concentration of the dopant element (e.g., Si concentration) in the N+ type source region 18, but is equal to or greater than the concentration of the acceptor element (e.g., Mg concentration) in the second P+ type region 20. Also, as shown in Fig. 23, the depth of the N+ type region 28 from the surface 10a is the same as the depth of the second P+ type region 20 from the surface 10a.

[0118] A depletion layer extends from the N+ type region 28 to the second P+ type region 20. As a result, in the second P+ type region 20, a second region 202 having a higher acceptor concentration (for example, Mg concentration) than the first region 201 is formed not only in the region adjacent to the N+ type source region 18 but also in the region adjacent to the N+ type region 28.

[0119] Like the GaN semiconductor device 100A according to the second embodiment, the GaN semiconductor device 100F according to the seventh embodiment includes a highly-doped first P+ type region 30 and a second P+ type region 20. The highly-doped first P+ type region 30 and the second P+ type region 20 can further improve the ohmic connection between the source electrode 25 and the P-type well region 14. Furthermore, in GaN semiconductor device 100F, Mg segregation and a decrease in the Mg concentration are suppressed not only in N+ type source region 18 but also in second region 202 adjacent to N+ type region 28. As a result, in GaN semiconductor device 100F, the proportion of the activated range in second P+ type region 20 (i.e., the proportion of the area of ​​second region 202) can be increased, and therefore, second P+ type region 20 can be made more highly concentrated.

[0120] 23 shows an example in which the N+ type source region 18 and the N+ type region 28 are not connected in plan view, but this is merely an example. In the seventh embodiment of the present invention, the N+ type source region 18 and the N+ type region 28 may also be connected in plan view. Furthermore, the dot-shaped N+ type regions 28 may be arranged arbitrarily as long as they are surrounded by the second P+ type regions 20 in a planar view. Also, while Figure 23 shows a case where the dot-shaped N+ type regions 28 are square in a planar view, this is merely an example. The dot-shaped N+ type regions 28 may be rectangular or circular in a planar view.

[0121] <Embodiment 8> In the above-described first to seventh embodiments, the vertical MOSFET included in the GaN semiconductor device is a planar type. However, in the embodiments of the present invention, the vertical MOSFET included in the GaN semiconductor device is not limited to a planar type, and may be a trench gate type.

[0122] 25 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100G according to embodiment 8 of the present invention. As shown in Fig. 25, the GaN semiconductor device 100G according to embodiment 8 has a trench H provided in a GaN substrate 10. The trench H opens to the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the P-type well region 14, and the bottom of the trench H reaches the N-type drift region 12. A gate insulating film 21 and a gate electrode 23 are disposed inside the trench H. The inner side and bottom surfaces of the trench H are covered with the gate insulating film 21. The gate electrode 23 is buried in the trench H via the gate insulating film 21. In the trench gate structure, the well region 14, which faces the gate electrode 23 via the gate insulating film 21 provided on the side surface of the trench H, becomes the channel region of the vertical MOSFET.

[0123] Like the GaN semiconductor device 100 according to the second embodiment, the GaN semiconductor device 100G according to the eighth embodiment includes a heavily doped first P+ type region 30 and a second P+ type region 20. The heavily doped first P+ type region 30 and the second P+ type region 20 can further improve the ohmic connection between the source electrode 25 and the P-type well region 14. Furthermore, the vertical MOSFET employs a trench gate structure, which allows the channel regions to be arranged more densely, facilitating the miniaturization of the device.

[0124] <Embodiment 9> The present invention may be applied to diodes. Fig. 26 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200 according to embodiment 9 of the present invention. As shown in Fig. 26, the GaN semiconductor device 200 according to embodiment 9 includes a GaN substrate 10 and one or more PN diodes 2 provided on the GaN substrate 10.

[0125] PN diode 2 includes N-type region 13 provided in GaN substrate 10, P-type region 15 provided in GaN substrate 10 and in contact with N-type region 13, first P+-type region 30 provided in GaN substrate 10 and in contact with P-type region 15, N+-type region 28 (an example of an "N-type region" in the present invention) provided in GaN substrate 10 and in contact with P-type region 15 and first P+-type region 30, anode electrode 35 (an example of an "electrode" in the present invention) provided on the front surface 10a of GaN substrate 10 and in contact with N+-type region 28, and cathode electrode 37 provided on the back surface 10b of GaN substrate 10 and in contact with N-type region 13. P-type region 15 is the anode region of PN diode 2. N-type region 13 is the cathode region of PN diode 2.

[0126] The P-type region 15 is formed by ion-implanting an acceptor element into the N-type GaN substrate 10 and then heat-treating the substrate 10. The acceptor element is, for example, Mg. The anode electrode 35 and the cathode electrode 37 are made of, for example, Al or an Al-Si alloy. The anode electrode 35 and the cathode electrode 37 may have a barrier metal layer between them and the GaN substrate 10. Ti may be used as the material for the barrier metal layer.

[0127] 26, the first P+ type region 30 is sandwiched between the P-type region 15 and the N+ type region 28 in the thickness direction (e.g., the Z-axis direction) of the GaN substrate 10. The concentration of the donor element (e.g., Si) in the N+ type region 28 is higher than the concentration of the acceptor element (e.g., Mg) in the first P+ type region 30.

[0128] In the step of forming the first P+ type region 30, a depletion layer is formed in a region (first P+ type formation region) of the P type region 15 located directly below the N+ type region 28. The Mg ions previously implanted into the first P+ type formation region are activated within the depletion layer. This forms the first P+ type region 30 with a high Mg concentration and a thickness of 1 nm to 25 nm. Because the first P+ type region 30 has a high Mg concentration and is thin, a tunnel junction is formed, achieving an ohmic connection with excellent ohmic properties between the N+ type region 28 and the P type region 15. Because there is ohmic contact between the anode electrode 35 and the N+ type region 28, and between the N+ type region 28 and the P type region 15, there is also an ohmic connection between the anode electrode 35 and the P type region 15. The anode electrode 35 can be connected to the P type region 15 via the N+ type region 28 and the first P+ type region 30.

[0129] <Embodiment 10> 27 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200A according to embodiment 10 of the present invention. As shown in FIG. 27, the GaN semiconductor device 200A according to embodiment 10 includes a GaN substrate 10 and one or more PN diodes 2 provided on the GaN substrate 10.

[0130] In the GaN semiconductor device 200A, the PN diode 2 has an N-type region 13, a P-type region 15, a first P+ type region 30, a second P+ type region 20 provided in the GaN substrate 10 and in contact with the first P+ type region 30, an N+ type region 28 in contact with the second P+ type region 20, an anode electrode 35 in contact with the second P+ type region 20 and the N+ type region 28, and a cathode electrode 37. The P-type region 15, the first P+ type region 30, and the second P+ type region 20 form the anode region of the PN diode 2. The N- type region 13 is the cathode region of the PN diode 2.

[0131] 27, the second P+ type regions 20 and the N+ type regions 28 are arranged alternately in the X-axis direction. As a result, in the second P+ type region 20, a depletion layer extends from the N+ type region 28, and a second region 202 having a higher concentration of the acceptor element (for example, Mg concentration) than the first region 201 is formed.

[0132] The GaN semiconductor device 200A according to the tenth embodiment includes a heavily doped first P+ type region 30 and a second P+ type region 20. The anode electrode 35 can be in ohmic contact with the P-type region 15 via the N+ type region 28 and the first P+ type region 30. Furthermore, by joining the anode electrode 35 to the second P+ type region 20, an anode contact with excellent ohmic properties can be achieved between the second P+ type region 20 and the anode electrode 35. This further improves the ohmic properties of the connection between the anode electrode 35 and the P-type region 15.

[0133] <Embodiment 11> Fig. 28 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200B according to embodiment 11 of the present invention. As shown in Fig. 28, the GaN semiconductor device 200B according to embodiment 11 includes a GaN substrate 10 and an MPS (Merged PiN Schottky) diode 2A provided on the GaN substrate 10. The MPS diode 2A is an element that combines a PN diode and a Schottky diode.

[0134] The MPS diode 2A has an N-type region 13 provided in the GaN substrate 10, a plurality of P-type regions 15 provided in the GaN substrate 10 and in contact with the N-type region 13, a first P+ type region 30 provided in the GaN substrate 10 and in contact with the P-type region 15, an N+ type region 28 provided in the GaN substrate 10 and in contact with the P-type region 15 and the first P+ type region 30, an anode electrode 35 provided on the front surface 10a of the GaN substrate 10 and in contact with the N-type region 13, the P-type region 15, the first P+ type region 30, and the N+ type region 28, and a cathode electrode 37 provided on the back surface 10b of the GaN substrate 10 and in contact with the N-type region 13.

[0135] 28, multiple P-type regions 15 are arranged apart from one another. An N-type region 13 is arranged between adjacent P-type regions 15. The first P+-type region 30 has a high Mg concentration and is thin, so an ohmic connection is established between the N+-type region 28 and the P-type region 15 by a tunnel junction. In addition, an ohmic contact is formed between the anode electrode 35 and the N+-type region 28.

[0136] A PN diode is formed by the anode electrode 35, the N+ type region 28, the first P+ type region 30, the P type region 15, the N- type region 13, and the cathode electrode 37. The P type region 15 is the anode region of the PN diode. The N- type region 13 is the cathode region of the PN diode. The anode electrode 35 and the N-type region 13 are connected by a Schottky junction. The anode electrode 35, the N-type region 13, and the cathode electrode 37 form a Schottky diode.

[0137] The anode electrode 35 and the cathode electrode 37 may be made of the same material or different materials. For example, the anode electrode 35 is made of one of nickel (Ni), platinum (Pt), and palladium (Pd). The cathode electrode 37 is made of Al, an Al-Si alloy, or titanium (Ti).

[0138] 28, in the MPS diode 2A, the second P+ type regions 20 and the N+ type regions 28 are arranged alternately in the X-axis direction. As a result, in the second P+ type region 20, a depletion layer extends from the N+ type region 28, and a second region 202 having a higher concentration of the acceptor element (for example, Mg concentration) than the first region 201 is formed.

[0139] GaN semiconductor device 200B according to embodiment 11 includes a high-concentration first P+ type region 30 in which Mg segregation is suppressed, similar to GaN semiconductor device 200 according to embodiment 9. Anode electrode 35 can be in ohmic contact with P type region 15 via N+ type region 28 and first P+ type region 30.

[0140] <Embodiment 12> 29 is a cross-sectional view showing a configuration example of a GaN semiconductor device 200C according to embodiment 12 of the present invention. As shown in FIG. 29, the GaN semiconductor device 200C according to embodiment 12 includes a GaN substrate 10 and an MPS diode 2A provided on the GaN substrate 10.

[0141] In the GaN semiconductor device 200C, the MPS diode 2A has an N-type region 13, a plurality of P-type regions 15, a first P+ type region 30, a second P+ type region 20 provided in the GaN substrate 10 and in contact with the first P+ type region 30, an N+ type region 28 in contact with the second P+ type region 20, an anode electrode 35 in contact with the N- type region 13, the N+ type region 28, and the second P+ type region 20, and a cathode electrode 37.

[0142] As shown in FIG. 29 , the multiple P-type regions 15 are spaced apart from one another. An N-type region 13 is disposed between adjacent P-type regions 15. Ohmic contact is formed between the anode electrode 35 and the second P+-type region 20, and between the N-type region 13 and the cathode electrode 37. Furthermore, since the first P+-type region 30 has a high Mg concentration and little variation in the Mg concentration, a tunnel junction can be formed between the N+-type region 28 and the P-type region 15. This allows an ohmic connection to be formed between the anode electrode 35 and the P-type region 15.

[0143] A PN diode is formed by the anode electrode 35, the first P+ type region 30, the second P+ type region 20, the P type region 15, the N- type region 13, and the cathode electrode 37. The P type region 15, the first P+ type region 30, and the second P+ type region 20 are the anode region of the PN diode. The N- type region 13 is the cathode region of the PN diode. The anode electrode 35 and the N-type region 13 are connected by a Schottky junction. The anode electrode 35, the N-type region 13, and the cathode electrode 37 form a Schottky diode.

[0144] 29, in the MPS diode 2A, the second P+ type regions 20 and the N+ type regions 28 are also arranged alternately in the X-axis direction. As a result, in the second P+ type region 20, a depletion layer extends from the N+ type region 28, and a second region 202 having a higher concentration of the acceptor element (for example, Mg concentration) than the first region 201 is formed.

[0145] The GaN semiconductor device 200C according to the twelfth embodiment, like the GaN semiconductor device 200A according to the tenth embodiment, includes a heavily doped first P+ type region 30 and a second P+ type region 20. The anode electrode 35 can be in ohmic contact with the P-type region 15 via the N+ type region 28 and the first P+ type region 30. Furthermore, by joining the anode electrode 35 to the second P+ type region 20, an anode contact with excellent ohmic properties can be achieved between the second P+ type region 20 and the anode electrode 35. This further improves the ohmic properties of the connection between the anode electrode 35 and the P-type region 15.

[0146] <Embodiment 13> In the above embodiment, the electrode of the present invention (e.g., source electrode 25 or anode electrode 35) is provided on an N-type region (e.g., N+ type source region 18 or N+ type region 28). However, the arrangement of the electrode of the present invention is not limited to this. The electrode of the present invention may penetrate the N-type region and be in contact with the first P-type region (e.g., first P+ type region 30). This embodiment is possible in both MOSFETs and diodes.

[0147] FIG. 30 is a plan view showing a configuration example of a GaN semiconductor device 300 according to embodiment 13 of the present invention. FIG. 31 is a cross-sectional view showing a configuration example of a GaN semiconductor device 300 according to embodiment 13 of the present invention. FIG. 31 shows a cross section taken along line X12-X'12 of the plan view of FIG. 30. Note that, similar to FIG. 2 described in embodiment 1, FIG. 30 shows the shape of N+ type source region 18 and the like in a plan view from the Z-axis direction, and therefore does not show gate pad 112, source pad 114 (see FIG. 1), gate electrode 23, and source electrode 25 (see FIG. 31).

[0148] As shown in Figures 30 and 31, a GaN semiconductor device 300 has, as components of a vertical MOSFET, an N- type drift region 12, a P- type well region 14, an N+ type source region 18, and a first P+ type region 30 provided in a GaN substrate 10, a gate insulating film 21 provided on a front surface 10a of the GaN substrate 10, a gate electrode 23 provided on the gate insulating film 21, a source electrode 25 provided on the front surface 10a of the GaN substrate 10 and electrically connected to the N+ type source region 18 and the P+ type region 20, and a drain electrode 27 provided on the back surface 10b of the GaN substrate 10 and electrically connected to the drift region 12.

[0149] 31 , in a GaN semiconductor device 300, a source electrode 25 is provided on an N+ type source region 18 and penetrates a portion of the N+ type source region 18 to be in contact with a first P+ type region 30. For example, a through-hole H1 is provided on the first P+ type region 30, penetrating the N+ type source region 18 in a thickness direction (e.g., the Z-axis direction). The source electrode 25 has a first portion 251 disposed in the through-hole H1 and in contact with the first P+ type region 30 at the bottom surface of the through-hole H1, and a second portion 252 disposed on the surface 10a of the GaN substrate 10 and in contact with the N+ type source region 18. The first portion 251 and the second portion 252 are in contact with each other.

[0150] The first portion 251 and the second portion 252 are made of a material that can make ohmic contact with the first P+ type region 30 and the N+ type source region 18, and are made of, for example, Al or an Al-Si alloy. The first portion 251 and the second portion 252 may be made of the same material, or may be made of different types of materials. The first portion 251 and the second portion 252 may be formed integrally. That is, the first portion 251 and the second portion 252 may be formed simultaneously in the same process.

[0151] Figures 32A to 32C are cross-sectional views showing, in the order of steps, a manufacturing method for a GaN semiconductor device 300 according to embodiment 13 of the present invention. Figure 33 is an enlarged cross-sectional view showing N+ type source region 18, first P+ type region 30, and P type well region 14 in Figure 32A. Figure 34 is a graph schematically showing the impurity concentration distribution in the depth direction of N+ type source region 18, first P+ type region 30, and P type well region 14 after heat treatment for activating Mg. As shown in FIG. 32A, the manufacturing equipment forms a P-type well region 14, an N+-type source region 18, and a first P+-type region 30 in a GaN substrate 10 in the same manner as in the first embodiment.

[0152] That is, in the step of forming the first P+ type region 30, a depletion layer is formed in a region of the P-type well region 14 located below the N+ type source region 18. The manufacturing equipment ions implants Mg as an acceptor element into a part of the region where this depletion layer is formed. In this ion implantation step, the implantation energy (acceleration voltage) of Mg is set so that the first P+ type region 30 is formed below the N+ type source region 18. Also, in this ion implantation step, the dose of Mg is set so that the Mg concentration in the first P+ type region 30 is equal to or lower than the Si concentration in the N+ type source region 18. For example, if the Mg concentration in the first P+ type region 30 is 1×10 19 cm -3 More than 1×10 21 cm -3 The dose of Mg is set as follows:

[0153] Next, the manufacturing equipment forms a protective film 53 (see FIG. 4D ) and performs a heat treatment on the GaN substrate 10 covered with the protective film 53 at a maximum temperature of 1300°C to 2000°C. The Fermi level E of the region located below the N+ type source region 18 is controlled so as not to approach the valence band due to the formation of a depletion layer, so that Mg is easily activated in this region and easily functions as an acceptor. This suppresses Mg segregation due to the heat treatment and suppresses a decrease in Mg concentration and variations in Mg concentration due to Mg segregation, thereby forming a high-concentration first P+ type region 30. After forming the first P+ type region 30, the manufacturing equipment removes the protective film 53 from the surface 10a of the GaN substrate 10.

[0154] 33, the depletion layer generated in the first P+ type region 30 by contact with the N+ type source region 18 preferably extends over the entire thickness of the first P+ type region 30. This makes it possible to suppress a decrease in the Mg concentration due to Mg segregation over the entire thickness of the first P+ type region 30.

[0155] Next, as shown in FIG. 32B, the manufacturing equipment forms a mask (not shown) on the surface 10a of the GaN substrate 10 and etches and removes the region of the N+ type source region 18 that is exposed from the mask. The mask is, for example, a resist pattern or a hard mask made of an insulating film such as a SiO2 film. As a result, as shown in FIG. 32B, the manufacturing equipment forms a through hole H1 in the N+ type source region 18. After forming the through hole H1, the manufacturing equipment removes the mask.

[0156] 34, the N+ type source region 18 has a higher concentration of donor elements than acceptor elements, and the first P+ type region 30 has a higher concentration of acceptor elements (e.g., Mg) than donor elements. By etching and removing the N+ type source region 18 (e.g., by forming a through hole H1) after the heat treatment for activating Mg, Mg segregation is suppressed, and a high concentration (e.g., Mg concentration of 1×10) is achieved in which the decrease in Mg concentration and the variation in Mg concentration due to Mg segregation are suppressed. 19 cm -3 More than 1×10 21 cm -3 The surface of the first P+ type region 30 (described below) can be exposed.

[0157] Next, the manufacturing equipment forms a gate insulating film on the surface 10a of the GaN substrate 10. For example, the manufacturing equipment forms a material film (e.g., an SiO2 film) that will become the gate insulating film on the surface 10a of the GaN substrate 10, forms a mask (not shown) on this material film, and etches and removes the portion of this material film that is exposed from the mask. This mask has a shape that covers the region where the gate insulating film will be formed and exposes other regions (e.g., through-hole H1 and N+ type source region 18 located around through-hole H1). This mask is, for example, a resist pattern or a hard mask made of a material different from that of the gate insulating film. As a result, as shown in FIG. 32C, the manufacturing equipment forms a gate insulating film 21 on the surface 10a of the GaN substrate 10.

[0158] Next, in FIG. 32C, the manufacturing equipment forms a conductive film (not shown) on the surface 10a of the GaN substrate 10 and fills the through-hole H1 with the conductive film. This conductive film is a material film capable of making ohmic contact with the first P+ type region 30 and the N+ type source region 18, such as an Al film or an Al-Si alloy film. Next, the manufacturing equipment forms a mask (not shown) on the conductive film and etches and removes the portions of the conductive film exposed from the mask. This forms a gate electrode 23 and a source electrode 25 (see FIG. 31) on the surface 10a of the GaN substrate 10. Through these steps, a GaN semiconductor device 300 (see FIG. 31) including a vertical MOSFET is completed.

[0159] As described above, according to the method for manufacturing GaN semiconductor device 300 of embodiment 13, N+ type source region 18 is utilized to control the Fermi level Ef of the region where first P+ type region 30 is formed (i.e., the first P+ type formation region) so that it approaches the conduction band Ec, and heat treatment is performed in this state to form a highly-doped first P+ type region 30. Next, a portion of N+ type source region 18 is removed to expose the surface of first P+ type region 30, and first portion 251 of source electrode 25 is formed so as to contact the exposed surface.

[0160] The first P+ type region 30 has a high concentration (for example, an Mg concentration of 1×10 19 cm -3 More than 1×10 21 cm -3 hereinafter), which is in contact with the first portion 251 of the source electrode 25. This allows an ohmic connection to be established between the first portion 251 of the source electrode 25 and the first P+ type region 30, and an ohmic connection to be established between the first portion 251 of the source electrode 25 and the P-type well region 14 via the first P+ type region 30.

[0161] <Embodiment 14> Fig. 35 is a plan view showing a configuration example of a GaN semiconductor device 300A according to embodiment 14 of the present invention. Fig. 36 is a cross-sectional view showing a configuration example of a GaN semiconductor device 300A according to embodiment 14 of the present invention. Fig. 36 shows a cross-section taken along line X13-X'13 of the plan view of Fig. 35. Note that, as with Fig. 30 described in relation to embodiment 13, Fig. 35 omits illustration of gate pad 112, source pad 114 (see Fig. 1), gate electrode 23, and source electrode 25 (see Fig. 36).

[0162] As shown in FIGS. 35 and 36, the GaN semiconductor device 300A according to the fourteenth embodiment differs from the GaN semiconductor device 300 according to the thirteenth embodiment (see FIGS. 30 and 31) in the arrangement of the first P+ type region 30. As shown in FIGS. 35 and 36, in the GaN semiconductor device 300A, a high concentration (for example, an Mg concentration of 1×10 19 cm -3 More than 1×10 21 cm -3 The first P+ type region 30 (hereinafter referred to as a first P+ type region 30) extends from below the first portion 251 of the source electrode 25 to below the N+ type source region 18. The first P+ type region 30 is provided between the first portion 251 of the source electrode 25 and the P type well region 14, and between the N+ type source region 18 and the P type well region 14.

[0163] According to the GaN semiconductor device 300A of the fourteenth embodiment, similarly to the thirteenth embodiment, the first portion 251 of the source electrode 25 and the high-concentration first P+ type region 30 are in contact with each other, and therefore an ohmic connection can be achieved between the first portion 251 of the source electrode 25 and the first P+ type region 30. An ohmic connection can be achieved between the first portion 251 of the source electrode 25 and the P-type well region 14 via the first P+ type region 30.

[0164] Furthermore, according to the GaN semiconductor device 300A, similarly to the first embodiment, a tunnel junction can be formed between the N+ type source region 18 and the P type well region 14 via the heavily doped first P+ type region 30. This tunnel junction can realize an ohmic connection between the source electrode 25 and the well region 14. According to the GaN semiconductor device 300A, an ohmic connection configuration using a tunnel junction is added to the configuration of the thirteenth embodiment, so that the ohmic connection between the source electrode 25 and the P-type well region 14 can be further improved.

[0165] <Embodiment 15> Fig. 37 is a plan view showing a configuration example of a GaN semiconductor device 300B according to embodiment 15 of the present invention. Fig. 38 is a cross-sectional view showing a configuration example of a GaN semiconductor device 300B according to embodiment 15 of the present invention. Fig. 38 shows a cross-section taken along line X14-X'14 of the plan view of Fig. 37. Note that, as with Fig. 30 described in relation to embodiment 13, Fig. 37 omits illustration of gate pad 112, source pad 114 (see Fig. 1), gate electrode 23, and source electrode 25 (see Fig. 38).

[0166] As shown in Figures 37 and 38, the GaN semiconductor device 300B according to embodiment 15 differs from the GaN semiconductor device 300 according to embodiment 13 (see Figures 30 and 31) in the gate structure of the vertical MOSFET. In embodiment 13, the vertical MOSFET is a planar type. In embodiment 15, the vertical MOSFET is a trench gate type. 38, a GaN semiconductor device 300B according to the fifteenth embodiment has a trench H formed in a GaN substrate 10. The trench H opens to the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the P-type well region 14, and the bottom of the trench H reaches the N-type drift region 12.

[0167] A gate insulating film 21 and a gate electrode 23 are disposed inside the trench H. The inner side and bottom surfaces of the trench H are covered with the gate insulating film 21. The gate electrode 23 is buried in the trench H via the gate insulating film 21. In the trench gate structure, the well region 14, which faces the gate electrode 23 via the gate insulating film 21 provided on the side surface of the trench H, becomes the channel region of the vertical MOSFET.

[0168] In the GaN semiconductor device 300B according to the fifteenth embodiment, similarly to the thirteenth embodiment, the first portion 251 of the source electrode 25 and the heavily doped first P+ type region 30 are in contact with each other, and therefore an ohmic connection can be achieved between the first portion 251 of the source electrode 25 and the first P+ type region 30. An ohmic connection can be achieved between the first portion 251 of the source electrode 25 and the P-type well region 14 via the first P+ type region 30. Furthermore, by employing a trench gate structure for the vertical MOSFET, it is possible to arrange the channel regions more densely, which facilitates miniaturization of the device.

[0169] As a modification, GaN semiconductor device 300B may have the configuration of embodiment 14 added thereto. That is, in GaN semiconductor device 300B shown in FIGS. 37 and 38 , heavily doped first P+ type region 30 may extend from below first portion 251 of source electrode 25 to below N+ type source region 18. First P+ type region 30 may be provided between first portion 251 of source electrode 25 and P type well region 14, and between N+ type source region 18 and P type well region 14. According to this modification, an ohmic connection is formed between the N+ type source region 18 and the P type well region 14 by a tunnel junction. This makes it possible to further improve the ohmic connection between the source electrode 25 and the P type well region 14, similar to the fourteenth embodiment.

[0170] <Embodiment 16> 39 is a cross-sectional view showing a configuration example of a GaN semiconductor device 400 according to embodiment 16 of the present invention. As shown in FIG. 39, the GaN semiconductor device 400 according to embodiment 16 includes a GaN substrate 10 and one or more PN diodes 4 provided on the GaN substrate 10.

[0171] The PN diode 4 has an N-type region 13 provided in the GaN substrate 10, a P-type region 15 provided in the GaN substrate 10 and in contact with the N-type region 13, a first P+ type region 30 provided in the GaN substrate 10 and in contact with the P-type region 15, an N+ type region 28 provided in the GaN substrate 10 and in contact with the P-type region 15 and the first P+ type region 30, an anode electrode 35 provided on the front surface 10a side of the GaN substrate 10 and in contact with the N+ type region 28, and a cathode electrode 37 in contact with the N-type region 13.

[0172] In the PN diode 4, the anode electrode 35 penetrates the N+ type region 28 and is in contact with the first P+ type region 30. For example, a through hole H2 penetrating the N+ type region 28 is provided on the front surface 10a side of the GaN substrate 10. The bottom surface of the through hole H2 is the first P+ type region 30. The anode electrode 35 is disposed within the through hole H2 and has a first portion 351 that is in contact with the first P+ type region 30 at the bottom surface of the through hole H2, and a second portion 352 that is disposed on the front surface 10a of the GaN substrate 10 and is in contact with the N+ type region 28. The first portion 351 and the second portion 352 are integrally formed.

[0173] In the PN diode 4, as in the PN diode 2 according to the ninth embodiment (see FIG. 26), the first P+ type region 30 is formed with a high Mg concentration by Fermi level control using a depletion layer formed directly below the N+ type region 28. For example, in the process of forming the first P+ type region 30, a depletion layer is formed in a region (first P+ type formation region) of the P type region 15 located directly below the N+ type region 28. Mg ions previously implanted into the first P+ type formation region are activated in the depletion layer during heat treatment. As a result, the Mg concentration increases to 1×10 19 cm -3 More than 1×10 21 cm -3 The first P+ type region 30 is formed with a high concentration of 1 nm or more and a thin concentration of 25 nm or less.

[0174] The first P+ type region 30 has a high Mg concentration and a small thickness, which allows the PN diode 4 to achieve an ohmic connection between the N+ type region 28 and the P type region 15 by a tunnel junction via the first P+ type region 30, as in the ninth embodiment. Furthermore, since the first portion 351 of the anode electrode 35 and the high-concentration first P+ type region 30 are in contact with each other, an ohmic connection can be achieved between the first portion 351 of the anode electrode 35 and the first P+ type region 30. An ohmic connection can be achieved between the first portion 351 of the anode electrode 35 and the P type region 15 via the first P+ type region 30.

[0175] According to the PN diode 4, the configuration of the ninth embodiment is supplemented by a configuration of ohmic connection between the first portion 351 of the anode electrode 35 and the P-type region 15, thereby further improving the ohmic connection between the anode electrode 35 and the P-type region 15. As a modification of the GaN semiconductor device 400 according to the sixteenth embodiment, the second portion 352 of the anode electrode 35 may extend from above the first portion 351 to above the N-type region 13. In this modification, the anode electrode 35, the N-type region 13, and the cathode electrode 37 may form a Schottky diode. The GaN semiconductor device 400 may include an MPS diode that combines the PN diode 4 and a Schottky diode, similar to the GaN semiconductor device 200B according to the eleventh embodiment (see FIG. 28).

[0176] <Embodiment 17> 40 is a cross-sectional view showing a configuration example of a GaN semiconductor device 400A according to embodiment 17 of the present invention. As shown in FIG. 40, the GaN semiconductor device 400A according to embodiment 17 includes a GaN substrate 10 and one or more PN diodes 4A provided on the GaN substrate 10.

[0177] 40 differs from the PN diode 4 shown in FIG. 39 in that the range in which through-hole H2 is formed extends over the entire N+ type region 28. In the process of forming the PN diode 4A, after the first P+ type region 30 is formed, the entire N+ type region 28 is removed to form through-hole H2, and a first portion 351 of the anode electrode 35 is formed in the formed through-hole H2, with the first portion 351 being in contact with the first P+ type region 30.

[0178] Even with this configuration, because the first portion 351 of the anode electrode 35 and the high-concentration first P+ type region 30 are in contact with each other, an ohmic connection can be achieved between the first portion 351 of the anode electrode 35 and the first P+ type region 30. An ohmic connection can be achieved between the first portion 351 of the anode electrode 35 and the P type region 15 via the first P+ type region 30.

[0179] As a modification of GaN semiconductor device 400A according to embodiment 17, second portion 352 of anode electrode 35 may be extended from above first portion 351 to above N-type region 13. In this modification, anode electrode 35, N-type region 13, and cathode electrode 37 may form a Schottky diode. GaN semiconductor device 400A may include an MPS diode that combines PN diode 4A and a Schottky diode, similar to GaN semiconductor device 200B according to embodiment 11 (see FIG. 28).

[0180] <Other embodiments> As described above, the present invention has been described by the embodiments and modifications, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, in the present invention, the vertical MOSFETs of the GaN semiconductor devices 100, 100A, 100C to 100D shown in the first, second, fourth to seventh embodiments may have a trench gate structure as shown in the eighth embodiment, instead of a planar type.

[0181] Furthermore, the first P+ type region 30 may be included in a lateral MOSFET in which a current flows in the horizontal direction of the GaN substrate 10, rather than in a vertical MOSFET in which a current flows in the vertical direction of the GaN substrate 10. Similarly, the second P+ type region 20 may also be included in a lateral MOSFET. Furthermore, the gate insulating film 21 is not limited to an SiO2 film, and may be another insulating film. A silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, or an aluminum oxide (Al2O3) film may also be used as the gate insulating film 21. A composite film formed by stacking several single-layer insulating films may also be used as the gate insulating film 21. A vertical MOSFET using an insulating film other than an SiO2 film as the gate insulating film 21 may be called a vertical MISFET. MISFET refers to an insulated gate transistor, which is a more comprehensive term that includes MOSFETs.

[0182] In the above-described embodiments 2 to 8 and 13 to 15, the electrode that makes ohmic contact with the P-type well region 14 via the first P+ type region 30 is the source electrode 25. In the above-described embodiments 9 to 12, 16, and 17, the electrode that makes ohmic contact with the P-type region 15 via the first P+ type region 30 is the anode electrode 35. However, the embodiments of the present invention are not limited to this. The electrode that makes ohmic contact with the P-type well region 14 via the first P+ type region 30 may be an electrode other than a source electrode. The electrode that makes ohmic contact with the P-type region 15 via the first P+ type region 30 may be an electrode other than an anode electrode. In addition, the first P-type region exemplified as the first P+ type region 30 may be included in an element other than a MISFET or a PN diode, such as a bipolar transistor, a capacitance element, or a resistance element.

[0183] As such, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present. [Explanation of symbols]

[0184] 1 Vertical MOSFET 2, 4, 4A PN diodes 2A MPS diode 10 GaN substrate 10a surface 10b back side 12 Drift Region 13 N-type region 14 well area 14´ Well formation area 15 P-type region 18 N+ type source region 18´ source formation region 20 2nd P+ type region 20´ 2nd P+ type formation area 20X 2nd part 20Y 1st part 21 Gate insulating film 23 Gate electrode 25 Source electrode 27 Drain electrode 28 N+ type region 30 1st P+ type region (hereinafter referred to as P+ type forming region) 30´ 1st P+ type formation area 35 Anode electrode 37 Cathode electrode 51, 52 Mask 53 Protective film 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 200, 200A, 200B, 200C, 300, 300A, 300B, 400, 400A GaN semiconductor devices 110 Active area 112 Gate Pad 114 Saucepad 121 Upper area 122 Lower area 130 Edge Termination Area 201 1st area 202 Second area 251, 351 Part 1 252, 352 2nd part D Drain terminal Gate terminal H Trench H1, H2 through holes S Source terminal

Claims

1. forming a P-type well region in the nitride semiconductor layer and an N-type region located within the well region; ion-implanting an acceptor element into a region located below the N-type region in the well region of the nitride semiconductor layer; and performing a heat treatment on the nitride semiconductor layer in which the well region and the N-type region are formed and into which the acceptor element has been ion-implanted to activate the acceptor element, thereby forming a first P-type region located in the well region and below the N-type region, the first P-type region having an upper surface in contact with the N-type region and a lower surface in contact with the well region, a top surface of the first P-type region is deeper than a top surface of the N-type region with respect to a depth from one surface of the nitride semiconductor layer; a top surface of the first P-type region is spaced apart from the one surface of the nitride semiconductor layer; In the step of forming the N-type region, ion-implanting the donor element into the nitride semiconductor layer at a high concentration so that the concentration of the donor element in the N-type region is equal to or greater than the concentration of the acceptor element in the first P-type region; In the step of ion-implanting the acceptor element into a region located in the well region below the N-type region, The concentration of the acceptor element in the first P-type region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The method for manufacturing a nitride semiconductor device includes ion-implanting the acceptor element so that:

2. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the maximum temperature of said heat treatment is 1300° C. or higher and 2000° C. or lower.

3. ion-implanting the acceptor element into regions sandwiched between the N-type regions, In the step of forming the first P-type region, the nitride semiconductor layer in which the N-type region is formed and the acceptor element is ion-implanted into a region located below the N-type region and regions sandwiched between the N-type regions, is subjected to the heat treatment to activate the acceptor element, thereby forming the first P-type region located below the N-type region and the second P-type region sandwiched between the N-type regions; In the step of forming the N-type region, ion-implanting the donor element into the nitride semiconductor layer at a high concentration so that the concentration of the donor element in the N-type region is equal to or greater than the concentration of the acceptor element in each of the first P-type region and the second P-type region; In the step of ion-implanting the acceptor element into the region sandwiched between the N-type regions, The concentration of the acceptor element in the second P-type region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the acceptor element is ion-implanted so as to satisfy the following conditions:

4. a step of ion-implanting the acceptor element into a region located below the N-type region; and a step of ion-implanting the acceptor element into regions sandwiched by the N-type regions on both sides, The method for manufacturing a nitride semiconductor device according to claim 3 , wherein the steps are performed simultaneously using a mask disposed on the one surface side of the nitride semiconductor layer.

5. removing at least a portion of the N-type region from the one surface side of the nitride semiconductor layer to form a through hole exposing the first P-type region at a bottom surface; 3. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising the step of forming an electrode in the through hole and bringing the electrode into contact with the first P-type region.

6. In the step of forming the through hole, a portion of the N-type region is removed to form the through-hole, and another portion of the N-type region is left in the nitride semiconductor layer; The step of forming the electrode includes: forming a first portion of the electrode in the through hole so that the first portion contacts the first P-type region; forming a second portion of the electrode on the one surface of the nitride semiconductor layer and bringing the second portion into contact with the other part of the N-type region.

7. In the step of forming the electrode, The method for manufacturing a nitride semiconductor device according to claim 6 , wherein the first portion and the second portion are integrally formed.

8. a nitride semiconductor layer; a P-type well region provided on one surface side of the nitride semiconductor layer; an N-type region provided in the well region on the one surface side of the nitride semiconductor layer; a first P-type region provided in the well region on the one surface side of the nitride semiconductor layer, located below the N-type region, with an upper surface in contact with the N-type region and a lower surface in contact with the well region; a top surface of the first P-type region is deeper than a top surface of the N-type region with respect to a depth from the one surface of the nitride semiconductor layer; a top surface of the first P-type region is spaced apart from the one surface of the nitride semiconductor layer; a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the first P-type region; The concentration of the acceptor element in the first P-type region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The nitride semiconductor device is as follows:

9. A nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a first P-type region provided on the one surface side of the nitride semiconductor layer and located below the N-type region, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the first P-type region; the concentration of the acceptor element in the first P-type region is not less than 1×10 19 cm −3 and not more than 1×10 21 cm −3 ; The nitride semiconductor device, wherein the first P-type region has a thickness of 1 nm or more and 25 nm or less.

10. a second P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, The concentration of the acceptor element in at least a portion of the second P-type region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ 10. The nitride semiconductor device according to claim 8, wherein:

11. A nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a first P-type region provided on the one surface side of the nitride semiconductor layer and located below the N-type region, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the first P-type region; the concentration of the acceptor element in the first P-type region is not less than 1×10 19 cm −3 and not more than 1×10 21 cm −3 ; a second P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, the concentration of the acceptor element in at least a portion of the second P-type region is 1×10 19 cm −3 or more and 1×10 21 cm −3 or less; a distance between the N-type regions at portions thereof sandwiching the second P-type region from both sides thereof being equal to or greater than 50 nm and equal to or less than 500 nm;

12. A nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a first P-type region provided on the one surface side of the nitride semiconductor layer and located below the N-type region, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the first P-type region; the concentration of the acceptor element in the first P-type region is not less than 1×10 19 cm −3 and not more than 1×10 21 cm −3 ; a second P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, the concentration of the acceptor element in at least a portion of the second P-type region is 1×10 19 cm −3 or more and 1×10 21 cm −3 or less; a depth of the N-type region from the one surface and a depth of the second P-type region from the one surface are the same.

13. A nitride semiconductor layer; an N-type region provided on one surface side of the nitride semiconductor layer; a first P-type region provided on the one surface side of the nitride semiconductor layer and located below the N-type region, a concentration of the donor element in the N-type region is equal to or greater than a concentration of the acceptor element in the first P-type region; the concentration of the acceptor element in the first P-type region is not less than 1×10 19 cm −3 and not more than 1×10 21 cm −3 ; a second P-type region provided on the one surface side of the nitride semiconductor layer and sandwiched between the N-type region on both sides, the concentration of the acceptor element in at least a portion of the second P-type region is 1×10 19 cm −3 or more and 1×10 21 cm −3 or less; The second P-type region is A first region; a second region located between the first region and the N-type region and in contact with the first region and the N-type region, the second region has a higher concentration of the acceptor element than the first region; The concentration of the acceptor element in the second region is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The nitride semiconductor device is as follows:

14. The nitride semiconductor device according to claim 13 , wherein a density of the acceptor segregation in said second region is lower than a density of the acceptor segregation in said first region.

15. The acceptor segregation is The length in one direction is 30 nm or more, and the concentration of the acceptor element is 5×10 ２０ cm －３ Rod-like acceptor segregation, The length in one direction is less than 30 nm, and the concentration of the acceptor element is 5×10 ２０ cm －３ and non-rod-shaped acceptor segregation, In the second region, the density of the rod-shaped acceptor segregation is 1×10 １４ cm －３ and the density of the non-rod-shaped acceptor segregation is 1×10 １５ cm －３ The nitride semiconductor device according to claim 14 , wherein the n-type nitride semiconductor layer is less than 1000 nm.

16. 16. The nitride semiconductor device according to claim 13, wherein a length of said second region in a direction in which said N-type regions sandwich said second P-type region from both sides is not less than 1 nm and not more than 25 nm.

17. The nitride semiconductor device according to claim 8 , further comprising an electrode provided on the N-type region.

18. The nitride semiconductor device according to claim 8 , further comprising an electrode that penetrates the N-type region and contacts the first P-type region.

19. The electrode is a first portion disposed in a through hole penetrating the N-type region and in contact with the first P-type region at a bottom surface of the through hole; The nitride semiconductor device according to claim 18 , further comprising: a second portion disposed on said one surface of said nitride semiconductor layer and in contact with said N-type region.

20. The nitride semiconductor device according to claim 19 , wherein said first portion and said second portion are integrally formed.

21. 21. The nitride semiconductor device according to claim 8, wherein the nitride semiconductor layer is made of gallium nitride.

22. 22. The nitride semiconductor device according to claim 8, wherein the acceptor element includes at least one of magnesium and beryllium.

23. a P-type well region provided in the nitride semiconductor layer; a field effect transistor provided in the nitride semiconductor layer, the field effect transistor having a channel formed in the well region; 23. The nitride semiconductor device according to claim 8, wherein said first P-type region has a higher concentration of said acceptor element than said well region and is in contact with said well region.

24. a diode provided in the nitride semiconductor layer, The nitride semiconductor device according to claim 8 , wherein said first P-type region is included in said diode.

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