Low resistivity DRAM buried wordline stacks.

Abstract

A method is described for a DRAM device with buried word lines. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing a metal cap layer on a substrate by physical vapor deposition (PVD) and depositing a molybdenum conductor layer on the metal cap layer by atomic layer deposition (ALD).

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device manufacturing. More particularly, embodiments of the present disclosure are directed to a method that includes depositing a metal cap layer on a substrate and depositing a molybdenum conductor layer on the metal cap layer. [Background technology]

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives use memory devices that offer ample data storage while consuming low power. There are two main types of random-access memory cells suitable for use in electronic devices: dynamic and static. Dynamic random-access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than a very short period of time. Static random-access memory (SRAM) is so named because it does not require periodic refreshing.

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field-effect transistor (FET) and a capacitor.

[0004] Fabricating a DRAM cell involves fabricating a transistor, a capacitor, and three contacts (one each for the bit line, word line, and reference voltage). DRAM manufacturing is a highly competitive business. There is a continuous push to reduce the size of individual cells and increase the density of memory cells so that more memory can be packed onto a single memory chip, especially at densities above 256 megabits. Limitations on cell size reduction include the path of both the active and passive word lines through the cell, the size of the cell capacitor, and compatibility with array and non-array devices.

[0005] In manufacturing, DRAM wordlines are made by atomic layer deposition of titanium nitride (TiN) and tungsten (W) stacks. These stacks have scaling issues as the dimensions of buried wordlines continue to shrink. Therefore, there is a need in the art for metal stacks that exhibit low resistivity in the fabrication of buried wordlines. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method for forming a buried word line. In some embodiments, the method includes depositing a metal cap layer by physical vapor deposition (PVD) on a substrate including at least one feature, the feature having one or more of a gate oxide layer and a work function metal layer deposited thereon; and depositing a molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

[0007] Another aspect of the present disclosure is directed to a method for forming a DRAM buried wordline having a resistance in the range of 10 μΩ-cm to 20 μΩ-cm. In one or more embodiments, the method includes depositing a metal cap layer on a substrate by DC physical vapor deposition (PVD), where the substrate is exposed to a metal precursor comprising tungsten at a DC of 35 kW and a bias of 1160 W, and depositing a molybdenum conductor layer on the metal cap layer by thermal atomic layer deposition, where the metal cap layer is exposed to the molybdenum precursor. In one or more embodiments, the method includes depositing a metal cap layer on a substrate by RF physical vapor deposition (PVD), where the substrate is exposed to a metal precursor comprising tungsten at a radio frequency of 3 kW, a bias of 50 W, and a pressure of 230 mTorr, and depositing a molybdenum conductor layer on the metal cap layer by thermal atomic layer deposition, where the metal cap layer is exposed to the molybdenum precursor. In one or more embodiments, the method includes depositing a metal cap layer on a substrate by RF physical vapor deposition (PVD), where the substrate is exposed to a metal precursor comprising molybdenum at a radio frequency of 3 kW, a bias of 50 W, and a pressure of 100 mTorr, and depositing a molybdenum conductor layer on the metal cap layer by thermal atomic layer deposition, where the metal cap layer is exposed to the molybdenum precursor.

[0008] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0009] [Figure 1] Process flow diagram of a method according to one or more embodiments of the present disclosure. [Figure 2] 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 3] 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 4] 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 5] 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 6] 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 7] 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 8] 1 is a cross-sectional view of a device according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic representations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein, and deviations in shapes due, for example, to manufacturing, may be included.

[0011] Before describing several exemplary embodiments of the invention, it is to be understood that the invention is not limited to the details of construction or process steps set forth in the following description as the invention is capable of other embodiments and of being practiced or carried out in various ways.

[0012] As used herein and in the appended claims, the term "substrate" is used to refer to a surface or portion of a surface on which processing occurs. Those skilled in the art will also understand that references to a substrate may refer to only a portion of the substrate, unless the context clearly dictates otherwise. Furthermore, references to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0013] As used herein, "substrate" refers to any substrate surface or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, in the present disclosure, any disclosed film treatment steps can also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates.

[0014] According to one or more embodiments, the term "on," with respect to a film or layer of a film, includes not only a film or layer that is directly on a surface, e.g., a substrate surface, but also includes the presence of one or more underlying layers between the film or layer and the surface, e.g., the substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film that is in contact with a surface, e.g., a substrate surface, without an intervening layer. Thus, the phrase "a layer that is directly on the substrate surface" refers to a layer that is in direct contact with the substrate surface without any intervening layers.

[0015] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0016] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the deposition of layers of material on a substrate surface by sequential exposure to two or more reactive compounds. A substrate or a portion of a substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, allowing each compound to adhere to and / or react with the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds such that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used herein and in the appended claims, the term "substantially" in this context means that, as will be understood by those skilled in the art, small portions of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, but simultaneous exposure is not intended.

[0017] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B (e.g., an oxidizer) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compound or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, with only the purge gas flowing during the time delay between pulses of reactive compound. Alternatively, the reactive compound is pulsed until the desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is one cycle. The cycle can begin with either compound A or compound B, and each sequence of cycles can be continued until a film of the desired thickness is achieved.

[0018] In one embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously delivered to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain, and the substrate is moved relative to the gas delivery system so that any given point on the substrate is exposed to both the first reactive gas and the second reactive gas.

[0019] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or when the precursor exposures largely overlap.

[0020] As used throughout this specification, "substantially simultaneously" means that the majority of the duration of exposure to the first reactive compound overlaps with exposure to the second reactive compound.

[0021] As used herein, the term "purging" includes any suitable purging process that removes unreacted precursors, reaction products, and by-products from the process region. A suitable purging process includes moving the substrate through a gas curtain to a portion or sector of the processing region that is free of reactants or substantially free of reactants. In one or more embodiments, purging the processing chamber includes applying a vacuum. In some embodiments, purging the processing region includes flowing a purge gas over the substrate. In some embodiments, the purge process includes flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N), helium (He), and argon (Ar). In some embodiments, purging of the substrate surface or reaction chamber can be carried out for a time period ranging from 0.2 seconds to 30 seconds, 0.2 seconds to 10 seconds, 0.2 seconds to 5 seconds, 0.5 seconds to 30 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds.

[0022] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores datum bits by storing a packet of charge (i.e., a binary 1) or no charge (i.e., a binary 0) in a capacitor. Charge is gated onto the capacitor through an access transistor and detected by examining the voltage perturbation created by turning on the same transistor and dumping the charge packet onto the interconnect line at the transistor's output. A single DRAM cell therefore consists of one transistor and one capacitor. DRAM devices are formed from an array of DRAM cells. Rows of access transistors are connected by word lines, and the transistor inputs / outputs are connected by bit lines. Historically, DRAM capacitors have evolved from planar polysilicon-oxide-substrate plate capacitors to 3D structures, which have branched into "stack" capacitors, where both plates are above the substrate, and "trench" capacitors, which use an etched cavity in the substrate as the common plate. Current DRAM buried word line (bWL) processes involve stacking titanium nitride (TiN) and tungsten (W). With further scaling of bWL dimensions, one focus has been removing the titanium nitride barrier from the stack to form a barrier-less metal fill within the trench structure. However, due to poor adhesion between the metal and the trench structure, void formation and delamination of the metal fill are often observed during high-temperature post-annealing processes. Such voids and delamination are undesirable because they cause problems in subsequent planarization or etching processes. Voids and delamination also contribute to increased resistance of the stack. Therefore, embodiments of the present disclosure relate to providing a process for fabricating a stack within a DRAM buried word line (bWL) on a substrate that advantageously reduces the resistance of the DRAM device. Resistance is reduced by removing nitrogen-based layers, such as a nitride cap layer and / or a nitride liner layer.

[0023] Traditionally, DRAM cells embed high work function metal structures within a buried word line structure. In DRAM devices, bit lines are formed in a metal level above the substrate, while word lines are formed at the surface of the substrate in a polysilicon gate level. In buried word line (bWL) devices, the word lines are buried below the surface of the semiconductor substrate, using metal as the gate electrode.

[0024] The choice of metal used as the gate electrode can have a significant impact on device performance. While not intending to be bound by theory, it is believed that using low-resistivity, low-melting-point metals advantageously results in reduced resistance in bWL DRAM. However, when exposed to the thermal process requirements used in bWL DRAM fabrication, these materials often delaminate from the surface. Delamination can affect the final array resistance and cause reliability issues.

[0025] In one or more embodiments, the resistance (μΩ-cm) of buried word lines having a total thickness of 100 Å is measured. In one or more embodiments, the buried word lines have a resistance of 40 μΩ-cm or less, 30 μΩ-cm or less, 25 μΩ-cm or less, or 20 μΩ-cm or less, or 15 μΩ-cm or less at a total thickness of 100 Å. In some embodiments, the buried word lines have a resistance of 20 μΩ-cm or less at a total thickness of 100 Å. In one or more embodiments, the buried word lines formed by method 100 have a resistance in the range of 50 μΩ-cm to 5 μΩ-cm, 40 μΩ-cm to 10 μΩ-cm, 30 μΩ-cm to 10 μΩ-cm, 25 μΩ-cm to 10 μΩ-cm, or 20 μΩ-cm to 10 μΩ-cm at a total thickness of 100 Å.

[0026] Figure 1 shows a process flow diagram of a method according to one or more embodiments of the present disclosure. Figures 2 through 8 are cross-sectional views illustrating a memory device 200 at various stages of processing for forming buried word lines (bWLs) according to one or more embodiments.

[0027] 1-8, one or more embodiments of the present disclosure are directed to a method 100 of forming buried word lines (bWLs) 215 on a substrate surface 202.

[0028] Referring to FIG. 2 , a substrate 202 is provided having a plurality of trenches 204. The trenches 204 form recessed channels. The trenches have a bottom 206 and at least one sidewall 208. The plurality of trenches 204 can be formed to have widths within a range of about 10 to about 100 nm, including, but not limited to, a range of about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm. As will be appreciated by those skilled in the art, the width of the plurality of trenches 204 is defined by the distance W1 from one sidewall 208 to another sidewall 208. The plurality of trenches 204 may be formed to have a depth within a range of about 120 nm to about 250 nm, including, but not limited to, about 120 nm to about 150 nm, about 150 nm to about 200 nm, about 200 nm to about 250 nm, about 120 nm to about 200 nm, or about 150 nm to about 250 nm. As will be appreciated by one skilled in the art, the depth of the plurality of trenches 204 is defined by the distance D1 from the substrate surface 203 to the bottom 206 of the plurality of trenches 204.

[0029] One or more embodiments of the present disclosure are directed to methods of depositing films in high aspect ratio features. High aspect ratio features are trenches, vias, or pillars having height:width ratios of about 10, 20, or 50 or more, or even greater. In some embodiments, films are conformally deposited on / in the high aspect ratio features. When used in this manner, conformal films have a thickness near the top of the feature that is in the range of about 80-120% of the thickness at the bottom of the feature.

[0030] A buffer insulating layer (e.g., a silicon oxide layer, not shown) may be formed on the substrate surface 203, and / or a hard mask layer (e.g., a nitride layer, not shown) may be formed to form the plurality of trenches 204. Such techniques are well known to those skilled in the art and therefore are not shown.

[0031] 3, a gate oxide layer 210 is conformally deposited on the substrate 202, on the substrate surface 203, and along the sidewall(s) 208 and bottom 206 of the plurality of trenches 204. In one or more embodiments, the gate oxide layer 210 comprises one or more of silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material.

[0032] While the term "silicon oxide" may be used to describe gate oxide layer 210, those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same applies to other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc.

[0033] In one or more embodiments, the term "high-k dielectric" refers to a material having a high dielectric constant (e.g., compared to silicon dioxide). In one or more embodiments, the high-k dielectric material is selected from one or more of hafnium oxide (HfO), zirconium oxide (ZrO), vanadium oxide (VO), titanium oxide (TiO), tin oxide (SnO), aluminum oxide (AlO), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), or zirconium silicon oxide (ZrSiO).

[0034] In one or more embodiments, the gate oxide layer 210 has a thickness in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0035] 4, in some embodiments, a work function metal layer 212 is formed on the gate oxide layer 210. As used herein, the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) relative to a vacuum level. In one or more embodiments, the work function metal layer has a work function of 4.3 eV or greater. In some embodiments, the work function metal layer 212 has a work function of 4.5 eV or greater. In other embodiments, the work function metal layer 212 has a work function of 4.3 eV or greater, including 4.4 eV or greater, 4.5 eV or greater, 4.6 eV or greater, 4.7 eV or greater, 4.8 eV or greater, 4.9 eV or greater, 5.0 eV or greater, 5.1 eV or greater, or 5.2 eV or greater.

[0036] In one or more embodiments, the work function metal layer 212 comprises a metal nitride. In one or more embodiments, the work function metal layer 212 comprises one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN. In one or more embodiments, the work function metal layer 212 is selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, WN / TiN, and combinations thereof. In one or more embodiments, the work function metal layer 212 comprises titanium nitride.

[0037] In one or more embodiments, the work function metal layer 212 has a thickness in the range of about 1 nm to about 5 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm.

[0038] 1 , in some embodiments, the method 100 includes an optional pretreatment operation 105. The pretreatment can be any suitable pretreatment known to those skilled in the art. Suitable pretreatments include, but are not limited to, preheating, cleaning, soaking, removing native oxides, or depositing an adhesion layer. In some embodiments, the pretreatment includes polishing, etching, reducing, oxidizing, halogenating, hydroxylating, annealing, baking, etc.

[0039] In some embodiments, the method 100 begins with a deposition operation 110. Referring to Figures 1 and 5, a physical vapor deposition (PVD) operation 110 performs a process to form a metal cap layer 213 in the plurality of trenches 204 on the gate oxide layer 210 and the work function metal layer 212. Those skilled in the art are familiar with PVD processing. In some embodiments, the metal cap layer 213 comprises a tungsten or molybdenum-containing species. Figure 5 shows the metal cap layer 213 formed in the plurality of trenches 204 on the gate oxide layer 210. The metal cap layer 213 has a third surface 270 (or top surface) facing the trenches 204.

[0040] In some embodiments, the metal cap layer 213 is deposited directly on the gate oxide layer 210. In other embodiments, the metal cap layer 213 is deposited directly on the work function metal layer 212.

[0041] In some embodiments, the physical vapor deposition (PVD) process includes one or more of direct current (DC) or radio frequency (RF) PVD. In some embodiments, the PVD process includes RF and DC. In some embodiments, DC is supplied to the substrate and RF is supplied to the metal target. In one or more embodiments, the DC components have a power in the range of 0 kilowatts (kW) to 100 kW, 10 kW to 80 kW, 20 kW to 60 kW, 30 kW to 50 kW, or 40 kW to 50 kW. In one or more embodiments, the RF components have a power in the range of 1 kW to 10 kW, 3 kW to 10 kW, 5 kW to 10 kW, 7 kW to 10 kW, 1 kW to 7 kW, 3 kW to 7 kW, 5 kW to 7 kW, 1 kW to 5 kW, 3 kW to 5 kW, or 1 kW to 3 kW.

[0042] In some embodiments, the PVD process includes applying a bias to the substrate to provide directional deposition. In one or more embodiments, the bias is in the range of 0 W to 1200 W, 0 W to 1000 W, 0 W to 800 W, 0 W to 600 W, 0 W to 400 W, 0 W to 200 W, 0 W to 1200 W, 200 W to 1000 W, 200 W to 800 W, 200 W to 600 W, 200 W to 400 W, 400 W to 1200 W, 400 W to 1000 W, 400 W to 800 W, 400 W to 600 W, 600 W to 1200 W, 600 W to 1000 W, 600 W to 800 W, 800 W to 1200 W, 800 W to 1000 W, or 1000 W to 1200 W.

[0043] In some embodiments, the PVD process is carried out at a temperature ranging from 200°C to 450°C, 250°C to 450°C, 300°C to 450°C, 350°C to 450°C, 400°C to 450°C, 200°C to 400°C, 250°C to 400°C, 300°C to 400°C, 350°C to 400°C, 200°C to 350°C, 250°C to 350°C, 300°C to 350°C, 200°C to 300°C, 250°C to 300°C, or 200°C to 250°C.

[0044] In some embodiments, the PVD process is carried out at a pressure in the range of 0.5 mTorr to 500 mTorr, or in the range of 10 mTorr to 500 mTorr, or in the range of 25 mTorr to 250 mTorr, or in the range of 50 mTorr to 150 mTorr.

[0045] In some embodiments, the metal cap layer 213 comprises an elemental metal. In some embodiments, the metal cap layer 213 consists essentially of a metal. As used in this context, the term "consisting essentially of a metal" means that the metal content in the film is greater than or equal to about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% metal, in atomic percent. Measurements of the composition of the metal cap layer 213 refer to the bulk of the metal cap layer 213, excluding interface regions where diffusion of elements from adjacent films may occur.

[0046] In some embodiments, the metal cap layer 213 is effective to inhibit and / or eliminate the diffusion of undesired elements into the underlying layer and / or the diffusion of silicon from the underlying layer. In some embodiments, the metal cap layer 213 is deposited substantially only on the bottom 206 of the feature. When used in this manner, the term "substantially only" refers to the metal cap layer. 5% This means that the following is formed on the sidewalls of the feature:

[0047] In one or more embodiments, the metal cap layer 213 can have any suitable thickness. For example, the metal cap layer 213 can have a thickness in the range of 10 Å to 200 Å, 20 Å to 200 Å, 50 Å to 200 Å, 100 Å to 200 Å, 150 Å to 200 Å, 10 Å to 150 Å, 50 Å to 150 Å, 100 Å to 150 Å, 10 Å to 100 Å, 50 Å to 100 Å, 10 Å to 50 Å, or 10 Å to 30 Å.

[0048] Once a predetermined thickness of the metal cap layer is formed, the method 100 proceeds to an atomic layer deposition 130 process, as shown in Figure 1. Referring to Figures 1 and 6, deposition 130 involves performing a process to deposit a molybdenum conductor layer 214 on the substrate 202 (substrate surface). The deposition process 130 may include one or more operations to form the molybdenum conductor layer 214 on the substrate 202. In some embodiments, the deposition process 130 is selective for deposition on the metal cap layer 213.

[0049] In some embodiments, the atomic layer deposition 130 process includes sequential exposure to a precursor and a reactant. In operation 132, the substrate 202 (or a substrate surface) is optionally exposed to the reactant. In some embodiments, the third surface 270 is exposed to the reactant. In some embodiments, the reactant includes a reducing agent. The reducing agent can be any suitable compound known to those skilled in the art. In some embodiments, the reducing agent includes hydrogen (H).

[0050] In some embodiments, the substrate 202 (or substrate surface) is exposed to a reducing agent at a temperature ranging from 350°C to 550°C, 400°C to 550°C, 450°C to 550°C, 500°C to 550°C, 350°C to 500°C, 400°C to 500°C, 450°C to 500°C, 350°C to 450°C, 400°C to 450°C, or 350°C to 400°C.

[0051] In some embodiments, the substrate 202 (or substrate surface) is exposed to the reducing agent for a time ranging from 5 seconds to 60 minutes, 1 minute to 60 minutes, 5 minutes to 60 minutes, 10 minutes to 60 minutes, 20 minutes to 60 minutes, 40 minutes to 60 minutes, 5 seconds to 40 minutes, 1 minute to 40 minutes, 5 minutes to 40 minutes, 10 minutes to 40 minutes, 20 minutes to 40 minutes, 5 seconds to 20 minutes, 1 minute to 20 minutes, 5 minutes to 20 minutes, 10 minutes to 20 minutes, 5 seconds to 10 minutes, 1 minute to 10 minutes, or 5 minutes to 10 minutes.

[0052] In some embodiments, the substrate 202 (or substrate surface) is exposed to the reducing agent at a dosage ranging from 100 sccm to 7000 sccm, 500 sccm to 7000 sccm, 1000 sccm to 7000 sccm, 3000 sccm to 7000 sccm, 5000 sccm to 7000 sccm, 100 sccm to 5000 sccm, 500 sccm to 5000 sccm, 1000 sccm to 5000 sccm, 3000 sccm to 5000 sccm, 100 sccm to 3000 sccm, 500 sccm to 3000 sccm, 1000 sccm to 3000 sccm, 100 sccm to 1000 sccm, 500 sccm to 1000 sccm, or 100 sccm to 500 sccm.

[0053] In some embodiments, the substrate 202 (or substrate surface) is exposed to the reducing agent at a pressure ranging from 5 Torr to 50 Torr, 10 Torr to 50 Torr, 25 Torr to 50 Torr, 5 Torr to 25 Torr, 10 Torr to 25 Torr, or 5 Torr to 10 Torr.

[0054] Referring to FIG. 1 , in operation 134, the processing chamber is optionally purged to remove unreacted reactants, reaction products, and by-products. When used in this manner, the term “processing chamber” also includes a portion of the processing chamber adjacent to the substrate surface, rather than encompassing the complete interior volume of the processing chamber. For example, in spatially separated processing chamber sectors, the portion of the processing chamber adjacent to the substrate surface is purged of metal precursor by any suitable technique, including, but not limited to, moving the substrate through a gas curtain to a portion or sector of the processing chamber that contains no or substantially no metal precursor. In one or more embodiments, purging the processing chamber includes applying a vacuum. In some embodiments, purging the processing chamber includes flowing a purge gas over the substrate. In some embodiments, a portion of the processing chamber refers to a microvolume or small-volume processing station within the processing chamber. The term “adjacent” in reference to the substrate surface refers to the physical space next to the surface of the substrate that can provide sufficient space for surface reactions (e.g., precursor adsorption) to occur. In one or more embodiments, the purge gas is selected from one or more of argon (Ar), nitrogen (N2), hydrogen (H2), and helium (He).

[0055] 1 and 6, in operation 136, the substrate 202 (or substrate surface) is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 214 on the substrate 202 (or substrate surface). In operation 136, the substrate 202 (or substrate surface) is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 214 on the metal cap layer 213. In operation 136, the substrate 202 (or substrate surface) is exposed to a molybdenum precursor to deposit a molybdenum conductor layer 214 on the reduced metal cap layer.

[0056] The molybdenum precursor can be any suitable molybdenum-containing compound that is capable of reacting (ie, adsorbing or chemisorbing) with the substrate surface to leave behind a molybdenum-containing species on the substrate surface.

[0057] 6 shows a molybdenum conductor layer 214 deposited on the metal cap layer 213. In some embodiments, the molybdenum conductor layer 214 comprises a molybdenum-containing species. In some embodiments, the molybdenum conductor layer 214 comprises a combination of layers to provide an active contact and / or a metal contact.

[0058] In some embodiments, the molybdenum conductor layer 214 is deposited directly on the metal cap layer 213 without any barrier to air. This type of processing is also referred to as in situ processing. In some embodiments of in situ processing, the atomic layer deposition 130 process begins in operation 136 by exposing the substrate to a molybdenum precursor.

[0059] In one or more embodiments, the molybdenum precursor comprises any suitable precursor known to those skilled in the art. In one or more embodiments, the molybdenum precursor is volatile and thermally stable, and therefore suitable for vapor deposition. In some embodiments, the molybdenum precursor comprises a molybdenum halide.

[0060] As used herein, the term "halide" refers to a binary system in which one part is a halogen atom and the other part is an element or radical less electronegative than the halogen, creating fluoride, chloride, bromide, iodide, or astatide. A halide ion is a negatively charged halogen atom. As known to those skilled in the art, halide anions include fluoride (F-), chloride (Cl-), bromide (Br-), iodide (I-), and astatide (At-). Thus, as used herein, the term "molybdenum halide" refers to any coordination complex of molybdenum with one or more halogen or halide ligands. The term molybdenum halide includes mixed molybdenum halides having at least two different halide atoms.

[0061] In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodochloride.

[0062] In some embodiments, the molybdenum precursor comprises a molybdenum oxyhalide species, which may comprise one or more of molybdenum oxide tetrachloride (MoClO), molybdenum oxide tetrabromide (MoBrO), molybdenum oxide tetraiodide (MoIO), molybdenum dioxide dibromide (MoOBr), molybdenum dioxide dichloride (MoClO), and / or molybdenum dioxide diiodide (MoIO).

[0063] In one or more specific embodiments, the molybdenum precursor comprises one or more of molybdenum chloride (MoCl), molybdenum fluoride (MoF), molybdenum iodide (MoI), molybdenum bromide (MoBr), molybdenum hexacarbonyl (Mo(CO)), molybdenum dioxide dichloride (MoOCl), molybdenum oxytetrachloride (MoOCl), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum.

[0064] In some embodiments, the substrate 202 (or substrate surface) is exposed to the molybdenum precursor at a temperature ranging from 350°C to 550°C, 400°C to 550°C, 450°C to 550°C, 500°C to 550°C, 350°C to 500°C, 400°C to 500°C, 450°C to 500°C, 350°C to 450°C, 400°C to 450°C, or 350°C to 400°C.

[0065] In some embodiments, the substrate 202 (or substrate surface) is exposed to the molybdenum precursor for a time ranging from 0.25 seconds to 20 minutes, 10 seconds to 20 minutes, 1 minute to 20 minutes, 5 minutes to 20 minutes, 10 minutes to 20 minutes, 0.25 seconds to 10 minutes, 10 seconds to 10 minutes, 1 minute to 10 minutes, 5 minutes to 10 minutes, 0.25 seconds to 5 minutes, 10 seconds to 5 minutes, 1 minute to 5 minutes, 0.25 seconds to 1 minute, or 10 seconds to 1 minute.

[0066] In some embodiments, the substrate 202 (or substrate surface) is exposed to the molybdenum precursor at a dosage ranging from 50 sccm to 700 sccm, 100 sccm to 700 sccm, 300 sccm to 700 sccm, 500 sccm to 700 sccm, 50 sccm to 500 sccm, 100 sccm to 500 sccm, 300 sccm to 500 sccm, 50 sccm to 300 sccm, 100 sccm to 300 sccm, or 50 sccm to 100 sccm.

[0067] In some embodiments, the substrate 202 (or substrate surface) is exposed to the molybdenum precursor at a pressure ranging from 5 Torr to 50 Torr, 10 Torr to 50 Torr, 25 Torr to 50 Torr, 5 Torr to 25 Torr, 10 Torr to 25 Torr, or 5 Torr to 10 Torr.

[0068] In some embodiments, the formed molybdenum conductor layer 214 comprises elemental molybdenum. In some embodiments, the molybdenum conductor layer 214 consists essentially of molybdenum. As used in this context, the term "consisting essentially of molybdenum" means that the molybdenum content in the film is, by atomic percent, about 80%, 85%, 90%, 95%, 98%, 99%, or 99.5% or more molybdenum. Measurements of the composition of the molybdenum conductor layer 214 refer to the bulk of the molybdenum conductor layer 214, excluding interface regions where diffusion of elements from adjacent films may occur.

[0069] The deposition operation 130 can be repeated to deposit a molybdenum conductor layer 214 having a predetermined thickness. In some embodiments, the thickness T1 of the molybdenum conductor layer 214 is controlled. In some embodiments, referring to FIG. 6 , the thickness T1 of the molybdenum conductor layer 214 is controlled relative to the depth D1 of the plurality of trenches 204. In some embodiments, the thickness T1 is greater than or equal to about 90% of the depth D1 of the plurality of trenches 204.

[0070] 7, in some embodiments, the thickness T1 of the molybdenum conductor layer 214 exceeds the depth D1 of the trench 204, and an excess of the molybdenum conductor layer 214 may be formed on the substrate. In some embodiments, the deposition operation 130 is repeated to provide a molybdenum conductor layer 214 having a thickness in the range of 1 nm to 50 nm, 5 nm to 50 nm, 10 nm to 50 nm, 25 nm to 50 nm, 1 nm to 25 nm, 5 nm to 25 nm, 10 nm to 25 nm, 1 nm to 10 nm, 5 nm to 10 nm, or 1 nm to 5 nm.

[0071] In some embodiments, the molybdenum precursor further comprises a co-reactant. In some embodiments, the co-reactant is a reducing agent. In some embodiments, the co-reactant is hydrogen (H).

[0072] In some embodiments, a molybdenum precursor is used to pretreat the metal cap layer 213 prior to depositing the molybdenum conductor layer 214. In some embodiments, the pretreatment includes etching. In some embodiments, the etching is performed for a time ranging from 5 seconds to 20 minutes, 10 seconds to 20 minutes, 1 minute to 20 minutes, 5 minutes to 20 minutes, 10 minutes to 20 minutes, 5 seconds to 10 minutes, 10 seconds to 10 minutes, 1 minute to 10 minutes, 5 minutes to 10 minutes, 5 seconds to 5 minutes, 10 seconds to 5 minutes, 1 minute to 5 minutes, 5 seconds to 1 minute, or 10 seconds to 1 minute. In some embodiments, the etching is performed with a molybdenum precursor at a dosage ranging from 5 sccm to 700 sccm, 50 sccm to 700 sccm, 100 sccm to 700 sccm, 300 sccm to 700 sccm, 5 sccm to 500 sccm, 50 sccm to 500 sccm, 100 sccm to 500 sccm, 300 sccm to 500 sccm, 5 sccm to 300 sccm, 50 sccm to 300 sccm, 100 sccm to 300 sccm, 5 sccm to 100 sccm, 50 sccm to 100 sccm, or 5 sccm to 50 sccm.

[0073] 1 , the processing chamber is optionally purged to remove unreacted molybdenum precursor, reaction products, and by-products in operation 138. Purging the processing chamber in operation 138 may be the same process as or a different process from the purging in operation 134. Purging the processing chamber, a portion of the processing chamber, an area adjacent to the substrate surface, etc., removes unreacted molybdenum precursor, reaction products, and by-products from the area adjacent to the substrate surface.

[0074] 1, in deposition operation 130, the substrate (or substrate surface) 202 is sequentially exposed to the reactant and the molybdenum precursor. In some embodiments, the substrate (or substrate surface) is first exposed to the molybdenum precursor and then to the reactant. In other embodiments, the substrate (or substrate surface) is first exposed to the reactant and then to the molybdenum precursor. In another embodiment, not shown, the substrate (or substrate surface) is exposed to the molybdenum precursor and the reactant substantially simultaneously.

[0075] In some embodiments, the molybdenum conductor layer 214 is formed inside the feature 204 on the third surface 270 of the metal cap layer 213. The molybdenum conductor layer 214 of some embodiments fills the gaps formed by the features in a bottom-up manner. As used in this manner, "bottom-up" means that deposition occurs substantially at the bottom of the feature relative to the sidewalls.

[0076] At decision 140, the thickness of the molybdenum conductor layer 214 is controlled. If the molybdenum conductor layer 214 reaches a predetermined thickness, the method 100 proceeds to optional post-processing operation 150. If the thickness of the molybdenum conductor layer 214 or the number of processing cycles has not reached a predetermined threshold, the method 100 returns to operation 130 and continues.

[0077] The optional post-treatment operation 150 can be, for example, a process that alters film properties (e.g., annealing) or a further film deposition process (e.g., an additional ALD or CVD process) to grow an additional film. In some embodiments, the optional post-treatment operation 150 can be a process that alters the properties of the deposited film. In some embodiments, the optional post-treatment operation 150 includes annealing the as-deposited film. In some embodiments, the annealing is performed at a temperature in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment in some embodiments includes one or more of an inert gas (e.g., molecular nitrogen (N), argon (Ar)), or a reducing gas (e.g., molecular hydrogen (H) or ammonia (NH)), or an oxidizing agent, such as, but not limited to, oxygen (O), ozone (O), or a peroxide. Annealing can be performed for any suitable time. In some embodiments, the film is annealed for a predetermined time ranging from about 15 seconds to about 90 minutes, or from about 1 minute to about 60 minutes. In some embodiments, annealing the as-deposited film increases the density, decreases the resistivity, and / or increases the purity of the film. In one or more embodiments, annealing can also be performed using a gas under a plasma. In one or more embodiments, the annealing temperature can be lower using a plasma.

[0078] In one or more embodiments, the plasma comprises one or more of nitrogen (N), argon (Ar), helium (He), hydrogen (H), carbon monoxide (CO), carbon dioxide (CO), methane (CH), and ammonia (NH). In some embodiments, the plasma is a remote plasma. In other embodiments, the plasma is a direct plasma.

[0079] In one or more embodiments, the plasma can be generated remotely or within the processing chamber. In one or more embodiments, the plasma is an inductively coupled plasma (ICP) or a conductively coupled plasma (CCP). In other embodiments, the plasma is a microwave plasma. Any suitable power can be used, depending, for example, on the reactants or other process conditions. In some embodiments, the plasma is generated at a plasma power ranging from about 10 W to about 3000 W. In some embodiments, the plasma is generated at a plasma power of about 3000 W or less, about 2000 W or less, about 1000 W or less, about 500 W or less, or about 250 W or less.

[0080] Referring to FIG. 8, in some embodiments, the molybdenum conductor layer 214 is recessed (embedded) by chemical mechanical polishing (CMP) and etch-back so that the molybdenum conductor layer 214 and the work function metal layer 212 do not protrude beyond the substrate surface 203 (e.g., so that the molybdenum conductor layer 214 is completely embedded within the substrate 202).

[0081] In one or more embodiments, buried word lines 215 (i.e., recessed molybdenum conductor layer 214) may be formed. In some embodiments, as shown in Figure 8, the work function metal layer 212 is recessed to the same level as the buried word lines 215. The top surfaces 217 of the buried word lines 215 and the work function metal layer 212 are recessed a depth or distance D2 from the substrate surface 203 of the plurality of trenches 204.

[0082] After formation of buried wordlines 215, processing of the substrate can continue to form memory devices, such processes being known to those skilled in the art.

[0083] In one or more embodiments, the method includes depositing a metal cap layer on a feature of a substrate in a first processing chamber; transferring the substrate to a second processing chamber integrated with the first processing chamber such that there is no air gap between the first processing chamber and the second processing chamber; and depositing a molybdenum conductor layer on the metal cap layer. In one or more embodiments, the method includes depositing a metal cap layer on a feature of a substrate in the first processing chamber; transferring the substrate to a second processing chamber integrated with the first processing chamber such that there is no air gap between the first processing chamber and the second processing chamber; exposing the metal cap layer to a reactant; transferring the substrate to a third processing chamber integrated with the second processing chamber such that there is no air gap between the second processing chamber and the third processing chamber; and depositing a molybdenum conductor layer on the metal cap layer that has been treated with a reducing agent.

[0084] Some embodiments of the present disclosure are directed to a method for bottom-up gap filling of features. A bottom-up gap filling process fills a feature from the bottom, whereas a conformal process fills a feature from the bottom and the sides. In some embodiments, the feature has a first material on the bottom and a second material on the sidewalls. In some embodiments, a metal cap layer is selectively deposited on a first material relative to a second material such that the metal cap layer fills the feature in a bottom-up manner. In some embodiments, a molybdenum conductor layer is selectively deposited on a first material relative to a second material such that the molybdenum conductor layer fills the feature in a bottom-up manner.

[0085] According to one or more embodiments, the substrate may be subjected to processing before and / or after the formation of a layer. This processing may occur in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is transferred from the first chamber to a separate second chamber for further processing. The substrate may be transferred directly from the first chamber to the separate processing chamber, or may be transferred from the first chamber to one or more transfer chambers and then to the separate processing chamber. Thus, the processing equipment may include multiple chambers in communication with a transfer station. This type of equipment may be referred to as a "cluster tool" or a "cluster system," among other terms.

[0086] Generally, a cluster tool is a modular system with multiple chambers that perform various functions, including substrate center detection and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can house a robot capable of transporting substrates back and forth between processing chambers and load lock chambers. The transfer chamber is typically maintained under reduced pressure and provides an intermediate stage for shuttled substrates from one chamber to another and / or to a load lock chamber located at the front end of the cluster tool. Two well-known cluster tools that may be compatible with the present disclosure are the Centura® and Endura®, both available from Applied Materials, Inc., Santa Clara, California, USA. However, the exact arrangement and combination of chambers may be varied for the purposes of performing specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal treatments such as RTP, plasma nitridation, degassing, alignment, hydroxylation, and other substrate processing. By performing processes in chambers on a cluster tool, surface contamination of the substrate from airborne impurities can be avoided without oxidation prior to depositing subsequent films.

[0087] According to one or more embodiments, the substrate is under continuous vacuum or "load-lock" and is not exposed to ambient air as it moves from one chamber to the next. Thus, the transfer chamber is under vacuum and is "pumped down" under vacuum. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants (e.g., one reactant). According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent reactants (e.g., one reactant) from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, a flow of inert gas forms a curtain at the outlet of the chamber.

[0088] Substrates can be processed in a single-substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before another substrate is processed. Substrates can also be processed in a continuous manner, similar to a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The geometry of the chamber and associated conveyor system can form a linear or curved path. Additionally, the processing chamber can be a carousel, where multiple substrates move around a central axis and are exposed to processes such as deposition, etching, annealing, cleaning, etc. throughout the carousel path.

[0089] During processing, the substrate may be heated or cooled. Such heating or cooling may be achieved by any suitable means, including, but not limited to, changing the temperature of the substrate support and flowing heated or cooled gases over the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to conductively change the substrate temperature. In one or more embodiments, the gas (reactive or inert) used is heated or cooled to locally change the substrate temperature. In some embodiments, a heater / cooler is positioned within the chamber adjacent to the substrate surface to change the substrate temperature by convection.

[0090] The substrate may also be stationary or rotating during processing. A rotating substrate may be rotated continuously or in discrete steps (about the substrate axis). For example, the substrate may be rotated throughout the entire process, or the substrate may be rotated in small increments between exposures to different reactive or purge gases. Rotating the substrate during processing (either continuously or in steps) can help achieve more uniform deposition or etching, for example, by minimizing the effects of local variations in gas flow geometry.

[0091] The present disclosure will now be described with reference to the following examples. Before describing certain exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0092] For ease of description, spatially relative terms such as "below," "below," "below," "above," "above," and the like may be used to describe the relationship of one element or feature shown in the figures to another element(s) or feature(s). It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures were turned over, elements described as "below" or "below" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein would be interpreted accordingly.

[0093] The use of the terms "a," "an," and "the," and similar referents in the context of describing the materials and methods discussed herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc."), provided herein is intended merely to further clarify the materials and methods and does not impose limitations on the scope of the claims unless otherwise expressly stated. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0094] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in an embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0095] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a buried word line, comprising: depositing a metal cap layer by physical vapor deposition (PVD) on a substrate including at least one trench, the at least one trench having one or more of a gate oxide layer and a work function metal layer deposited thereon, the metal cap layer being deposited substantially only on a bottom of the at least one trench, the metal cap layer comprising one or more of tungsten and molybdenum; depositing a molybdenum conductor layer by atomic layer deposition (ALD) selectively on the metal cap layer such that the molybdenum conductor layer fills the at least one trench in a bottom-up manner; 1. A method for forming a buried word line, comprising:

2. The method of claim 1 , wherein the metal cap layer comprises one or more of tungsten or molybdenum.

3. The method of claim 1 , wherein the metal cap layer is deposited using a DC PVD process.

4. The method of claim 1 , wherein the metal cap layer is deposited using an RF PVD process.

5. The method of claim 1 , wherein the PVD process includes biasing the substrate to provide directional deposition.

6. The method of claim 1 , wherein the metal cap layer is deposited at a temperature in the range of 300° C. to 350° C.

7. The method of claim 1 , wherein the metal cap layer is deposited to a thickness in the range of 10 Å to 200 Å.

8. The method of claim 1 , wherein the ALD process is a thermal process.

9. 10. The method of claim 1, wherein the ALD process comprises sequentially exposing the substrate to a reactant and a molybdenum precursor.

10. 10. The method of claim 9, wherein the molybdenum precursor comprises a molybdenum halide or a molybdenum oxyhalide.

11. 11. The method of claim 10, wherein the molybdenum precursor comprises one or more of molybdenum pentachloride or molybdenum dichloride dioxide.

12. The reactant is hydrogen (H ２ 10. The method of claim 9, comprising:

13. The method of claim 9 , wherein the molybdenum conductor layer is deposited to a thickness in the range of 1 nm to 50 nm.

14. 10. The method of claim 9, wherein the ALD process is carried out at a temperature in the range of 450°C to 500°C.

15. 2. The method of claim 1, wherein the buried word lines have a resistance of 20 μΩ-cm or less at a total thickness of 100 Å.

16. 16. The method of claim 15, wherein the at least one trench has a width in the range of 10 nm to 12 nm.

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