Circuit device, oscillator, and manufacturing method

Abstract

To provide a circuit device and the like capable of outputting an output clock signal having an appropriate duty ratio and reduced noise deterioration.SOLUTION: A circuit device 20 includes an output circuit 80 that has a waveform shaping circuit 82 of an oscillation signal OSC and outputs an output clock signal CKQ on the basis of a waveform-shaped clock signal CK, a bias voltage output circuit 50 that outputs a bias voltage VBS of the oscillation signal OSC input to the waveform shaping circuit 82, a comparator 62 that compares a DC voltage VDC obtained by smoothing the waveform-shaped clock signal CK with a reference voltage VRF, a logic circuit 60 that sets an adjustment value AJ for the bias voltage VBS, and a memory circuit 70. In the test mode, the logic circuit 60 changes the adjustment value AJ, determines the set value of the adjustment value AJ on the basis of the output of the comparator 62 when the adjustment value AJ is changed, and stores the determined set value in the storage circuit 70.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, an oscillator, a manufacturing method, and the like. [Background technology]

[0002] In a circuit device that outputs a clock signal based on an oscillation signal, a sinusoidal oscillation signal is shaped to output a square-wave clock signal. In this case, there are required specifications for the duty ratio of the clock signal, and if a clock signal that does not meet the required specifications is output, it can cause malfunctions in downstream digital circuits. For example, in the oscillator disclosed in Patent Document 1, a low-pass filter smooths the square-wave clock signal. A feedback circuit then changes the DC voltage component of the oscillation signal so that the DC voltage obtained by the smoothing matches a constant voltage, thereby outputting a clock signal with a constant duty ratio. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-297641 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in this conventional technology, during normal operation when the oscillator outputs a clock signal, a signal based on the clock signal is fed back to the amplifier on the input side, which causes noise to leak through the feedback path, degrading the noise characteristics of the clock signal. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including: an output circuit having a waveform shaping circuit that shapes the waveform of an oscillation signal and that outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit; a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit; a comparator that compares a DC voltage obtained by smoothing the clock signal after waveform shaping with a reference voltage; a logic circuit that sets an adjustment value for the bias voltage of the bias voltage output circuit; and a memory circuit, wherein the logic circuit changes the adjustment value in a test mode, determines a setting value for the adjustment value based on the output of the comparator when the adjustment value is changed, and stores the determined setting value in the memory circuit.

[0006] Another aspect of the present disclosure includes a vibrator and a circuit device that oscillates the vibrator to generate an oscillation signal, the circuit device having a waveform shaping circuit that shapes the oscillation signal, an output circuit that outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit, a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit, a comparator that compares a DC voltage obtained by smoothing the clock signal after waveform shaping with a reference voltage, a logic circuit that sets an adjustment value for the bias voltage of the bias voltage output circuit, and a memory circuit, wherein the logic circuit relates to an oscillator that changes the adjustment value in a test mode, determines a setting value for the adjustment value based on the output of the comparator when the adjustment value is changed, and stores the determined setting value in the memory circuit.

[0007] Another aspect of the present disclosure relates to a manufacturing method for an oscillator including a vibrator and a circuit device that generates an oscillation signal by oscillating the vibrator, the circuit device having a waveform shaping circuit that shapes the waveform of the oscillation signal, an output circuit that outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit, a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit, a comparator that compares a DC voltage obtained by smoothing the clock signal after the waveform shaping with a reference voltage, and a memory circuit, the manufacturing method including the steps of: setting the circuit device to a test mode; changing the adjustment value in the test mode; searching for the adjustment value that sets the duty ratio of the output clock signal to a predetermined duty ratio based on an output of the comparator when the adjustment value is changed; determining the searched adjustment value as a setting value for the adjustment value; and storing the determined setting value in the memory circuit. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows an example of the configuration of a circuit device according to an embodiment of the present invention. [Figure 2] 1 shows a specific configuration example of a circuit device and an oscillator according to the present embodiment. [Figure 3] FIG. 1 is an explanatory diagram of phase noise of a clock signal. [Figure 4] 10 shows another specific configuration example of the circuit device of the present embodiment. [Figure 5] 10 shows another specific configuration example of the circuit device of the present embodiment. [Figure 6] An example of a temperature compensation circuit configuration. [Figure 7] FIG. 10 is an explanatory diagram of a process for determining a setting value by a binary search. [Figure 8] FIG. 10 is a flowchart of a process for determining a setting value by binary search. [Figure 9] FIG. 3 is a flow diagram illustrating a method for manufacturing the oscillator according to the present embodiment. [Figure 10] First example of oscillator structure. [Figure 11] Second example of oscillator structure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0010] 1.Circuit device 1 shows an example of the configuration of a circuit device 20 according to this embodiment. The circuit device 20 according to this embodiment includes a bias voltage output circuit 50, a logic circuit 60, a comparator 62, a memory circuit 70, and an output circuit 80.

[0011] An oscillation signal OSC is input to the output circuit 80. For example, as will be described later, the oscillation signal OSC generated by oscillating an oscillator is input to the output circuit 80. The output circuit 80 then has a waveform shaping circuit 82 that shapes the waveform of the input oscillation signal OSC. For example, the waveform shaping circuit 82 shapes the waveform of the sine-wave oscillation signal OSC to output a square-wave clock signal CK. The output circuit 80 then outputs an output clock signal CKQ based on the clock signal CK after waveform shaping by the waveform shaping circuit 82. For example, in FIG. 1, an output buffer circuit 84 is provided downstream of the waveform shaping circuit 82, and the output buffer circuit 84 buffers the clock signal CK to output the output clock signal CKQ.

[0012] The bias voltage output circuit 50 outputs a bias voltage VBS of the oscillation signal OSC that is input to the waveform shaping circuit 82. By supplying the bias voltage VBS to the input node NI of the oscillation signal OSC via, for example, a resistor RB, the bias voltage output circuit 50 can set the center voltage of the oscillation signal OSC to the bias voltage VBS. For example, a sine wave oscillation signal OSC with the bias voltage VBS as its center voltage can be input to the waveform shaping circuit 82.

[0013] The comparator 62 compares the DC voltage VDC, obtained by smoothing the waveform-shaped clock signal CK, with a reference voltage VRF. For example, a smoothing resistor R and capacitor C are provided between the output node of the clock signal CK and a ground node. The connection node between the resistor R and capacitor C is connected to the first input terminal of the comparator 62. This allows the DC voltage VDC, obtained by smoothing the clock signal CK, to be input to the first input terminal of the comparator 62. The reference voltage VRF is input to the second input terminal of the comparator 62, allowing the comparator 62 to compare the DC voltage VDC with the reference voltage VRF. Note that in FIG. 1, the first input terminal is the non-inverting input terminal of the comparator 62, and the second input terminal is the inverting input terminal of the comparator 62. However, this embodiment is not limited to this, and the reverse may also be true. Furthermore, when the target duty ratio for duty adjustment is 50%, the reference voltage VRF is, for example, half the power supply voltage. 1, the output signal of the waveform shaping circuit 82 is the clock signal CK, but the clock signal CK may be any signal after waveform shaping by the waveform shaping circuit 82, such as a signal from a node between the buffer circuits of the output buffer circuit 84. In the following, ground will be referred to as GND where appropriate. GND can also be called VSS, and the ground voltage is, for example, the ground potential.

[0014] The logic circuit 60 sets an adjustment value AJ of the bias voltage VBS of the bias voltage output circuit 50. For example, the logic circuit 60 changes the adjustment value AJ, thereby changing the bias voltage VBS output by the bias voltage output circuit 50. The storage circuit 70 is a circuit that stores information, such as a memory.

[0015] In this embodiment, the logic circuit 60 changes the adjustment value AJ in the test mode. The logic circuit 60 determines the setting value of the adjustment value AJ based on the output of the comparator 62 when the adjustment value AJ is changed. The logic circuit 60 then stores the determined setting value in the memory circuit 70.

[0016] For example, suppose the reference voltage VRF is half the power supply voltage and the target duty ratio for duty adjustment is 50%. In this case, suppose the DC voltage VDC obtained by smoothing the clock signal CK becomes higher than the reference voltage VRF, causing the comparator 62 to output an H level. For example, if the H level width of the clock signal CK becomes longer than the L level width and the duty ratio increases, the DC voltage VDC rises and becomes higher than the reference voltage VRF, causing the comparator 62 to output an H level. In this case, the logic circuit 60 outputs an adjustment value AJ to the bias voltage output circuit 50 to lower the bias voltage VBS. This adjusts the duty ratio to a smaller value.

[0017] Also, suppose that the DC voltage VDC obtained by smoothing the clock signal CK becomes lower than the reference voltage VRF, causing the comparator 62 to output an L level. For example, if the H level width of the clock signal CK becomes shorter than the L level width, causing the duty ratio to decrease, the DC voltage VDC drops and becomes lower than the reference voltage VRF, causing the comparator 62 to output an L level. In this case, the logic circuit 60 outputs an adjustment value AJ to increase the bias voltage VBS to the bias voltage output circuit 50. This adjusts the duty ratio to a larger value. Note that the H level refers to a high level, and the L level refers to a low level.

[0018] The logic circuit 60 then determines the adjustment value AJ when the duty ratio of the output clock signal CKQ is set to a predetermined duty ratio as the set value, and writes the determined set value to the memory circuit 70. In the normal mode during which the circuit device 20 normally operates, the bias voltage output circuit 50 outputs the bias voltage VBS based on the adjustment value AJ according to the set value stored in the memory circuit 70.

[0019] Fig. 2 shows a specific configuration example of the circuit device 20. In Fig. 2, the circuit device 20 is provided with an oscillator circuit 30 that generates an oscillation signal OSC using a vibrator 10. Fig. 2 also shows specific configuration examples of a bias voltage output circuit 50, a waveform shaping circuit 82, and an output buffer circuit 84, and a nonvolatile memory 72 is provided as the storage circuit 70 in Fig. 1.

[0020] The circuit device 20 of this embodiment is, for example, an integrated circuit device called an IC (Integrated Circuit). For example, the circuit device 20 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. The oscillator 4 of this embodiment includes a resonator 10 and the circuit device 20. The resonator 10 is electrically connected to the circuit device 20. For example, the resonator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the circuit device 20.

[0021] The vibrator 10 is an element that generates mechanical vibrations in response to an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness-shear mode, such as an AT-cut or SC-cut cut angle, a tuning-fork type quartz crystal vibrating piece, or a double-ended tuning-fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built into a temperature-compensated crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built into an oven-controlled crystal oscillator (OCXO) that has a thermostatic oven. Alternatively, the vibrator 10 may be a vibrator built into an SPXO (Simple Packaged Crystal Oscillator). Note that the vibrator 10 of this embodiment can also be realized by various vibrating pieces, such as a vibrating piece other than a thickness-shear type, tuning-fork type, or double-ended tuning-fork type, or a piezoelectric vibrating piece made of a material other than quartz. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate can be used.

[0022] The oscillator circuit 30 is a circuit that oscillates the resonator 10. For example, the oscillator circuit 30 is electrically connected to pads PX1 and PX2 and generates an oscillation signal OSC by oscillating the resonator 10. Pad PX1 is a pad for connecting a first resonator, and pad PX2 is a pad for connecting a second resonator. For example, the oscillator circuit 30 can be realized by an oscillation driver circuit provided between pads PX1 and PX2 and active elements such as capacitors and resistors. The driver circuit can be realized, for example, by a CMOS inverter circuit or a bipolar transistor. The driver circuit is the core circuit of the oscillator circuit 30, and the driver circuit drives the resonator 10 with voltage or current to oscillate the resonator 10. Various types of oscillator circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used as the oscillator circuit 30. The oscillator circuit 30 also includes a variable capacitance circuit, the capacitance of which can be adjusted to adjust the oscillation frequency. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor. For example, the variable capacitance circuit can be realized by a variable capacitance element whose capacitance is controlled based on a temperature compensation voltage. Alternatively, the variable capacitance circuit may be realized by a capacitor array and a switch array connected to the capacitor array. Furthermore, the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows electrical signals to be transmitted, and is a connection that enables information to be transmitted by electrical signals. The electrical connection may be a connection via a passive element or the like.

[0023] The waveform shaping circuit 82 includes a first-stage inverter circuit IV1 to which the oscillation signal OSC is input, and a second-stage inverter circuit IV2 to which the output of the inverter circuit IV1 is input. The inverter circuit IV1 includes a P-type transistor TA1 and an N-type transistor TA2 connected in series between a node of the power supply voltage VREG and a GND node. The inverter circuit IV2 includes a P-type transistor TA3 and an N-type transistor TA4 connected in series between the node of VREG and a GND node. The power supply voltage VREG is, for example, a voltage obtained by regulating an external power supply voltage using a regulator.

[0024] The output buffer circuit 84 includes buffer circuits BF1, BF2, and BF3. The output of the waveform shaping circuit 82 is input to the buffer circuit BF1. The buffer circuit BF3 outputs the output clock signal CKQ to the pad PCK, which is the output terminal of the circuit device 20. The buffer circuit BF2 is provided between the buffer circuits BF1 and BF3. The buffer circuit BF3 may be a CMOS output circuit or a circuit that outputs a clipped sine wave signal. Note that the waveform-shaped clock signal CK is the output signal of the waveform shaping circuit 82 in FIG. 1, but is the output signal of the buffer circuit BF2 in FIG. 2. In this way, the waveform-shaped clock signal CK may be any signal based on the signal waveform-shaped by the waveform shaping circuit 82.

[0025] Resistors R1 and R2 are connected in series between the VREG node and the GND node, and have the same resistance value. Therefore, the comparator 62 receives a DC voltage VDC, which is a smoothed version of the waveform-shaped clock signal CK, at its first input terminal, which is its non-inverting input terminal, and a reference voltage VRF=VREG / 2 at its second input terminal, which is its inverting input terminal.

[0026] The logic circuit 60 is a control circuit that performs various control processes. For example, the logic circuit 60 performs overall control of the circuit device 20 and controls the operation sequence of the circuit device 20. The logic circuit 60 also performs various processes for controlling the oscillator circuit 30 and controls the reading and writing of information from and to the nonvolatile memory 72. The logic circuit 60 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and routed using a gate array or the like.

[0027] The nonvolatile memory 72 is a memory that retains information even when power is not supplied. For example, the nonvolatile memory 72 is a memory that can retain information even when power is not supplied and that allows information to be rewritten. The nonvolatile memory 72 stores various information necessary for the operation of the circuit device 20. The nonvolatile memory 72 can be realized by an EEPROM (Electrically Erasable Programmable Read-Only Memory) realized by a FAMOS memory (Floating gate Avalanche injection MOS memory) or a MONOS memory (Metal-Oxide-Nitride-Oxide-Silicon memory), or the like.

[0028] The bias voltage output circuit 50 includes a ladder resistor circuit 52 and a selector 54. The ladder resistor circuit 52 is provided between a VREG node, which is a high-potential power supply node, and a GND node, which is a low-potential power supply node. For example, the ladder resistor circuit 52 includes multiple resistors provided in series between the VREG node and the GND node. The selector 54 selects one of the multiple voltage division taps TP1 to TPn (n is an integer of 2 or greater) of the ladder resistor circuit 52 based on the adjustment value AJ. Each of the voltage division taps TP1 to TPn is a tap at a connection node between two adjacent resistors of the multiple resistors that make up the ladder resistor circuit 52.

[0029] In the circuit device 20 of this embodiment configured as described above, the comparator 62 compares the DC voltage VDC obtained by smoothing the clock signal CK after the oscillation signal OSC has been waveform-shaped by the waveform shaping circuit 82 with the reference voltage VRF, and outputs the comparison result to the logic circuit 60. The bias voltage output circuit 50 outputs a bias voltage VBS for the oscillation signal OSC to be input to the waveform shaping circuit 82, and the logic circuit 60 sets an adjustment value AJ for the bias voltage VBS of the bias voltage output circuit 50. In test mode, the logic circuit 60 changes the adjustment value AJ and determines the setting value of the adjustment value AJ based on the output of the comparator 62 when the adjustment value AJ is changed. For example, the circuit device 20 is set to test mode during inspection of the circuit device 20 and the oscillator 4 before product shipment. In this test mode, the logic circuit 60 varies the adjustment value AJ using a predetermined search algorithm, such as a binary search (described later), to vary the bias voltage VBS of the oscillation signal OSC and monitor the output of the comparator 62, which compares the DC voltage VDC, which is a smoothed version of the clock signal CK, with the reference voltage VRF. Based on the output of the comparator 62, the logic circuit 60 uses the search algorithm to search for an adjustment value AJ that sets the duty ratio of the clock signal CK to a predetermined duty ratio, such as 50%. For example, in FIG. 2, the comparator 62 compares the DC voltage VDC with a reference voltage VRF=VREG / 2, which is half the power supply voltage VREG of the waveform shaping circuit 82 that shapes the waveform of the oscillation signal OSC. Therefore, based on the output of the comparator 62, the logic circuit 60 can determine the setting value of the adjustment value AJ that sets the duty ratio of the output clock signal CKQ to, for example, 50% by searching for the adjustment value AJ that makes the DC voltage VDC approximately equal to the reference voltage VRF. The logic circuit 60 then stores the set value of the adjustment value AJ determined in this manner in the nonvolatile memory 72, which is the storage circuit 70. In this way, the adjustment value AJ determined in this manner is input to the bias voltage output circuit 50, which enables the bias voltage output circuit 50 to output a bias voltage VBS that sets the duty ratio of the output clock signal CKQ, which is based on the clock signal CK, to a predetermined duty ratio, such as 50%.This allows the circuit device 20 to output an output clock signal CKQ with a predetermined duty ratio as an output clock signal CKQ based on the clock signal CK.

[0030] For example, in the prior art of Patent Document 1, during normal operation when an oscillator outputs a clock signal, a signal based on the clock signal is fed back to the amplifier on the input side. This causes noise leakage, which can ultimately lead to a further deterioration of the noise characteristics of the clock signal. For example, Figure 3 is an explanatory diagram of phase noise occurring in a clock signal. The horizontal axis of Figure 3 represents frequency, and the vertical axis represents phase noise. In the prior art method of feeding back a signal based on the clock signal to the amplifier on the input side, spurious signals are generated around a frequency of, for example, 200 kHz, as shown by A1 in Figure 3, deteriorating the noise characteristics.

[0031] In this regard, the technique of this embodiment, as shown in A2 of FIG. 3, does not generate spurious signals as in the conventional technology, and can prevent deterioration of noise characteristics. That is, in this embodiment, in test mode, the adjustment value AJ is set to an appropriate setting value, and the bias voltage VBS of the oscillation signal OSC is set to an appropriate voltage, thereby setting the duty ratio of the output clock signal CKQ to a duty ratio within the required specification range. For example, the duty ratio is set to a duty ratio within the required specification range, such as 50% ±2%. Furthermore, in normal mode, which is the normal operation mode, feedback as in the conventional technology is not required, and therefore deterioration of noise characteristics can be effectively prevented, as shown in A2 of FIG. 3.

[0032] Next, the relationship between the setting of the bias voltage VBS using the adjustment value AJ and the duty ratio will be described. For example, when the bias voltage VBS is adjusted to a low voltage using the adjustment value AJ, the duty ratio corresponding to the width of the H level of the output signal of the inverter circuit IV1 in the first stage of the waveform shaping circuit 82 increases. As a result, the duty ratio corresponding to the width of the H level of the output clock signal CKQ, which is the final output of the circuit device 20, decreases. Furthermore, when the bias voltage VBS is adjusted to a high voltage using the adjustment value AJ, the duty ratio of the output signal of the inverter circuit IV1 in the first stage of the waveform shaping circuit 82 decreases. As a result, the duty ratio of the output clock signal CKQ increases.

[0033] Suppose, for example, that fluctuations in the semiconductor manufacturing process cause the performance of the N-type transistors to slow down. In this case, the performance of the N-type transistor TA2 in the first-stage inverter circuit IV1 of the waveform shaping circuit 82 is low, so the duty ratio of the output signal from the inverter circuit IV1 increases, and the duty ratio of the output clock signal CKQ becomes smaller than 50%, for example. In this case, to make the duty ratio of the output clock signal CKQ 50%, the bias voltage VBS is increased by the adjustment value AJ. Increasing the bias voltage VBS in this way reduces the duty ratio of the output signal from the first-stage inverter circuit IV1 of the waveform shaping circuit 82 and increases the duty ratio of the output clock signal CKQ, making it possible to adjust the duty ratio to 50%.

[0034] As described above, in this embodiment, in test mode during manufacturing, the duty ratio of the output clock signal CKQ is set by adjusting the bias voltage VBS using the adjustment value AJ. This makes it possible to store the setting value of the adjustment value AJ, which sets the output clock signal CKQ to an appropriate duty ratio, in the storage circuit 70, such as the nonvolatile memory 72, even if the transistor performance fluctuates due to variations in the manufacturing process. Therefore, it is possible to prevent variations in the duty ratio of the output clock signal CKQ due to variations in the manufacturing process.

[0035] In this embodiment, the bias voltage output circuit 50 outputs the bias voltage VBS in normal mode based on the adjustment value AJ, which is determined by the setting value stored in the memory circuit 70. For example, in this embodiment, as described above, the setting value of the adjustment value AJ, which sets the output clock signal CKQ to an appropriate duty ratio, is determined in test mode, and the determined setting value is stored in the memory circuit 70. In normal mode, the bias voltage output circuit 50 outputs the bias voltage VBS of the oscillation signal OSC based on the adjustment value AJ, which is determined by the setting value stored in the memory circuit 70. In this manner, in normal mode, the bias voltage output circuit 50 can output the bias voltage VBS based on the adjustment value AJ, which is determined by the setting value, which sets the output clock signal CKQ to an appropriate duty ratio in test mode. Therefore, in normal mode, the circuit device 20 can output the output clock signal CKQ with an appropriate duty ratio, just like in test mode. Furthermore, since a feedback path such as that described in Patent Document 1 is not required in normal mode, deterioration of noise characteristics can be prevented, as described in FIG. 3. Therefore, it is possible to achieve both the output of the output clock signal CKQ with an appropriate duty ratio and the prevention of deterioration of noise characteristics.

[0036] 2, the bias voltage output circuit 50 includes a ladder resistor circuit 52 provided between the VREG node and the GND node, and a selector 54 that selects one of the multiple voltage division taps TP1 to TPn of the ladder resistor circuit 52 based on the adjustment value AJ. In this manner, the selector 54 selects one of the multiple voltage division taps TP1 to TPn of the ladder resistor circuit 52 based on the adjustment value AJ from the logic circuit 60, thereby making it possible to output a bias voltage VBS corresponding to the adjustment value AJ as the bias voltage for the oscillation signal OSC. Therefore, the bias voltage output circuit 50 with a simple configuration can output the bias voltage VBS corresponding to the adjustment value AJ from the logic circuit 60, and output an output clock signal CKQ with an appropriate duty ratio.

[0037] 2, the storage circuit 70 in FIG. 1 is replaced with a nonvolatile memory 72. In this way, the setting value of the adjustment value AJ that sets the output clock signal CKQ to an appropriate duty ratio is stored in the nonvolatile memory 72, which can retain information even without power being supplied. Therefore, when power is turned on in normal mode, the logic circuit 60 reads the setting value of the adjustment value AJ from the nonvolatile memory 72 and outputs it to the bias voltage output circuit 50, thereby making it possible to output an output clock signal CKQ with an appropriate duty ratio.

[0038] 2. Other specific examples FIG. 4 shows another specific example of the configuration of the circuit device 20 of this embodiment. The difference between the configuration of FIG. 4 and that of FIG. 2 is that the bias voltage output circuit 50 includes transistors TB1 and TB2, which are replicas of the transistors TA1 and TA2 of the first-stage inverter circuit IV1 of the waveform shaping circuit 82. That is, in FIG. 4, the bias voltage output circuit 50 includes a P-type transistor TB1, which is provided between a VREG node, which is a high-potential power supply node, and one end of a ladder resistor circuit 52 and receives a bias voltage VBS at its gate. One end of the ladder resistor circuit 52 is the high-potential end of the ladder resistor circuit 52, i.e., the end of the resistor located at the highest potential among the multiple resistors in the ladder resistor circuit 52. The bias voltage output circuit 50 also includes an N-type transistor TB2, which is provided between the other end of the ladder resistor circuit 52 and a GND node, which is a low-potential power supply node, and receives a bias voltage VBS at its gate. The other end of the ladder resistor circuit 52 is one end on the low potential side of the ladder resistor circuit 52, and is one end of the resistor of the plurality of resistors in the ladder resistor circuit 52 that is provided on the lowest potential side.

[0039] In this way, by providing transistors TB1 and TB2, which are replicas of the transistors TA1 and TA2 of the first-stage inverter circuit IV1 of the waveform shaping circuit 82, in the bias voltage output circuit 50, it is possible to suppress the effects of corner variations in the semiconductor manufacturing process. Corner variations include variations in FF, SS, SF, and FS. FF is the case when both the N-type transistor and the P-type transistor are fast. SS is the case when both the N-type transistor and the P-type transistor are slow. SF is the case when the N-type transistor is slow and the P-type transistor is fast. FS is the case when the N-type transistor is fast and the P-type transistor is slow.

[0040] For example, in Figure 4, when the N-type transistor TA2 and P-type transistor TA1 of the waveform shaping circuit 82 become FAST, the N-type transistor TB2 and P-type transistor TB1 of the ladder resistor circuit 52 also become FAST. Therefore, the effect of corner variations in FF can be reduced. Also, when the N-type transistor TA2 and P-type transistor TA1 of the waveform shaping circuit 82 become SLOW, the N-type transistor TB2 and P-type transistor TB1 of the ladder resistor circuit 52 also become SLOW. Therefore, the effect of corner variations in SS can be reduced. The same applies to corner variations in FS and SF.

[0041] Furthermore, by reducing the effect of corner variations in the semiconductor manufacturing process in this way, the adjustment range in the ladder resistor circuit 52 can be narrowed, thereby realizing a reduction in the area of ​​the bias voltage output circuit 50. For example, the layout area of ​​the multiple resistors in the ladder resistor circuit 52 is larger than that of other circuits, but by reducing the adjustment range, the layout area of ​​these multiple resistors can be reduced, thereby realizing a reduction in the area of ​​the circuit device 20.

[0042] 5 shows another specific example of the configuration of the circuit device 20 and oscillator 4 of this embodiment. In FIG. 5, the circuit device 20 further includes a temperature compensation circuit 40, a temperature sensor 48, and a power supply circuit 90. Furthermore, the power supply voltage VDD and the ground voltage GND are supplied from the terminals TVDD and TGND of the oscillator 4 to the pads PVDD and PGND of the circuit device 20. Furthermore, the output clock signal CKQ from the output circuit 80 is output to the outside from the pad PCK of the circuit device 20 via the terminal TCK of the oscillator 4.

[0043] The power supply circuit 90 is supplied with VDD from the pad PVDD and GND from the pad PGND, and supplies various power supply voltages for the internal circuits of the circuit device 20 to the internal circuits. For example, the power supply circuit 90 supplies regulated power supply voltages obtained by regulating the power supply voltage VDD to each circuit of the circuit device 20.

[0044] The temperature compensation circuit 40 is a circuit that performs temperature compensation for the oscillation frequency of the oscillation circuit 30. For example, the temperature compensation circuit 40 outputs a temperature compensation voltage VCP that temperature-compensates the oscillation frequency of the oscillation circuit 30 based on a temperature detection voltage VTS that is the temperature detection result of the temperature sensor 48. Temperature compensation is a process that suppresses and compensates for fluctuations in the oscillation frequency due to temperature fluctuations, for example. In other words, the temperature compensation circuit 40 performs temperature compensation for the oscillation frequency of the oscillation circuit 30 so that the oscillation frequency remains constant even when temperature fluctuations occur.

[0045] Specifically, the temperature compensation circuit 40 performs analog temperature compensation using, for example, polynomial approximation. For example, when the temperature compensation voltage VCP that compensates for the frequency-temperature characteristics of the vibrator 10 is approximated by a polynomial, the temperature compensation circuit 40 performs analog temperature compensation based on coefficient information of the polynomial. Analog temperature compensation is temperature compensation achieved by, for example, adding analog signals such as current signals and voltage signals. For example, when the temperature compensation voltage VCP is approximated by a high-order polynomial, the zeroth-order coefficient, first-order coefficient, and higher-order coefficient of the polynomial are stored, for example, in the nonvolatile memory 72 as zeroth-order correction data, first-order correction data, and higher-order correction data, respectively. The high-order coefficients are, for example, coefficients of a higher order than first order, and the high-order correction data is correction data corresponding to the higher-order coefficients. For example, when the temperature-compensated voltage VCP is approximated by a third-order polynomial, the zeroth-order coefficient, first-order coefficient, second-order coefficient, and third-order coefficient of the polynomial are stored in the nonvolatile memory 72 as zeroth-order correction data, first-order correction data, second-order correction data, and third-order correction data. The temperature compensation circuit 40 then performs temperature compensation based on the zeroth-order correction data to the third-order correction data. In this case, the second-order correction data and temperature compensation based on the second-order correction data may be omitted. For example, when the temperature-compensated voltage VCP is approximated by a fifth-order polynomial, the zeroth-order coefficient, first-order coefficient, second-order coefficient, third-order coefficient, fourth-order coefficient, and fifth-order coefficient of the polynomial are stored in the nonvolatile memory 72 as zeroth-order correction data, first-order correction data, second-order correction data, third-order correction data, fourth-order correction data, and fifth-order correction data. The temperature compensation circuit 40 then performs temperature compensation based on the zeroth-order correction data to the fifth-order correction data. In this case, the second-order correction data or fourth-order correction data, or temperature compensation based on the second-order correction data or fourth-order correction data may be omitted. The degree of polynomial approximation may be any, and for example, polynomial approximation of a degree greater than 5 may be performed. The temperature sensor 48 may also perform zero-order correction.

[0046] The temperature sensor 48 is a sensor that detects temperature. Specifically, the temperature sensor 48 outputs a temperature-dependent voltage that changes according to the environmental temperature as the temperature detection voltage VTS. For example, the temperature sensor 48 generates the temperature detection voltage VTS, which is a temperature detection signal, by using a circuit element that has temperature dependency. Specifically, the temperature sensor 48 outputs the temperature detection voltage VTS, which changes depending on the temperature, by using, for example, the temperature dependency of the forward voltage of a PN junction. Note that a modification using a digital temperature sensor circuit as the temperature sensor 48 is also possible. In this case, the temperature detection data can be D / A converted to generate the temperature detection voltage VTS.

[0047] As described above, the circuit device 20 of this embodiment includes a temperature compensation circuit 40 that performs temperature compensation for the oscillation frequency of the oscillation signal OSC. As shown in Fig. 5, the bias voltage output circuit 50 outputs a bias voltage VBS for the oscillation signal OSC and also outputs a reference voltage VRC for temperature compensation of the temperature compensation circuit 40 to the temperature compensation circuit 40.

[0048] For example, as described above, the selector 54 of the bias voltage output circuit 50 selects one of the multiple voltage division taps of the ladder resistor circuit 52 based on the adjustment value AJ from the logic circuit 60, thereby outputting the bias voltage VBS of the oscillation signal OSC. Meanwhile, the selector 54 selects one of the multiple voltage division taps of the ladder resistor circuit 52 based on the second adjustment value AJ2 from the logic circuit 60, thereby outputting the temperature compensation reference voltage VRC to the temperature compensation circuit 40. In this way, circuits such as the selector 54 of the bias voltage output circuit 50 can be effectively utilized to generate and output not only the bias voltage VBS but also the temperature compensation reference voltage VRC, thereby enabling circuit sharing and enabling the circuit device 20 to be made smaller.

[0049] FIG. 6 shows an example configuration of the temperature compensation circuit 40. The temperature compensation circuit 40 is a circuit that outputs a temperature-compensated voltage VCP by polynomial approximation using temperature as a variable. This temperature compensation circuit 40 includes a current generation circuit 42 and a current-voltage conversion circuit 46. The current generation circuit 42 generates a function current based on the temperature detection result of a temperature sensor 48. For example, the current generation circuit 42 generates a function current for temperature compensation of the frequency-temperature characteristics of the resonator 10 based on a temperature detection voltage VTS, which is the temperature detection result from the temperature sensor 48. The current-voltage conversion circuit 46 then converts the function current from the current generation circuit 42 into a voltage and outputs the temperature-compensated voltage VCP.

[0050] The current generating circuit 42 includes a first-order correction circuit 43 and a high-order correction circuit 44. The first-order correction circuit 43 outputs a first-order current that approximates a linear function based on the temperature detection voltage VTS. For example, the first-order correction circuit 43 outputs a linear function current based on first-order correction data corresponding to a first-order coefficient of a polynomial in the polynomial approximation. The high-order correction circuit 44 outputs a high-order current that approximates a high-order function based on the temperature detection voltage VTS to the current-voltage conversion circuit 46. For example, the high-order correction circuit 44 outputs a high-order current based on high-order correction data corresponding to a high-order coefficient of a polynomial in the polynomial approximation. As an example, the high-order correction circuit 44 outputs a tertiary current that approximates a cubic function. In this case, the high-order correction circuit 44 includes a first differential circuit that performs a differential operation based on the temperature detection voltage VTS and a second differential circuit that performs a differential operation based on the output voltage of the first differential circuit and the temperature detection voltage VTS to output a tertiary current. In FIG. 6, the temperature sensor 48 performs offset correction of the temperature detection voltage VTS based on zero-order correction data corresponding to the zero-order coefficient of the polynomial. That is, the temperature sensor 48 adjusts the offset of the temperature detection voltage VTS by the amount of the offset indicated by the zero-order correction data. The offset correction of the temperature detection voltage VTS corresponds to zero-order correction in temperature compensation of the oscillation frequency. The high-order correction circuit 44 may further include a correction circuit that performs fourth-order or higher correction. For example, the high-order correction circuit 44 may further include a fourth-order correction circuit that outputs a fourth-order current that approximates a fourth-order function and a fifth-order correction circuit that outputs a fifth-order current that approximates a fifth-order function.

[0051] The current-voltage conversion circuit 46 adds the primary current and the higher-order current and performs current-to-voltage conversion on the added current to output a temperature-compensated voltage VCP, thereby generating a temperature-compensated voltage VCP that approximates a polynomial function.

[0052] The temperature compensation reference voltage VRC from the bias voltage output circuit 50 is supplied to the current-voltage conversion circuit 46 as shown in FIG. 6, and is also supplied to the first-order correction circuit 43 and the high-order correction circuit 44 of the current generation circuit 42. For example, the reference voltage VRC is supplied to the first-order correction circuit 43 and the high-order correction circuit 44 as a voltage corresponding to an inflection point of the temperature characteristics. For example, at an inflection point corresponding to a typical temperature, the currents flowing from the first-order correction circuit 43 and the high-order correction circuit 44 are set to zero. The first-order correction circuit 43 generates a current of a linear function with the inflection point as its origin. The high-order correction circuit 44 generates a current of a high-order function with the inflection point as its origin. The inflection point is set by the reference voltage VRC.

[0053] 3. Binary Search In this embodiment, the logic circuit 60 determines the setting value of the adjustment value AJ by changing the adjustment value AJ, for example, by binary search. Then, the logic circuit 60 writes the setting value determined in the test mode to the storage circuit 70, such as the nonvolatile memory 72. In this way, it is possible to efficiently search for the setting value of the adjustment value AJ that sets the output clock signal CKQ to an appropriate duty ratio by binary search, and to store the searched setting value in the storage circuit 70.

[0054] FIG. 7 is an explanatory diagram of the process for determining a set value using a binary search. In this embodiment, a binary search search algorithm is used to search for an adjustment value AJ that sets the bias voltage VBS so that the duty ratio is 50%. First, as shown in B1 of FIG. 7, the logic circuit 60 inputs an intermediate value as the adjustment value AJ to the bias voltage output circuit 50. As a result, when the output of the comparator 62 becomes high as shown in FIG. 7, it means that the duty ratio is greater than 50%. Therefore, the logic circuit 60 inputs an intermediate value on the setting side that reduces the duty ratio as shown in B2. As a result, when the output of the comparator 62 becomes low as shown in FIG. 7, it means that the duty ratio is less than 50%. Therefore, the logic circuit 60 inputs an intermediate value on the setting side that increases the duty ratio as shown in B3. In this way, the search is repeated three more times as shown in B4, B5, and B6 of FIG. 7. After six iterations, the logic circuit 60 successfully finds the adjustment value AJ that sets the duty ratio to 50%. In Figure 7, it is found that the duty ratio is 50% when the adjustment value AJ = 45, as shown in B6, so the setting value AJ = 45 is written to the memory circuit 70, such as the non-volatile memory 72.

[0055] 8 is a flowchart of the process for determining a set value using a binary search. First, the logic circuit 60 sets the adjustment value AJ to be input to the bias voltage output circuit 50 to the center value of the search range (step S11). Then, the logic circuit 60 determines whether the output of the comparator 62 is H level or L level (step S12). If the output of the comparator 62 is H level, the logic circuit 60 determines whether the search range is divisible (step S13). If divisible, the logic circuit 60 narrows the search range to half on the MSB side (step S14) and returns to step S11. On the other hand, if the output of the comparator 62 is L level, the logic circuit 60 determines whether the search range is divisible (step S15). If divisible, the logic circuit 60 narrows the search range to half on the LSB side (step S16) and returns to step S11. The logic circuit 60 repeats the above process until the search range is no longer divisible, thereby determining the setting value of the adjustment value AJ, and stores the determined setting value in the memory circuit 70. As described above, in this embodiment, the setting value of the adjustment value AJ is determined by changing the adjustment value through a binary search, so that it is possible to efficiently search for the setting value of the adjustment value AJ that sets the output clock signal CKQ to an appropriate duty ratio through a binary search.

[0056] 4. Manufacturing method Next, a method for manufacturing the oscillator 4 of this embodiment will be described. Fig. 9 is a flow diagram illustrating the method for manufacturing the oscillator 4 of this embodiment. Note that the flow diagram of Fig. 9 is based on the premise that a process for manufacturing an IC chip of the circuit device 20 by forming circuit elements on a semiconductor wafer and dicing it, and a process for manufacturing the oscillator 4 by packaging the IC chip of the circuit device 20 and the resonator 10 have been performed.

[0057] First, as shown in step S21 of FIG. 9 , a step of setting the circuit device 20 to a test mode is performed. The test mode setting is realized, for example, by using a tester to write the test mode setting to a mode setting register of the logic circuit 60. Next, as shown in step S22, a step of changing the adjustment value AJ in the test mode is performed. Then, as shown in step S23, a step of searching for an adjustment value AJ that sets the duty ratio of the output clock signal CKQ to a predetermined duty ratio, such as 50%, is performed based on the output of the comparator 62 when the adjustment value AJ is changed. For example, a search for an adjustment value AJ that sets the duty ratio to a predetermined duty ratio is performed by a binary search as shown in FIGS. 7 and 8 . Specifically, the logic circuit 60 searches for an adjustment value AJ that sets the duty ratio to a predetermined duty ratio by executing a search algorithm such as a binary search while changing the adjustment value AJ.

[0058] Next, as shown in step S24, it is determined whether an adjustment value AJ for setting the output clock signal CKQ to a predetermined duty ratio has been found, and if not, the process returns to step S22. On the other hand, if an adjustment value AJ has been found, a step of determining the found adjustment value AJ as a set value is performed as shown in step S25. Then, as shown in step S26, a step of writing the determined set value into the storage circuit 70 is performed. Specifically, the logic circuit 60 performs a process of writing the determined set value into the storage circuit 70, such as the nonvolatile memory 72.

[0059] As described above, the manufacturing method of this embodiment includes the step of setting the circuit device 20 to a test mode (S21) and the step of varying the adjustment value AJ in the test mode (S22). The manufacturing method of this embodiment also includes the steps of searching for an adjustment value AJ that sets the duty ratio of the output clock signal CKQ to a predetermined duty ratio based on the output of the comparator 62 when the adjustment value AJ is varied (S23, S24). The manufacturing method of this embodiment also includes the step of determining the searched adjustment value AJ as the setting value of the adjustment value AJ (S25) and the step of storing the determined setting value in the memory circuit 70 (S26). This manufacturing method of the oscillator 4 makes it possible to manufacture an oscillator 4 that can output an output clock signal CKQ that is appropriately set to a predetermined duty ratio and that can effectively prevent deterioration of the noise characteristics of the output clock signal CKQ.

[0060] 5. Oscillator FIG. 10 shows a first structural example of the oscillator 4 of this embodiment. The oscillator 4 has a resonator 10, a circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 is made of, for example, ceramic or the like, and has an internal housing space in which the resonator 10 and the circuit device 20 are housed. The housing space is hermetically sealed and is preferably in a reduced pressure state that is close to a vacuum. The package 15 can suitably protect the resonator 10 and the circuit device 20 from impact, dust, heat, moisture, and the like.

[0061] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of the base 16, which supports the resonator 10 and the circuit device 20, and the lid 17, which is bonded to the upper surface of the base 16 so as to form an accommodation space between the base 16 and the lid 17. The resonator 10 is supported via terminal electrodes on a stepped portion provided on the inside of the base 16. The circuit device 20 is disposed on the inside bottom surface of the base 16. Specifically, the circuit device 20 is disposed so that its active surface faces the inside bottom surface of the base 16. The active surface is the surface on which circuit elements of the circuit device 20 are formed. Bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inside bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, and the resonator 10 and the circuit device 20 are electrically connected via the bumps BMP, the internal wiring of the package 15, and the terminal electrodes. The circuit device 20 is also electrically connected to external terminals 18 and 19 of the oscillator 4 via bumps BMP and internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. This makes it possible to output a clock signal or the like to the external device.

[0062] 10, the circuit device 20 is flip-mounted so that the active surface of the circuit device 20 faces downward, but this embodiment is not limited to such mounting. For example, the circuit device 20 may be mounted so that the active surface of the circuit device 20 faces upward. In other words, the circuit device 20 is mounted so that the active surface faces the vibrator 10.

[0063] FIG. 11 shows a second structural example of the oscillator 4. The oscillator 4 includes a resonator 10, a circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 includes a base 16 and a lid 17. The base 16 includes a first substrate 6, which is an intermediate substrate; a second substrate 7 having a substantially rectangular frame shape and stacked on the top surface of the first substrate 6; and a third substrate 8 having a substantially rectangular frame shape and stacked on the bottom surface of the first substrate 6. The lid 17 is bonded to the top surface of the second substrate 7, and the resonator 10 is housed in a housing space S1 formed by the first substrate 6, the second substrate 7, and the lid 17. For example, the resonator 10 is hermetically sealed in the housing space S1, preferably in a reduced pressure state close to a vacuum. This allows the resonator 10 to be suitably protected from impact, dust, heat, moisture, and the like. The housing space S2 formed by the first substrate and the third substrate 8 houses a circuit device 20, which is a semiconductor chip. Furthermore, external terminals 18 and 19, which are electrode terminals for external connection of oscillator 4, are formed on the bottom surface of third substrate 8.

[0064] In the accommodation space S1, the vibrator 10 is connected to a first electrode terminal and a second electrode terminal (not shown) formed on the upper surface of the first substrate 6 via conductive connection parts CDC1 and CDC2. The conductive connection parts CDC1 and CDC2 may be implemented by conductive bumps such as metal bumps or by a conductive adhesive. Specifically, for example, a first electrode pad (not shown) formed on one end of the tuning-fork-shaped vibrator 10 is connected to a first electrode terminal formed on the upper surface of the first substrate 6 via the conductive connection part CDC1. The first electrode terminal is then electrically connected to a pad PX1 of the circuit device 20. A second electrode pad (not shown) formed on the other end of the tuning-fork-shaped vibrator 10 is connected to a second electrode terminal formed on the upper surface of the first substrate 6 via the conductive connection part CDC2. The second electrode terminal is then electrically connected to a pad PX2 of the circuit device 20. This allows one end and the other end of the vibrator 10 to be electrically connected to the pads PX1 and PX2 of the circuit device 20 via the conductive connection parts CDC1 and CDC2. Furthermore, conductive bumps BMP are formed on a plurality of pads of the circuit device 20, which is a semiconductor chip, and these conductive bumps BMP are connected to a plurality of electrode terminals formed on the bottom surface of the first substrate 6. The electrode terminals connected to the pads of the circuit device 20 are then electrically connected to external terminals 18, 19 of the oscillator 4 via internal wiring or the like.

[0065] The oscillator 4 may be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes a semiconductor substrate, a base having a through electrode penetrating between the first and second surfaces of the semiconductor substrate, a resonator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding material such as a metal bump, and external terminals provided on the second surface of the semiconductor substrate via an insulating layer such as a relocation wiring layer. An integrated circuit serving as the circuit device 20 is formed on the first or second surface of the semiconductor substrate. In this case, a first semiconductor wafer having multiple bases on which the resonators 10 and the integrated circuits are arranged is bonded to a second semiconductor wafer having multiple lids, and the multiple bases and lids are then bonded together. The oscillators 4 are then individually separated using a dicing saw or the like. This allows for the realization of a wafer-level package oscillator 4, enabling high-throughput, low-cost manufacturing of the oscillators 4.

[0066] As described above, the circuit device of this embodiment includes a waveform shaping circuit that shapes the waveform of an oscillation signal and an output circuit that outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit.The circuit device also includes a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit, a comparator that compares a DC voltage obtained by smoothing the waveform-shaped clock signal with a reference voltage, a logic circuit that sets an adjustment value for the bias voltage of the bias voltage output circuit, and a memory circuit.The logic circuit changes the adjustment value in test mode, determines a setting value for the adjustment value based on the output of the comparator when the adjustment value is changed, and stores the determined setting value in the memory circuit.

[0067] According to this embodiment, an oscillation signal is waveform-shaped, and an output clock signal based on the waveform-shaped clock signal is output, along with a bias voltage for the oscillation signal. Furthermore, a DC voltage obtained by smoothing the waveform-shaped clock signal is compared with a reference voltage to set an adjustment value for the bias voltage. Then, in a test mode, the adjustment value is changed, and a set value for the adjustment value is determined based on the output of the comparator when the adjustment value is changed, and the determined set value is stored in a memory circuit. By determining the set value for the adjustment value in this manner, the duty ratio of the output clock signal can be set to an appropriate duty ratio. Furthermore, by storing the set value for the adjustment value in a memory circuit, deterioration of noise characteristics in the output clock signal can be prevented. Therefore, it is possible to provide a circuit device or the like that can output an output clock signal with an appropriate duty ratio and reduced noise deterioration.

[0068] In this embodiment, the bias voltage output circuit may output the bias voltage based on an adjustment value according to the set value stored in the storage circuit in the normal mode.

[0069] In this way, in the normal mode, the bias voltage output circuit can output the bias voltage based on the adjustment value according to the setting value that sets the output clock signal to an appropriate duty ratio in the test mode.

[0070] In addition, in this embodiment, the bias voltage output circuit may include a ladder resistor circuit provided between the high-potential side power supply node and the low-potential side power supply node, and a selector that selects one of multiple voltage division taps of the ladder resistor circuit based on an adjustment value.

[0071] In this way, a bias voltage output circuit with a simple configuration can output a bias voltage according to the adjustment value from the logic circuit, and an output clock signal with an appropriate duty ratio can be output.

[0072] In addition, in this embodiment, the bias voltage output circuit may include a P-type transistor provided between the high-potential side power supply node and one end of the ladder resistor circuit, and having a bias voltage input to its gate, and an N-type transistor provided between the other end of the ladder resistor circuit and the low-potential side power supply node, and having a bias voltage input to its gate.

[0073] This makes it possible to reduce the influence of corner variations in the semiconductor manufacturing process, and to narrow the adjustment width in the ladder resistor circuit.

[0074] In this embodiment, the logic circuit may determine the set value by changing the adjustment value through a binary search.

[0075] In this way, it is possible to efficiently search for the setting value of the adjustment value that sets the output clock signal to an appropriate duty ratio by binary search, and to store the searched setting value in the memory circuit.

[0076] In this embodiment, the storage circuit may be a nonvolatile memory.

[0077] In this way, the setting value of the adjustment value for setting the output clock signal to an appropriate duty ratio is stored in a nonvolatile memory that can retain information even without power supply.

[0078] This embodiment also includes a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the oscillation signal, and the bias voltage output circuit may output a reference voltage for temperature compensation to the temperature compensation circuit as well as outputting a bias voltage for the oscillation signal.

[0079] In this way, the bias voltage output circuit can be effectively utilized to generate and output not only the bias voltage but also the reference voltage for temperature compensation, thereby enabling the circuit to be shared and realizing a smaller circuit device.

[0080] The oscillator of this embodiment includes a resonator and a circuit device that generates an oscillation signal by oscillating the resonator. The circuit device also includes an output circuit that has a waveform shaping circuit that shapes the oscillation signal and outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit, a bias voltage output circuit that outputs a bias voltage for the oscillation signal input to the waveform shaping circuit, a comparator that compares a DC voltage obtained by smoothing the waveform-shaped clock signal with a reference voltage, a logic circuit that sets an adjustment value for the bias voltage of the bias voltage output circuit, and a memory circuit. The logic circuit changes the adjustment value in a test mode, determines a setting value for the adjustment value based on the output of the comparator when the adjustment value is changed, and stores the determined setting value in the memory circuit.

[0081] In this way, it is possible to provide an oscillator that can output an output clock signal that is set to an appropriate duty ratio and in which noise deterioration is reduced.

[0082] A manufacturing method according to this embodiment is a method for manufacturing an oscillator including a resonator and a circuit device that generates an oscillation signal by oscillating the resonator. The circuit device includes an output circuit having a waveform shaping circuit that shapes the waveform of the oscillation signal and outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit, a bias voltage output circuit that outputs a bias voltage for the oscillation signal input to the waveform shaping circuit, a comparator that compares a DC voltage obtained by smoothing the waveform-shaped clock signal with a reference voltage, and a memory circuit. The manufacturing method according to this embodiment includes the steps of setting the circuit device to a test mode, varying an adjustment value in the test mode, and searching for an adjustment value that sets the duty ratio of the output clock signal to a predetermined duty ratio based on the output of the comparator when the adjustment value is varied. The manufacturing method according to this embodiment also includes the steps of determining the found adjustment value as a setting value for the adjustment value and storing the determined setting value in the memory circuit.

[0083] In this way, it is possible to manufacture an oscillator that can output an output clock signal set to an appropriate predetermined duty ratio and that can effectively prevent deterioration of the noise characteristics of the output clock signal.

[0084] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device and oscillator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0085] 4...oscillator, 6...first board, 7...second board, 8...third board, 10...resonator, 15...package, 16...base, 17...lid, 18...external terminal, 19...external terminal, 20...circuit device, 30...oscillator circuit, 40...temperature compensation circuit, 42...current generation circuit, 43...first-order correction circuit, 44...high-order correction circuit, 46...current-voltage conversion circuit, 48...temperature sensor, 50...bias voltage output circuit, 52...ladder resistor circuit, 54...selector, 60...logic circuit, 62...comparator, 70...memory circuit, 72...non-volatile memory, 80...output circuit, 82...wave shaping circuit, 84...output buffer circuit, 90...power supply circuit , AJ...adjustment value, AJ2...second adjustment value, BF1, BF2, BF3...buffer circuit, BMP...bump, C...capacitor, CK...clock signal, CKQ...output clock signal, IV1, IV2...inverter circuit, NI...input node, OSC...oscillation signal, PCK, PGND, PVDD, PX1, PX2...pad, R, R1, R2, RB...resistor, S1, S2...accommodation space, TCK, TGND, TVDD...terminal, TP1~TPn...voltage division tap, VBS...bias voltage, VCP...temperature compensation voltage, VDC...DC voltage, VDD...power supply voltage, VRF, VRC, VREG...reference voltage, VTS...temperature detection voltage

Claims

1. an output circuit having a waveform shaping circuit for shaping the waveform of an oscillation signal, and outputting an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit; a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit; a comparator that compares a DC voltage obtained by smoothing the clock signal after the waveform shaping with a reference voltage; a logic circuit that sets an adjustment value of the bias voltage of the bias voltage output circuit; A memory circuit; Including, The logic circuit in a test mode, varying the adjustment value, determining a setting value for the adjustment value based on an output of the comparator when the adjustment value is varied, and storing the determined setting value in the memory circuit; The bias voltage output circuit a ladder resistor circuit provided between a high potential side power supply node and a low potential side power supply node; a selector that selects one of a plurality of voltage division taps of the ladder resistor circuit based on the adjustment value; A circuit device comprising:

2. 2. The circuit device according to claim 1, The bias voltage output circuit A circuit device, characterized in that in a normal mode, the bias voltage is output based on the adjustment value according to the setting value stored in the memory circuit.

3. 3. The circuit device according to claim 1, The bias voltage output circuit a P-type transistor provided between the high-potential power supply node and one end of the ladder resistor circuit, the P-type transistor having a gate to which a bias voltage is input; an N-type transistor provided between the other end of the ladder resistor circuit and the low potential side power supply node, the N-type transistor having a gate to which a bias voltage is input; A circuit device comprising:

4. 4. The circuit device according to claim 1, The logic circuit A circuit device characterized in that the setting value is determined by changing the adjustment value through a binary search.

5. 5. The circuit device according to claim 1, The circuit device is characterized in that the storage circuit is a nonvolatile memory.

6. 6. The circuit device according to claim 1, a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the oscillation signal; The bias voltage output circuit A circuit device that outputs the bias voltage of the oscillation signal and also outputs a reference voltage for temperature compensation to the temperature compensation circuit.

7. A vibrator and a circuit device that oscillates the vibrator to generate an oscillation signal; Including, The circuit device comprises: an output circuit having a waveform shaping circuit that shapes the waveform of the oscillation signal, and that outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit; a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit; a comparator that compares a DC voltage obtained by smoothing the clock signal after the waveform shaping with a reference voltage; a logic circuit that sets an adjustment value of the bias voltage of the bias voltage output circuit; A memory circuit; Including, The logic circuit in a test mode, varying the adjustment value, determining a setting value for the adjustment value based on an output of the comparator when the adjustment value is varied, and storing the determined setting value in the memory circuit; The bias voltage output circuit a ladder resistor circuit provided between a high potential side power supply node and a low potential side power supply node; a selector that selects one of a plurality of voltage division taps of the ladder resistor circuit based on the adjustment value; An oscillator comprising:

8. A method for manufacturing an oscillator including a vibrator and a circuit device that generates an oscillation signal by oscillating the vibrator, The circuit device comprises: an output circuit having a waveform shaping circuit that shapes the waveform of the oscillation signal, and that outputs an output clock signal based on the clock signal after waveform shaping by the waveform shaping circuit; a bias voltage output circuit that outputs a bias voltage of the oscillation signal input to the waveform shaping circuit; a comparator that compares a DC voltage obtained by smoothing the clock signal after the waveform shaping with a reference voltage; A memory circuit; Including, The bias voltage output circuit a ladder resistor circuit provided between a high potential side power supply node and a low potential side power supply node; a selector that selects one of a plurality of voltage division taps of the ladder resistor circuit based on an adjustment value; Including, setting the circuit device in a test mode; varying the adjustment value in the test mode; searching for an adjustment value that sets the duty ratio of the output clock signal to a predetermined duty ratio based on an output of the comparator when the adjustment value is changed; determining the searched adjustment value as a setting value of the adjustment value; storing the determined setting value in the storage circuit; A manufacturing method comprising:

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