Multilayer Printed Circuit Board

Abstract

To enable a reduction in reflection of a transmission signal generated in a signal path reached to an inner via hole (IVH) via a laser via hole (LVH) from a wiring pattern in a multilayer printed board even if an impedance of the IVH is not matched to the wiring pattern.SOLUTION: A multilayer printed board 1 comprises: an IVH 26 that penetrates two or more dielectric layers D3 to D5 on an inner layer side of the multilayer printed board, and conducts both of wiring patterns 16 and 18 formed in pattern layers P3 and P5 holding the dielectric layer therebetween; and LVHs 22 and 24 that are provided in dielectric layers D1 and D2 on the front layer side from the IVH, and conduct both of wiring patterns 12 to 14 and 14 to 16 of the pattern layers P1, P2, and P3 laminated on their front and back surfaces. In each pattern layer of both ends of the LVH, a clearance between the LVH and a ground pattern at the circumference is smaller on the inner layer side as compared with the front layer side.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to multilayer printed circuit boards. [Background technology]

[0002] Due to the strict requirements for radiated emissions, electronic control devices installed in vehicles are constructed using multilayer printed circuit boards that can utilize inner layer wiring. These types of multilayer printed circuit boards are becoming more and more multilayered, and not only do they have higher density wiring, but they are also required to transmit signals at speeds exceeding several GHz.

[0003] To meet this demand, it is necessary to match the impedance between the wiring patterns on each layer and the via holes that connect those wiring patterns to suppress reflection of the transmission signal.For this reason, as described in Patent Document 1, it has been proposed to provide ground vias around the via holes and adjust the clearance between the via holes and the surrounding ground patterns, thereby matching the impedance of the via holes with the wiring patterns. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6535546 Summary of the Invention [Problem to be solved by the invention]

[0005] In the case of a build-up board, which is a type of multilayer printed circuit board, the wiring patterns on each layer are connected using laser via holes (hereinafter referred to as LVHs) and inner via holes (hereinafter referred to as IVHs).The impedance of the LVHs and IVHs is lower than that of the wiring patterns on each layer.

[0006] In particular, IVHs have strong electromagnetic field coupling with the ground due to the ratio of the via diameter to the insulating layer thickness, resulting in lower impedance compared to other via holes such as LVHs. For this reason, the method described in Patent Document 1 has the problem that the impedance improvement effect is weak despite the large wiring constraints, and it is difficult to match the impedance of the IVH with the impedance of the surface wiring pattern.

[0007] One aspect of the present disclosure aims to reduce reflection of a transmission signal that occurs in a signal path from a wiring pattern to an IVH via an LVH in a multilayer printed circuit board, even if the impedance of the IVH does not match the surface wiring pattern. [Means for solving the problem]

[0008] A multilayer printed circuit board according to one aspect of the present disclosure includes a plurality of dielectric layers (D1-D7) and a plurality of pattern layers (P1-P8) alternately stacked, and includes an IVH (26) and an LVH (22, 24). As mentioned above, an IVH stands for an inner via hole, and an LVH stands for a laser via hole.

[0009] The IVH penetrates two or more dielectric layers on the inner layer side of a multilayer printed circuit board, providing electrical continuity between the wiring patterns (16-18) formed on the two pattern layers that sandwich the two or more dielectric layers. In other words, the IVH is a type of so-called interstitial via hole, also known as a buried via hole, that connects inner layers.

[0010] The LVH is provided on the dielectric layer on the surface side of the IVH, and connects the wiring patterns (12-14, 14-16) of the pattern layers stacked on the front and back sides of the dielectric layer, thereby forming a signal path between the wiring patterns on the surface side of the multilayer printed circuit board and the IVH.

[0011] In the plurality of pattern layers disposed on both ends of the LVH, the clearance between the LVH and the ground pattern around the LVH is smaller on the inner layer side than on the surface layer side of the LVH.

[0012] Therefore, in the multilayer printed circuit board of the present disclosure, the impedance of the input section on the surface side of the LVH can be maintained high while the impedance of the output section on the opposite side can be reduced, thereby suppressing reflection of transmission signals between the surface wiring pattern and the LVH and between the LVH and the IVH.

[0013] In other words, according to the multilayer printed circuit board of the present disclosure, the impedance change is gradual in the signal path from the wiring pattern on the surface layer to the IVH, and the reflection loss of the transmission signal occurring in that signal path can be reduced.

[0014] Therefore, the multilayer printed circuit board of the present disclosure can reduce the reflection loss of a transmission signal even when the impedance of the IVH is not matched to the impedance of the wiring pattern on the surface layer. Therefore, compared to the multilayer printed circuit board described in Patent Document 1, restrictions on manufacturing conditions and peripheral wiring can be relaxed, and the degree of freedom in designing a multilayer printed circuit board can be increased. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view illustrating a configuration of a multilayer printed circuit board according to an embodiment. [Figure 2] 10 is an explanatory diagram showing the shapes of pattern layers at both ends of an LVH connected to an IVH via a wiring pattern. FIG. [Figure 3] 3 is a perspective view showing a clearance between the LVH and the ground pattern in the pattern layers on both ends of the LVH shown in FIG. 2. FIG. [Figure 4] FIG. 1 is an explanatory diagram showing the size of the clearance around the LVH. [Figure 5] FIG. 10 is an explanatory diagram showing an example of a connection between a surface wiring pattern and an LVH and an IVH. [Figure 6]6 is an explanatory diagram showing the relationship between impedance and return loss of the wiring pattern, LVH, and IVH shown in FIG. 5. [Figure 7] FIG. 10 is an explanatory diagram showing the change in impedance when the clearances on the front and back surfaces of the LVH of the embodiment are the same. [Figure 8] 10 is an explanatory diagram showing a change in impedance when the clearance between the front and rear surfaces of the LVH of the embodiment is changed. FIG. [Figure 9] 1 is an explanatory diagram showing reflection loss occurring in a transmission path from a surface layer of a multilayer printed circuit board to an IVH according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [composition] As shown in Fig. 1, the multilayer printed circuit board 1 of this embodiment is a build-up board having N dielectric layers D1 to DN and N+1 pattern layers P1 to PN+1. A build-up board is a board manufactured by alternately stacking dielectric layers D and pattern layers P on a core printed circuit board. In this embodiment, the case where N=7 is illustrated.

[0017] 1, an electronic component 10 is mounted on a pattern layer P1, which is the surface layer of a multilayer printed circuit board 1. In addition, a wiring pattern 18 is formed on an inner pattern layer P6 of the multilayer printed circuit board 1, which constitutes a circuit that transmits and receives high-frequency signals to and from the electronic component 10 and performs signal processing.

[0018] Furthermore, in the multilayer printed circuit board 1, LVHs 22, 24 and IVHs 26 are used to connect the electronic components 10 on the surface layer with the wiring patterns 18 on the inner layers to form a transmission path for high frequency signals.

[0019] The IVHs 26 are provided so as to penetrate two or more dielectric layers, specifically, dielectric layers D3, D4, and D5, on the inner layers of the multilayer printed circuit board 1. The IVHs 26 provide electrical continuity between the wiring patterns 16 and 18 formed on the outer and inner pattern layers P3 and P6, respectively, of these dielectric layers D3 to D5.

[0020] The LVHs 22 and 24 penetrate the dielectric layers D1 and D2 on the surface side of the IVH 26, respectively, and provide electrical continuity between the signal transmission wiring patterns 12-14 and 14-16 formed on the pattern layers P1, P2, and P3 laminated on the front and back surfaces of the dielectric layers D1 and D2, respectively.

[0021] The LVH is a buried via that penetrates one dielectric layer D and connects two adjacent pattern layers P with the dielectric layer D in between, and is a well-known hole that is drilled using a laser.

[0022] Therefore, a high frequency signal output from electronic component 10 on the surface layer is transmitted to wiring pattern 18 on the inner layer through wiring pattern 12, LVH 22, wiring pattern 14, LVH 24, wiring pattern 16, and IVH 26 on the surface layer in this order.

[0023] To suppress the reflection of high-frequency signals that occurs in this transmission path and transmit high-frequency signals with low loss, the impedance of the wiring patterns 12, 14, 16, LVHs 22, 24, and IVHs 26 that make up the transmission path should be matched to the impedance of the wiring pattern 18.

[0024] However, since the IVH 26 is provided so as to sandwich a plurality of dielectric layers D, the impedance is smaller than that of the LVHs 22 and 24 due to the ratio between the diameter of the via and the thickness of the insulating layer formed by the plurality of dielectric layers D.

[0025] Therefore, even if the impedance of the IVH 26 is adjusted as described in Patent Document 1, it is difficult to match the impedance with the surface wiring pattern 12. Therefore, in this embodiment, rather than adjusting the impedance of the IVH 26, reflections occurring in the transmission path from the surface wiring pattern 12 to the IVH 26 are reduced, assuming that the impedance of the IVH 26 is low. In other words, by gradually changing the impedance of the LVHs 22, 24 arranged between the surface wiring pattern 12 and the IVH 26, reflections occurring in the transmission path are reduced.

[0026] For this reason, in this embodiment, in the pattern layers P1, P2, and P3 arranged on both ends of the LVHs 22 and 24, the clearance between the LVHs 22 and 24 and the surrounding ground patterns is adjusted so that it becomes smaller toward the inner layer side.

[0027] 2 and 3 show the LVH 24 and its surrounding ground patterns 32 and 33 on the pattern layers P2 and P3. As is clear from these figures, the sizes of the anti-pads AP1 and AP2 between the LVH 24 and its surrounding ground patterns 32 and 33 are adjusted so that the anti-pad AP2 on the inner layer side is smaller than the anti-pad AP1 on the exterior side.

[0028] Specifically, in each of the pattern layers P2 and P3, the diameters Φap1 and Φap2 of the anti-pads AP1 and AP2 from the center of the LVH 24 to the ground patterns 32 and 33 are set so that Φap1>Φap2.

[0029] 2 and 3 show the LVH 24 and its surrounding ground patterns 32 and 33 on the pattern layers P2 and P3, but the antipads between the LVH 22 and its surrounding ground patterns on the pattern layers P1 and P2 are set in the same way.

[0030] That is, the diameter of these anti-pads is set so that the anti-pads on the pattern layer P1 are larger than the anti-pads on the pattern layer P2. The reason for adjusting the size of the clearance between the ground pattern and the anti-pads around LVH22 and LVH24 in the pattern layers P1-P2 and P2-P3 by making the diameters of the anti-pads smaller on the inner layer side than on the surface layer side will be explained below.

[0031] First, the impedance Zo of the interlayer line formed by the LVH is expressed by equation (1), where L is the inductance of the LVH and C is the coupling capacitance between the LVH and the ground. Furthermore, as shown in Figure 4, where d is the distance between the LVH and the ground pattern, the coupling capacitance C is expressed by equation (2).

[0032]

number

[0033] In equation (2), the distance d is calculated as "d = Φap - Φvp / 2," where Φvp is the diameter of the LVH in the pattern layer and Φap is the diameter of the anti-pad AP around the LVH, as shown in Figure 4. Furthermore, ε represents the relative permittivity of the dielectric layer, and S represents the area of ​​the end pattern of the LVH.

[0034] From equations (1) and (2), it can be seen that as the diameter Φap of the anti-pad AP decreases, the distance d decreases, the coupling capacitance C increases, and the impedance decreases. On the other hand, as shown in Figure 5, if the impedance of the surface wiring pattern is Z1, the impedance of the LVH is Z2, and the impedance of the IVH is Z3, if there is a mismatch between the impedances Z1, Z2, and Z3, high-frequency signals will be reflected at the connection points.

[0035] In this case, the reflection coefficient γ is expressed by equation (3). Note that equation (3) represents the reflection coefficient at the connection between the surface wiring pattern and the LVH, but the reflection coefficient at the connection between the LVH and IVH can also be calculated in the same way.

[0036]

number

[0037] In this case, reflections at the connection points can be suppressed by matching the impedances Z2 and Z3 of the LVH and IVH with the impedance Z1 of the surface wiring pattern. The impedance Z2 of the surface LVH can be matched with the surface wiring pattern by providing ground via holes 44 around the LVH or adjusting the distance between the LVH and the ground pattern, as shown in Figure 2.

[0038] However, since there are ground patterns on each layer around the IVH impedance Z2 on the inner layer side, the electromagnetic field coupling with the ground patterns is strong, resulting in a smaller impedance than the LVH.

[0039] Therefore, even if the impedance Z2 of the LVH can be set to 85 Ω, the same as the impedance Z1 of the surface wiring pattern, the impedance Z3 of the IVH cannot be matched to the impedance Z1, as shown in the upper part of Figure 6.

[0040] In this case, if the impedance Z3 of the IVH is 55Ω, the reflection coefficient γ at the connection with the LVH is 0.214, and if the input signal Vin to the wiring pattern is 1000 mV, the reflected signal Vr at the connection is 214 mV.

[0041] In contrast, if the impedance Z2 of the LVH is set to an intermediate value between the impedance Z1 of the surface wiring pattern and the impedance Z3 of the IVH, for example, 70 Ω, reflections will also occur at the connection between the surface wiring pattern and the LVH.

[0042] In this case, as shown in the lower part of Figure 6, the reflection coefficient γ1 at the connection between the surface wiring pattern and the LVH is 0.096, and the reflected signal Vr1 at this connection is 96 mV. Also, the reflection coefficient γ2 at the connection between the LVH and IVH is 0.12, and the reflected signal Vr2 at this connection is 108 mV.

[0043] Therefore, in this case, the transmission loss of the input signal Vin occurring in the transmission path from the surface wiring pattern via the LVH to the IVH is Vr1 + Vr2 = 204 mV, which is smaller than when the impedance Z2 of the LVH is matched to the surface wiring pattern.

[0044] Therefore, in this embodiment, the impedance of the LVHs 22 and 24 is set to an intermediate value between the impedance of the surface wiring pattern 12 and the impedance of the IVH 26, and the LVH 24 on the built-in side is set to be smaller than the LVH 22 on the surface side.

[0045] However, in this case, if the diameters of both ends of the LVHs 22 and 24 are made equal to the diameter of the surrounding anti-pads AP in the pattern layers P1-P2 and P2-P3, respectively, the impedance in the transmission path from the surface wiring pattern to the IVH changes in a step-like manner, as shown in Figure 7.

[0046] Therefore, in this embodiment, in the pattern layers P1-P2 and P2-P3, the diameter of the surrounding anti-pads AP is set to become gradually smaller from the surface layer side to the inner layer side relative to the diameter of both end portions of the LVHs 22 and 24.

[0047] That is, in the pattern layers P1-P2 and P2-P3, the clearance between the LVHs 22, 24 and the surrounding ground patterns is set to become smaller in stages from the surface layer side to the inner layer side.

[0048] As a result, as shown in FIG. 8, the impedance in the transmission path from the surface wiring pattern 12 to the IVH 26 changes gradually rather than stepwise, which makes it possible to further reduce the reflection of high-frequency signals in this transmission path.

[0049] Therefore, as illustrated in FIG. 9, when the wavelength of the transmission signal is λ, by setting the length of the transmission path from the surface wiring pattern 12 to the IVH 26 to "n×λ / 2+λ / 4", it is possible to suppress the reflection loss of the transmission signal and transmit the transmission signal with low loss.

[0050] In Figure 9, the reflection characteristics shown by the dotted line are the reflection characteristics when the clearances around both end portions of LVH 22 and 24 are the same as a comparative example, and it can be seen that according to this embodiment, the reflection loss of the transmission signal can be improved by 5 dB or more.

[0051] In this embodiment, the clearances around the LVHs 22 and 24 are adjusted in the pattern layers P1-P2 and P2-P3 to suppress reflections that occur in the transmission path up to the IVH 26, but reflections of the transmission signal also occur at the connection between the IVH 26 and the wiring pattern 18.

[0052] 8, if the impedance of the wiring pattern 18 is set to match that of the surface wiring pattern 12, the reflection occurring at the connection between the VH 26 and the wiring pattern 18 will be large.

[0053] Therefore, in this embodiment, the impedance of the wiring pattern 18 is further adjusted to match the impedance of the IVH 26 . 2 to 4, in the multilayer printed circuit board 1 of this embodiment, the wiring patterns 12, 14, 16, and 18 connected via the LVHs 22 and 24 and the IVH 26 are wiring patterns for balanced transmission, in which two microstrip lines are arranged in parallel. The differential impedance of this wiring pattern for balanced transmission can be adjusted by changing the line width and the line spacing of the two microstrip lines.

[0054] Therefore, the differential impedance of the inner layer wiring pattern 18 is set to match the differential impedance of the two IVHs 26 to which each microstrip line is connected by adjusting the line width and wiring spacing of each microstrip line.

[0055] As a result, in the multilayer printed circuit board 1 of this embodiment, not only can reflections occurring in the transmission path from the surface wiring pattern 12 to the IVH 26 be suppressed, but also reflections occurring between the IVH 26 and the wiring pattern 18 can be suppressed.

[0056] [effect] As described above, in the multilayer printed circuit board 1 of this embodiment, the clearances between the LVHs 22, 24 and the surrounding ground patterns are set to become smaller toward the inner layer on the pattern layers P1 to P3. In addition, the differential impedance of the wiring pattern 18 on the inner layer is adjusted to match the differential impedance of the two IVHs to which the two microstrip lines constituting this wiring pattern 18 are connected.

[0057] Therefore, in the multilayer printed circuit board 1 of this embodiment, reflection of the transmission signal on the transmission path from the surface wiring pattern 12 to the inner layer wiring pattern 18 can be suppressed, thereby improving the transmission characteristics of the transmission signal.

[0058] Furthermore, in order to reduce the reflection loss in this transmission path, the reflection loss of the transmission signal can be reduced even when the impedance of the LVHs 22, 24, and IVHs 26 is not matched to the impedance of the surface wiring pattern. Therefore, according to this embodiment, the restrictions on the manufacturing conditions and peripheral wiring of the multilayer printed circuit board 1 can be relaxed, and the degree of freedom in design can be increased.

[0059] [Other embodiments] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0060] (a) For example, in the multilayer printed circuit board 1 of the above embodiment, two wiring patterns 14, 16 are provided on the pattern layers P2, P3, connecting the LVH 22 and the LVH 24, and the LVH 24 and the IVH 26, respectively.

[0061] The lengths of the wiring patterns 14 and 16 can be made extremely short. However, if the differential impedance of the wiring patterns 14 and 16 deviates from the differential impedance at the ends of the LVHs 22 and 24 and the IVHs 26 to which the wiring patterns 14 and 16 are connected, reflection of the transmission signal increases.

[0062] Therefore, the differential impedance of the wiring pattern 14 may be set to be an intermediate value between the differential impedance of the LVH 22 at the end of the pattern layer P2 and the differential impedance of the LHV 24 at the end of the pattern layer P2.

[0063] Similarly, the differential impedance of the wiring pattern 16 may be set to be an intermediate value between the differential impedance of the LVH 24 at the end of the pattern layer P3 and the differential impedance of the IHV 26 at the end of the pattern layer P3.

[0064] In this way, it is possible to reduce reflection loss of the transmission signal that occurs in the wiring patterns 14 and 16, and it becomes possible to transmit the transmission signal, which is a high-frequency signal, in the multilayer printed circuit board 1 with even less loss.

[0065] The differential impedance of the wiring patterns 14, 16 can be adjusted by adjusting the spacing between the two microstrip lines that make up each of the wiring patterns 14, 16.

[0066] (b) Also, as shown in FIG. 1, a surface wiring pattern different from the wiring pattern 12 may be connected to a location other than the connection portion of the wiring pattern 18 with the IVH 26 via the IVH and two LHVs.

[0067] In this way, when an IVH and two LHVs are connected to the wiring pattern 18 for connecting to the surface wiring pattern, the diameter of the anti-pad around the LHV and the impedance of the IVHs on each pattern layer P1, P2, and P3 can be set in the same manner as above.

[0068] In other words, this arrangement can reduce reflection loss of a transmission signal that occurs in the transmission path from the wiring pattern on the inner layer to the wiring pattern on the surface layer. (c) In the above embodiment, the wiring patterns 12 to 18 have been described as wiring patterns for balanced transmission, but the wiring patterns 12 to 18 may also be wiring patterns for unbalanced transmission configured by a single microstrip line.

[0069] In this case, one LVH 22, 24 and one IVH 26 are provided to be connected to each of the wiring patterns 12 to 18, and there is no need to adjust the spacing between the two via holes that make up the LVH 22, 24 and IVH 26, which simplifies the design.

[0070] (d) In the above embodiment, two LVHs 22, 24 are provided between the surface wiring pattern 12 and the IVH 26. However, the number of LVHs connecting the surface wiring pattern 12 and the IVH 26 on each layer may be one, or three or more.

[0071] (e) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

[0072] (f) In addition to the multilayer printed circuit board described above, the present disclosure can also be realized in various forms, such as a system including the multilayer printed circuit board as a component, and a method for adjusting impedance of a multilayer printed circuit board. [Explanation of symbols]

[0073] 1... multilayer printed circuit board, 10... electronic components, 12 to 18... wiring patterns, 22, 24... LVH (laser via hole), 26... IVH (inner via hole), 32, 33... ground patterns, D1 to D7... dielectric layers, P1 to P8... pattern layers.

Claims

1. A multilayer printed circuit board in which a plurality of dielectric layers (D1 to D7) and a plurality of pattern layers (P1 to P8) are alternately stacked, an inner via hole (26) that penetrates two or more of the dielectric layers on the inner layer side of the multilayer printed circuit board and electrically connects the wiring patterns (16-18) formed on the two pattern layers that sandwich the two or more dielectric layers; laser via holes (22, 24) provided in the dielectric layer on the surface side of the inner via holes in the multilayer printed circuit board, for conducting the wiring patterns (12-14, 14-16) of the pattern layers laminated on the front and back surfaces of the dielectric layer to form a signal path between the wiring patterns on the surface side of the multilayer printed circuit board and the inner via holes; and in the plurality of pattern layers arranged on both ends of the laser via hole, a clearance between the ground pattern around the laser via hole and the laser via hole is smaller on the inner layer side than on the surface layer side of the laser via hole.

2. 2. The multilayer printed circuit board according to claim 1, The impedance of the wiring pattern connected to the opposite side of the inner via hole from the laser via hole is matched to the impedance of the inner via hole.

3. 3. The multilayer printed circuit board according to claim 1, A multilayer printed circuit board, wherein the impedance of the wiring pattern connected to the inner layer side of the laser via hole is set to be intermediate between the impedances of two via holes connected to both ends of the wiring pattern.

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