Semiconductor devices grown by selective region epitaxy growth using masks to enhance or reduce growth at the edges.

Abstract

To provide structures and manufacturing processes that enable reliable, manufacturable modulators monolithically integrated with lasers and optical amplifiers having well confined current injection.SOLUTION: A method of forming a photonic integrated circuit including a photonic device and a gain element structure is provided. The gain element is formed by a process including: depositing by epitaxy a first doped layer on a wafer; depositing by epitaxy an active layer capable of optical gain on the first doped layer; depositing by epitaxy a second doped layer on the active layer; pattern-etching at least the second doped layer and the active layer to form a first ridge; and depositing by epitaxy a current blocking layer that is laterally adjacent to the first ridge and at least partially fills the volume of the active layer removed by the pattern etching; where the current blocking layer forms a portion of the photonic device.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure generally relates to semiconductors, i.e., photonic components for use in optical devices and optical networks. More particularly, the present disclosure relates to systems and methods for monolithically integrated gain elements. The present disclosure also relates to semiconductor devices having selective area epitaxy (SAE) growth utilizing masks for suppressing or promoting growth at edges, and to modulators having monolithically integrated optical amplifiers.

Background Art

[0002] The various possible configurations of planar optical waveguides used in photonic integrated circuits (PICs) are often broadly categorized into two types based on the strength of the lateral guidance: strong waveguides and weak waveguides. The strength of the lateral guidance determines the extent to which optical modes are confined to the center of the waveguide and the minimum radius that a curved optical waveguide can achieve before modes are radiated outside the waveguide without coupling. As shown in Figure 1A, waveguide 3 may consist of a core waveguide region 5 with an optical index of refraction of Ng and a laterally adjacent cladding region 7 with an optical index of refraction of Nc. A strong waveguide refers to one where the difference between Ng and Nc is large. For example, in an indium phosphide (InP) based PIC with a strong waveguide, the waveguide core 5 has an optical index of Ng=3.54, while the cladding 7, made of a dielectric material such as silicon dioxide (SiO2), may have an index of Nc=1.5. Conversely, a weak waveguide refers to a design where the core index Ng is slightly higher than the cladding index Nc. For example, if the InP-based PIC lateral cladding 7 is manufactured from a semiconductor instead of silicon dioxide, the waveguide 5 still has Ng=3.54, but the lateral cladding 7 has Nc=3.46, which may form a weak waveguide. Another weak waveguide structure is shown in Figure 1B. Here, there is no actual index change in the material 7 adjacent to the waveguide core 5, but the waveguide ridge 9 located in the center above the core 5 creates an effective index difference in the region adjacent to the waveguide core 5 in the lateral direction. Such a weak waveguide 3 is also called a shallow ridge waveguide and may have an exponential contrast of Ng-Nc < 0.05.

[0003] In the photonic components industry, low-cost, compact, and high-performance InP-based Mach-Zehnder modulators (MZMs) are widely known. Generally, such modulators preferably use a strongly guiding waveguide with a dielectric cladding 7 as shown in Figure 1A. A strongly guiding waveguide not only allows for miniaturization by routing the waveguide compactly, but also allows for the confinement of modes in the central part 5 of the waveguide 3, which provides the optical modulation function, thereby achieving high efficiency.

[0004] The types of modulators described herein typically mix a continuous wave (CW) optical carrier input, which contains no data, with a broadband electrical signal that transmits data. The frequency of the CW carrier is, for example, about 193 THz, and is typically as narrow as possible, for example, a linewidth of 100 kHz is desirable. The bandwidth of the electrical data signal may range, for example, from 500 MHz to 10 GHz, or from 500 MHz to 70 GHz in modern high-capacity communication systems. Depending on the modulation scheme used, data rates of 10 Gbit / s to 400 Gbit / s or more can be obtained. The data is transmitted as an optical carrier at the frequency of the original CW optical carrier input and has envelope modulation determined by the electrical data signal. Thus, the modulator performs an upconversion function from the baseband of the original RF (Radio Frequency) data to the optical frequency, enabling transmission over optical fiber. Furthermore, modulators often synthesize multiple amplitude-modulated RF data tributaries into a more complex phase-amplitude-modulated format, which improves the signal-to-noise ratio (SNR) of the data at the receiving end of the fiber, for example.

[0005] A crucial element for the function of such modulators is the input of a CW optical carrier. In some applications, the CW optical carrier is provided by an external laser, which, if packaged separately, is coupled to the modulator input via a short optical fiber, or, if co-packaged, is coupled via a microlens or optical waveguide system. In these applications, the light lost during the coupling and modulation process becomes a critical performance parameter. If too much light from the CW optical carrier is lost, the output power of the upconverted data signal output from the modulator will be low, resulting in a decrease in the signal-to-noise ratio (SNR) at the receiver. One obvious solution is to use a high-power laser to compensate for the loss. However, there are technical limitations to increasing the laser power, and engineering implications such as power loss, performance non-idealization, and cost. These problems can be solved by monolithically integrating a semiconductor optical amplifier (SOA) with the modulator.

[0006] In other applications, it is preferable to monolithically integrate the laser itself with the modulator, thereby avoiding optical coupling losses, package complexity, and the costs associated with external solutions. Of course, laser integration can also be combined with integrated SOAs to further increase optical output. Lasers and SOAs are generally referred to as active elements or gain elements. Whether it is a laser or an SOA, the technical landscape for lateral optical waveguide means is fundamentally similar. Such integration often necessitates the integration of photonic components other than modulators, lasers, or SOAs, namely detectors, optical monitors, phase adjustment elements, and variable optical attenuators. Thus, extending the present invention to the integration of gain elements (lasers and SOAs) with photonic components other than modulators is fundamentally important.

[0007] Known shallow ridges, or stripes, lasers, and SOAs have configurations like those shown in Figure 1B. In addition to being weakly guided, they lack lateral current confinement, causing current to spread unevenly and inefficiently over a wide area, resulting in reduced gain.

[0008] Because the etched sidewalls of the waveguide core 5 leave dangling chemical bonds that act as mid-level traps, known planar deep-ridge lasers and SOAs similar to Figure 1A have lateral cladding 7 of the dielectric and, like most modulators, are largely unused. These mid-level traps add a large non-radioactive component to the recombination of the associated carriers, making the current-gain curve highly unfavorable. These dangling chemical bonds can be eliminated by properly chemically treating the sidewalls and overgrowth the semiconductor.

[0009] While numerous variations exist for known buried heterostructure (BH) lasers and SOA structures, and they have become the current industry standard, a more advanced placement of the current-blocking layer achieves preferred current confinement into a multi-quantum well (MQW) core. One drawback is the complexity of the regrowth method and the difficulty in monolithically integrating the modulator in a manufacturable manner. Furthermore, BH lasers and SOAs with Al-containing cores are also known for reliability issues. As shown in Figure 2A, the BH structure 15 is fabricated by blanketing an N-InP wafer 10 with the initial growth of MQW material 12. Subsequently, selective etching is performed to form MQW ridges. Next, a multilayer stack 16 is selectively grown around the MQW ridges on the N-InP wafer 10 to a sensitive critical dimension. Finally, overgrowth of the P-type semiconductor 18 is blanketed on top of the MQW ridges and multilayer stack 16. In this way, the current is very confined, but the waveguide still weakly guides.

[0010] In recent years, attempts have been made to simplify the complex arrangement of current-blocking layers in BH lasers using self-aligned single-growth technology. This structure exhibits beneficial current confinement. As shown in Figure 2B, the simplified BH structure 15b is fabricated by blanketing an N-InP wafer 10 in the initial growth of MQW 12 and P-type semiconductor material 18. Selective etching is performed to form MQW ridges. Subsequently, a single blanket layer of undoped InP 17 is grown on the structure 15. This undoped InP 17 is removed from the top of the ridges using self-aligned etching technology. Similar to the more complex BH structure 15a (Figure 2A), this simplified BH structure 15b (Figure 2B) achieves good current confinement but still exhibits weak waveguide.

[0011] Neither the shallow ridge structure (Figure 1B) nor the BH structure (Figure 2B) can be directly optically coupled to a modulator because the waveguides are not interchangeable. For example, some kind of interconnection means is needed to bridge a strongly guiding waveguide and a weakly guiding waveguide, as described in Patent Document 1.

[0012] Thus, there is still a need in the art for reliable, monolithically integrated, manufacturable modulators with lasers and optical amplifiers with well-confined current injection, as well as structures and processes that enable such devices.

[0013] Furthermore, selective region epitaxy (SAE) involves the localized growth of epitaxial layers via an amorphous dielectric mask (typically silicon dioxide (SiO2) or silicon nitride (Si3N4)) patterned on a semiconductor wafer. The semiconductor growth conditions are selected to ensure epitaxial growth on the exposed wafer rather than on the dielectric mask. SAE is formed by covering a portion of the semiconductor surface with a mask material where growth does not occur. Traditionally, SAE has been used to intentionally accelerate the growth of epitaxial layers. The larger the area of ​​the masked region, the greater the rate of crystal growth adjacent to the mask. The degree of growth acceleration depends on many factors, including growth temperature, growth pressure, mask composition, mask region, and mask orientation.

[0014] Unintended growth acceleration at the mask edge is a persistent problem with SAE. Solutions to date have focused on altering growth conditions for epitaxial growth. Notably, SAE is a technique used in the fabrication of InP photonics. An example of such an optical modulator is described in Patent Document 2, titled "Monolithic Optoelectronic TWE-component Structure for High Frequencies and Low Optical Insertion Loss," the contents of which are incorporated herein by reference in their entirety.

[0015] Changing growth conditions to suppress unintended growth has the drawback of suppressing intentional growth enhancement, which is often the very purpose of pursuing SAE growth in the first place. The use of conventional straight-sided SAE masks results in a linear structure of enhanced growth material along the mask edge, which is fragile and can break off, forming contamination on the device surface and negatively impacting manufacturability and reliability. [Prior art documents] [Patent Documents]

[0016] [Patent Document 1] U.S. Patent No. 7,184,207 [Patent Document 2] U.S. Patent No. 9,182,546 [Overview of the Initiative]

[0017] This disclosure relates to a system and method for semiconductor devices having selective regional epitaxy (SAE) growth utilizing a mask to suppress or promote growth at the edge. Again, SAE is a technique for crystal growth on a semiconductor wafer. A wafer region is covered or masked with a thin film of dielectric material (e.g., SiO2, Si3N4, etc.). In a crystal growth reactor, such as a metal-organic chemical vapor deposition (MOCVD) chamber, crystal growth proceeds selectively only in regions not covered by the mask. This disclosure provides a process for manufacturing a semiconductor device that includes regions that grow selectively in any direction, and is free from unwanted growth promotion and corresponding defects at the edges outside the masked region. Specifically, this process includes a variable profile of the mask edge used to suppress or promote growth at the edge.

[0018] Furthermore, this disclosure provides a design for efficiently monolithically integrating an optical amplifier into a deeply etched ridge waveguide modulator formed on an InP wafer, particularly a multi-growth modulator, as described in Patent Document 2, for example. This design allows for the reuse of existing undoped overgrowth in the TWE modulator for the purpose of current isolation. Subsequent deep etching of the current-isolated buried ridge provides independent control of the confinement coefficient and enables efficient coupling to the deeply etched modulator. Thus, this disclosure provides a means of reusing overgrowth already present in standard modulator process sequences, thereby reducing many epitaxial growth-related problems such as cost, complexity, and reliability issues. This disclosure provides better current confinement and therefore better electrical efficiency than alternative shallow ridge solutions. This disclosure decouples current confinement (provided by the i-InP blocks detailed below) from optical confinement (provided by the etched regions detailed below). Therefore, this disclosure provides an efficient alternative for coupling light from a modulator to a gain unit without introducing additional or new optical elements into the design, such as those provided in Patent Document 1.

[0019] This disclosure provides a modulator having an optical amplifier, comprising an N-type layer, a multiple quantum well material disposed on the N-type layer, and a P-type layer disposed on the multiple quantum well material opposite the N-type layer. A portion of the N-type layer, the multiple quantum well material, and a portion of the P-type layer collectively form a ridge structure, and using selective regional epitaxy, an intentionally undoped material (generally called intrinsic, or i-type) is disposed on the N-type layer and around the sides of the ridge structure. The common designation for an intentionally undoped semiconductor is i-type, but i-type materials may have low levels of unintended trace dopant contamination, sometimes as low as 1e16 atoms / cm³. 3As described above, although it is possible to exist, those skilled in the art will understand that usually lower concentrations are desired. Optionally, the type-I material is etched deeper to form a strong waveguide structure. The N-type layer contains N-InP. The P-type layer contains either P-InGaAs or P-InP. The type-I material contains i-InP, but alternatively, it may be any suitable current blocking material that blocks the flow of current, such as semi-insulating iron-doped InP. Optionally, over all or part of the length, the width of the strong waveguide structure is selected to efficiently couple to a strongly guided modulator waveguide.

Brief Description of the Drawings

[0020] [Figure 1] Figures 1A and 1B are a series of schematic diagrams showing a conventional strongly guiding waveguide and a weakly guiding waveguide (shallow ridge), respectively. [Figure 2A] Figures 2A and 2B are a series of schematic diagrams showing a manufacturing method of a conventional BH laser and SOA structure. [Figure 2B] Figures 2A and 2B are a series of schematic diagrams showing a manufacturing method of a conventional BH laser and SOA structure. [Figure 3] Figure 3 is a series of schematic diagrams showing a manufacturing method of a conventional gain element. [Figure 4] Figure 4 is a series of schematic diagrams showing a manufacturing method of one exemplary embodiment of the gain element of the present disclosure. [Figure 5] Figure 5 is a series of schematic diagrams showing the manufacturing of another exemplary embodiment of the gain element of the present disclosure and the coupling of the related SOA and modulator. [Figure 6] Figure 6 is a schematic diagram showing the flaring of the width of a waveguide SOA or modulator to match the optical mode of a related modulator SOA according to the method of the present disclosure. [Figure 7] Figure 7 is another schematic diagram showing the flaring of the width of a waveguide modulator to match the SOA optical mode according to the method of the present disclosure. [Figure 8]FIG. 8 is a schematic diagram showing a new geometry for the edge of a mask used to overgrow an epitaxial layer and suppress unwanted growth promotion according to the method of the present disclosure. [Figure 9A] FIGS. 9A-9D are block diagrams showing steps of an SAE growth process on a wafer, showing excess growth at the edge of a mask. [Figure 9B] FIGS. 9A-9D are block diagrams showing steps of an SAE growth process on a wafer, showing excess growth at the edge of a mask. [Figure 9C] FIGS. 9A-9D are block diagrams showing steps of an SAE growth process on a wafer, showing excess growth at the edge of a mask. [Figure 9D] FIGS. 9A-9D are block diagrams showing steps of an SAE growth process on a wafer, showing excess growth at the edge of a mask. [Figure 10] FIG. 10 is a photograph of an actual wafer after the step of FIG. 9D. [Figure 11] FIG. 11A is a top view of a wafer showing an area. FIG. 11B is a photograph of a wafer showing an area spreading over a mask and excess growth. [Figure 12] FIGS. 12A and 12B are photographs showing cross-sections of the P island of FIGS. 9A-9D in the direction of the waveguide (FIG. 12A) and in the direction perpendicular to the waveguide (FIG. 12B). [Figure 13] FIG. 13 is a view of a wafer, i.e., a view of an InP wafer oriented in a (100) plane having a major flat and a minor flat perpendicular to the major flat, and a graph showing the preferred direction of the wafer. [Figure 14] FIG. 14 is a view of a rectangular mask with an angled orientation according to Series 2 and a zigzag mask with a variable angle from both Series 1 and 2. [Figure 15] FIG. 15 is a view of an InP wafer showing an example of placing a mask on the wafer. [Figure 16] Figure 16 shows an example of an InP wafer with mask 12B placed on it. [Figure 17] Figure 17 is a flowchart of the process for growing an epitaxial layer on a semiconductor wafer for semiconductor devices. [Figure 18] Figure 18 is a photograph of a circular mask in a high-resolution field of view (FOV) showing how the preferred angle was determined. [Modes for carrying out the invention]

[0021] This disclosure is illustrated and described herein with reference to various drawings, where similar reference numerals are used, where appropriate, to indicate similar system components / method steps.

[0022] To reiterate, this disclosure provides a design for efficiently monolithically integrating an optical amplifier into a deeply etched ridge waveguide modulator formed on an InP wafer, particularly a multi-growth modulator, as described, for example, in Patent Document 2. This design allows for the reuse of existing undoped overgrowth in the TWE modulator for the purpose of current isolation. Subsequent deep etching of the current-isolated buried ridge provides independent control of the confinement coefficient and enables efficient coupling to the deeply etched modulator. Thus, this disclosure provides a means of reusing overgrowth already present in standard modulator process sequences, thereby reducing many epitaxial growth-related problems such as cost, complexity, and reliability issues. This disclosure provides better current confinement and therefore better electrical efficiency than alternative shallow ridge solutions. This disclosure decouples current confinement (provided by the i-InP blocks detailed below) from optical confinement (provided by the etched regions detailed below). Therefore, this disclosure provides an efficient alternative for coupling light from a modulator to a gain unit without introducing additional or new optical elements into the design, such as those provided in Patent Document 1.

[0023] This disclosure provides a modulator having an optical amplifier, comprising an N-type layer, a multiple quantum well material disposed on the N-type layer, and a P-type layer disposed on the multiple quantum well material opposite the N-type layer. A portion of the N-type layer, the multiple quantum well material, and a portion of the P-type layer collectively form a ridge structure, and using selective regional epitaxy, an intentionally undoped material (undoped, or i-type) is disposed on the N-type layer and around the sides of the ridge structure. Optionally, the i-type material is further etched to form a strong waveguide structure. The N-type layer contains N-InP. The P-type layer contains either P-InGaAs or P-InP. The i-type material contains i-InP, but may instead be any suitable current-blocking material of any kind that blocks the flow of current, such as semi-insulating iron-doped InP. Optionally, the width of the strong waveguide structure is selected over all or part of its length to efficiently couple to a strongly guided modulator waveguide.

[0024] Monolithic integrated gain element Figure 3 shows the manufacturing of a conventional modulator structure 25, for example, by the process provided in Patent Document 2. The modulator structure 25 is manufactured by blanketing an N-type wafer 10 having the initial growth of MQW material 12 and a P-type layer 18. In the i-type ridge embodiment, the P-type layer 18 is then selectively etched to selectively grow a u-InP layer 20 in the etched region. Subsequently, the P-type layer 18 and MQW material 12 are selectively etched to leave an i-InP capped ridge in the i-type ridge SOA embodiment and a P-type capped ridge in the P-type ridge modulator embodiment. Thus, a selective i-type growth step is commonly used. It is still desirable to monolithically integrate the SOA with the modulator without introducing a risky placement growth step and to provide performance similar to the BH structure 15 (Figures 2A and 2B). Also, for monolithically integrated SOAs, it is still desirable to create a BH-like structure with lateral optical modes suitable for optical coupling to a deeply etched modulator ridge.

[0025] Referring specifically to Figure 4, in one embodiment, the gain element structure 35 of the present disclosure is manufactured by blanketing an N-type layer 1 having the initial growth of an optical gain material 12 and a P-type layer 18. Next, the P-type layer 18, the optical gain material 12, and the N-type layer 10 are selectively etched to leave a P-capped ridge covered with a mask 19. Subsequently, an i-type growth step is used to fill the lateral region of the ridge with i-InP material 20. Hereinafter, the lateral i-InP material 20 provides excellent current interruption without requiring additional growth steps or precarious placement associated with BH manufacturing.

[0026] Figure 5 is a series of schematic diagrams illustrating the fabrication of another exemplary embodiment of the gain element structure 35 of the present disclosure, as well as the coupling means for the associated SOA 37 and modulator 39. The i-InP material 20 and N-type material 10 are etched to form walls of i-InP material on both sides of the ridge, thereby providing strong waveguides on both sides of the ridge. Furthermore, by widening the deeply etched modulator waveguide, lateral optical matching can be achieved. In Figure 5, it will be understood that the lower schematic represents a modulator waveguide width-matched to the SOA input / output waveguide shown in the central schematic. In the SOA 37, W1 (current confinement) and W2 (optical mode overlap) can be varied independently, and the gain can be varied along the length of the SOA 37, for example, to mitigate the effects of spatial hole burning.

[0027] Figure 6 is a schematic diagram showing the flaring of the waveguide SOA or modulator width to match the optical mode of the associated modulator SOA according to the method of the present disclosure. Any combination of tapered central width and outer width is possible. For example, it is possible to taper only the central portion and omit certain portions at the beginning and end. This provides practical advantages for spatial hole burning by having high optical confinement at the beginning and increasing the injection amount, but reducing optical overlap at the end.

[0028] Figure 7 is another schematic diagram showing the flaring of the waveguide modulator width to match the SOA optical mode according to the method of the present disclosure. Here, the SOA waveguide 37 is coupled to the modulator waveguide 39 via a tapered passive waveguide 38 or SOA waveguide 37 or the tapered portion of the modulator waveguide 39.

[0029] In the conventional modulator structure 25 shown in Figure 3, there is already selective growth of the i-InP layer 20, and its thickness may be determined by the optimization of the modulator design. This same growth is used herein to provide better current interruption for the SOA. As shown in Figure 4, the i-InP layer 20 from the conventional modulator may be deposited on either side of the SOA ridge 19. However, the design requirements of the modulator 25 may not provide a thickness of i-InP layer 20 sufficient to match the height of the SOA ridge 19. Growth accelerators may be used to create a more planar top surface to improve manufacturability in subsequent processing steps. It should be noted that the width may be increased to improve the thermal impedance of the SOA for areas where increased lateral confinement is not required for the current interruption mesa. Also, if it is desired to enhance lateral optical confinement (to match the modes of the modulator and / or to improve the efficiency of the SOA), a deep etching ridge can be used.

[0030] Semiconductor devices in which selective area epitaxy (SAE) growth is suppressed or promoted. Furthermore, this disclosure relates to a system and method for semiconductor devices having selective regional epitaxy (SAE) growth utilizing a mask to suppress or promote growth at the edge. Again, SAE is a technique for crystal growth on a semiconductor surface. A wafer region is covered or masked with a thin film of dielectric material (e.g., SiO2, Si3N4, etc.). In a crystal growth reactor such as a metal-organic vapor deposition (MOCVD) chamber, crystal growth proceeds selectively only in regions not covered by the mask. This disclosure provides a process for manufacturing a semiconductor device that includes regions that grow selectively in any direction, and which does not have unwanted growth promotion and corresponding defects at the edges outside the masked region. Specifically, this process includes a variable profile of the mask edge used to suppress or promote growth at the edge.

[0031] As an implementation technique, Figure 8 shows a novel shape 50 for the edge of a mask used to overgrow an epitaxial layer. For example, undesirable accelerated crystal growth often occurs at mask edges where the pattern is in the

[0011] or [0-11] direction. By using a nonlinear shape 50 for the mask edge, this undesirable accelerated growth can be suppressed. Using a zigzag pattern instead of a straight edge for the mask edge is a novel solution. Unintended accelerated growth at the mask edge is an ongoing problem in selective region growth. Previous solutions have focused on changing the growth conditions for epitaxial growth. Selective region epitaxy is a technique used in the manufacture of many InP optical modulators. This technique and the use of mask patterns to suppress unintended acceleration are related to multi-growth modulators of InP wafers, as described in Patent Document 2. Suppressing unintended acceleration by changing the growth conditions has the disadvantage of suppressing intentional accelerated growth, which is often the very purpose of pursuing selective region growth in the first place. The use of conventional straight-side SAE masks results in a linear structure of growth-promoting material along the mask edges, which is fragile and can break off, forming contamination on the device surface and negatively impacting manufacturability and reliability. By using the shape solution 50, intentional growth promotion at the mask edges can be suppressed without compromising intentional growth promotion. The effect of unintended growth promotion at the mask edges is anisotropic on the wafer surface. The effect is strong along an axis in one direction but weaker along a perpendicular axis. By placing the zigzag pattern 50 along the edges susceptible to promotion, there are virtually no boundaries parallel to the lines where unintended growth promotion occurs.

[0032] Figures 9A to 9D are block diagrams showing the steps of the SAE growth process 95 on wafer 100, illustrating excessive growth at the edge of mask 102. Wafer 100 is a wafer comprising wafer 104, a P island 106 of indium phosphide (InP), and a contact layer 108 containing, for example, indium gallium arsenide (InGaAs). Mask 102 may contain SiO2 and is deposited (coated) onto the contact layer 108 in Figure 9A. In Figure 9B, a region is etched through mask 102, P island 106, and contact layer 108. In Figure 9C, SAE growth is performed on the etched region. Note that there is no SAE growth on mask 100. In Figure 9D, mask 100 is removed. Figures 9C and 9D include excessive growth 110 at the edge of mask 100.

[0033] Figure 10 is a photograph of Figure 9D on an actual wafer 100. Specifically, it shows that the conventional use of a straight-side SAE mask 102 results in a linear structure of growth-promoting material 110 along the mask edge, which is fragile, forms contamination on the device surface, and negatively impacts manufacturability and reliability. Figure 10 shows how, during residual oxide cleanup, the edges parallel to the minor flat (perpendicular to the waveguide length) are clean, but the excess growth 110 fractures along the edges of the P island 106 parallel to the major flat.

[0034] Figure 11A is a top view of wafer 100 showing region 140, and Figure 11B is a photograph of wafer 100 showing region 140 and excess growth 110 extending over the mask 102. The bare wafer is masked with oxide, and region 140 has thick overgrowth of InP. This forms a "cap" of excess growth that extends beyond the oxide. Subsequent etching is sufficient to remove the oxide beneath the cap, but tends to destroy other materials.

[0035] Figures 12A and 12B are photographs showing cross-sections of P island 106 in the waveguide direction (Figure 12A) and perpendicular to the waveguide (Figure 12B). It should be noted that in Figure 12A, the interface exhibits good behavior in the waveguide direction. On the other hand, Figure 12B shows the state after wet cleanup, where the excess growth has been destroyed. Prior to this, there is a large "mushroom cap" shape of InP. This feature leaves a residual column of material when subsequently etched.

[0036] In various ways, this disclosure notes that certain preferred angles of the mask 102, adaptations of the shape and / or orientation of the mask 102, and / or zigzag edges of the mask 102 can lead to suppression (or promotion) of growth at the edges of the mask 102. That is, the mask 102 includes certain shapes that suppress or promote intentional growth promotion at the edges of the mask 102 without impairing the intentional growth promotion that is the objective of the SAE. The effect of unintended promotion at the mask edges is anisotropic on the wafer surface, i.e., it will have different values ​​when measured in different directions. The effect is strong along an axis in one direction, but weaker along an axis perpendicular to it. This is illustrated in Figures 12A and 12B.

[0037] In one embodiment, by placing a zigzag pattern or other angular pattern along an edge susceptible to acceleration, most of the boundary is not parallel to the line where unintended acceleration occurs.

[0038] Through growth experiments of III-V semiconductor material (specifically, InP wafers oriented to the (100) plane), the edges of the mask 102 aligned along a specific crystal axis are particularly

[0011] or

number

[0039] Furthermore, the converse of the above has also been determined to be true. That is, along a specific crystallographic direction, undesirable accelerated crystal growth is suppressed, and in fact, along the

[0011] axis or

number

[0011] axis 164 and the InP wafer 510 and the flats 152, 154.

number

[0040] For an InP wafer 150 oriented on the (100) plane (wafer 100), growth acceleration passes through a null when, for example, the edge of the SAE mask 102 is aligned to one of the following angles ("preferred angles") with respect to the

[0011] direction 164 which are joined in two series. [Table 1]

[0041] Each series includes four angular directions, each direction being 90 degrees away from the other three directions in the series. For an InP wafer 150 in the (100) direction, there are a total of eight directions available for the edge of the SAE mask 102 free from fading and defects. Specifically, Graph 160 shows series 1, 2 in graph form relative to the

[0011] direction 164. The angles of series 1, 2 are specified relative to the

[0011] direction 164, but as those skilled in the art will know, these angles relative to the edge of the mask 102 are

number

[0042] Figure 14 is a perspective view of a rectangular mask 102A angled according to Series 2, and a zigzag-shaped mask 102B with a variable angle from both Series 1 and 2. Figure 15 is a perspective view of an InP wafer 150 with the exemplary mask 102A placed on it. Figure 16 is a perspective view of an InP wafer 150 with the exemplary mask 102B placed on it. Those skilled in the art will recognize that Figures 13–16 are not to scale. Typically, the InP wafer 150 may be on the order of centimeters in size (diameter) from the measuring flat 152 to the opposite side (top). The mask 102 is on the order of several hundred microns in length and several tens of microns in width, and the zigzag teeth are on the order of microns.

[0043] The use of a mask 102 having an InP wafer 150 is utilized to form a semiconductor device having a SAE, which is manufactured through a process of growing an epitaxial layer on the semiconductor wafer 150. In one embodiment, the semiconductor device includes 1) a first region covered by the mask 102 that inhibits crystal growth on the surface of the semiconductor wafer 150, 2) a second region that is complementary (proximity) to the first region and is not covered by the mask 102, which allows crystal growth on the semiconductor wafer 150, and 3) a perimeter of the mask 102 that surrounds the first region and serves as a boundary between the first and second regions, where the majority of the length of the perimeter is substantially aligned along a preferred crystal orientation that provides reduced growth facilitation on the semiconductor wafer 150.

[0044] Furthermore, the semiconductor wafer 150 may have portions where growth acceleration is desired and portions where growth acceleration is not desired, and this disclosure provides flexibility to satisfy both needs. For example, growth acceleration is desired for the spot size converter, while growth minimization is desired for the traveling wave electrode.

[0045] In one embodiment, the mask 102A is a quadrilateral, i.e., a polygon having four sides (or flanks) and four vertices or angles. That is, the perimeter may also be quadrilateral. The important thing is that one of the four sides coincides with a preferred angle.

[0046] In another embodiment, the mask 102B has the shape of a series of zigzag patterns, i.e., the perimeter includes a series of small corners along the preferred corners.

[0047] The semiconductor wafer surface 150 is composed of a compound of Group III and Group V elements. In one embodiment, the semiconductor wafer surface 150 is InP cut near the (100) direction. Preferred crystal orientations are one or more angles of approximately 34, 124, 214, 304, 56, 146, 236, and 326 degrees with respect to the

[0011] direction. It should be noted that each of the last four numbers is (360 - one of the first four numbers), and vice versa, i.e., 326 = 360 - 34, 236 = 360 - 124, etc.

[0048] Figure 17 is a flowchart of step 180 for growing an epitaxial layer on a semiconductor wafer for semiconductor devices. Step 180 includes the steps of depositing one or more masks on a semiconductor wafer having an in-planar orientation, each mask being configured to cover a portion of the semiconductor wafer, and each mask having a periphery having a plurality of sides substantially aligned along a preferred crystal direction with respect to an orientation that provides enhanced or reduced growth facilitation at substantially aligned side edges (step 184). It also includes the step of performing selected area epitaxy (SAE) growth on the surface of the semiconductor wafer (step 186).

[0049] The periphery has a quadrilateral shape or a series of zigzag patterns. The semiconductor wafer may contain compounds of Group III and Group V elements. The semiconductor wafer may be indium phosphide (InP), and the plane may be close to the (100) direction. Preferred crystal orientations may be one or more angles with respect to the

[0011] direction of the semiconductor wafer that are close to 34, 124, 214, 304, 56, 146, 236, and 326 degrees.

[0050] In one embodiment, the mask is for a spot size transducer, and the preferred crystal orientation is selected to provide maximum growth enhancement. In another embodiment, the mask is for a traveling wave electrode, and the preferred crystal orientation is selected to provide reduced growth enhancement.

[0051] Furthermore, semiconductor devices can be formed by process 180.

[0052] In another embodiment, the semiconductor device is manufactured by a process of growing an epitaxial layer on a semiconductor wafer via selective region epitaxy (SAE), and includes a first region covered by a mask that suppresses crystal growth on the surface of the first region, a second region adjacent to the first region and not covered by the mask, which allows crystal growth on the surface of the second region, and a periphery of the mask that serves as a boundary between the first and second regions. Multiple sides of the periphery are substantially aligned along a preferred crystal orientation with respect to the direction of the semiconductor wafer, minimizing or maximizing growth enhancement at the edges of the substantially aligned sides.

[0053] Figure 18 is a photograph of a circular mask in a high-resolution field of view (FOV) showing how the preferred angles were determined. It should be noted that the circular mask represents all possible angular values ​​(0 to 360 degrees) relative to the

[0011] direction 164. In this method, it was possible to isolate small islands and extract data. It was determined that the height and volume of the islands could be correlated with the angles. Thus, it was determined that the preferred crystal orientations were one or more angles relative to the

[0011] direction of the InP wafer 150, approximately 34, 124, 214, 304, 56, 146, 236, and 326 degrees. Those skilled in the art will recognize that this same approach, i.e., using circular masks to experimentally determine growth characteristics at different angles, can be used for other types of wafers 100, etc., with other crystal axes, to determine the angles of the preferred mask 102.

[0054] While this disclosure has been illustrated and described herein with reference to preferred embodiments and specific examples thereof, it will be readily apparent to those skilled in the art that other embodiments and examples may perform similar functions and / or achieve similar results. All such equivalent embodiments and examples are in the spirit and scope of this disclosure, contemplated thereby, and intended to be the subject of the following claims.

Claims

1. Step (184) of depositing a mask (102A, 102B) on a semiconductor wafer (150) having orientation in a plane, wherein the mask (102A, 102B) is configured to cover a portion of the semiconductor wafer, and the mask (102A, 102B) includes a peripheral portion having a plurality of sides all connected to each other to form a single shape, thereby substantially aligning most of the peripheral portion of the mask (102A, 102B) along a preferred crystal direction with respect to the orientation, thereby enhancing or reducing growth acceleration at the edges of the substantially aligned single-shape sides, The step (186) includes performing selected region epitaxy (SAE) growth on the surface of the semiconductor wafer, The peripheral portion has a series of zigzag patterns. The preferred crystal orientation of the semiconductor wafer with respect to the [011] direction is one or more angles of approximately 34, 124, 214, 304, 56, 146, 236, and 326 degrees, Method (180).

2. The method according to claim 1 (180), wherein the peripheral portion has a quadrilateral shape.

3. The method according to claim 1 (180), wherein the surface has a compound of a group III element and a group V element.

4. The method according to claim 3 (180), wherein the surface is indium phosphide (InP) and the plane is close to the [100] direction.

5. The method according to any one of claims 1 to 4 (180), wherein the masks (102A, 102B) are for a spot size converter.

6. The method according to claim 5 (180), wherein the preferred crystal orientation is selected to provide maximum growth promotion.

7. The method according to any one of claims 1 to 4 (180), wherein the masks (102A, 102B) are for traveling wave electrodes, and the preferred crystal orientation is selected to provide the reduced growth promotion.

8. The method according to any one of claims 1 to 4 (180), wherein the preferred crystal orientation is selected to provide the reduced growth promotion.

9. The method (180) of any one of claims 1 to 8, which is carried out using the single mask with the enhanced or reduced growth promotion based on the position of the single mask.

10. A semiconductor device formed by the method (180) of any one of claims 1 to 9.

11. A first region covered by masks (102A, 102B) that suppress crystal growth on the surface of the first region, A second region adjacent to the first region and not covered by the mask (102A, 102B), which enables crystal growth on the surface of the second region, The peripheral portion of the mask (102A, 102B) which functions as a boundary between the first region and the second region, comprises Multiple sides are all connected to each other to form a single shape and are arranged in the periphery, so that most of the periphery of the mask (102A, 102B) is substantially aligned along a preferred crystal direction with respect to the orientation of the semiconductor wafer (150), thereby enhancing or reducing growth acceleration at the edges of the substantially aligned single shape sides. It is manufactured through a process of growing an epitaxial layer on a semiconductor wafer (150) via selective region epitaxy (SAE), The peripheral portion has a series of zigzag patterns. A semiconductor device wherein the preferred crystal orientation of the semiconductor wafer with respect to the [011] direction is one or more angles of approximately 34, 124, 214, 304, 56, 146, 236, and 326 degrees.

12. The semiconductor device according to claim 11, wherein the surface of the first region or the second region is indium phosphide (InP).

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