Semiconductor device, method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device whose reliability is ensured, and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises: a substrate made of silicon carbide of a first conductivity type; an epitaxial layer made of silicon carbide of the first conductivity type; a plurality of base layers made of silicon carbide of a second conductivity type; a plurality of source layers made of silicon carbide of the first conductivity type, respectively; a plurality of contact layers made of silicon carbide of the second conductivity type, respectively; a plurality of gate insulation layers formed in contact with respective source layers of adjacent base layers; a plurality of gate electrode layers formed on the plurality of gate insulation layers, respectively; a plurality of source electrode layers formed over source layers and contact layers on the plurality of respective base layers; a drain electrode layer formed on the substrate; and an ion injection layer formed at a surface layer part of a contact layer in a transition defect-present region of the epitaxial layer in top view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same semiconductor device. [Background technology]

[0002] In semiconductor device substrates, if dislocation defects exist, stacking faults may expand when current is applied, depending on the type of dislocation. Patent Document 1 discloses a method for manufacturing a semiconductor device to prevent the expansion of such dislocations. According to this manufacturing method, the impact of dislocation defects on the semiconductor device can be suppressed by removing the gate electrode layer in the region where the dislocation defects exist. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2007-318031 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, removing the gate electrode layer in a region containing dislocation defects significantly alters the electric field distribution in the semiconductor device. This can lead to a deterioration in the semiconductor device's breakdown voltage, fluctuations in the threshold voltage, and other issues, making it difficult to ensure the reliability of the semiconductor device.

[0005] This disclosure was made to solve the problems described above. The purpose of this disclosure is to provide a reliable semiconductor device and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0006] The semiconductor device relating to this disclosure is A substrate formed of first-conductivity silicon carbide, On the first surface of the substrate, an epitaxial layer is formed of silicon carbide of a first conductivity type with a lower impurity concentration than the substrate, and contains dislocation defects. Multiple base layers formed of silicon carbide of the second conductivity type are provided on the epitaxial layer, A plurality of source layers are formed on each of the plurality of base layers, each of which is made of silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, Each of the aforementioned multiple base layers is surrounded by a source layer, and each of the multiple contact layers is formed of a second-conductivity silicon carbide with a higher impurity concentration than the base layer, Multiple gate insulating layers formed to contact each source layer of an adjacent base layer, A plurality of gate electrode layers formed on each of the plurality of gate insulating layers, On each of the aforementioned multiple base layers, a plurality of source electrode layers are formed spanning the source layer and the contact layer, A drain electrode layer formed on the second surface of the substrate, In a top view, in the region where dislocation defects exist in the epitaxial layer, an ion implantation layer formed on the surface of the contact layer, It is equipped.

[0007] One embodiment of this disclosure is that the ion implantation layer is formed of silicon carbide of a first conductivity type with a higher impurity concentration than the epitaxial layer.

[0008] One embodiment of this disclosure is that the ion implantation layer is formed to have deep energy levels.

[0009] One embodiment of this disclosure is that the ion implantation layer is formed so as to extend beyond the contact layer towards the source layer in the region where dislocation defects exist in the epitaxial layer when viewed from above.

[0010] One embodiment of this disclosure is that the ion implantation layer is formed in such a way that, in a top view, the region where dislocation defects exist in the epitaxial layer is prevented from contacting the source electrode layer, at least from the contact layer to the region in contact with the source layer.

[0011] In one aspect of the present invention, the ion implantation layer is formed such that the current value flowing through the region where dislocation defects exist in the epitaxial layer in a top view is 1 / 1,000,000 or more and 1 / 10 or less of the current value flowing through the region without dislocation defects.

[0012] The ion implantation layer has a nitrogen concentration of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. In one aspect of the present invention, the ion implantation layer is formed in this manner.

[0013] In one aspect of the present disclosure, the ion implantation layer is formed such that the ratio of the nitrogen concentration to the aluminum concentration is 1 to 3 times.

[0014] The method for manufacturing a semiconductor device according to the present disclosure includes an epitaxial layer forming step of forming an epitaxial layer of silicon carbide of a first conductivity type having a lower impurity concentration than the substrate on a first surface of a substrate formed of silicon carbide of the first conductivity type; a dislocation defect detecting step of detecting dislocation defects in the epitaxial layer; a base layer forming step of forming a plurality of base layers of silicon carbide of a second conductivity type on the epitaxial layer; a source layer forming step of forming a plurality of source layers of silicon carbide of the first conductivity type having a higher impurity concentration than the epitaxial layer on each of the plurality of base layers; a contact layer forming step of forming a plurality of contact layers of silicon carbide of the second conductivity type having a higher impurity concentration than the base layer so as to be surrounded by the source layer on each of the plurality of base layers; a gate insulating layer forming step of forming a plurality of gate insulating layers so as to contact the source layers of adjacent base layers; a gate electrode layer forming step of forming a plurality of gate electrode layers on the plurality of gate insulating layers; A source electrode layer formation step is performed in which multiple source electrode layers are formed on each of the multiple base layers so as to span the source layer and the contact layer, A drain electrode layer formation step in which a drain electrode layer is formed on the second surface of the substrate, Prior to the source electrode layer formation step, an ion implantation layer formation step is performed in which an ion implantation layer is formed on the surface of the contact layer in a region where dislocation defects exist in the epitaxial layer when viewed from above. It is equipped.

[0015] One embodiment of this disclosure is that the ion implantation layer formation step includes a step of forming the ion implantation layer by an ion implantation method such that the ion implantation layer is silicon carbide of the first conductivity type with a higher impurity concentration than the epitaxial layer.

[0016] One embodiment of this disclosure is that the ion implantation layer formation step includes a step of forming the ion implantation layer by an ion implantation method such that the ion implantation layer has deep energy levels.

[0017] One embodiment of this disclosure is that the ion implantation layer formation step includes a step of forming the ion implantation layer in a region of the epitaxial layer where dislocation defects exist when viewed from above, such that the ion implantation layer extends beyond the contact layer towards the source layer.

[0018] One embodiment of this disclosure is that the ion implantation layer formation step includes forming the ion implantation layer in a region of the epitaxial layer where dislocation defects exist in a top view, from the contact layer to at least the region in contact with the source layer, and in such a manner that it prevents contact with the source electrode layer.

[0019] One embodiment of this disclosure is that the ion implantation layer formation step includes a step of forming the ion implantation layer such that, in a top view, the current value flowing through the region of the epitaxial layer where dislocation defects exist is at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through the region without dislocation defects.

[0020] The ion implantation layer formation step is performed when the nitrogen concentration is 1 × 10 18 cm -3 The above and 1 × 10 21 cm -3 One embodiment of this disclosure includes a step of forming the ion implantation layer as follows.

[0021] One embodiment of this disclosure is that the ion implantation layer formation step includes a step of forming the ion implantation layer such that the ratio of nitrogen concentration to aluminum concentration is 1 to 3 times.

[0022] A resist forming step of forming a resist so as to cover the epitaxial layer, the plurality of base layers, the plurality of source layers, and the plurality of contact layers, A contact layer exposure step is performed in which a portion of the resist is removed in a region of the epitaxial layer where dislocation defects exist when viewed from above, thereby exposing the contact layer. Equipped with, One embodiment of the ion implantation layer formation step is to form the ion implantation layer on the surface of the contact layer. [Effects of the Invention]

[0023] According to this disclosure, it is possible to provide a reliable semiconductor device and a method for manufacturing the semiconductor device. [Brief explanation of the drawing]

[0024] [Figure 1] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 1. [Figure 2] This is a top view of the main part of the semiconductor device in Embodiment 1. [Figure 3] This figure illustrates an example of impurity concentrations in the base layer, contact layer, and ion implantation layer of the semiconductor device in Embodiment 1. [Figure 4] This is a flowchart illustrating the manufacturing method of the semiconductor device in Embodiment 1. [Figure 5]This is a diagram for explaining the forward current flow of the semiconductor device in Embodiment 1. [Figure 6] This is a diagram for explaining the body diode current flow of the semiconductor device in Embodiment 1. [Figure 7] This is a longitudinal sectional view of the main part of the semiconductor device in Embodiment 2. [Figure 8] This is a longitudinal sectional view of the main part of the semiconductor device in Embodiment 3. [Figure 9] This is a longitudinal sectional view of the main part of the semiconductor device in Embodiment 4. [Figure 10] This is a longitudinal sectional view of the main part of the semiconductor device in Embodiment 5.

Embodiments for Carrying Out the Invention

[0025] Embodiment 1. FIG. 1 is a longitudinal sectional view of the main part of the semiconductor device in Embodiment 1. <​​​​​​​​​This is a type of layer. For example, epitaxial layer 3 is formed on substrate 2 by epitaxial growth. Epitaxial layer 3 contains dislocation defects. For example, region A is a region that does not contain dislocation defects in the unit structure. For example, region B is a region that contains dislocation defects in the unit structure. In Figure 1, dislocation defects are indicated by C.

[0028] Multiple base layers 4 are formed on the epitaxial layer 3. Multiple base layers 4 are formed of second-conductivity silicon carbide. For example, multiple base layers 4 are p - It is a type of layer. For example, multiple base layers 4 are formed by ion implantation with aluminum as an impurity. Multiple source layers 5 are formed on each of the multiple base layers 4. Multiple source layers 5 are formed of silicon carbide of the first conductivity type with a higher impurity concentration than epitaxial layer 3. For example, multiple source layers 5 are n + It is a type of layer. For example, multiple source layers 5 are formed by ion implantation with nitrogen as an impurity. Multiple contact layers 6 are formed on each of the multiple base layers 4. In each of the multiple base layers 4, the contact layer 6 is surrounded by the source layer 5. The multiple contact layers 6 are formed of silicon carbide of the second conductivity type with a higher impurity concentration than the multiple base layers 4. For example, the multiple contact layers 6 are p + These are molded layers. For example, multiple contact layers 6 are formed by ion implantation using aluminum as an impurity.

[0029] Multiple gate insulating layers 7 are formed to be in contact with the respective source layers 5 of adjacent base layers 4. Specifically, the multiple gate insulating layers 7 are formed to span the base layer 4 adjacent to the epitaxial layer 3 and the respective source layers 5 located inside it. For example, the multiple gate insulating layers 7 are formed by thermal oxidation. Multiple gate electrode layers 8 are each formed on top of the multiple gate insulating layers 7. For example, the multiple gate electrode layers 8 are formed from polysilicon by CVD.

[0030] Multiple interlayer insulating layers 9 are formed to cover each of the multiple gate electrode layers 8. For example, the multiple interlayer insulating layers 9 are formed by the CVD method. Multiple source electrode layers 10 are formed corresponding to each of the multiple base layers 4. The source electrode layers 10 are formed to span the source layer 5 and the contact layer 6. For example, the multiple source electrode layers 10 are formed by depositing Ni or the like by sputtering and then heat-treating them. The wiring electrode layer 11 is formed to cover the multiple source electrode layers 10. For example, the wiring electrode layer 11 is formed of an aluminum alloy by sputtering.

[0031] The drain electrode layer 12 is formed on the second surface (bottom surface in Figure 1) of the substrate 2. For example, the drain electrode layer 12 is formed by depositing Ni or the like by sputtering and then heat-treating it.

[0032] In this embodiment, an ion-implanted layer 13 is added. The ion-implanted layer 13 is not formed in region A where dislocation defects C of the epitaxial layer 3 do not exist when viewed from above. The ion-implanted layer 13 is formed in region B where dislocation defects C of the epitaxial layer 3 exist when viewed from above. The ion-implanted layer 13 is formed on the surface of the contact layer 6 in region B.

[0033] The ion implantation layer 13 is formed in region B so as to extend beyond the contact layer 6 towards the source layer 5. The ion implantation layer 13 is formed in region B so as to prevent contact between the contact layer 6 and at least the region in contact with the source layer and the source electrode layer 10. The ion implantation layer 13 is formed so as to be at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing in region A.

[0034] For example, the ion implantation layer 13 is formed of silicon carbide of the first conductivity type with a higher impurity concentration than the epitaxial layer 3. For example, the ion implantation layer 13 is n + It is a layer of type . For example, the ion implanted layer 13 is formed by ion implantation with nitrogen as an impurity. For example, the ion implanted layer 13 has a nitrogen concentration of 1 × 10⁻⁶ 18 cm -3The above and 1 × 10 21 cm -3 The following conditions are met. For example, the ion implantation layer 13 is formed such that the ratio of nitrogen concentration to aluminum concentration is between 1 and 3 times.

[0035] Next, we will explain the details of the ion implantation layer 13 using Figure 2. Figure 2 is a top view of the main parts of the semiconductor device in Embodiment 1. In Figure 2, the substrate 2, epitaxial layer 3, multiple base layers 4, multiple gate insulating layers 7, multiple gate electrode layers 8, wiring electrode layer 11, and drain electrode layer 12 are not shown.

[0036] In Figure 2, the dislocation defect C spans three unit structures. In these three unit structures, the region B containing the dislocation defect C is indicated by the dashed line. To avoid complexity, it is not shown in the diagram, but in each unit structure, the region A that does not contain the dislocation defect C is the region other than the shown region B. Note that in the cross-section along the DD line, the cross-section corresponding to region E corresponds to the cross-section in Figure 1.

[0037] In the example shown in Figure 2, three ion-implanted layers 13 are formed corresponding to three regions B. For example, in three unit structures where regions B exist, the ion-implanted layers 13 are formed not only within region B but also extending into region A by a predetermined amount. For example, the ion-implanted layers 13 are formed extending into region A by an amount determined according to the depth of the dislocation defect C.

[0038] Next, using Figure 3, we will explain an example of the impurity concentrations in the base layer 4, contact layer 6, and ion implantation layer 13 of the semiconductor device 1. Figure 3 is a diagram illustrating an example of impurity concentrations in the base layer, contact layer, and ion implantation layer of the semiconductor device in Embodiment 1. The horizontal axis of Figure 3 represents the depth (μm) from the top surface of the semiconductor device 1. The vertical axis of Figure 3 represents the impurity concentration (cm³). -3 )

[0039] In Figure 3, the boundary X1 between the base layer 4 and the contact layer 6 is defined as being at a depth of 0.40 μm from the top surface of the semiconductor device 1. The boundary X2 between the contact layer 6 and the ion implantation layer 13 is defined as being at a position where the aluminum concentration and the nitrogen concentration are approximately the same. In Figure 3, the boundary X2 between the contact layer 6 and the ion implantation layer 13 is defined as being at a depth of 0.08 μm.

[0040] Here, F is the aluminum concentration as an impurity concentration in base layer 4. G is the aluminum concentration as an impurity concentration in contact layer 6. H is the aluminum concentration as an impurity concentration in ion implantation layer 13. J is the nitrogen concentration as an impurity concentration in ion implantation layer 13. K is the nitrogen concentration as an impurity concentration in contact layer 6.

[0041] In the example shown in Figure 3, the maximum aluminum concentration in base layer 4 is 1 × 10⁻⁶. 18 cm -3 It is approximately such a value. In the contact layer 6, the maximum value of aluminum concentration is 1 × 10⁻⁶. 19 cm -3 This value is slightly smaller than that. In the ion implantation bed 13, the maximum nitrogen concentration is 1 × 10⁻⁶. 19 cm -3 It is a slightly smaller value than that.

[0042] Next, the manufacturing method of the semiconductor device 1 will be explained using Figure 4. Figure 4 is a flowchart illustrating the manufacturing method of the semiconductor device in Embodiment 1.

[0043] As shown in Figure 4, the semiconductor device 1 is manufactured through a substrate formation process, an epitaxial layer formation process, a dislocation defect detection process, a base layer formation process, a source layer formation process, a contact layer formation process, a resist formation process, a contact layer exposure process, an ion implantation layer formation process, an annealing process, a gate insulating layer formation process, a gate electrode layer formation process, an interlayer insulating layer formation process, a source electrode layer formation process, a wiring electrode layer formation process, and a drain electrode layer formation process.

[0044] In step S1, a substrate formation process is performed. In the substrate formation process, substrate 2 is formed. Subsequently, in step S2, an epitaxial layer formation process is performed. In the epitaxial layer formation process, epitaxial layer 3 is formed. Subsequently, in step S3, a dislocation defect detection process is performed. In the dislocation defect detection process, dislocation defects C in epitaxial layer 3 are detected by photoluminescence, X-ray topography, etc. Information on the locations where dislocation defects C are detected is stored in a computer (not shown).

[0045] Subsequently, in step S4, a base layer formation process is performed. In the base layer formation process, multiple base layers 4 are formed. Then, in step S5, a source layer formation process is performed. In the source layer formation process, multiple source layers 5 are formed. Then, in step S6, a contact layer formation process is performed. In the contact layer formation process, multiple contact layers 6 are formed.

[0046] Subsequently, in step S7, a resist formation process is performed. In the resist formation process, a resist is formed to cover the epitaxial layer 3, multiple base layers 4, multiple source layers 5, and multiple contact layers 6. Subsequently, in step S8, a contact layer exposure process is performed. In the contact layer exposure process, in step S3, a region B in which dislocation defects C exist is identified from the information of the locations detected in the dislocation defect detection process and stored in the computer. Subsequently, in the area corresponding to region B, a portion of the resist is exposed by laser lithography or electron beam lithography, etc. Subsequently, the exposed resist is removed through a resist development process. As a result, in the area corresponding to region B, at least the area from the contact layer 6 to the area in contact with the source layer is exposed. Subsequently, in step S9, an ion implantation layer formation process is performed. In the ion implantation layer formation process, an ion implantation layer 13 is formed on the surface of the contact layer 6. Subsequently, in step S10, an annealing process is performed. In the annealing process, an annealing treatment is performed to activate the ion-implanted impurities.

[0047] Subsequently, in step S11, a gate insulating layer formation process is performed. In the gate insulating layer formation process, multiple gate insulating layers 7 are formed. Subsequently, in step S12, a gate electrode layer formation process is performed. In the gate electrode layer formation process, multiple gate electrode layers 8 are formed. Subsequently, in step S13, an interlayer insulating layer formation process is performed. In the interlayer insulating layer formation process, an interlayer insulating layer 9 is formed.

[0048] Subsequently, in step S14, a source electrode layer formation process is performed. In the source electrode layer process, a source electrode layer 10 is formed. Then, in step S15, a wiring electrode layer formation process is performed. In the wiring electrode layer formation process, a wiring electrode layer 11 is formed. Then, in step S16, a drain electrode layer formation process is performed. In the drain electrode layer formation process, a drain electrode layer 12 is formed.

[0049] Next, we will explain the flow of forward current using Figure 5. Figure 5 is a diagram illustrating the flow of forward current in the semiconductor device in Embodiment 1.

[0050] As shown in Figure 5, the forward current reaches the substrate 2 from the drain electrode layer 12. Then the forward current reaches the epitaxial layer 3. Then the forward current flows toward the gate electrode layer 8. Then the forward current reaches the base layers 4 on both sides of the gate electrode layer 8. Then the forward current reaches the source layers 5 on both sides of the gate electrode layer 8. Then the forward current reaches the source electrode layer 10.

[0051] In this case, the forward current does not pass through the ion implantation layer 13 in region B. Therefore, the ion implantation layer 13 does not affect the forward current.

[0052] Next, we will explain the flow of current in the body diode using Figure 6. Figure 6 is a diagram illustrating the flow of body diode current in the semiconductor device in Embodiment 1.

[0053] As shown in Figure 6, the body diode current flows from the source electrode layer 10 toward the contact layer 6. Subsequently, the body diode current reaches the base layer 4. After that, the body diode current reaches the epitaxial layer 3.

[0054] In this case, in region A, the body diode current flows directly from the source electrode layer 10 to the contact layer 6. In contrast, in region B, the body diode current flows from the source electrode layer 10 to the contact layer 6 via the ion implantation layer 13. Therefore, the value of the body diode current in region B is significantly smaller than the value of the body diode current in region A.

[0055] According to Embodiment 1 described above, the ion implantation layer 13 is formed on the surface of the contact layer 6 in the region B where dislocation defects C of the epitaxial layer 3 exist when viewed from above. Therefore, the reliability of the semiconductor device 1 can be ensured.

[0056] Furthermore, the ion implantation layer 13 is formed in region B so as to extend beyond the contact layer 6 towards the source layer 5. The ion implantation layer 13 is formed in region B so as to prevent contact between the contact layer 6 and at least the region in contact with the source layer and the source electrode layer 10. This ensures that the body diode current value in region B is reliably reduced. As a result, the expansion of dislocation defects C is suppressed, and the reliability of the semiconductor device 1 can be more reliably ensured.

[0057] Specifically, the ion implantation layer 13 is formed such that the current flowing through region B is at least 1 / 1,000,000 and at least 1 / 10 of the current flowing through region A. Because only a small current flows through the ion implantation layer 13 and it does not provide insulation, the electric field distribution remains almost undisturbed even during the actual operation of the semiconductor device 1. As a result, the reliability of the semiconductor device 1 can be more reliably ensured.

[0058] For example, the ion implantation layer 13 is formed of silicon carbide of the first conductivity type with a higher impurity concentration than the epitaxial layer 3. For example, the ion implantation layer 13 has a nitrogen concentration of 1 × 10⁻⁶ 18 cm -3 The above and 1 × 10 21 cm -3 The following configuration is achieved. For example, the ion implantation layer 13 is formed such that the ratio of aluminum concentration to nitrogen concentration is between 1 and 3 times. This significantly reduces the value of the body diode current in region B. As a result, the expansion of dislocation defects C is suppressed, and the reliability of the semiconductor device 1 can be more reliably ensured.

[0059] Furthermore, the ion implantation layer 13 is formed in the area corresponding to region B through a resist formation process and a contact layer exposure process. Therefore, the reliability of the semiconductor device 1 can be ensured by adding a simple process.

[0060] In particular, in silicon carbide MOSFETs, many additional field relaxation layers are provided to avoid field concentration as high-voltage elements exceeding 1000V. In contrast, according to this disclosure, the gate electrode layer 8 and the source electrode layer 10 are not removed. Therefore, the precisely designed field distribution is not disturbed. As a result, the reliability of the semiconductor device 1 can be ensured without causing degradation of the breakdown voltage or fluctuations in the threshold voltage.

[0061] In Figure 2, in the three unit structures where region B exists, the ion implantation layer 13 does not necessarily have to extend into region A. For example, the ion implantation layer 13 may be formed such that its end is positioned at the boundary between region B and region A. Alternatively, the ion implantation layer 13 may be formed such that its end is positioned a predetermined amount closer to region B than the boundary between region B and region A.

[0062] Embodiment 2. Figure 7 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 2. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0063] In Figure 7, the ion-implanted layer 14 is formed to have deep energy levels. For example, the ion-implanted layer 14 is formed by ion implantation using a transition metal such as vanadium as an impurity. For example, the ion-implanted layer 14 is formed by ion implantation using hydrogen, helium, neon, argon, etc. as impurities. If the impurities are hydrogen, helium, neon, argon, etc., in Figure 4, steps S7 to S9 may be performed from step S10 onwards until before step S14.

[0064] According to Embodiment 2 described above, the ion implantation layer 14 is formed to have deep energy levels. As a result, the resistance of the ion implantation layer 14 becomes large. For example, due to the resistance of the ion implantation layer 14, the current value flowing through region B becomes at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through region A. As a result, the expansion of dislocation defects C is suppressed, and the reliability of the semiconductor device 1 can be more reliably ensured.

[0065] Embodiment 3. Figure 8 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 3. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0066] In Figure 8, the ion implantation layer 15 is formed of silicon carbide of the first conductivity type with a higher impurity concentration than the epitaxial layer 3. The width of the ion implantation layer 15 is formed to be the same as or wider than the width of the source electrode layer 10.

[0067] According to Embodiment 3 described above, the width of the ion implantation layer 15 is formed to be the same as or wider than the width of the source electrode layer 10. Therefore, for example, not only the body diode current but also the forward current will have a current value of at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing in region B. As a result, the expansion of dislocation defects C can be suppressed, and the reliability of the semiconductor device 1 can be more reliably ensured.

[0068] Embodiment 4. Figure 9 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 4. Note that the same or equivalent parts as in Embodiment 2 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0069] In Figure 9, the ion implantation layer 16 is formed to have deep energy levels. The width of the ion implantation layer 16 is formed to be the same as or wider than the width of the source electrode layer 10.

[0070] According to Embodiment 4 described above, the width of the ion implantation layer 16 is formed to be the same as or wider than the width of the source electrode layer 10. As a result, not only the body diode current but also the forward current is such that the current value flowing through region B is at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through region A. As a result, the expansion of dislocation defects C is suppressed, and the reliability of the semiconductor device 1 can be more reliably ensured.

[0071] Embodiment 5. Figure 10 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 5. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0072] As shown in Figure 10, the semiconductor device 1 is of the trench type. An ion implantation layer 13 is also added to the semiconductor device 1.

[0073] According to Embodiment 5 described above, even if the semiconductor device 1 is of the trench type, an ion implantation layer 13 is added. Therefore, the reliability of the semiconductor device 1 can be ensured.

[0074] In Embodiments 1 to 5, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case as well, the reliability of the semiconductor device 1 can be ensured.

[0075] While several aspects of at least one embodiment have been described, it should be understood that various modifications, alterations, and improvements will be readily conceivable to those skilled in the art. Such modifications, alterations, and improvements are intended to be part of and within the scope of this disclosure.

[0076] It should be understood that the embodiments of the methods and apparatus described herein are not limited to their application to the structural and arrangement details of the components described above or illustrated in the accompanying drawings. The methods and apparatus can be implemented in other embodiments and carried out or performed in various ways.

[0077] Specific implementation examples are provided here for illustrative purposes only and are not intended to be limiting.

[0078] The expressions and terms used in this disclosure are for illustrative purposes only and should not be considered limiting. The use herein of “includes,” “equips,” “possesses,” “contains,” and variations thereof means the inclusion of the items listed herein and their equivalents, as well as the supplementary items.

[0079] The use of "or" can be interpreted as meaning that any term used with "or" refers to one, more than one, or all of the terms described.

[0080] References to front / back, left / right, top / bottom / top / bottom, width / height, and front / back are all intended for convenience of description. Such references do not mean that the components of this disclosure are limited to any single positional or spatial orientation. Accordingly, the above description and drawings are illustrative only. [Explanation of Symbols]

[0081] 1. Semiconductor layer, 2. Substrate, 3. Epitaxial layer, 4. Base layer, 5. Source layer, 6. Contact layer, 7. Gate insulating layer, 8. Gate electrode layer, 9. Interlayer insulating layer, 10. Source electrode layer, 11. Wiring electrode layer, 12. Drain electrode layer, 13-16. Ion implantation layer

Claims

1. A substrate formed of first-conductivity silicon carbide, On the first surface of the substrate, an epitaxial layer is formed of silicon carbide of a first conductivity type with a lower impurity concentration than the substrate, and contains dislocation defects. A plurality of base layers formed of second-conductivity silicon carbide are provided on the epitaxial layer, Each of the above-mentioned multiple base layers is formed on each of the above-mentioned multiple source layers with silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, Each of the aforementioned multiple base layers is surrounded by a source layer, and each of the multiple contact layers is formed of a second-conductivity silicon carbide with a higher impurity concentration than the base layer, Multiple gate insulating layers formed to contact each source layer of an adjacent base layer, A plurality of gate electrode layers formed on each of the plurality of gate insulating layers, On each of the aforementioned multiple base layers, a plurality of source electrode layers are formed spanning the source layer and the contact layer, A drain electrode layer formed on the second surface of the substrate, In a top view, in the region where dislocation defects exist in the epitaxial layer, an ion implantation layer formed on the surface of the contact layer, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the ion implantation layer is formed of silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer.

3. The semiconductor device according to claim 1, wherein the ion implantation layer is formed to have deep energy levels.

4. The semiconductor device according to any one of claims 1 to 3, wherein the ion implantation layer is formed in a region where dislocation defects exist in the epitaxial layer when viewed from above, and extends beyond the contact layer towards the source layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein the ion implantation layer is formed in a region where dislocation defects exist in the epitaxial layer when viewed from above, from the contact layer to at least the region in contact with the source layer, and so as to prevent contact with the source electrode layer.

6. The semiconductor device according to any one of claims 1 to 3, wherein the ion implantation layer is formed such that, in a top view, the current flowing through the region where dislocation defects exist in the epitaxial layer is at least 1 / 1,000,000 and at least 1 / 10 of the current flowing through the region without dislocation defects.

7. The ion implantation bed has a nitrogen concentration of 1 × 10 １８ cm －３ The above and 1 x 10 ２１ cm －３ The semiconductor device according to claim 2, which is formed as follows.

8. The semiconductor device according to claim 2, wherein the ion implantation layer is formed such that the ratio of nitrogen concentration to aluminum concentration is 1 to 3 times.

9. An epitaxial layer formation step of forming an epitaxial layer of first conductivity type silicon carbide having a lower impurity concentration than the substrate on the first surface of a substrate formed of first conductivity type silicon carbide, A dislocation defect detection step for detecting dislocation defects in the epitaxial layer, A base layer formation step in which multiple base layers are formed on the epitaxial layer using silicon carbide of the second conductivity type, A source layer formation step is to form a plurality of source layers on each of the plurality of base layers using a first conductivity type silicon carbide with a higher impurity concentration than that of the epitaxial layer, A contact layer formation step is performed in which multiple contact layers are formed on each of the multiple base layers, surrounded by a source layer, using a second conductive type of silicon carbide with a higher impurity concentration than the base layer, A gate insulating layer formation step in which multiple gate insulating layers are formed so as to be in contact with the respective source layers of adjacent base layers, A gate electrode layer formation step in which a plurality of gate electrode layers are formed on the plurality of gate insulating layers, A source electrode layer formation step is performed in which multiple source electrode layers are formed on each of the multiple base layers so as to span the source layer and the contact layer, A drain electrode layer formation step in which a drain electrode layer is formed on the second surface of the substrate, Prior to the source electrode layer formation step, an ion implantation layer formation step is performed in which an ion implantation layer is formed on the surface of the contact layer in a region where dislocation defects exist in the epitaxial layer when viewed from above. A method for manufacturing a semiconductor device equipped with [the specified features].

10. The method for manufacturing a semiconductor device according to claim 9, comprising the step of forming the ion-implanted layer by an ion implantation method such that the ion-implanted layer is composed of silicon carbide of a first conductivity type with a higher impurity concentration than the epitaxial layer.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the ion implantation layer formation step includes a step of forming the ion implanted layer by an ion implantation method such that the ion implanted layer is at a deep energy level.

12. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the ion implantation layer formation step includes forming the ion implantation layer in a region of the epitaxial layer where dislocation defects exist when viewed from above, such that the ion implantation layer extends beyond the contact layer towards the source layer.

13. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the ion implantation layer formation step includes forming the ion implantation layer in a region where dislocation defects exist in the epitaxial layer when viewed from above, from the contact layer to at least the region in contact with the source layer, and preventing contact with the source electrode layer.

14. A method for manufacturing a semiconductor device according to any one of claims 9 to 11, comprising the step of forming the ion implanted layer such that the current value flowing through the region of the epitaxial layer where dislocation defects exist, when viewed from above, is at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through the region without dislocation defects.

15. The ion implantation layer formation step is performed when the nitrogen concentration is 1 × 10 １８ cm －３ The above and 1 x 10 ２１ cm －３ A method for manufacturing a semiconductor device according to claim 10, comprising the step of forming the ion implantation layer as follows.

16. The method for manufacturing a semiconductor device according to claim 10, wherein the ion implantation layer formation step includes a step of forming the ion implantation layer such that the ratio of nitrogen concentration to aluminum concentration is 1 to 3 times.

17. A resist forming step of forming a resist so as to cover the epitaxial layer, the plurality of base layers, the plurality of source layers, and the plurality of contact layers, A contact layer exposure step is performed in which a portion of the resist is removed in a region of the epitaxial layer where dislocation defects exist when viewed from above, thereby exposing the contact layer. Equipped with, The method for manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the ion implantation layer formation step involves forming the ion implantation layer on the surface layer of the contact layer.

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