Electronic device and method for manufacturing electronic device

Abstract

This electronic device comprises a support member, a wiring layer, a barrier metal, a bonding layer, and an electronic component. The support member has a main surface directed toward one side in the thickness-direction. The wiring layer is formed on the main surface. The barrier metal is formed on the wiring layer. The bonding layer is formed on the barrier metal. The electronic component is bonded to the wiring layer via the bonding layer and the barrier metal, and is electrically conductive with the wiring layer. The barrier metal and the wiring layer each contain mutually different metals. The barrier metal is smaller than the wiring layer when viewed in the thickness direction.

Description

Electronic device and method for manufacturing the same

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to electronic devices and methods for manufacturing electronic devices.

[0002] Conventionally, electronic devices including a plurality of electronic components have been known. For example, Patent Document 1 discloses an example of a conventional electronic device. The electronic device (module substrate) described in Patent Document 1 includes a wiring board and a plurality of electronic components. The plurality of electronic components include semiconductor elements (flip-chip ICs) and passive elements. The passive elements are, for example, resistor elements, inductor elements, and capacitor elements. The semiconductor elements and passive elements are mounted on a wiring board. A wiring layer is disposed on the surface of the wiring board. The semiconductor elements and passive elements are bonded to the wiring layer via a conductive bonding material (a solder layer in Patent Document 1).

[0003] JP 2009-147115 A

[0004] In a configuration in which electronic components are bonded to a wiring layer via a bonding layer (conductive bonding material) like the electronic device (module substrate), a defect in the bonding layer can reduce the bonding strength between the electronic components and the wiring layer and the electrical conductivity between the electronic components and the wiring layer. Such reduced bonding strength and electrical conductivity reduce the reliability of the electronic device.

[0005] An object of the present disclosure is to provide an electronic device that is improved over conventional devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide an electronic device that can suppress a decrease in reliability. Another object of the present disclosure is to provide a method for manufacturing an electronic device in which a decrease in reliability is suppressed.

[0006] An electronic device provided by a first aspect of the present disclosure includes a support member having a main surface facing one side in a thickness direction, a wiring layer formed on the main surface, a barrier metal formed on the wiring layer, a bonding layer formed on the barrier metal, and an electronic component bonded to the wiring layer via the bonding layer and the barrier metal and conducting to the wiring layer. The barrier metal and the wiring layer contain different metals. The barrier metal is smaller than the wiring layer in the thickness direction.

[0007] A method for manufacturing an electronic device according to a second aspect of the present disclosure includes the steps of: preparing a support member having a main surface facing in one direction in a thickness direction; forming a wiring layer on the main surface; forming a barrier layer on the wiring layer; forming a plating layer on the barrier layer; forming a bonding layer on the plating layer; mounting an electronic component on the bonding layer; and bonding the electronic component by melting the bonding layer by reflow and solidifying the molten bonding layer by cooling. The plating layer contains tin and silver.

[0008] According to the above configuration, it is possible to suppress a decrease in reliability of the electronic device. Furthermore, according to the above configuration, it is possible to manufacture an electronic device in which a decrease in reliability is suppressed.

[0009] FIG. 1 is a perspective view of an electronic device according to a first embodiment, as seen from the bottom side. FIG. 2 is a plan view of the electronic device according to the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 3 is a diagram of the plan view of FIG. 2, with the sealing resin omitted and with a semiconductor element and multiple electronic components indicated by imaginary lines. FIG. 4 is a bottom view of a semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a partially enlarged cross-sectional view of a bonding portion of an electronic component in the electronic device shown in FIG. 1, enlarging a portion (the bonding portion of the electronic component) of FIG. 7. FIG. 9 is an enlarged cross-sectional view of a bonding portion of an electronic component in the electronic device shown in FIG. 1, according to another example. FIG. 10 is a bottom view of a semiconductor element constituting the electronic device shown in FIG. 1. FIG. 11 is an enlarged cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 13 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 14 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 15 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 16 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 17 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 18 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 19 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 20 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 21 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 22 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 23 is a cross-sectional view showing a step of a manufacturing method for an electronic device according to the first embodiment. FIG. 24 is an enlarged cross-sectional view of a main part of an electronic device according to a second embodiment, and corresponds to the cross section of FIG. 8 . 25 and 26 are enlarged cross-sectional views of a main part showing a step in the method for manufacturing an electronic device according to the second embodiment.FIG. 27 is an enlarged cross-sectional view of a main part showing a step of a method for manufacturing an electronic device according to the second embodiment. FIG. 28 is an enlarged cross-sectional view of a main part showing a step of a method for manufacturing an electronic device according to the second embodiment. FIG. 29 is an enlarged cross-sectional view of a main part showing a step of a method for manufacturing an electronic device according to the second embodiment. FIG. 30 is an enlarged cross-sectional view of a main part showing a step of a method for manufacturing an electronic device according to the second embodiment. FIG. 31 is a cross-sectional view showing an electronic device according to another embodiment. FIG. 32 is a cross-sectional view showing a step of a method for manufacturing the electronic device shown in FIG. 31. FIG. 33 is a plan view showing an electronic device according to another embodiment, in which a sealing resin and a semiconductor element are shown by imaginary lines. FIG. 34 is a plan view showing an electronic device according to another embodiment, in which a sealing resin and a semiconductor element are shown by imaginary lines.

[0010] Preferred embodiments of the electronic device and the method for manufacturing the electronic device according to the present disclosure will be described below with reference to the drawings. In the following, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B," unless otherwise specified. Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, "a surface A faces in a certain direction B (one side or the other side of a certain direction B)," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted with respect to direction B. Furthermore, "a surface A is perpendicular to a surface B," unless otherwise specified, is not limited to the case where surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted with respect to surface B.

[0012] 1 to 11 show an electronic device A10 according to a first embodiment. The electronic device A10 includes a semiconductor element 1, a plurality of electronic components 19, a support member 2, a wiring layer 30, a barrier metal 35, a plurality of bonding layers 41, a plurality of bonding layers 42, a plurality of terminals 5, and a sealing resin 6.

[0013] For ease of explanation, the mutually orthogonal thickness direction z, first direction x, and second direction y will be referred to. As an example, the thickness direction z corresponds to the thickness direction of the electronic device A10. In the following explanation, terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. Furthermore, "planar view" refers to the view in the thickness direction z.

[0014] The electronic device A10 is a device to be surface-mounted on a wiring board of an electronic device, an electric vehicle, etc. The electronic device A10 is a leadless package type, particularly a QFN (Quad Flat Non-leaded Package) type. The electronic device A10 has a rectangular shape in a plan view.

[0015] The semiconductor element 1 is a component that is the core of the electronic device A10's functions. The semiconductor element 1 is, for example, an integrated circuit such as an LSI. Unlike this example, the semiconductor element 1 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete element such as a transistor or diode. The semiconductor element 1 is rectangular in plan view. The semiconductor element 1 is supported by a support member 2. The semiconductor element 1 overlaps the support member 2 in plan view.

[0016] 5 and 6 , the semiconductor element 1 has an element main surface 10a and an element back surface 10b. The element main surface 10a and the element back surface 10b are spaced apart in the thickness direction z. The element main surface 10a and the element back surface 10b face in opposite directions. The element main surface 10a faces the support member 2.

[0017] As shown in FIGS. 10 and 11 , the semiconductor device 1 includes a main body 11, a plurality of pads 12, an insulating film 13, and rewirings 14. Each of the pads 12 is electrically connected to a circuit (not shown) configured in the main body 11. The main surface 10a of the device corresponds to the lower surface of the main body 11 (the surface facing downward in the thickness direction z). The insulating film 13 is disposed on the lower surface (main surface 10a) of the main body 11. The pads 12 are exposed from the insulating film 13. The insulating film 13 contains polyimide or polybenzoxazole. The rewirings 14 are provided on the insulating film 13. The rewirings 14 are connected to at least one of the pads 12. The rewirings 14 contain copper (Cu). As shown in FIGS. 10 and 11 , the rewirings 14 are bonded to the wiring layer 30 via at least one of a plurality of bonding layers 41. As a result, each of the plurality of pads 12 is electrically connected to the wiring layer 30 via either the rewiring 14 or the plurality of bonding layers 41 .

[0018] As shown in FIGS. 2 and 5 to 7 , the electronic components 19 are supported by the support member 2. Each of the electronic components 19 is an SMD (Surface Mount Device). Each of the electronic components 19 is, for example, a resistor, a capacitor, or a diode. The electronic components 19, together with the semiconductor element 1, are functional elements of the electronic device A10. As shown in FIGS. 5 and 7 , each of the electronic components 19 has a pair of side surfaces 190 a. The pair of side surfaces 190 a faces in a direction perpendicular to the thickness direction z (the orthogonal direction). The pair of side surfaces 190 a faces opposite each other in the orthogonal direction. In the illustrated example, the electronic components 19 include one whose orthogonal direction is the first direction x and another whose orthogonal direction is the second direction y. As shown in FIGS. 5 and 7 , each of the electronic components 19 includes a pair of terminals 191. In each electronic component 19, the pair of terminals 191 is disposed on both sides of the orthogonal direction. Each of the pair of terminals 191 includes a side electrode 191a. Each of the side electrodes 191a of the pair of terminals 191 individually covers a pair of side surfaces 190a. The number of electronic components 19 is not limited to the example shown in the figure.

[0019] As shown in FIGS. 2 and 5 to 7 , the support member 2 supports the semiconductor element 1 and multiple electronic components 19. The support member 2 includes, for example, a resin material. The resin material may be the same as the sealing resin 6, but may be different from the sealing resin 6. The support member 2 may also include a filler such as silica mixed into the aforementioned resin material. The support member 2 may be configured to include a single-crystal intrinsic semiconductor (e.g., silicon (Si)) instead of a resin material. As shown in FIGS. 2 to 4 , the support member 2 has a rectangular shape in a plan view. The thickness of the support member 2 (the dimension along the thickness direction z) is not limited in any way, but is, for example, 30 μm or more and 200 μm or less. The support member 2 has a main surface 21, a back surface 22, and multiple side surfaces 23.

[0020] 5 to 7 , the main surface 21 and the back surface 22 are spaced apart in the thickness direction z. The main surface 21 and the back surface 22 face opposite each other. The main surface 21 is the upper surface of the support member 2, and the back surface 22 is the lower surface of the support member 2. The main surface 21 faces the semiconductor element 1 (element main surface 10a). The back surface 22 faces the wiring board when the electronic device A10 is mounted on the wiring board. In this embodiment, the main surface 21 is covered with the sealing resin 6, and the back surface 22 is exposed from the sealing resin 6.

[0021] 2 to 10 , each of the multiple side surfaces 23 is sandwiched between the main surface 21 and the back surface 22. The upper end of each side surface 23 in the thickness direction z is connected to the main surface 21, and the lower end of each side surface 23 in the thickness direction z is connected to the back surface 22. Each side surface 23 is flat and perpendicular to both the main surface 21 and the back surface 22.

[0022] The wiring layer 30 is a conductor disposed inside the electronic device A10. The wiring layer 30 contains, for example, Cu. The wiring layer 30 is, for example, a laminate of a seed layer (containing, for example, titanium (Ti)) and a metal layer (containing, for example, Cu), but may also be a single layer made of a conductor. As shown in FIG. 3 , the wiring layer 30 includes a plurality of pattern wiring portions separated from one another. The plurality of pattern wiring portions includes one that is electrically connected to the semiconductor element 1, one that is electrically connected to one of the plurality of electronic components 19, and one that is not electrically connected to either the semiconductor element 1 or the plurality of electronic components 19. In this embodiment, the wiring layer 30 is formed on the main surface 21 and is in contact with the main surface 21. The thickness of the wiring layer 30 (the dimension along the thickness direction z) is 3 μm or more and 100 μm or less.

[0023] 8 or 9 , the wiring layer 30 includes an interposed portion 321 and an extending portion 322. The interposed portion 321 is a portion of the wiring layer 30 that is interposed between the support member 2 and the electronic component 19 in the thickness direction z. The extending portion 322 is connected to the interposed portion 321. The extending portion 322 is a portion of the wiring layer 30 that is disposed outward from the electronic component 19 in a plan view.

[0024] The plurality of barrier metals 35 are each formed on the wiring layer 30. Each barrier metal 35 contains a metal different from that of the wiring layer 30. Each barrier metal 35 contains nickel (Ni) as the metal. Each of the plurality of barrier metals 35 is smaller than the wiring layer 30 in a plan view. Therefore, as shown in FIG. 8 or FIG. 9, a step is formed between each barrier metal 35 and the wiring layer 30. In this embodiment, in a plan view, the wiring layer 30 protrudes outward from the barrier metal 35. As shown in FIGS. 5 and 6, the plurality of barrier metals 35 include one interposed between the bonding layer 41 and the wiring layer 30 and one interposed between the bonding layer 42 and the wiring layer 30. Note that the plurality of barrier metals 35 do not necessarily include one interposed between the bonding layer 41 and the wiring layer 30. For example, the thickness of each barrier metal 35 is 1 μm or more and 10 μm or less.

[0025] Each of the multiple bonding layers 41 bonds the wiring layer 30 to one of the multiple rewirings 14 of the semiconductor element 1. The semiconductor element 1 is electrically connected to the wiring layer 30 via the multiple bonding layers 41. Each of the multiple bonding layers 41 is a conductive bonding material. The multiple bonding layers 41 are, for example, solder. The solder contains an alloy containing tin (Sn) in its composition (for example, an Sn-silver (Ag) alloy) and also contains flux. Note that the composition of each of the multiple bonding layers 41 is not limited to this example. The thickness (dimension along the thickness direction z) of each bonding layer 41 is not limited in any way, but is, for example, 15 μm or more and 100 μm or less.

[0026] The multiple bonding layers 42 bond the wiring layer 30 to a corresponding one of the multiple terminals 191 of the multiple electronic components 19. Each of the multiple bonding layers 42 is formed on a corresponding one of the multiple barrier metals 35. Each bonding layer 42 may not be in contact with the wiring layer 30, as shown in FIG. 8, or may be in contact with the wiring layer 30, as shown in FIG. 9, or may have a mixture of a portion that contacts the wiring layer 30 and a portion that does not contact the wiring layer 30. In the example shown in FIG. 8, the entire bonding layer 42 is disposed on the corresponding barrier metal 35, while in the example shown in FIG. 9, the bonding layer 42 entirely covers the corresponding barrier metal 35. Each of the multiple bonding layers 42 is a conductive bonding material. Each of the multiple bonding layers 42 includes an alloy layer stacked on the barrier metal 35. The alloy layer contains Sn in its composition, for example, an Sn—Ag alloy. Note that the composition of each of the multiple bonding layers 42 is not limited to this example. Each bonding layer 42 is, for example, solder. Each bonding layer 42 may or may not contain flux. The thickness (dimension along the thickness direction z) of each bonding layer 42 is not limited in any way, but is, for example, not less than 1 μm and not more than 20 μm.

[0027] 8 or 9, each of the bonding layers 42 includes a fillet portion 421. The fillet portion 421 contacts the lateral electrode 191a. In the example shown in Fig. 8 or 9, the side surface of the fillet portion 421 is convexly curved, but it may be concavely curved or may not be curved.

[0028] Each of the multiple terminals 5 is electrically connected to the wiring layer 30 and is a conductor exposed to the outside of the electronic device A10. Each of the multiple terminals 5 serves as a terminal when the electronic device A10 is mounted on a wiring board. As shown in FIGS. 5 to 7 , each of the multiple terminals 5 penetrates the support member 2 in the thickness direction z. The multiple terminals 5 include those that are electrically connected to the semiconductor element 1 via the wiring layer 30, those that are electrically connected to the semiconductor element 1 and one of the multiple electronic components 19 via the wiring layer 30, those that are electrically connected to one of the multiple electronic components 19 via the wiring layer 30, and those that are not electrically connected to either the semiconductor element 1 or the multiple electronic components 19. In the illustrated example, all of the multiple terminals 5 are disposed outside the semiconductor element 1 in a planar view and do not overlap either the semiconductor element 1 or the multiple electronic components 19 in a planar view. Unlike this example, some of the multiple terminals 5 may overlap either the semiconductor element 1 or the multiple electronic components 19 in a planar view.

[0029] 5 to 7, each of the plurality of terminals 5 includes a columnar portion 51 and an external electrode portion 52. The columnar portion 51 and the external electrode portion 52 described below are common to all terminals 5 unless otherwise specified.

[0030] As shown in FIGS. 5 to 7 , the columnar portion 51 penetrates the support member 2 in the thickness direction z. The columnar portion 51 includes, for example, a metal material. The metal material is not limited to, but is, for example, Cu. The planar shape of the columnar portion 51 is not limited to, but is rectangular or polygonal in the illustrated example. The upper surface of the columnar portion 51 (the surface facing upward in the thickness direction z) is, for example, flush with the main surface 21 of the support member 2. The upper surface of this columnar portion 51 contacts the wiring layer 30. Note that, among the multiple terminals 5, some of the columnar portions 51 may have an upper surface that does not contact the wiring layer 30. Such terminals 5 serve as dummy terminals. The lower surface of the columnar portion 51 (the surface facing downward in the thickness direction z) is exposed from the support member 2. The lower surface of this columnar portion 51 is, for example, flush with the back surface 22 of the support member 2. In this embodiment, in all terminals 5, the side surfaces of the columnar portions 51 (the surfaces facing the first direction x or the second direction y) are covered by the support member 2, but unlike this example, some terminals 5 may have exposed side surfaces of the columnar portions 51.

[0031] As shown in FIGS. 5 to 7 , the external electrode portion 52 contacts a portion of the columnar portion 51 that is exposed from the rear surface 22 of the support member 2. The external electrode portion 52 protrudes from the rear surface 22. The external electrode portion 52 is formed by electroless plating. For example, the external electrode portion 52 is composed of multiple metal layers stacked in the following order from the side that contacts the columnar portion 51: a Ni layer, a palladium (Pd) layer, and a gold (Au) layer. The external electrode portion 52 can also be configured as multiple metal layers stacked in the following order from the side that contacts the columnar portion 51: a Ni layer and an Au layer, or multiple metal layers stacked in the following order from the side that contacts the columnar portion 51. The material and formation method of the external electrode portion 52 are not limited to these examples.

[0032] The sealing resin 6 is a synthetic resin whose main component is, for example, a black epoxy resin. The sealing resin 6 may contain a filler such as silica mixed into the epoxy resin. As shown in FIGS. 2 and 4 to 7, the sealing resin 6 covers the semiconductor element 1, the plurality of electronic components 19, the wiring layer 30, and the like. As shown in FIGS. 2 and 5 to 7, the sealing resin 6 also covers a portion of the support member 2, the plurality of bonding layers 41, and the plurality of bonding layers 42. The sealing resin 6 is formed on the main surface 21. The sealing resin 6 is rectangular in plan view. As shown in FIGS. 1 to 7, the sealing resin 6 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 63.

[0033] As shown in FIGS. 5 to 7 , the resin main surface 61 and the resin back surface 62 are spaced apart in the thickness direction z. The resin main surface 61 and the resin back surface 62 face opposite each other in the thickness direction z. The resin main surface 61 faces the same direction as the main surface 21 in the thickness direction z, and the resin back surface 62 faces the same direction as the back surface 22 in the thickness direction z. The resin back surface 62 is in contact with the main surface 21. The resin back surface 62 has irregularities according to the shape of the wiring layer 30. As shown in FIGS. 5 to 7 , each of the multiple resin side surfaces 63 is sandwiched between the resin main surface 61 and the resin back surface 62 in the thickness direction z and is connected to them. The multiple resin side surfaces 63 are flush with a corresponding one of the multiple side surfaces 23.

[0034] Next, an example of a method for manufacturing the electronic device A10 will be described with reference to Figures 12 to 23. Figures 12 to 23 are cross-sectional views showing a step in the method for manufacturing the electronic device A10. These cross-sectional views correspond to the cross-section shown in Figure 7. Note that the thickness direction z in the cross-sectional views shown in Figures 22 and 23 is opposite to that in the cross-sectional views shown in Figures 12 to 21.

[0035] First, as shown in FIG. 12 , a support substrate 80 is prepared, and multiple columnar conductors 851 are formed on the support substrate 80. The support substrate 80 includes, for example, a single-crystal intrinsic semiconductor material. The semiconductor material is, for example, Si. In the process of preparing the support substrate 80, for example, a silicon wafer is prepared as the support substrate 80. The support substrate 80 has a substrate main surface 80a and a substrate back surface 80b facing opposite sides in the thickness direction z. The multiple columnar conductors 851 are formed, for example, by the following process. First, a seed layer is formed on the substrate main surface 80a. The seed layer is formed by, for example, sputtering. Then, a resist is patterned on the seed layer, and the multiple columnar conductors 851 are formed by electrolytic plating. Thereafter, the resist layer and any unnecessary seed layer are removed. Through these processes, multiple columnar conductors 851 are formed on the substrate main surface 80a of the support substrate 80. The columnar conductors 851 are portions that will later become the columnar portions 51 of the terminals 5.

[0036] Next, as shown in FIG. 13 , a first resin layer 82 covering the columnar conductors 851 is formed on the substrate main surface 80a of the support substrate 80. The first resin layer 82 is formed, for example, by molding. The first resin layer 82 is a synthetic resin whose main component is, for example, a black epoxy resin. The first resin layer 82 may be made of another insulating resin material instead of the synthetic resin. The first resin layer 82 has a main surface 821 and a bottom surface 822 that face opposite each other in the thickness direction z. The main surface 821 faces the same direction as the substrate main surface 80a, and the bottom surface 822 faces the substrate main surface 80a. The first resin layer 82 is a component that will later become the support member 2.

[0037] Next, as shown in FIG. 14 , the first resin layer 82 is ground. The first resin layer 82 is ground from the main surface 821 side until the columnar conductors 851 are exposed from the main surface 821. The grinding method is not particularly limited. The first resin layer 82 may also be reduced in height by a method other than grinding. As a result, the columnar portions 51 are formed from the columnar conductors 851. The first resin layer 82 formed through the above steps is an example of a "support member." Therefore, in this embodiment, the steps from preparing the support substrate 80 to grinding the first resin layer 82 are an example of a "step of preparing a support member."

[0038] Next, as shown in FIG. 15 , the wiring layer 30 is formed. The wiring layer 30 is formed, for example, by the following process. First, a seed layer is formed on the main surface 821 and each columnar section 51. The seed layer is formed, for example, by sputtering. For example, a Ti layer and a Cu layer are stacked in this order as the seed layer. Then, a resist is patterned on the seed layer, and a metal layer is formed by electrolytic plating. For example, the metal layer contains Cu. After that, the resist and unnecessary seed layer (seed layer exposed from the metal layer) are removed. Through these processes, the wiring layer 30 is formed.

[0039] Next, as shown in FIG. 16 , multiple barrier layers 350 and multiple plating layers 351 are formed in sequence. Each barrier layer 350 contains a metal different from that of the wiring layer 30, such as Ni. Each plating layer 351 contains Sn and Ag (Sn—Ag alloy). The formation of each barrier layer 350 and each plating layer 351 is not limited, but may be performed, for example, by electrolytic plating. In this electrolytic plating, a seed layer serving as a conductive path may be newly formed, or the seed layer formed in the step of forming the wiring layer 30 may be used without removing it. In this embodiment, the multiple barrier layers 350 and the multiple plating layers 351 are formed in the region where the semiconductor element 1 is bonded and the region where the multiple electronic components 19 are bonded, respectively. Each barrier layer 350 formed is smaller than the wiring layer 30 in a planar view.

[0040] 17 , a plurality of bonding layers 420 are formed. In the process of forming the plurality of bonding layers 420, for example, a solder paste as each bonding layer 420 is formed on a corresponding plating layer 351 by screen printing. The corresponding plating layer 351 is one of the plurality of plating layers 351 to which a plurality of electronic components 19 will be bonded later.

[0041] Next, as shown in FIGS. 18 and 19 , multiple electronic components 19 are mounted, and then the multiple electronic components 19 are bonded together. As shown in FIG. 18 , in the process of mounting the multiple electronic components 19, the terminals 191 of the electronic components 19 are placed so that they correspond to the bonding layers 420. Next, reflow is performed with the electronic components 19 placed. The heat from this reflow melts the bonding layers 420. At this time, the plating layers 351 also melt due to the heat from the reflow, and the plating layers 351 and the bonding layers 420 intertwine. Next, the melted bonding layers 420 and plating layers 351 are cooled. This solidifies the bonding layers 420 and plating layers 351, and the electronic components 19 are bonded together. At this time, the bonding layers 420 and plating layers 351 are integrated to form the bonding layer 42. 19, each bonding layer 42 comes into contact with a corresponding barrier layer 350, and the barrier layer 350 serves as the barrier metal 35. As shown in FIG. 19, a fillet portion 421 is formed in each of the formed bonding layers 42.

[0042] Next, as shown in FIGS. 19 and 20 , the semiconductor element 1 is mounted, and then the semiconductor element 1 is bonded. As shown in FIG. 19 , in the process of mounting the semiconductor element 1, each bonding layer 410 formed on the semiconductor element 1 is placed so that it corresponds to the plating layer 351. Note that, although the present embodiment illustrates an example in which each bonding layer 410 is formed on the rewiring 14 of the semiconductor element 1, it may also be formed on the corresponding plating layer 351. In this case, the corresponding plating layer 351 refers to the one of the multiple plating layers 351 to which the semiconductor element 1 will later be bonded. Flux is also added to each bonding layer 410 formed on the semiconductor element 1. Next, reflow is performed with the semiconductor element 1 placed. The heat generated by this reflow melts each bonding layer 410. At this time, the plating layer 351 also melts due to the heat generated by the reflow, and the plating layer 351 and each bonding layer 410 are mixed together. Next, the melted bonding layer 410 and plating layer 351 are cooled. As a result, each bonding layer 410 and plating layer 351 solidifies, bonding the semiconductor element 1. At this time, the bonding layer 410 and plating layer 351 are integrated to form bonding layer 41. Therefore, each bonding layer 41 comes into contact with the corresponding barrier layer 350, as shown in FIG. 20 , and the barrier layer 350 becomes the barrier metal 35.

[0043] Next, as shown in FIG. 21 , a second resin layer 86 is formed. The second resin layer 86 is formed above the support member 2 so as to cover the semiconductor element 1, the plurality of electronic components 19, and the wiring layer 30. The second resin layer 86 is formed, for example, by molding. The second resin layer 86 is a synthetic resin whose main component is, for example, a black epoxy resin. The second resin layer 86 may be made of another insulating resin material instead of the synthetic resin. The second resin layer 86 is a component that will later become the sealing resin 6. The second resin layer 86 has a top surface 861 facing one side in the thickness direction z. The top surface 861 corresponds to the resin main surface 61 of the sealing resin 6.

[0044] Next, as shown in Fig. 22, the support substrate 80 is removed. To remove the support substrate 80, for example, in the state shown in Fig. 21, the support substrate 80 is ground from the rear surface 80b side of the substrate. In this grinding, the support substrate 80 is ground from the rear surface 80b side of the substrate. In the illustrated example, the grinding is continued even after the support substrate 80 is removed, thereby reducing the height of the support member 2 and the columnar portion 51. This reduction in height does not have to be performed.

[0045] Next, as shown in Fig. 23, the external electrode portion 52 is formed. The external electrode portion 52 is formed on the top surface of the columnar portion 51 exposed from the rear surface 22. The external electrode portion 52 is formed by, for example, electroless plating. In this electroless plating, a Ni layer, a Pd layer, and an Au layer are laminated in this order from the side in contact with the columnar portion 51. In this way, a plurality of terminals 5 are formed, each including a columnar portion 51 and an external electrode portion 52.

[0046] 23 , the second resin layer 86 is cut along the cutting lines CL to separate the electronic device A10. The second resin layer 86 is cut by cutting using a dicing blade, for example. The sealing resin 6 of the electronic device A10 is formed by dividing the second resin layer 86 along the cutting lines CL.

[0047] Through the above steps, the electronic device A10 shown in FIGS. 1 to 11 is manufactured. The manufacturing method for the electronic device A10 is not limited to the above example. For example, when the support member 2 includes a single-crystal intrinsic semiconductor (e.g., Si), the electronic device A10 is manufactured as follows. Grooves are formed in the support substrate 80 (silicon wafer) by etching or the like. Next, multiple columnar conductors 851 are formed in the grooves. Next, the wiring layer 30 is formed without forming the first resin layer 82. Furthermore, after forming the second resin layer 86, the support substrate 80 is not removed, but is ground until the multiple columnar conductors 851 formed in the grooves are exposed. In this configuration, the support substrate 80 is an example of a "support member." By modifying the process in this way, the electronic device A10 is manufactured in which the support member 2 is made of a semiconductor material.

[0048] The functions and effects of the electronic device A10 and the method for manufacturing the electronic device A10 are as follows.

[0049] The electronic device A10 includes a barrier metal 35, a bonding layer 42, and an electronic component 19. The barrier metal 35 is formed on a wiring layer 30, and the bonding layer 42 is formed on the barrier metal 35. The electronic component 19 is bonded to the wiring layer 30 via the bonding layer 42 and the barrier metal 35. The barrier metal 35 is smaller than the wiring layer 30 in the thickness direction z. This configuration creates a step between the wiring layer 30 and the barrier metal 35. This step prevents the bonding layer 42 from spreading along the wiring layer 30. A defect in the bonding layer 42 that reduces the reliability of the electronic device A10 is, for example, an insufficient thickness of the bonding layer 42 (a small dimension in the thickness direction z). In the electronic device A10, an insufficient thickness of the bonding layer 42 reduces the bonding strength of the electronic component 19. As described above, if the bonding layer 42 spreads along the wiring layer 30, the bonding layer 42 may become insufficient in thickness. However, as described above, the electronic device A10 can prevent the bonding layer 42 from spreading along the wiring layer 30, thereby preventing an insufficient thickness of the bonding layer 42. In other words, the electronic device A10 can prevent a decrease in the bonding strength of the electronic component 19, thereby preventing a decrease in reliability.

[0050] Furthermore, in the electronic device A10, a barrier metal 35 is interposed between the wiring layer 30 and the bonding layer 42. This configuration can reduce the area where the bonding layer 42 contacts the wiring layer 30. For example, if the bonding layer 42 is solder and the wiring layer 30 contains Cu, the wiring layer 30 may penetrate into the bonding layer 42 in the area where the bonding layer 42 and the wiring layer 30 are in direct contact. This penetration may cause a conduction defect in the wiring layer 30. However, in the electronic device A10, the barrier metal 35 can reduce the contact area between the bonding layer 42 and the wiring layer 30, thereby reducing the conduction defect in the wiring layer 30. In other words, the electronic device A10 can reduce a decrease in reliability.

[0051] The manufacturing method of the electronic device A10 includes the steps of forming a barrier layer 350 on the wiring layer 30 (barrier layer forming step), forming a plating layer 351 on the barrier layer 350 (plating layer forming step), forming a bonding layer 420 on the plating layer 351 (bonding layer forming step), mounting an electronic component 19 on the bonding layer 420 (mounting step), and bonding the electronic component 19 by melting the bonding layer 420 by reflow and solidifying the molten bonding layer 420 by cooling (bonding step). Factors that reduce the reliability of the electronic device A10 include defects in the bonding layer 42, such as the occurrence of voids (air gaps) in the bonding layer 42. Research by the present inventors has revealed the following regarding the occurrence of voids in the bonding layer 42. That is, it was found that by performing the barrier layer formation process and the plating layer formation process in the manufacturing method of the electronic device A10, it is possible to suppress the occurrence of voids in the bonding layer 42 after the bonding process, compared to when these processes are not performed (i.e., when the bonding layer 420 is formed directly on the wiring layer 30). Therefore, the manufacturing method of the electronic device A10 can suppress the occurrence of voids in the bonding layer 42 and suppress defects in the bonding layer 42. In other words, according to the manufacturing method of this embodiment, it is possible to manufacture the electronic device A10 in which the occurrence of defects in the bonding layer 42 is suppressed and a decrease in reliability is suppressed.

[0052] Furthermore, in the manufacturing method, the bonding layer 420 and the plating layer 351 are integrated in the bonding step. Therefore, the manufactured electronic device A10 has a configuration in which each electronic component 19 is bonded to the wiring layer 30 via the bonding layer 42 (the bonding layer 420 and the plating layer 351) and the barrier metal 35 (the barrier layer 350). Therefore, in the electronic device A10, the occurrence of voids in the bonding layer 42 is suppressed, and defects in the bonding layer 42 are suppressed. In other words, the electronic device A10 of the present disclosure can suppress defects in the bonding layer 42 and suppress a decrease in reliability.

[0053] In the manufacturing method of the electronic device A10, each bonding layer 420 is formed by screen printing. This configuration ensures that the bonding layer 42 formed from the bonding layer 420 has a sufficient thickness. Therefore, the electronic device A10 of the present disclosure can ensure an appropriate thickness for the bonding layer 42, thereby preventing the bonding layer 42 from becoming insufficiently thick. In other words, the electronic device A10 can prevent a decrease in the bonding strength of the electronic component 19, thereby preventing a decrease in reliability.

[0054] The electronic device A10 includes a sealing resin 6 that covers the electronic component 19. When the electronic component 19 is sealed with the sealing resin 6 in this manner, if voids are generated in the bonding layer 42, the sealing resin 6 will flow into the voids during the process of forming the sealing resin 6. In this case, the sealing resin 6 formed in the voids reduces the bonding strength of the electronic component 19 and also reduces the electrical conductivity between the electronic component 19 and the wiring layer 30. Therefore, in the electronic device A10 that includes the sealing resin 6, suppressing the generation of voids in the bonding layer 42 is particularly preferable in terms of suppressing a decrease in reliability.

[0055] In the electronic device A10, the electronic component 19 has a side surface 190a and a lateral electrode 191a. The bonding layer 42 includes a fillet portion 421 that contacts the lateral electrode 191a. This configuration can increase the bonding strength of the bonding layer 42 to the electronic component 19. In other words, the electronic device A10 can suppress a decrease in reliability.

[0056] In the electronic device A10, the support member 2 includes a resin material, and this resin material is the same as the sealing resin 6. With this configuration, the difference between the linear expansion coefficient of the support member 2 and the linear expansion coefficient of the sealing resin 6 can be reduced, thereby suppressing thermal stress generated in the electronic device A10.

[0057] Other embodiments and modifications of the electronic device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other to the extent that no technical contradiction occurs.

[0058] Fig. 24 shows an electronic device A20 according to the second embodiment. The cross section shown in Fig. 24 corresponds to the cross section of the electronic device A10 in Fig. 8. The electronic device A20 differs from the electronic device A10 in the following respect: the wiring layer 30 has a portion protruding in the thickness direction z.

[0059] In the electronic device A20, the wiring layer 30 includes a main body portion 311 and a pedestal portion 312. The main body portion 311 corresponds to the wiring layer 30 of the electronic device A10. The pedestal portion 312 protrudes from the main body portion 311 to one side (upward) in the thickness direction z. The shape of the pedestal portion 312 in a planar view is not limited in any way, but may be rectangular, for example. As can be seen from FIG. 24 , the pedestal portion 312 is smaller than the barrier metal 35 in a planar view.

[0060] 25 to 30 each show a step in the method for manufacturing the electronic device A20. The steps shown in Figures 25 to 30 correspond to the step of forming the wiring layer 30 (see Figure 15) and the step of forming the barrier layer 350 and the plating layer 351 (see Figure 16) in the method for the electronic device A10. The remaining steps are the same as those for the electronic device A10.

[0061] In the manufacturing method of the electronic device A20, after forming a plurality of columnar sections 51 and a first resin layer 82 on a support substrate 80 in the same manner as in the manufacturing method of the electronic device A10, a seed layer 301 is formed over the entire main surface 821 of the first resin layer 82, as shown in Fig. 25. The seed layer 301 has a structure in which, for example, a Ti layer and a Cu layer are stacked in order. The seed layer 301 is formed by, for example, a sputtering method.

[0062] Next, as shown in FIGS. 26 and 27 , a metal layer 302 is formed. In forming the metal layer 302, first, as shown in FIG. 26 , a resist 891 for forming the metal layer 302 is patterned by photolithography. Then, the metal layer 302 is formed by electrolytic plating using the seed layer 301 as a conductive path. Subsequently, as shown in FIG. 27 , the resist 891 is removed. Note that the method for removing the resist 891 is not limited in any way. In this way, the metal layer 302 is formed. At the stage where the metal layer 302 is formed, the seed layer 301 remains formed without being removed, as shown in FIG. 27 . Note that the formation of the seed layer 301 and the formation of the metal layer 302 corresponds to the step of forming the wiring layer 30 in the manufacturing method of the electronic device A10.

[0063] Next, as shown in FIGS. 28 and 29 , the base portion 312, the barrier layer 350, and the plating layer 351 are sequentially stacked on the metal layer 302. Specifically, as shown in FIG. 28 , a resist 892 for forming the base portion 312, the barrier layer 350, and the plating layer 351 is first patterned by photolithography. Then, the base portion 312, the barrier layer 350, and the plating layer 351 are sequentially formed by electrolytic plating using the seed layer 301 as a conductive path. The base portion 312 contains Cu, the barrier layer 350 contains Ni, and the plating layer 351 contains an Sn alloy (e.g., an Sn—Ag alloy). Note that the resist 892 may be provided separately when the base portion 312, the barrier layer 350, and the plating layer 351 are formed. Next, as shown in FIG. 29 , the resist 892 is removed. Note that the method for removing the resist 892 is not limited in any way. This forms the base portion 312, the barrier layer 350, and the plating layer 351. Immediately after the resist 892 is removed, the base portion 312, the barrier layer 350, and the plating layer 351 completely overlap each other in a plan view, as shown in Fig. 29. Also, as shown in Fig. 29, the seed layer 301 remains formed without being removed.

[0064] Next, as shown in FIG. 30 , the seed layer 301 exposed from the metal layer 302 is removed. The seed layer 301 is removed by, for example, etching. The etching solution used to remove the seed layer 301 is, for example, a mixed solution of HSO and HO. This etching solution reacts not only with the seed layer 301 but also with the pedestal portion 312, and the pedestal portion 312 is slightly eroded from the side surface exposed from the barrier layer 350. Therefore, as can be seen from FIG. 30 , the pedestal portion 312 becomes smaller than the barrier layer 350 in plan view. By removing the seed layer 301 exposed from the metal layer 302, the main body portion 311 is formed by the metal layer 302 and the seed layer 301 covered by the metal layer 302.

[0065] After the seed layer 301 is removed, the processes subsequent to the formation of the bonding layer 420 (see FIGS. 17 to 23) are performed in the same manner as in the manufacturing method of the electronic device A10. Through the above steps, the electronic device A20 is manufactured.

[0066] In the electronic device A20, similar to the electronic device A10, the barrier metal 35 prevents the bonding layer 42 from spreading along the wiring layer 30, thereby preventing insufficient thickness of the bonding layer 42. In other words, similar to the electronic device A10, the electronic device A20 prevents a decrease in the bonding strength of the electronic components 19, thereby preventing a decrease in reliability. Furthermore, the electronic device A20 and its manufacturing method share the same configuration as the electronic device A10 and its manufacturing method, thereby achieving the same effects as the electronic device A10 and its manufacturing method. For example, similar to the manufacturing method of the electronic device A10, the manufacturing method of the electronic device A20 performs the barrier layer formation process and the plating layer formation process, thereby preventing voids from occurring in the bonding layer 42 and preventing defects in the bonding layer 42. In other words, the manufacturing method of this embodiment allows the manufacture of an electronic device A20 with reduced reliability. Furthermore, similar to the electronic device A10, the electronic device A20 has a configuration in which each electronic component 19 is bonded to the wiring layer 30 via the bonding layer 42 and the barrier metal 35 (barrier layer 350). That is, the electronic device A20 can suppress the occurrence of defects in the bonding layer 42 (voids being mixed into the bonding layer 42) and suppress a decrease in reliability.

[0067] In the electronic device A20, the wiring layer 30 includes a main body portion 311 and a pedestal portion 312. The barrier metal 35 protrudes outward beyond the pedestal portion 312 in a plan view. This configuration increases the step between the barrier metal 35 and the main body portion 311. This further reduces the contact area between the bonding layer 42 and the wiring layer 30 in the electronic device A20, thereby preventing a decrease in reliability.

[0068] In each of the electronic devices A10 and A20 according to the first and second embodiments, the sealing resin 6 may have steps on each resin side surface 63. For example, Fig. 31 shows an example of such a modified electronic device applied to the electronic device A10 according to the first embodiment. While Fig. 31 shows an example applied to the electronic device A10 according to the first embodiment, it can also be applied to the electronic device A20 according to the second embodiment.

[0069] In the electronic device shown in FIG. 31 , each resin side surface 63 has a first side portion 631 and a second side portion 632. In each resin side surface 63, the first side portion 631 and the second side portion 632 face the same direction. In a plan view, the first side portion 631 is disposed outward from the second side portion 632. The first side portion 631 is connected to the resin main surface 61, and the second side portion 632 is connected to a corresponding one of the multiple side surfaces 23. The second side portion 632 is flush with the connected side surface 23. With this configuration, each resin side surface 63 has a step. In the electronic device shown in FIG. 31 , the multiple terminals 5 include a terminal 5A in which the columnar portion 51 is exposed from the side surface 23. In the terminal 5A, the external electrode portion 52 covers the surface of the columnar portion 51 exposed from the rear surface 22 of the support member 2 and the surface exposed from the side surface 23 of the support member 2.

[0070] FIG. 32 shows a step in the manufacturing method of the electronic device shown in FIG. 31 . The manufacturing method of the electronic device shown in FIG. 31 is the same as the manufacturing method of the electronic device A10 described above up to the step of removing the support substrate 80. FIG. 32 shows the steps subsequent to the removal of the support substrate 80. In the manufacturing method according to this modification, after removing the support substrate 80, as shown in FIG. 32 , multiple grooves 869 are formed from the first resin layer 82 to the second resin layer 86. The multiple grooves 869 are formed, for example, by half-cutting using a dicing blade. By forming the multiple grooves 869, the support member 2 is divided into individual semiconductor elements 1, and the side surfaces of the support member 2 are exposed in the grooves 869. Next, external electrode portions 52 are formed by electroless plating on the surfaces of the columnar portions 51 exposed from the rear surface 22 and the surfaces exposed in the grooves 869. Thereafter, the second resin layer 86 is cut along the cutting lines CL shown in FIG. 32 to separate the electronic device. As shown in FIG. 32 , the cutting lines CL pass through the grooves 869. Cutting of second resin layer 86 is performed by cutting using a dicing blade, similar to electronic device A10, and the thickness of this dicing blade is thinner than the dicing blade used in forming (half-cutting) groove portion 869. Through the above steps, the electronic device shown in FIG.

[0071] The electronic device shown in Fig. 31 also achieves the same effects as the electronic device A10. Furthermore, in the electronic device shown in Fig. 31 , the external electrode portion 52 of the terminal 5A is also formed on the surface of the columnar portion 51 that is exposed from the side surface 23. With this configuration, when the electronic device shown in Fig. 31 is mounted on a wiring board of an electronic device or the like, a fillet can be formed in the conductive bonding material (e.g., solder) used during the mounting. Therefore, the electronic device shown in Fig. 31 can be easily visually inspected to determine whether it is properly joined to the wiring board of an electronic device or the like.

[0072] In the electronic device of the present disclosure, the number and arrangement of the semiconductor elements 1 and electronic components 19, the pattern of the wiring layer 30, and the number and arrangement of the terminals 5 are not limited to the examples shown in the drawings. For example, the electronic device of the present disclosure may have the configuration shown in FIGS. 33 and 34. Compared to the electronic device A10, the electronic devices shown in FIGS. 33 and 34 differ, for example, in the number and arrangement of the electronic components 19, the layout of the wiring layer 30, and the number and arrangement of the plurality of terminals 5. As can be seen from these variations, the planar layout of the electronic device of the present disclosure is not limited to the example shown in FIG. 2, and various modifications are possible.

[0073] The electronic device of the present disclosure is not limited to a configuration including a semiconductor element 1 as a functional element, but may include at least one electronic component 19. For example, the electronic device of the present disclosure may be a discrete device including one electronic component 19.

[0074] The electronic device and the method for manufacturing an electronic device according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the electronic device according to the present disclosure and the specific processing of each step of the method for manufacturing an electronic device according to the present disclosure can be freely designed and modified in various ways. For example, the present disclosure includes the embodiments described in the following appendices. Appendix 1. An electronic device comprising: a support member having a main surface facing one side in the thickness direction; a wiring layer formed on the main surface; a barrier metal formed on the wiring layer; a bonding layer formed on the barrier metal; and an electronic component bonded to the wiring layer via the bonding layer and the barrier metal and conducting to the wiring layer, wherein the barrier metal and the wiring layer contain different metals, and the barrier metal is smaller than the wiring layer in the thickness direction. Appendix 2. The electronic device according to Appendix 1, wherein the wiring layer protrudes outward beyond the barrier metal in the thickness direction. Appendix 3. The electronic device according to Supplementary Note 1 or Supplementary Note 2, wherein the wiring layer includes a main body portion and a pedestal portion protruding from the main body portion to one side in the thickness direction, and the barrier metal protrudes outward from the pedestal portion as viewed in the thickness direction. Supplementary Note 4. The electronic device according to any of Supplementary Note 1 to Supplementary Note 3, wherein the electronic component has a side surface facing an orthogonal direction perpendicular to the thickness direction and a side electrode formed on the side surface. Supplementary Note 5. The electronic device according to Supplementary Note 4, wherein the bonding layer includes a fillet portion in contact with the side electrode. Supplementary Note 6. The electronic device according to any of Supplementary Note 1 to Supplementary Note 5, wherein the barrier metal includes nickel, and the wiring layer includes copper. Supplementary Note 7. The electronic device according to any of Supplementary Note 1 to Supplementary Note 6, wherein the barrier metal includes nickel, and the wiring layer includes copper. Supplementary Note 8. The electronic device according to any of Supplementary Note 1 to Supplementary Note 6, wherein the wiring layer includes an intermediate portion interposed between the support member and the electronic component in the thickness direction, and an extending portion connected to the intermediate portion and disposed outward of the electronic component as viewed in the thickness direction. 8. The electronic device according to claim 1, further comprising a sealing resin that covers the electronic components.Appendix 9. A method for manufacturing an electronic device, comprising: a step of preparing a support member having a main surface facing one side in a thickness direction; a wiring layer forming step of forming a wiring layer on the main surface; a barrier layer forming step of forming a barrier layer on the wiring layer; a plating layer forming step of forming a plating layer on the barrier layer; a bonding layer forming step of forming a bonding layer on the plating layer; a mounting step of mounting an electronic component on the bonding layer; and a bonding step of bonding the electronic component by melting the bonding layer by reflowing and solidifying the molten bonding layer by cooling, wherein the plating layer contains tin and silver. Appendix 10. The method for manufacturing an electronic device according to Appendix 9, wherein the wiring layer includes a main body portion formed on the main surface and a pedestal portion protruding from the main body portion to one side in the thickness direction, and wherein the barrier layer forming step forms the barrier layer on the pedestal portion. Appendix 11. Appendix 12. The method for manufacturing an electronic device according to Appendix 11, further comprising an etching step after the plating layer forming step and before the bonding layer forming step, wherein the etching step removes the seed layer exposed from the metal layer. Appendix 13. The method for manufacturing an electronic device according to any one of Appendix 9 to Appendix 12, wherein the barrier layer and the wiring layer contain different metals. Appendix 14. The method for manufacturing an electronic device according to Appendix 13, wherein the barrier layer contains nickel, and the wiring layer contains copper. Appendix 15. Attachment 16. The method for manufacturing an electronic device according to any one of attachments 9 to 14, wherein in the barrier layer forming step, the barrier layer is formed to be smaller than the wiring layer as viewed in the thickness direction. Attachment 16. The method for manufacturing an electronic device according to any one of attachments 9 to 15, wherein in the bonding layer forming step, the bonding layer is formed by screen-printing a solder paste.Supplementary Note 17. The method for manufacturing an electronic device according to any one of Supplementary Note 9 to Supplementary Note 16, wherein the electronic component has side electrodes arranged on both ends in a direction perpendicular to the thickness direction, and a fillet that contacts the side electrodes is formed in the bonding layer by the bonding step. Supplementary Note 18. The method for manufacturing an electronic device according to any one of Supplementary Note 9 to Supplementary Note 17, further comprising a step of forming a sealing resin that covers the electronic component.

[0075] A10, A20: Electronic device 1: Semiconductor element 10a: Element main surface 10b: Element back surface 11: Main body portion 12: Pad 13: Insulating film 14: Rewiring 19: Electronic component 190a: Side surface 191: Terminal 191a: Lateral electrode 2: Support member 21: Main surface 22: Back surface 23: Side surface 30: Wiring layer 301: Seed layer 302: Metal layer 311: Main body portion 312: Pedestal portion 321: Interposition portion 322: Extension portion 35: Barrier metal 350: Barrier layer 351: Plating layer 41, 410: Bonding layer 42, 420: Bonding layer 421: Fillet portion 5: Terminal 5A: Terminal 51: Column portion 52: External electrode portion 6: Sealing resin 61: Resin main surface 62: Resin back surface 63: Resin side surface 631: First side portion 632: Second side portion 80: Support substrate 80a: Substrate main surface 80b: Substrate back surface 82: First resin layer 821: Main surface 822: Bottom surface 851: Columnar conductor 86: Second resin layer 861: Top surface 869: Groove portion 891, 892: Resist CL: Cutting line

Claims

1. a support member having a main surface facing in one direction in the thickness direction; a wiring layer formed on the main surface; a barrier metal formed on the wiring layer; a bonding layer formed on the barrier metal; an electronic component bonded to the wiring layer via the bonding layer and the barrier metal and electrically connected to the wiring layer; Equipped with the barrier metal and the wiring layer contain different metals, The barrier metal is smaller than the wiring layer in the thickness direction.

2. The electronic device according to claim 1 , wherein the wiring layer protrudes outward from the barrier metal beyond the barrier metal when viewed in the thickness direction.

3. the wiring layer includes a main body portion and a pedestal portion protruding from the main body portion to one side in the thickness direction, 3. The electronic device according to claim 1, wherein the barrier metal protrudes outward from the base portion beyond the base portion when viewed in the thickness direction.

4. 3. The electronic device according to claim 1, wherein the electronic component has a side surface facing a direction perpendicular to the thickness direction, and a side electrode formed on the side surface.

5. The electronic device according to claim 4 , wherein the bonding layer includes a fillet portion in contact with the side electrode.

6. the barrier metal includes nickel, 3. The electronic device according to claim 1, wherein the wiring layer contains copper.

7. 3. The electronic device according to claim 1, wherein the wiring layer includes an intervening portion interposed between the support member and the electronic component in the thickness direction, and an extending portion connected to the intervening portion and positioned outside the electronic component as viewed in the thickness direction.

8. The electronic device according to claim 1 , further comprising a sealing resin that covers the electronic components.

9. providing a support member having a main surface facing in one direction in a thickness direction; a wiring layer forming step of forming a wiring layer on the main surface; a barrier layer forming step of forming a barrier layer on the wiring layer; a plating layer forming step of forming a plating layer on the barrier layer; a bonding layer forming step of forming a bonding layer on the plating layer; a mounting step of mounting an electronic component on the bonding layer; a bonding step of melting the bonding layer by reflow and solidifying the melted bonding layer by cooling to bond the electronic component; and The method for manufacturing an electronic device, wherein the plating layer contains tin and silver.

10. the wiring layer includes a main body portion formed on the main surface and a pedestal portion protruding from the main body portion to one side in the thickness direction, The method for manufacturing an electronic device according to claim 9 , wherein in the barrier layer forming step, the barrier layer is formed on the pedestal portion.

11. the wiring layer forming step includes a first process of forming a seed layer on the main surface, a second process of forming a metal layer on a part of the seed layer by electrolytic plating using the seed layer as a conductive path, and a third process of forming the pedestal portion on a part of the metal layer, The method for manufacturing an electronic device according to claim 10 , wherein the main body portion has a laminated structure of the part of the seed layer and the metal layer.

12. Further, an etching step is performed after the plating layer forming step and before the bonding layer forming step, The method for manufacturing an electronic device according to claim 11 , wherein the etching step removes the seed layer exposed from the metal layer.

13. The method for manufacturing an electronic device according to claim 9 , wherein the barrier layer and the wiring layer contain different metals.

14. the barrier layer comprises nickel; The method for manufacturing an electronic device according to claim 13 , wherein the wiring layer contains copper.

15. 15. The method for manufacturing an electronic device according to claim 9, wherein in the barrier layer forming step, the barrier layer is formed to be smaller than the wiring layer when viewed in the thickness direction.

16. 15. The method for manufacturing an electronic device according to claim 9, wherein in the bonding layer forming step, the bonding layer is formed by screen printing a solder paste.

17. the electronic component has side electrodes disposed on both ends in an orthogonal direction orthogonal to the thickness direction, 15. The method for manufacturing an electronic device according to claim 9, wherein a fillet that contacts the side electrode is formed in the bonding layer by the bonding step.

18. 15. The method for manufacturing an electronic device according to claim 9, further comprising the step of forming a sealing resin to cover the electronic components.