Through-electrode substrate intermediate, through-electrode substrate, through-electrode substrate with element, and semiconductor device

Abstract

The present disclosure provides a through-electrode substrate intermediate including: a glass substrate having a first surface and a second surface facing the first surface and having through-holes; through-electrodes disposed in the through-holes of the glass substrate; an elastic insulating layer disposed on the first-surface side of the glass substrate; vias penetrating the elastic insulating layer and electrically connected to the through-electrodes; a via pad part that is disposed on a surface of the elastic insulating layer, the surface being opposite the glass substrate, and that is electrically connected to the vias; and a wiring board connection pad part that is disposed on the surface of the elastic insulation layer, the surface being opposite the glass substrate, and that is electrically connected to a wiring board. On the surface of the elastic insulating layer on which the via pad part and the wiring board connection pad part are disposed, the elastic insulating layer has a relief pattern including a plurality of protrusions and a plurality of recesses.

Description

Through-hole electrode substrate intermediate, through-hole electrode substrate, through-hole electrode substrate with element, and semiconductor device

[0001] The present disclosure relates to a through hole electrode substrate intermediate, a through hole electrode substrate, a through hole electrode substrate with an element, and a semiconductor device.

[0002] Conventionally, various techniques have been proposed for interposers that connect chips and motherboards having different terminal pitches (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-73684

[0004] It is known that a through-electrode substrate having through-electrodes is used as an interposer. Also, known types of interposers include silicon interposers, organic interposers, and glass interposers. Among these, organic interposers and glass interposers are attracting attention for their cost reduction.

[0005] However, the thermal expansion coefficient of the organic material, such as glass epoxy, used in the organic interposer is significantly different from that of the semiconductor material, such as silicon, used in the element. Therefore, when heating is performed in the manufacturing process of the semiconductor device or the semiconductor device is used in a high-temperature environment, the difference in the thermal expansion coefficient between the organic material and the semiconductor material causes stress in the joints, pads, and wiring that electrically connect the organic interposer and the element, which can easily cause cracks and disconnections.

[0006] On the other hand, in the case of a glass interposer, the difference between the thermal expansion coefficient of the glass substrate used in the glass interposer and the thermal expansion coefficient of the semiconductor material can be made small.

[0007] However, the thermal expansion coefficient of the glass substrate is significantly different from that of the glass epoxy substrate commonly used for motherboards. Therefore, when heating is performed during the manufacturing process of a semiconductor device or when the semiconductor device is used in a high-temperature environment, the difference in the thermal expansion coefficient between the glass substrate of the glass interposer and the glass epoxy substrate of the motherboard causes stress to be generated in the joints, pads, and wiring that electrically connect the glass interposer and the motherboard, making them more susceptible to cracks and disconnections.

[0008] The present disclosure is an invention made in view of the above circumstances, and has a main object to provide a through hole electrode substrate intermediate, a through hole electrode substrate, a through hole electrode substrate with an element, and a semiconductor device that can suppress disconnection.

[0009] One embodiment of the present disclosure provides a through electrode substrate intermediate comprising: a glass substrate having a first surface and a second surface opposite the first surface and having a through hole; a through electrode disposed in the through hole of the glass substrate; an elastic insulating layer disposed on the first surface side of the glass substrate; a via penetrating the elastic insulating layer and electrically connected to the through electrode; a via pad portion disposed on the surface of the elastic insulating layer opposite the glass substrate and electrically connected to the via; and a wiring board connection pad portion disposed on the surface of the elastic insulating layer opposite the glass substrate and electrically connected to a wiring board, wherein the elastic insulating layer has an uneven shape including a plurality of convex portions and a plurality of concave portions on the surface facing the via pad portion and the wiring board connection pad portion.

[0010] Another embodiment of the present disclosure provides a through electrode substrate having the above-mentioned through electrode substrate intermediate and a bellows wiring layer arranged on the surface of the through electrode substrate intermediate facing the elastic insulating layer, having a bellows-shaped portion with multiple peaks and multiple valleys, and electrically connecting the via pad portion and the wiring board connection pad portion.

[0011] Another embodiment of the present disclosure provides a through hole electrode substrate with an element, including the through hole electrode substrate described above and an element mounted on the through hole electrode substrate.

[0012] Another embodiment of the present disclosure provides a semiconductor device including the aforementioned element-equipped through hole electrode substrate and a wiring substrate electrically connected to the wiring substrate connection pads of the aforementioned through hole electrode substrate.

[0013] Another embodiment of the present disclosure provides a through electrode substrate having: a glass substrate having a first surface and a second surface opposite the first surface and having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a covering insulating layer disposed on the first surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate and having a second through hole connecting to the first through hole; a first via disposed in the second through hole of the covering insulating layer and electrically connected to the through electrode; an elastic insulating layer disposed on the surface of the covering insulating layer opposite the glass substrate and having a third through hole; a second via disposed in the third through hole of the elastic insulating layer and electrically connected to the first via; and a wiring board connection pad portion disposed on the surface of the elastic insulating layer opposite the covering insulating layer, electrically connected to the second via, and electrically connected to a wiring board.

[0014] Another embodiment of the present disclosure provides a through hole electrode substrate with an element, including the through hole electrode substrate described above and an element mounted on the through hole electrode substrate.

[0015] Another embodiment of the present disclosure provides a semiconductor device including the aforementioned element-equipped through hole electrode substrate and a wiring substrate electrically connected to the wiring substrate connection pads of the aforementioned through hole electrode substrate.

[0016] The present disclosure has the effect of suppressing disconnection.

[0017] FIG. 1 is a schematic plan view and a cross-sectional view illustrating a through electrode substrate intermediate in the first embodiment of the present disclosure. FIG. 2 is a schematic plan view and a cross-sectional view illustrating a through electrode substrate in the first embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a through electrode substrate with element in the first embodiment of the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device in the first embodiment of the present disclosure. FIG. 5 is a schematic plan view and a cross-sectional view illustrating a through electrode substrate intermediate in the first embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating a through electrode substrate with element in the first embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device in the first embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating an elastic insulating layer of a through electrode substrate intermediate in the first embodiment of the present disclosure. FIG. 9 is a schematic plan view illustrating a through electrode substrate intermediate in the first embodiment of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating a through hole in a glass substrate of a through electrode substrate intermediate in the present disclosure. FIG. 11 is a schematic cross-sectional view illustrating a gap and a bulge that occur in a through electrode substrate. FIG. 12 is a schematic cross-sectional view illustrating a through electrode substrate intermediate in the first embodiment of the present disclosure. FIG. 1 is a schematic cross-sectional view illustrating a glass substrate and a covering insulating layer of a through electrode substrate intermediate in a first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a through electrode substrate intermediate in a first embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a through electrode substrate intermediate in a first embodiment of the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating an elastic insulating layer and a bellows wiring layer of the through electrode substrate in a first embodiment of the present disclosure. FIG. 5 is a schematic plan view illustrating a through electrode substrate intermediate in a first embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating a through electrode substrate in a first embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating a through electrode substrate in a first embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating a through electrode substrate in a second embodiment of the present disclosure. FIG. 9 is a schematic cross-sectional view illustrating a through electrode substrate with an element in a second embodiment of the present disclosure. FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device in a second embodiment of the present disclosure. FIG. 11 is a schematic cross-sectional view illustrating a through electrode substrate in a second embodiment of the present disclosure.FIG. 1 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating an elastic insulating layer of a through electrode substrate according to the present disclosure. FIG. 4 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure. FIG. 5 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating a through electrode substrate according to a second embodiment of the present disclosure.

[0018] Embodiments of the present disclosure will be described below with reference to the drawings and the like. However, the present disclosure can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, to clarify the explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual form, but these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the preceding drawings will be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0019] In this specification, when describing an aspect in which another component is placed on a certain component, the term "above" or "below" refers to both a case in which another component is placed directly above or below the component so as to be in contact with the component, and a case in which another component is placed above or below the component with another component interposed therebetween, unless otherwise specified. Also, in this specification, when describing an aspect in which another component is placed on the surface of a certain component, the term "on the surface side" or "on the surface" refers to both a case in which another component is placed directly above or below the component so as to be in contact with the component, and a case in which another component is placed above or below the component with another component interposed therebetween, unless otherwise specified.

[0020] The present disclosure includes two embodiments, each of which will be described below.

[0021] I. First Embodiment First, a through hole electrode substrate intermediate, a through hole electrode substrate, a through hole electrode substrate with an element, and a semiconductor device in a first embodiment of the present disclosure will be described in detail.

[0022] A. Through-hole electrode substrate intermediate The through-hole electrode substrate intermediate in this embodiment has a first surface and a second surface opposite the first surface, and includes a glass substrate having a through hole, a through-hole electrode arranged in the through-hole of the glass substrate, an elastic insulating layer arranged on the first surface side of the glass substrate, a via penetrating the elastic insulating layer and electrically connected to the through-hole electrode, a via pad arranged on the surface of the elastic insulating layer opposite the glass substrate and electrically connected to the via, and a wiring substrate connection pad arranged on the surface of the elastic insulating layer opposite the glass substrate and electrically connected to a wiring substrate, wherein the elastic insulating layer has an uneven shape including a plurality of convex portions and a plurality of concave portions on the surface facing the via pad portion and the wiring substrate connection pad portion.

[0023] 1(a) and 1(b) are a schematic plan view and a cross-sectional view showing an example of a through-hole electrode substrate intermediate in this embodiment, and FIG. 1(b) is a cross-sectional view taken along line AA in FIG. 1(a). 1( a) and 1(b), the through electrode substrate intermediate 1 includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a and having a through hole 2c, a through electrode 3 disposed in the through hole 2c of the glass substrate 2, a first wiring layer 4 disposed on the first surface 2a of the glass substrate 2, electrically connected to the through electrode 3, and including a conductive layer 4a, an elastic insulating layer 5 disposed on the side of the first wiring layer 4 opposite the glass substrate 2, a via 6 penetrating the elastic insulating layer 5 and electrically connected to the first wiring layer 4, a via pad 7 disposed on the side of the elastic insulating layer 5 opposite the first wiring layer 4 and electrically connected to the via 6, and a wiring substrate connection pad 8 disposed on the side of the elastic insulating layer 5 opposite the first wiring layer 4 and electrically connected to the wiring substrate. The elastic insulating layer 5 has an uneven shape 9 including a plurality of protrusions 9a and a plurality of recesses 9b on the surface facing the via pad 7 and the wiring substrate connection pad 8.

[0024] 2(a) and 2(b) are a schematic plan view and a cross-sectional view showing an example of a through electrode substrate having a through electrode substrate intermediate in this embodiment, and FIG. 2(b) is a cross-sectional view taken along line A-A in FIG. 2(a). 2(a) and 2(b) are examples in which the through electrode substrate has the through electrode substrate intermediate shown in FIG. 1(a) and FIG. 1(b). As shown in FIG. 2(a) and FIG. 2(b), the through electrode substrate 20 has a through electrode substrate intermediate 1 and a bellows-shaped portion 21 having a plurality of peaks 21a and a plurality of valleys 21b, which is disposed on the surface of the through electrode substrate intermediate 1 facing the elastic insulating layer 5, and which electrically connects the via pad portion 7 and the wiring board connection pad portion 8.

[0025]

[0033] Figure 3 is a schematic cross-sectional view showing an example of an element-equipped through electrode substrate having a through electrode substrate intermediate in this embodiment. Figure 3 shows an example in which the element-equipped through electrode substrate has the through electrode substrate intermediate shown in Figures 1(a) and 1(b). As shown in Figure 3, the element-equipped through electrode substrate 30 has a through electrode substrate 20, a first bonding portion 31 electrically connected to the element connection pad portion 11 of the through electrode substrate 20, and an element 32 electrically connected to the first bonding portion 31.

[0026] 4 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate intermediate in this embodiment. Fig. 4 shows an example of a semiconductor device having the through electrode substrate intermediate shown in Fig. 1(a) and Fig. 1(b). As shown in Fig. 4, a semiconductor device 40 has a through electrode substrate 20, a first bonding portion 31 electrically connected to the element connection pad portion 11 of the through electrode substrate 20, an element 32 electrically connected to the first bonding portion 31, a second bonding portion 41 electrically connected to the wiring substrate connection pad 8 of the through electrode substrate 20, and a wiring substrate 42 electrically connected to the second bonding portion 41.

[0027] For example, if the first joint is a solder joint, and the through-hole electrode substrate and the element are joined via the solder joint during a reflow process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the element expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the first joint and the element connection pad, making cracks and disconnections more likely. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the first joint and the element connection pad, making cracks and disconnections more likely.

[0028] In contrast, in this embodiment, the through electrode substrate has a glass substrate and is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate and the semiconductor material, thereby suppressing stress from occurring in the first bonding portion and the element connection pad portion. This in turn prevents cracks and breaks in the first bonding portion and the element connection pad portion.

[0029] Furthermore, for example, when the second joint portion is a solder joint portion and the through-hole electrode substrate and the wiring substrate are joined via the solder joint portion during a reflow process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, disconnection between the through-hole electrode substrate and the wiring substrate is likely to occur. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the second joint portion and the wiring substrate connection pad portion, making cracks and disconnection more likely to occur.

[0030] In contrast, in this embodiment, the elastic insulating layer is elastic and has an uneven shape on the surface facing the via pad portion and the wiring board connection pad portion, so that the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion is stretchable. Furthermore, as the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion stretches and contracts, the via deforms obliquely. In this way, the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion stretches and contracts, causing the via to deform obliquely, thereby alleviating stress caused by the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring board. Therefore, cracks and breaks in the second joint portion and the wiring board connection pad portion can be suppressed.

[0031] Furthermore, in this embodiment, since the elastic insulating layer has an uneven surface, the bellows wiring layer disposed on the surface of the elastic insulating layer has an bellows-shaped portion that conforms to the uneven surface of the elastic insulating layer. Furthermore, since the bellows-shaped portion is provided, the bellows wiring layer has flexibility. The flexibility of the bellows wiring layer further reduces stress caused by the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate. Therefore, cracks and breaks in the second joint portion and the wiring substrate connection pad portion can be effectively suppressed.

[0032] 5(a) and 5(b) are schematic plan views and cross-sectional views showing another example of a through electrode substrate intermediate in this embodiment, and Fig. 5(b) is a cross-sectional view taken along line A-A in Fig. 5(a). As shown in Fig. 5(a) and 5(b), the through electrode substrate intermediate 1 includes a glass substrate 2 having a first surface 2a and a second surface 2b opposite the first surface 2a, and having a through hole 2c, a through electrode 3 disposed in the through hole 2c of the glass substrate 2, an elastic insulating layer 5 disposed on the first surface 2a side of the glass substrate 2, a via 6 penetrating the elastic insulating layer 5 and electrically connected to the through electrode 3, a via pad portion 7 disposed on the surface of the elastic insulating layer 5 opposite the glass substrate 2 and electrically connected to the via 6, and a wiring substrate connection pad portion 8 disposed on the surface of the elastic insulating layer 5 opposite the glass substrate 2 and electrically connected to the wiring substrate. The elastic insulating layer 5 has an uneven shape 9 including a plurality of convex portions 9a and a plurality of concave portions 9b on the surface facing the via pad portion 7 and the wiring board connection pad portion 8. The size of the surface of the elastic insulating layer 5 facing the glass substrate 2 toward the via 6 in a plan view is smaller than the size of the surface of the through electrode 3 facing the first surface 2a of the glass substrate 2 in a plan view, and the elastic insulating layer 5 is arranged so as to cover the boundary α between the through electrode 3 and the glass substrate 2. The through electrode substrate intermediate 1 shown in Figures 5(a) and 5(b) differs from the through electrode substrate intermediate 1 shown in Figures 1(a) and 1(b) above in that it is arranged on the first surface 2a of the glass substrate 2, is electrically connected to the through electrode 3 and the via pad portion 7, and does not have the first wiring layer 4 including the conductive layer 4a.

[0033] Figures 6(a) and 6(b) are a schematic plan view and a cross-sectional view showing another example of a through electrode substrate having a through electrode substrate intermediate in this embodiment, and Figure 6(b) is a cross-sectional view taken along line A-A in Figure 6(a). Figures 6(a) and 6(b) are examples in which the through electrode substrate has the through electrode substrate intermediate shown in Figures 5(a) and 5(b). In Figures 6(a) and 6(b), apart from the through electrode substrate intermediate, the structure is the same as the example shown in Figures 2(a) and 2(b).

[0034] Fig. 7 is a schematic cross-sectional view showing another example of an element-attached through-hole electrode substrate having a through-hole electrode substrate intermediate in this embodiment. Fig. 7 shows an example in which the element-attached through-hole electrode substrate has the through-hole electrode substrate intermediate shown in Fig. 5(a) and Fig. 5(b). In Fig. 7, apart from the through-hole electrode substrate intermediate, the example shown in Fig. 3 is the same as that shown in Fig. 3.

[0035] Fig. 8 is a schematic cross-sectional view showing another example of a semiconductor device having a through electrode substrate intermediate in this embodiment. Fig. 8 is an example in which the semiconductor device has the through electrode substrate intermediate shown in Fig. 5(a) and Fig. 5(b). In Fig. 8, other than the through electrode substrate intermediate, the example shown in Fig. 4 is the same as that shown in Fig.

[0036] In this embodiment, the through electrode substrate intermediate shown in FIGS. 5(a) and 5(b) also provides the same effects as the through electrode substrate intermediate shown in FIGS. 1(a) and 1(b).

[0037] Therefore, in this embodiment, the connection reliability can be improved.

[0038] Hereinafter, the through-hole electrode substrate intermediate in this embodiment will be described for each component.

[0039] 1. Elastic Insulating Layer The elastic insulating layer in this embodiment is disposed on the first surface side of the glass substrate, and has an uneven shape including a plurality of protrusions and a plurality of recesses on the surface facing the via pad portion and the wiring board connection pad portion.

[0040] (1) Uneven Shape The elastic insulating layer has an uneven shape including a plurality of convex portions and a plurality of concave portions on the surface on the via pad portion and wiring board connection pad portion side.

[0041] In the uneven shape, the difference in height between adjacent convex and concave portions is preferably smaller than the thickness of the elastic insulating layer in a semiconductor device having a through-hole electrode substrate intermediate of this embodiment. The difference in height is, for example, 50 μm or less, or may be 15 μm or less, or 10 μm or less. If the difference in height is too large, the bellows wiring layer disposed on the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion may come into contact with the wiring board. On the other hand, the difference in height is, for example, 1 μm or more, or may be 3 μm or more, or may be 5 μm or more. If the difference in height is too small, the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion may be less likely to expand or contract. Specifically, the difference in height is 1 μm or more to 50 μm or less, or may be 3 μm or more to 15 μm or less, or may be 5 μm or more to 10 μm or less. The height difference between adjacent convex and concave portions is indicated by the symbol H1 as shown in FIG. 9, for example, and is the distance between adjacent convex and concave portions in the normal direction of the first surface of the glass substrate.

[0042] The height difference between adjacent convex and concave portions is measured based on an image of the cross section of the through hole electrode substrate intermediate taken with a scanning electron microscope (SEM). The height difference between adjacent convex and concave portions is the arithmetic mean value of the height differences at any 10 points.

[0043] In the concave-convex shape, the spacing between adjacent convex portions is, for example, 2 μm or more, 5 μm or more, or 6 μm or more. On the other hand, the spacing between adjacent convex portions is, for example, 20 μm or less, 10 μm or less, or 9 μm or less. The spacing is preferably larger within the above range. The larger spacing can reduce the stress amplitude in the bellows wiring layer disposed on the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion. Therefore, when the bellows wiring layer is subjected to repeated thermal stress, breakage is suppressed and connection reliability is improved. Specifically, the spacing is 2 μm or more and 20 μm or less, 5 μm or more and 10 μm or less, or 6 μm or more and 9 μm or less. The spacing between adjacent convex portions is indicated by the symbol P1, as shown in FIG. 9 , for example.

[0044] The distance between adjacent protrusions is measured based on an image of the cross section of the through hole electrode substrate intermediate taken with a scanning electron microscope (SEM). The distance between adjacent protrusions is the arithmetic mean value of the distances at any 10 positions.

[0045] In the uneven shape, the convex portions and concave portions may be arranged regularly or irregularly.

[0046] The cross-sectional shape of the convex portion is preferably such that the top of the convex portion is rounded, e.g., semicircular or semi-elliptical. The cross-sectional shape of the concave portion is preferably such that the bottom of the concave portion is rounded, e.g., semicircular or semi-elliptical. Such a shape can prevent breakage of the bellows wiring layer disposed on the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion.

[0047] On the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion, the uneven shape may be at least arranged in the region where the bellows wiring layer is arranged. For example, on the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion, the uneven shape may be arranged over the entire surface, or may be arranged partially. For example, in FIG. 1B, the uneven shape 9 is arranged in the region where the bellows wiring layer is arranged. For example, in FIG. 10, the uneven shape 9 is arranged not only in the region where the bellows wiring layer is arranged, but also in the region between the wiring board connection pad 8 corresponding to the via pad 7 electrically connected to one of the adjacent through electrodes 3 and the via pad 7b electrically connected to the other through electrode 3. Also, in FIG. 10, the uneven shape 9 is arranged in the region other than the via pad portion 7 and the wiring board connection pad portion 8. Furthermore, although not shown, when a concave-convex shape is arranged over the entire surface of the elastic insulating layer on the side of the via pads and wiring board connection pads, the bellows wiring layer may also serve as the via pads and wiring board connection pads, as will be described later. In this case, the concave-convex shape is also arranged in the areas of the via pads and wiring board connection pads on the side of the elastic insulating layer on the side of the via pads and wiring board connection pads.

[0048] (2) Physical Properties of the Elastic Insulating Layer The elastic modulus of the elastic insulating layer, as measured by nanoindentation, is preferably, for example, 5 GPa or less, more preferably 1 GPa or less. If the elastic modulus is within the above range, stress due to the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate can be alleviated. On the other hand, the elastic modulus is, for example, 0.01 GPa or more, and may be 0.05 GPa or more. Specifically, the elastic modulus is preferably 0.01 GPa or more and 5 GPa or less, more preferably 0.05 GPa or more and 1 GPa or less.

[0049] The modulus of elasticity is measured by nanoindentation at 25°C in accordance with ISO 14577. For example, a HYSITRON "TI950 TriboIndenter" is used as the device. A Berkovich indenter is used as the indenter. The surface of the elastic insulating layer onto which the Berkovich indenter is pressed is the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion. The measurement conditions are a maximum indentation depth of 100 nm, a loading time of 5 seconds, a holding time of 5 seconds, and an unloading time of 5 seconds. Measurements are performed at five random locations, and the arithmetic average value is used as the modulus of elasticity.

[0050] Furthermore, the elastic insulating layer preferably exhibits a thermal weight change rate of, for example, 3% or less when heated for 1 hour at 260° C. If the thermal weight change rate is within the above range, sufficient heat resistance can be obtained.

[0051] The rate of change in thermogravimetry is measured by thermogravimetry (TGA). The measurement conditions are as follows. A "TGA550" manufactured by TA Instruments is used as the thermogravimetry measuring device. <Measurement conditions> Atmosphere: Nitrogen atmosphere Heating rate: 10°C / min Holding time: 1 hour

[0052] (3) Material for Elastic Insulation Layer Examples of materials for the elastic insulation layer include elastomers. Examples of elastomers include styrene-based elastomers, olefin-based elastomers, urethane-based elastomers, amide-based elastomers, nitrile-based elastomers, vinyl chloride-based elastomers, ester-based elastomers, 1,2-polybutadiene-based elastomers, fluorine-based elastomers, silicone rubber, urethane rubber, fluorine-containing rubber, polybutadiene, polyisobutylene, polystyrene butadiene, and polychloroprene. The material for the elastic insulation layer may also be photosensitive.

[0053] (4) Shape of Elastic Insulating Layer In this embodiment, as shown in Fig. 5(b), for example, the elastic insulating layer 5 is disposed so as to cover at least the boundary α between the through electrode 3 and the glass substrate 2, and may also serve as a covering insulating layer, which will be described later. The covering insulating layer will be described later.

[0054] The thickness of the elastic insulating layer is, for example, 5 μm or more, or may be 15 μm or more, or may be 50 μm or more. If the thickness of the elastic insulating layer is within the above range, the surfaces of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion are more likely to expand and contract. On the other hand, the thickness of the elastic insulating layer is, for example, 200 μm or less, or may be 100 μm or less, or may be 60 μm or less. If the thickness of the elastic insulating layer is too thick, the thickness of the entire through-hole electrode substrate intermediate may become thick. Specifically, the thickness of the elastic insulating layer is 5 μm or more and 200 μm or less, or may be 15 μm or more and 100 μm or less, or may be 50 μm or more and 60 μm or less.

[0055] In this specification, the thickness of each layer is measured based on an image of the cross section of the through hole electrode substrate intermediate taken with a scanning electron microscope (SEM). The thickness is the arithmetic average of thicknesses at any five points.

[0056] (5) Method for Forming Elastic Insulating Layer The elastic insulating layer can be formed by applying the above-mentioned material. In addition, as a method for forming the concave and convex shape, for example, shaping using a mold can be mentioned.

[0057] 2. Vias The vias in this embodiment penetrate the elastic insulating layer and are electrically connected to the through electrodes.

[0058] The material for the vias is not particularly limited as long as it is a conductive material, and conductive materials used for general vias can be used, and is selected appropriately depending on the shape of the vias, the formation method, etc.

[0059] A common via formation method can be used, and is appropriately selected depending on the shape of the via. In the via formation method, first, a through hole is formed in the elastic insulating layer, and then a via is formed in the through hole in the elastic insulating layer. Examples of methods for forming a through hole in the elastic insulating layer include laser processing, photolithography, and shaping using a mold. In the case of shaping using a mold, a concave-convex shape may be formed on the surface of the elastic insulating layer by shaping using the mold, and at the same time, a through hole may be formed in the elastic insulating layer by shaping using the mold. Examples of methods for forming a via in a through hole in the elastic insulating layer include, for example, PVD methods such as vacuum deposition and sputtering, CVD methods, and plating methods. A via may be formed by filling a conductive material in the through hole in the elastic insulating layer, and at the same time, a via pad may be formed from the conductive material. In the case of plating, first, a through hole is formed in the elastic insulating layer, and then a seed layer is formed on the entire surface of the elastic insulating layer by sputtering or the like, then a photoresist layer is formed on the seed layer, and then the photoresist layer is patterned to have openings for via pads, and then electroplating is performed on the openings in the photoresist layer to form plating layers, thereby simultaneously forming the vias and via pads. In this case, the vias and via pads have the seed layer and plating layers.

[0060] 3. Via Pad Portion The via pad portion in this embodiment is disposed on the surface of the elastic insulating layer opposite to the glass substrate, and is electrically connected to the via.

[0061] The material of the via pad portion is not particularly limited as long as it is a conductive material, and conductive materials used for general wiring can be used. Examples of conductive materials that can be used include metals such as copper, molybdenum, titanium, tungsten, tantalum, aluminum, gold, silver, nickel, and palladium, alloys containing at least one selected from these metals, and metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). Among these, copper is preferably used.

[0062] The shape of the via pad portion in plan view is not particularly limited, and examples thereof include a circle, an ellipse, a square, and a rectangle.

[0063] The thickness of the via pad portion is the same as that of a general wiring. The thickness of the via pad portion is, for example, 0.05 μm to 100 μm, or may be 0.1 μm to 50 μm, or may be 0.2 μm to 10 μm. This allows sufficient conductivity to be obtained.

[0064] The via pad can be formed by a general wiring forming method, for example, by forming a conductive film by a dry film forming method such as a PVD method such as a CVD method or a sputtering method, or by a plating method, and then patterning the conductive film by a photolithography method. Also, as described above, the via and the via pad may be formed simultaneously.

[0065] 4. Wiring Board Connection Pads The wiring board connection pads in this embodiment are arranged on the surface of the elastic insulating layer opposite to the glass substrate, and are electrically connected to the wiring board.

[0066] The material, shape in plan view, thickness, and forming method of the wiring board connection pad portion are the same as the material, shape in plan view, thickness, and forming method of the above-mentioned via pad portion.

[0067] The via pads and the wiring substrate connection pads are electrically connected by the bellows wiring layer. Therefore, the via pads and the wiring substrate connection pads are arranged close to each other. In this case, the distance from the via pads to the wiring substrate connection pads is appropriately set depending on the size of the through-hole electrode substrate intermediate, but may be, for example, 50 μm or more, or 200 μm or more. If the distance is too short, the length of the bellows wiring layer tends to be short, making the bellows wiring layer less flexible and more susceptible to breakage. If the distance is within the above range, the length of the bellows wiring layer can be ensured and the stress amplitude can be reduced. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, breakage is suppressed and connection reliability can be maintained. On the other hand, the distance is, for example, 1000 μm or less, or may be 500 μm or less, or may be 300 μm or less. If the distance is too long, the length of the bellows wiring layer tends to be long, which may result in deterioration of electrical characteristics. Specifically, the distance is 50 μm or more and 1000 μm or less, or may be 100 μm or more and 500 μm or less, or may be 200 μm or more and 300 μm or less. The distance from the via pad portion to the wiring board connection pad portion refers to the distance from the center of the via pad portion to the center of the wiring board connection pad portion.

[0068] As described above, when the elastic insulating layer has an uneven surface on the surface facing the via pad portion and the wiring board connection pad portion, and when the bellows wiring layer also serves as the via pad portion and the wiring board connection pad portion, as described below, it is difficult to define the via pad portion and the wiring board connection pad portion. In such a case, in a semiconductor device having a through electrode substrate intermediate, it is sufficient that the distance from the via penetrating the elastic insulating layer of the through electrode substrate intermediate to the first joint portion is within the above range. The distance from the via to the first joint portion refers to the distance from the center of the via to the center of the first joint portion.

[0069] The via pads 7 and the wiring substrate connection pads 8 are preferably arranged radially in a plan view, as shown in, for example, FIGS. 1( a) and 11 . This facilitates alleviation of stress due to the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate. In this case, as shown in FIG. 1( a), the via pads 7 and the wiring substrate connection pads 8 may be arranged radially so that the via pads 7 are on the outside and the wiring substrate connection pads 8 are on the inside. Alternatively, as shown in FIG. 11, the via pads 7 and the wiring substrate connection pads 8 may be arranged radially so that the via pads 7 are on the inside and the wiring substrate connection pads 8 are on the outside.

[0070] In particular, as shown in FIG. 11 , it is preferable that the via pads 7 and the wiring substrate connection pads 8 are radially arranged so that the via pads 7 are on the inside and the wiring substrate connection pads 8 are on the outside. When the wiring substrate connection pads are arranged outside the via pads, in a semiconductor device having a through electrode substrate intermediate, the second joints that electrically connect the through electrode substrate and the wiring substrate and support the through electrode substrate are arranged on the outside. Therefore, the through electrode substrate and the wiring substrate are horizontally stabilized. This allows for a stable soldering process. Furthermore, when the wiring substrate connection pads are arranged outside the via pads, compressive stress acts on the bellows wiring layer due to the stress caused by the difference in thermal expansion coefficients between the through electrode substrate and the wiring substrate. On the other hand, when the wiring substrate connection pads are arranged inside the via pads, tensile stress acts on the bellows wiring layer due to the stress caused by the difference in thermal expansion coefficients between the through electrode substrate and the wiring substrate. In the case of compressive stress, the bellows wiring layer is less susceptible to breakage than in the case of tensile stress. Therefore, it is preferable that the wiring board connection pads are disposed outside the via pads.

[0071] Furthermore, it is preferable that the wiring substrate connection pads are regularly arranged in a plan view, which makes the thermal history of the second joint that electrically connects the through hole electrode substrate and the wiring substrate uniform during the manufacturing process of the semiconductor device using the through hole electrode substrate intermediate, thereby improving the yield.

[0072] 5. Glass Substrate The glass substrate in this embodiment has a first surface and a second surface opposite to the first surface, and has a through-hole penetrating through the substrate in the thickness direction.

[0073] Glass substrates have excellent flatness, allowing for the formation of fine wiring at narrow pitches. In addition, the thermal expansion coefficient of glass substrates can be adjusted by changing the composition, allowing for the selection of glass substrates with a desirable thermal expansion coefficient.

[0074] Examples of glass used for the glass substrate include alkali-free glass and quartz.

[0075] The thermal expansion coefficient of the glass substrate is preferably, for example, 2 ppm / ° C. to 9 ppm / ° C. If the thermal expansion coefficient of the glass substrate is within the above range, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the element can be sufficiently reduced.

[0076] In this specification, the thermal expansion coefficient refers to a linear expansion coefficient, which is measured by thermomechanical analysis (TMA) in accordance with JIS R3102:1995.

[0077] The shape of the glass substrate in plan view is not particularly limited, but examples thereof include rectangular shapes such as a rectangle and a square.

[0078] The planar shape of the through hole in the glass substrate is, for example, approximately circular. Furthermore, the cross-sectional shape of the through hole 2c in the glass substrate 2 can be, for example, a straight shape as shown in FIG. 1(b), an inverted tapered shape as shown in FIG. 12(a) in which the opening diameter on the first surface 2a side is larger than the opening diameter on the second surface 2b side, a forward tapered shape as shown in FIG. 12(b) in which the opening diameter on the first surface 2a side is smaller than the opening diameter on the second surface 2b side, an hourglass shape including a portion where the diameter is minimum at a predetermined position between the first surface 2a and the second surface 2b as shown in FIG. 12(c), or a bowing shape where the diameter is maximum at a predetermined position between the first surface 2a and the second surface 2b as shown in FIG. 12(d). FIGS. 12(a) to 12(d) are schematic cross-sectional views illustrating examples of the cross-sectional shape of the through hole in the glass substrate. As will be described later, when a coating insulating layer is disposed on the first surface side of the glass substrate, the cross-sectional shape of the through hole in the glass substrate is preferably either an inverted tapered shape or an hourglass shape. In addition, in each cross-sectional shape of the through hole in the glass substrate, an edge E1 of the opening of the through hole 2c on the first surface 2a of the glass substrate 2, an edge E2 of the opening of the through hole 2c on the second surface 2b of the glass substrate 2, and a minimum and maximum diameter portion of the through hole 2c in the glass substrate 2 are preferably curved surfaces having a curvature, which can suppress disconnection between the through electrode and the via or conductive layer in contact with the through electrode.

[0079] The thickness of the glass substrate is, for example, 100 μm or more, or may be 200 μm or more, 300 μm or more, or 400 μm or more. Having a glass substrate thickness within the above range can prevent the glass substrate from warping too much. This can prevent the glass substrate from becoming difficult to handle during the manufacturing process, or from warping due to internal stress of a thin film or the like disposed on the first or second surface of the glass substrate. Meanwhile, the thickness of the glass substrate is, for example, 2000 μm or less, or may be 1000 μm or less, or 800 μm or less. When the thickness of the glass substrate is within the above range, the time required for the process of forming a through hole in the glass substrate can be shortened.

[0080] 6. Through Electrode The through electrode in this embodiment is disposed in the through hole of the glass substrate.

[0081] The through electrode may be of any form as long as it can electrically connect the first and second surfaces of the glass substrate. The form of the through electrode may be, for example, a through electrode that fills a through hole in the glass substrate, a so-called filled via, or a through electrode that is disposed only on the side wall of the through hole in the glass substrate, a so-called conformal via. Furthermore, when the through electrode is a conformal via, a hollow portion may be disposed within the through hole, and the through hole may be filled with a resin portion.

[0082] When the through electrode is a conformal via and a hollow portion is disposed within the through hole, the through electrode can be formed integrally with the conductive layer constituting the first wiring layer or the conductive layer constituting the second wiring layer described below.

[0083] The material of the through electrode is not particularly limited as long as it is a conductive material, and conductive materials commonly used for through electrodes can be used, and the material is appropriately selected depending on the shape of the through electrode, the method of formation, etc. Examples of materials for the through electrode include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, and alloys containing these metals.

[0084] The through electrode may be a single layer or a multilayer structure having multiple layers stacked together. For example, the through electrode may have a seed layer disposed on the sidewall of the through hole in the glass substrate and a plating layer disposed on the surface of the seed layer opposite the sidewall of the through hole. The material of the seed layer can be appropriately selected from materials used for seed layers in general plating methods. The material of the seed layer is preferably a conductive material that has adhesion to the glass substrate, such as titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, compounds thereof, and alloys thereof. When the plating layer contains copper, the material of the seed layer is preferably a material that can suppress the diffusion of copper into the glass substrate, such as titanium nitride, molybdenum nitride, and tantalum nitride. The material of the plating layer is preferably a conductive material that has adhesion to the seed layer, such as the materials of the through electrode described above.

[0085] Furthermore, in the through electrode, it is preferable that an adhesion layer is disposed on the side wall of the through hole in the glass substrate. The adhesion layer improves adhesion between the glass substrate and the through electrode. The adhesion layer has high adhesion to the glass substrate. Furthermore, the adhesion layer may have the role of suppressing diffusion of metal elements in the through electrode into the interior of the glass substrate via the side wall of the through hole. When the through electrode has an adhesion layer, the through electrode may have, in this order from the side wall side of the through hole in the glass substrate, an adhesion layer, a seed layer, and a plating layer.

[0086] When the conductive material constituting the through electrode is copper, examples of the material for the adhesion layer include titanium, titanium oxide, titanium nitride, molybdenum, molybdenum nitride, tantalum, and tantalum nitride. The adhesion layer may be a single layer or a multilayer. In particular, it is preferable that the adhesion layer contains titanium oxide as a main component.

[0087] Furthermore, when the through electrode is a conformal via and the through hole is filled with a resin portion, examples of the material for the resin portion include epoxy resin, acrylic resin, polyimide, polyamide, polyester, etc.

[0088] As a method for forming the through electrode, a general method for forming a through electrode can be used, and is appropriately selected depending on the shape of the through electrode, etc. Examples of the method for forming the through electrode include PVD methods such as vacuum deposition and sputtering, CVD methods, and plating methods.

[0089] 7. Covering Insulating Layer and Second Via The through electrode substrate intermediate in this embodiment preferably includes a covering insulating layer disposed between the glass substrate and the elastic insulating layer so as to cover at least the boundary between the through electrode and the glass substrate, and having a second through hole connecting to the through hole, and a second via disposed in the second through hole of the covering insulating layer, electrically connected to the through electrode, and electrically connected to the via pad portion.

[0090] In the manufacture of a semiconductor device in which a through-hole electrode substrate is interposed between an element and a motherboard, heat treatments such as annealing and reflow soldering are performed. FIGS. 13( a) and 13(b) are schematic diagrams illustrating the state of the through-hole electrode substrate during heat treatment in the manufacturing process of the semiconductor device. In a through-hole electrode substrate having through-holes 3 filled in through-holes 2c as shown in FIG. 13(a), a gap G may occur between the glass substrate 2 and the through-hole electrode 3 during heat treatment due to the difference in thermal expansion between the glass substrate 2 and the through-hole electrode 3, as shown in FIG. 13(b). Furthermore, during heat treatment, the through-hole electrode 3 may bulge relative to the main surface of the glass substrate 2 due to the difference in thermal expansion between the glass substrate 2 and the through-hole electrode 3, as shown in FIG. 13(b). Furthermore, during heat treatment, gas components such as moisture and hydrogen remaining in the material constituting the through-hole electrode 3 may be released, causing the through-hole electrode 3 to be pushed up. Such gaps or bulges may cause disconnections in the conductive layer or pad portion located near the boundary between the through-hole electrode and the glass substrate. Furthermore, the wiring connected to the pad may break.

[0091] 14, the through electrode substrate intermediate 1 has a covering insulating layer 15 disposed between the glass substrate 2 and the elastic insulating layer 5 so as to cover at least the boundary α between the through electrode 3 and the glass substrate 2, and having a second through hole 15c connected to the through hole 3, and a second via 16 disposed in the second through hole 15c of the covering insulating layer 15 and electrically connected to the through electrode 3 and to the via pad portion 7. In Fig. 14, the first wiring layer 4 is disposed between the covering insulating layer 15 and the elastic insulating layer 5, and the second via 16 is electrically connected to the via 6 and the via pad portion 7 via the conductive layer 4a and the fourth via 4c of the first wiring layer 4.

[0092] As will be described later, a resin is used for the covering insulating layer 15. As shown in FIG. 14 , when the covering insulating layer 15 is arranged to cover the boundary α between the glass substrate 2 and the through electrode 3, a portion of the covering insulating layer 15 contacts a portion of the through electrode 3. Therefore, even if gas is released from inside the through electrode 3 during heat treatment, the gas can be released to the outside through the covering insulating layer 15. This prevents the conductive layer 4 a of the first wiring layer 4, which is arranged near the boundary α, from swelling. Furthermore, because the covering insulating layer 15 is arranged to cover the boundary α between the glass substrate 2 and the through electrode 3, even if a gap occurs between the through electrode 3 and the glass substrate 2 during heat treatment, the gap between the through electrode 3 and the glass substrate 2 can be covered by the covering insulating layer 15, preventing disconnection of the conductive layer 4 a of the first wiring layer 4 located on the boundary α. Furthermore, even if a step occurs between the through electrode 3 and the glass substrate 2 due to a gap or swelling during heat treatment, the covering insulating layer 15 can absorb the step between the through electrode 3 and the glass substrate 2, thereby preventing a sudden step from occurring in the conductive layer 4a of the first wiring layer 4 located near the boundary α.

[0093] 5, the elastic insulating layer 5 also serves as a covering insulating layer, and is disposed so as to cover at least the boundary α between the through electrode 3 and the glass substrate 2. The via 6 also serves as a second via.

[0094] As described above, the elastic insulating layer is made of an elastomer. As shown in FIG. 5 , when the elastic insulating layer 5, which also serves as a covering insulating layer, is arranged to cover the boundary α between the glass substrate 2 and the through electrode 3, a portion of the elastic insulating layer 5 contacts a portion of the through electrode 3. Therefore, even if gas is released from inside the through electrode 3 during heat treatment, the gas can be released to the outside through the elastic insulating layer 5. This prevents bulging of the via pad 7 located near the boundary α. Furthermore, because the elastic insulating layer 5 is arranged to cover the boundary α between the glass substrate 2 and the through electrode 3, even if a gap occurs between the through electrode 3 and the glass substrate 2 during heat treatment, the gap between the through electrode 3 and the glass substrate 2 can be covered by the elastic insulating layer 5, preventing disconnection of the via pad 7 located on the boundary α. Furthermore, even if a step occurs between the through electrode 3 and the glass substrate 2 due to a gap or swelling during heat treatment, the elastic insulating layer 5 can absorb the step between the through electrode 3 and the glass substrate 2, thereby preventing a sudden step from occurring in the via pad portion 7 arranged near the boundary α. Furthermore, it is also possible to prevent disconnection of the bellows wiring layer connected to the via pad portion.

[0095] In this way, the covering insulating layer is arranged so as to cover the boundary between the glass substrate and the through electrode, thereby preventing disconnection of the conductive layer and pad portion arranged near the boundary between the through electrode and the glass substrate, thereby increasing yield and improving reliability.

[0096] The covering insulating layer is preferably in direct contact with the glass substrate. The covering insulating layer has a second through hole that penetrates the covering insulating layer in the thickness direction and connects to the through hole of the glass substrate.

[0097] The material of the insulating coating layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0098] The method for forming the second through holes is appropriately selected depending on the material of the covering insulating layer, and examples thereof include photolithography and laser processing. In the case of photolithography, the material of the covering insulating layer may be a photosensitive material, and a resist pattern may be formed on the covering insulating layer.

[0099] 15(a) to 15(c) are schematic cross-sectional views illustrating the arrangement of the through holes of the glass substrate and the covering insulating layer in a through electrode substrate intermediate. In FIGS. 15(a) to 15(c), components other than the glass substrate and the covering insulating layer are omitted. As shown in FIG. 15(a), the second through hole 15c in the covering insulating layer 15 is connected to the through hole 2c in the glass substrate 2. It is preferable that the central axis C1 of the through hole 2c in the glass substrate 2 substantially coincides with the central axis C2 of the second through hole 15c in the covering insulating layer 15.

[0100] Furthermore, the opening diameter d2 of the second through hole 15c in the coating insulating layer 15 on the glass substrate 2 side is preferably smaller than the opening diameter d1 of the through hole 2c in the glass substrate 2 on the first surface 2a side. The ratio of d2 / d1 may be, for example, 0.5 or greater but less than 1.0, or 0.6 or greater but 0.9 or less. The opening diameter d1 of the through hole 2c in the glass substrate 2 on the first surface 2a side may be, for example, 50 μm or greater but 100 μm or less, or 60 μm or greater but 90 μm or less. On the other hand, the opening diameter d2 of the second through hole 15c in the coating insulating layer 15 on the glass substrate 2 side is not particularly limited, and may be, for example, 40 μm or greater but 85 μm or less, or 50 μm or greater but 80 μm or less.

[0101] It is also preferable that the edge E4 of the opening of the second through hole 15c on the surface of the covering insulating layer 2 facing the glass substrate 2 is located more inward than the edge E1 of the opening of the through hole 2c on the first surface 2c of the glass substrate 2. By arranging such a covering insulating layer having the second through hole, the boundary α between the glass substrate 2 and the through electrode 3 can be covered by the covering insulating layer 15.

[0102] The cross-sectional shape of the second through hole 15c in the coating insulating layer 15 is preferably an inverted tapered shape, in which the opening diameter d2 of the second through hole 15c on the glass substrate 2 side is smaller than the opening diameter d3 on the side opposite the glass substrate side, as shown in FIG. 15(b). When the second through hole has an inverted tapered shape, the angle θ between the sidewall SS of the second through hole 15c and the surface of the coating insulating layer 2 opposite the glass substrate 2 side becomes an obtuse angle in the cross-sectional view. Therefore, even if the through electrode 3 expands and bulges, stress concentration near the edge E3 of the opening of the second through hole 15c on the surface of the coating insulating layer 2 opposite the glass substrate 2 can be suppressed. This can suppress disconnection of the pad portion and the conductive layer arranged on the surface of the coating insulating layer opposite the glass substrate.

[0103] The angle θ is not particularly limited, but may be, for example, greater than 90 degrees and less than or equal to 130 degrees, or greater than or equal to 100 degrees and less than or equal to 120 degrees. By setting the angle θ within the above range, disconnection of the pad portion and conductive layer arranged on the surface of the covering insulating layer opposite the glass substrate can be further suppressed. On the other hand, if the angle θ is too large, the opening diameter d3 of the second through hole 15c on the side opposite the glass substrate 2 becomes large, which may make it unsuitable for high-density mounting.

[0104] 15(c), in a cross-sectional view, it is preferable that the edge E3 of the opening of the second through hole 15c on the surface of the covering insulating layer 15 opposite to the glass substrate 2 is a curved surface having a curvature. By having the edge E3 as a curved surface having a curvature, it is possible to further suppress disconnection of the pad portion and the conductive layer arranged on the surface of the covering insulating layer opposite to the glass substrate.

[0105] A second via is disposed in the second through hole of the covering insulating layer. The second via is electrically connected to the through electrode and the via pad portion. The second via is preferably directly connected to the through electrode.

[0106] The second via may be a via that fills the second through hole in the covering insulating layer, a so-called filled via, or may be a via that is arranged only on the side wall of the second through hole in the covering insulating layer, a so-called conformal via.

[0107] The material of the second via is the same as the material of the through electrode, and it is preferable that the material of the through electrode and the material of the second via are the same.

[0108] The second via can be formed, for example, by electrolytic plating. When a conductive layer of the first wiring layer (described later) is disposed on the surface of the covering insulating layer opposite the glass substrate, the second via is preferably formed simultaneously with the conductive layer of the first wiring layer. Furthermore, when the elastic insulating layer also serves as the covering insulating layer, the second via can be formed simultaneously with the via pad portion.

[0109] 8. Second Covering Insulating Layer and Third Via The through electrode substrate intermediate in this embodiment preferably has a second covering insulating layer disposed on the second surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate and having a third through hole connecting to the through hole, and a third via disposed in the third through hole of the second covering insulating layer and electrically connected to the through electrode.

[0110] 16, the through electrode substrate intermediate 1 has a covering insulating layer 17 disposed on the second surface 2b side of the glass substrate 2 so as to cover at least the boundary β between the through electrode 3 and the glass substrate 2, and having a third through hole 17c connecting to the through hole 3, and a third via 18 disposed in the third through hole 17c of the second covering insulating layer 17 and electrically connected to the through electrode 3 and to the element connection pad portion 11. In Fig. 16, a second wiring layer 12 is disposed on the surface of the second covering insulating layer 17 opposite to the glass substrate 2, and the third via 18 is electrically connected to the element connection pad portion 11 via the conductive layer 12a and the fifth via 12c of the second wiring layer 12.

[0111] The second covering insulating layer has the same effect as the covering insulating layer described above. The second covering insulating layer and the third via have the same effects as the covering insulating layer and the second via described above, respectively.

[0112] 9. First Wiring Layer The through electrode substrate intermediate in this embodiment may have a first wiring layer disposed between the glass substrate and the elastic insulating layer and electrically connected to the through electrode.

[0113] The first wiring layer includes at least a conductive layer and may further include an interlayer insulating layer. The conductive layer may be one layer or two or more layers. When the first wiring layer includes two or more conductive layers, the conductive layers are stacked in the thickness direction with an interlayer insulating layer interposed therebetween. The conductive layers are electrically connected through vias. For example, in FIG. 17 , the first wiring layer 4 includes, from the glass substrate 2 side, a conductive layer 4 a, an interlayer insulating layer 4 b, a conductive layer 4 a, an interlayer insulating layer 4 b, and a conductive layer 4 a, and the conductive layers 4 a are electrically connected by a fourth via 4 c.

[0114] The material for the conductive layer is not particularly limited as long as it is a conductive material, and conductive materials generally used for wiring in interposers can be used. Examples of conductive materials include metallic materials such as metals and metal oxides, conductive resins containing conductive fillers and resins, and conductive polymers.

[0115] The thickness of the conductive layer is, for example, 0.1 μm or more, or may be 0.5 μm or more, 1 μm or more, 3 μm or more, or 5 μm or more. On the other hand, the thickness of the conductive layer is, for example, 20 μm or less, or may be 15 μm or less. The thickness of the conductive layer is, for example, 0.1 μm or more to 20 μm or less, or may be 0.5 μm or more to 15 μm or less, or 1 μm or more to 15 μm or less, or may be 3 μm or more to 15 μm or less, or may be 5 μm or more to 15 μm or less. For example, when the conductive layer is formed by a sputtering method, a relatively thin conductive layer can be obtained. Furthermore, when the conductive layer is formed by a plating method, a relatively thick conductive layer can be obtained.

[0116] The method for forming the conductive layer may be an additive method or a subtractive method. In the additive method, for example, a resist pattern is formed by photolithography, and a patterned wiring layer is obtained by plating the portions exposed from the resist pattern. When using electrolytic plating, a conductive film may be formed on the first surface of the glass substrate or on the surface of the interlayer insulating layer opposite the glass substrate before forming the resist pattern. In the subtractive method, for example, a resist pattern is formed on a conductive film formed on the entire first surface of the glass substrate, and the portions exposed from the resist pattern are etched to obtain a patterned conductive layer.

[0117] The material of the interlayer insulating layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0118] The thickness of the interlayer insulating layer is, for example, 1.5 μm or more, and may be 2.5 μm or more. On the other hand, the thickness of the interlayer insulating layer is, for example, 6 μm or less. The thickness of the interlayer insulating layer is, for example, 1.5 μm or more and 6 μm or less, and may be 2.5 μm or more and 6 μm or less.

[0119] Examples of methods for forming the interlayer insulating layer include photolithography and printing.

[0120] 10. Second Wiring Layer The through electrode substrate intermediate in this embodiment may have a second wiring layer disposed on the second surface side of the glass substrate and electrically connected to the through electrodes.

[0121] The second wiring layer includes at least a conductive layer and may further include an interlayer insulating layer. The conductive layer may be one layer or two or more layers. When the second wiring layer includes two or more conductive layers, the conductive layers are stacked in the thickness direction via an interlayer insulating layer. The conductive layers are electrically connected via vias. For example, in FIG. 18 , the second wiring layer 12 includes, in order from the glass substrate 2 side, a conductive layer 12a, an interlayer insulating layer 12b, a conductive layer 12a, an interlayer insulating layer 12b, a conductive layer 12a, an interlayer insulating layer 12b, and a conductive layer 12a, and the conductive layers 12a are electrically connected by a fifth via 12c. The conductive layer 12a located on the surface of the second wiring layer 12 opposite the glass substrate 2 includes an element connection pad portion 11.

[0122] The conductive layers and interlayer insulating layers in the second wiring layer are similar to the conductive layers and interlayer insulating layers in the first wiring layer.

[0123] The shape of the element connection pad portion in plan view is the same as the shape of the via pad portion in plan view.

[0124] B. Through-hole electrode substrate The through-hole electrode substrate in this embodiment includes the above-described through-hole electrode substrate intermediate, and a bellows wiring layer that is disposed on the surface of the through-hole electrode substrate intermediate on the elastic insulating layer side, has a bellows-shaped portion with a plurality of peaks and a plurality of valleys, and electrically connects the via pad portion and the wiring board connection pad portion.

[0125] 2(a) and 2(b) are a schematic plan view and a cross-sectional view showing an example of a through electrode substrate in this embodiment, and Fig. 2(b) is a cross-sectional view taken along line A-A in Fig. 2(a). As shown in Fig. 2(a) and Fig. 2(b), the through electrode substrate 20 includes the above-described through electrode substrate intermediate 1 and a bellows-shaped portion 21 having a plurality of peaks 21a and a plurality of valleys 21b, which is disposed on the surface of the through electrode substrate intermediate 1 facing the elastic insulating layer 5, and which electrically connects the via pads 7 and the wiring board connection pads 8.

[0126] 3 is a schematic cross-sectional view showing an example of an element-equipped through electrode substrate having a through electrode substrate in this embodiment. As shown in Fig. 3, the element-equipped through electrode substrate 30 has a through electrode substrate 20, a first bonding portion 31 electrically connected to an element connection pad portion 11 of the through electrode substrate 20, and an element 32 electrically connected to the first bonding portion 31.

[0127] 4 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate according to this embodiment. As shown in Fig. 4, a semiconductor device 40 has a through electrode substrate 20, a first bonding portion 31 electrically connected to an element connection pad portion 11 of the through electrode substrate 20, an element 32 electrically connected to the first bonding portion 31, a second bonding portion 41 electrically connected to a wiring substrate connection pad 8 of the through electrode substrate 20, and a wiring substrate 42 electrically connected to the second bonding portion 41.

[0128] In this embodiment, as described in the above section "A. Through-hole electrode substrate intermediate," the through-hole electrode substrate has a glass substrate and is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate and the semiconductor material, thereby suppressing stress generation in the first bonding portion and the element connection pad portion. This therefore prevents cracks and disconnections in the first bonding portion and the element connection pad portion.

[0129] Furthermore, in this embodiment, as described in the above section "A. Through-hole electrode substrate intermediate," the elastic insulating layer is elastic and has an uneven shape on the surface facing the via pad portion and the wiring board connection pad portion, so that the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion is stretchable. Furthermore, as the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion stretches and contracts, the via deforms obliquely. In this way, the surface of the elastic insulating layer facing the via pad portion and the wiring board connection pad portion stretches and contracts, and the via deforms obliquely, thereby alleviating stress due to the difference in thermal expansion coefficients between the through-hole electrode substrate and the wiring board. Therefore, cracks and breaks in the second joint portion and the element connection pad portion can be suppressed.

[0130] Furthermore, in this embodiment, as described in the above section "A. Through-hole electrode substrate intermediate," the elastic insulating layer has an uneven surface, and therefore the bellows wiring layer disposed on the surface of the elastic insulating layer has an bellows-shaped portion that conforms to the uneven surface of the elastic insulating layer. Furthermore, the bellows-shaped portion of the bellows wiring layer provides flexibility. The flexibility of the bellows wiring layer further alleviates stress caused by the difference in thermal expansion coefficients between the through-hole electrode substrate and the wiring substrate. Therefore, cracks and breaks in the second joint portion and the element connection pad portion can be effectively suppressed.

[0131] Therefore, in this embodiment, the connection reliability can be improved.

[0132] Hereinafter, the through electrode substrate in this embodiment will be described for each configuration.

[0133] 1. Through-hole electrode substrate intermediate The through-hole electrode substrate intermediate has been described in detail above in "A. Through-hole electrode substrate intermediate," and therefore description thereof will be omitted here.

[0134] 2. Bellows Wiring Layer The bellows wiring layer in this embodiment is disposed on the surface of the through electrode substrate intermediate body facing the elastic insulating layer, has a bellows-shaped portion with a plurality of peaks and a plurality of valleys, and electrically connects the via pad portion and the wiring substrate connection pad portion.

[0135] (1) Bellows-Shaped Portion The bellows-shaped wiring layer has a bellows-shaped portion having a plurality of peaks and a plurality of valleys.

[0136] In the bellows-shaped portion, the height difference between adjacent peaks and valleys is preferably smaller than the thickness of the second joint electrically connecting the through-hole electrode substrate and the wiring substrate in the semiconductor device having the through-hole electrode substrate of this embodiment. The height difference is, for example, 50 μm or less, or may be 15 μm or less, or 10 μm or less. If the height difference is too large, the bellows wiring layer may come into contact with the wiring substrate. On the other hand, the height difference is, for example, 1 μm or more, or may be 3 μm or more, or 5 μm or more. If the height difference is too small, the bellows wiring layer may be difficult to expand and contract. The height difference is, for example, 1 μm or more to 50 μm or less, or may be 3 μm or more to 15 μm or less, or may be 5 μm or more to 10 μm or less. The height difference between adjacent peaks and valleys is indicated by symbol H2, as shown in FIG. 19 , and is the distance between adjacent peaks and valleys in the normal direction of the first surface of the glass substrate.

[0137] The height difference between adjacent peaks and valleys is measured based on an image of the cross section of the through hole electrode substrate taken with a scanning electron microscope (SEM). The height difference between adjacent peaks and valleys is the arithmetic mean value of the height differences at any 10 locations.

[0138] In the bellows-shaped portion, the spacing between adjacent peaks is, for example, 2 μm or more, or may be 5 μm or more, or 6 μm or more. Meanwhile, the spacing between adjacent peaks is, for example, 20 μm or less, or may be 10 μm or less, or may be 9 μm or less. The spacing is preferably large within the above range. A large spacing can reduce the stress amplitude in the bellows wiring layer. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, disconnection is suppressed and connection reliability is improved. Specifically, the spacing is 2 μm or more and 20 μm or less, or may be 5 μm or more and 10 μm or less, or may be 6 μm or more and 9 μm or less. The spacing between adjacent peaks is indicated by the symbol P2, as shown in FIG. 19 , for example.

[0139] The distance between adjacent peaks is measured based on an image of the cross section of the through hole electrode substrate taken with a scanning electron microscope (SEM). The distance between adjacent peaks is the arithmetic mean value of the distances at 10 arbitrary points.

[0140] In the bellows-shaped portion, the peaks and valleys may be arranged regularly or irregularly.

[0141] (2) Form of the bellows wiring layer The bellows wiring layer is arranged so as to electrically connect the via pad portion and the wiring board connection pad portion.

[0142] The planar shape of the bellows wiring layer may be any shape as long as it is arranged to electrically connect the via pad portion and the wiring board connection pad portion. Examples of such shapes include a straight line as shown in FIG. 2A, a curve as shown in FIG. 20, and a wavy line, zigzag line, or right-angled line (not shown). When the planar shape of the bellows wiring layer is other than a straight line, the length of the bellows wiring layer increases. This reduces the stress amplitude. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, breakage is suppressed, improving connection reliability.

[0143] The length of the bellows wiring layer is appropriately set depending on the size of the through-hole electrode substrate, but is preferably 50 μm or more, and may be 100 μm or more, or 200 μm or more. If the length of the bellows wiring layer is too short, the bellows wiring layer may be less flexible and more prone to breakage. If the length of the bellows wiring layer is within the above range, the stress amplitude can be reduced. Therefore, when the bellows wiring layer is repeatedly subjected to thermal stress, breakage is suppressed and connection reliability can be maintained. On the other hand, the length of the bellows wiring layer is, for example, 1000 μm or less, or may be 500 μm or less, or may be 300 μm or less. If the length of the bellows wiring layer is too long, the electrical characteristics may be degraded. Specifically, the length of the bellows wiring layer is 50 μm or more and 1000 μm or less, or may be 100 μm or more and 500 μm or less, or may be 200 μm or more and 300 μm or less. The length of the bellows wiring layer refers to the length of the bellows wiring layer in a planar view.

[0144] The thickness of the bellows wiring layer is not particularly limited. For example, when the material of the bellows wiring layer is not elastic, as described below, the thickness of the bellows wiring layer is, for example, 1 nm or more, or may be 100 nm or more, or 1000 nm or more. In this case, the thickness of the bellows wiring layer is, for example, 100 μm or less, or may be 10 μm or less, or may be 3 μm or less. That is, in this case, the thickness of the bellows wiring layer is, for example, 1 nm or more and 100 μm or less, or may be 100 nm or more and 10 μm or less, or may be 1000 nm or more and 3 μm or less. On the other hand, when the material of the bellows wiring layer is elastic, as described below, the thickness of the bellows wiring layer is, for example, 5 μm or more, or may be 10 μm or more, or may be 20 μm or more. In this case, the thickness of the bellows wiring layer is, for example, 60 μm or less, or may be 50 μm or less, or may be 40 μm or less. That is, in this case, the thickness of the bellows wiring layer is, for example, 5 μm or more and 60 μm or less, or may be 10 μm or more and 50 μm or less, or may be 20 μm or more and 40 μm or less.

[0145] The width of the bellows wiring layer is, for example, not less than 10 μm and not more than 100 μm.

[0146] As described above, when a concave-convex shape is arranged over the entire surface of the elastic insulating layer facing the via pad portions and wiring board connection pad portions, the bellows wiring layer may also serve as the via pad portions and wiring board connection pad portions. For example, in Fig. 21, a concave-convex shape 9 is arranged over the entire surface of the elastic insulating layer 5 facing the via pad portions 7 and wiring board connection pad portions 8, and the bellows wiring layer 22 also serves as the via pad portions 7 and wiring board connection pad portions 8. In this case, a concave-convex shape is also arranged in the areas of the via pads and wiring board connection pads on the surface of the elastic insulating layer facing the via pads and wiring board connection pads.

[0147] (3) Physical Properties of the Corrugated Wiring Layer The elastic modulus of the corrugated wiring layer measured by nanoindentation is, for example, 100 MPa or more, and may be 200 MPa or more. On the other hand, the elastic modulus is, for example, 300 GPa or less, may be 200 GPa or less, or may be 100 GPa or less. That is, the elastic modulus may be 100 MPa or more and 300 GPa or less, 100 MPa or more and 200 GPa or less, 200 MPa or more and 200 GPa or less, or 200 MPa or more and 100 GPa or less.

[0148] (4) Material of the Corrugated Wiring Layer The material of the corrugated wiring layer may or may not be elastic. Examples of non-elastic materials include metals such as gold, silver, copper, aluminum, platinum, and chromium, and alloys containing these metals. On the other hand, examples of elastic materials include conductive compositions containing conductive particles and an elastomer. In this case, the corrugated wiring layer includes conductive particles and an elastomer. Examples of conductive particles include particles of gold, silver, copper, nickel, palladium, platinum, and carbon. Examples of elastomers include styrene-based elastomers, acrylic-based elastomers, olefin-based elastomers, urethane-based elastomers, silicone rubber, urethane rubber, fluororubber, nitrile rubber, polybutadiene, and polychloroprene.

[0149] (5) Method for Forming the Bellows Wiring Layer The method for forming the Bellows wiring layer is not particularly limited. For example, when the material of the Bellows wiring layer is not stretchable, a conductive film may be formed by a method such as vapor deposition, sputtering, plating, metal foil transfer, or pressure bonding, and then the conductive film may be patterned by photolithography. On the other hand, when the material of the Bellows wiring layer is stretchable, a conductive composition containing conductive particles and an elastomer may be printed in a pattern by a general printing method.

[0150] 3. First Polymer Layer The through hole electrode substrate in this embodiment preferably has a first polymer layer between the elastic insulating layer and the bellows wiring layer. For example, in Figure 22, a first polymer layer 23 is disposed between the elastic insulating layer 5 and the bellows wiring layer 22. The first polymer layer can reduce the stress and stress amplitude applied to the bellows wiring layer.

[0151] The elastic modulus of the first polymer layer is preferably greater than that of the elastic insulating layer. If the elastic modulus of the first polymer layer is smaller than that of the elastic insulating layer and is therefore too soft, the stress applied to the bellows wiring layer may become uneven. This may result in stress concentration and lead to breakage of the bellows wiring layer.

[0152] The elastic modulus of the first polymer layer, as measured by nanoindentation, is, for example, 20 GPa or less. If the elastic modulus is too large, the first polymer layer may be torn and the bellows wiring layer may be broken. On the other hand, as described above, the elastic modulus of the first polymer layer is preferably greater than the elastic modulus of the elastic insulating layer, and the lower limit of the first polymer layer is not particularly limited.

[0153] The material of the first polymer layer is preferably polyimide or parylene.

[0154] The first polymer layer only needs to be disposed in the area where the bellows wiring layer is disposed in a plan view. In particular, as illustrated in Fig. 22, it is preferable that the first polymer layer 23 is not disposed in any area other than the area where the bellows wiring layer 22 is disposed. There is a risk that the first polymer layer will suppress expansion and contraction of the surfaces of the elastic insulating layer facing the via pad portion and the wiring board connection pad.

[0155] The first polymer layer is arranged to have openings above the via pad portions and the wiring board connection pads in a plan view so that the bellows wiring layer is electrically connected to the via pad portions and the wiring board connection pads.

[0156] The first polymer layer also has a bellows-shaped portion in a region overlapping with the bellows wiring layer in a plan view.

[0157] The thickness of the first polymer layer is, for example, not less than 1 nm and not more than 100 μm.

[0158] 4. Second Polymer Layer The through electrode substrate in this embodiment preferably has a second polymer layer on the side of the bellows wiring layer opposite the elastic insulating layer. For example, in FIG. 22 , a second polymer layer 24 is disposed on the side of the bellows wiring layer 22 opposite the elastic insulating layer 5. The second polymer layer can reduce the stress and stress amplitude applied to the bellows wiring layer.

[0159] It is preferable that at least one of the first polymer layer and the second polymer layer is disposed, more preferable that at least the first polymer layer is disposed, and even more preferable that both the first polymer layer and the second polymer layer are disposed. For example, in Fig. 22, both the first polymer layer 23 and the second polymer layer 24 are disposed.

[0160] The modulus of elasticity, material and thickness of the second polymer layer are the same as those of the first polymer layer.

[0161] The second polymer layer only needs to be disposed in the area where the bellows wiring layer is disposed in a plan view. As shown in Fig. 22, the second polymer layer 24 is preferably not disposed in any area other than the area where the bellows wiring layer 22, the via pads 7, and the wiring board connection pads 8 are disposed. The second polymer layer may restrict expansion and contraction of the surface of the elastic insulating layer facing the via pads and the wiring board connection pads.

[0162] As shown in FIG. 22, the second polymer layer 24 is preferably disposed so as to overlap the via pads 7 and the wiring board connection pads 8 in plan view.

[0163] The second polymer layer also has a bellows-shaped portion in a region overlapping with the bellows wiring layer in a plan view.

[0164] C. Through-hole electrode substrate with element The through-hole electrode substrate with element in this embodiment has the through-hole electrode substrate described above and an element mounted on the through-hole electrode substrate.

[0165] 3 is a schematic cross-sectional view showing an example of an element-equipped through electrode substrate in this embodiment. As shown in Fig. 3, the element-equipped through electrode substrate 30 includes the above-mentioned through electrode substrate 20, a first bonding portion 31 electrically connected to the element connection pad portion 11 of the through electrode substrate 20, and an element 32 electrically connected to the first bonding portion 31.

[0166] The element-equipped through hole electrode substrate in this embodiment has the above-described through hole electrode substrate, and therefore, can suppress disconnection and improve connection reliability.

[0167] Hereinafter, the element-equipped through hole electrode substrate in this embodiment will be described for each configuration.

[0168] 1. Through-electrode Substrate The through-electrode substrate has been described in detail above in "B. Through-electrode Substrate," so a detailed description thereof will be omitted here.

[0169] 2. Elements In this embodiment, examples of elements include active elements such as ICs, transistors, and diodes, and passive elements such as resistors, capacitors, and inductors. Examples of elements include IC chips, LSI chips, and MEMS chips.

[0170] The element is mounted on the element connection pad of the through-hole electrode substrate via a first bonding portion. A bonding portion generally used for mounting elements can be used as the first bonding portion. Examples of materials for the first bonding portion include solder, gold or gold alloy, conductive paste, anisotropic conductive paste, and anisotropic conductive film.

[0171] Furthermore, an underfill resin portion may be disposed by filling an underfill resin between the through electrode substrate and the element, or the element may be sealed with a mold resin, so that the mold resin portion is disposed to cover the element.

[0172] D. Semiconductor Device The semiconductor device in this embodiment has the aforementioned element-equipped through hole electrode substrate, and a wiring substrate electrically connected to the wiring substrate connection pads of the through hole electrode substrate.

[0173] 4 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. As shown in Fig. 4, a semiconductor device 40 includes a through electrode substrate 20, a first bonding portion 31 electrically connected to an element connection pad portion 11 of the through electrode substrate 20, an element 32 electrically connected to the first bonding portion 31, a second bonding portion 41 electrically connected to a wiring board connection pad 8 of the through electrode substrate 20, and a wiring board 42 electrically connected to the second bonding portion 41.

[0174] The semiconductor device in this embodiment has the element-equipped through electrode substrate described above, and therefore can suppress disconnection and improve connection reliability.

[0175] Hereinafter, the semiconductor device according to this embodiment will be described in detail for each of its components.

[0176] 1. Element-Attached Through Electrode Substrate The element-attached through electrode substrate has been described in detail above in "C. Element-Attached Through Electrode Substrate," and therefore a detailed description thereof will be omitted here.

[0177] 2. Wiring Board As the wiring board in this embodiment, a general wiring board can be used.

[0178] The wiring board is electrically connected to the wiring board connection pads of the through electrode substrate via second bonding portions, which are made of the same material as the first bonding portion.

[0179] 3. Applications Applications of the semiconductor device in this embodiment are not particularly limited, and examples thereof include notebook personal computers, tablet terminals, mobile phones, smartphones, digital video cameras, digital cameras, digital clocks, and servers.

[0180] II. Second Embodiment Next, a through hole electrode substrate, a through hole electrode substrate with an element, and a semiconductor device according to a second embodiment of the present disclosure will be described in detail.

[0181] A. Through-hole electrode substrate The through-hole electrode substrate in this embodiment has a first surface and a second surface opposite the first surface, and includes a glass substrate having a first through hole, a through-hole electrode disposed in the first through hole of the glass substrate, a covering insulating layer disposed on the first surface side of the glass substrate so as to cover at least the boundary between the through-hole electrode and the glass substrate, and having a second through hole connected to the first through hole, a first via disposed in the second through hole of the covering insulating layer and electrically connected to the through-hole electrode, an elastic insulating layer disposed on the surface of the covering insulating layer opposite the glass substrate and having a third through hole, a second via disposed in the third through hole of the elastic insulating layer and electrically connected to the first via, and a wiring board connection pad portion disposed on the surface of the elastic insulating layer opposite the covering insulating layer, electrically connected to the second via, and electrically connected to a wiring board.

[0182] 23 is a schematic cross-sectional view showing an example of a through electrode substrate in this embodiment. As shown in Fig. 23, the through electrode substrate 101 has a first surface 102a and a second surface 102b opposite to the first surface 102a, and includes a glass substrate 102 having a first through hole 102c, a through electrode 103 arranged in the first through hole 102c of the glass substrate 102, a covering insulating layer 104 arranged on the first surface 102a side of the glass substrate 102 so as to cover the boundary α between the through electrode 103 and the glass substrate 102 and having a second through hole 104c connected to the first through hole 102c, a first via 105 arranged in the second through hole 104c of the covering insulating layer 104 and electrically connected to the through electrode 103, and a second insulating layer 104 formed on the glass substrate 102. the first wiring layer 106 being disposed on the surface of the covering insulating layer 104 opposite the glass substrate 102 and including a first conductive layer 106a electrically connected to the first via 105; an elastic insulating layer 107 being disposed on the surface of the covering insulating layer 104 opposite the glass substrate 102 and having a third through hole 107c; ​​a second via 108 being disposed in the third through hole 107c of the elastic insulating layer 107 and electrically connected to the first via 105 via the first conductive layer 106a of the first wiring layer 106; and a wiring substrate connection pad portion 109 being disposed on the surface of the elastic insulating layer 107 opposite the covering insulating layer 104 and electrically connected to the second via 108 and electrically connected to the wiring substrate.

[0183]

[0063] Figure 23 is a schematic cross-sectional view showing an example of a through electrode substrate with elements having a through electrode substrate in this embodiment. In Figure 23, the through electrode substrate 101 is arranged on the second surface 102b side of the glass substrate 102, is electrically connected to the through electrodes 103, and further has element connection pads 111 electrically connected to the elements. As shown in Figure 23, the through electrode substrate 120 with elements has the through electrode substrate 101, a first bonding portion 121 electrically connected to the element connection pads 111 of the through electrode substrate 101, and an element 122 electrically connected to the first bonding portion 121.

[0184] 25 is a schematic cross-sectional view showing an example of a semiconductor device having a through electrode substrate according to this embodiment. As shown in Fig. 25, a semiconductor device 130 has a through electrode substrate 1, a first bonding portion 121 electrically connected to an element connection pad portion 111 of the through electrode substrate 101, an element 122 electrically connected to the first bonding portion 121, a second bonding portion 131 electrically connected to a wiring substrate connection pad 109 of the through electrode substrate 101, and a wiring substrate 132 electrically connected to the second bonding portion 131.

[0185] For example, if the first joint is a solder joint, and the through-hole electrode substrate and the element are joined via the solder joint during a reflow process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the element expand due to heat and then contract due to cooling. If the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the first joint and the element connection pad, making cracks and disconnections more likely. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the element is large, stress is generated in the first joint and the element connection pad, making cracks and disconnections more likely.

[0186] In contrast, in this embodiment, the through electrode substrate 101 has a glass substrate 102, and the through electrode substrate 101 is used as a so-called glass interposer. This reduces the difference in thermal expansion coefficient between the glass substrate 102 and the element 122, and suppresses stress from occurring in the first bonding portion 121 and the element connection pad portion 111. This prevents cracks and breaks in the first bonding portion 121 and the element connection pad portion 111.

[0187] Furthermore, for example, when the second joint portion is a solder joint portion and the through-hole electrode substrate and the wiring substrate are joined via the solder joint portion during a reflow process in the manufacturing process of the semiconductor device, the through-hole electrode substrate and the wiring substrate expand due to heat and then contract due to cooling. At this time, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, disconnection between the through-hole electrode substrate and the wiring substrate is likely to occur. Furthermore, for example, when the semiconductor device is used in a high-temperature environment, if the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring substrate is large, stress is generated in the second joint portion and the wiring substrate connection pad portion, making cracks and disconnection more likely to occur.

[0188] In contrast, in this embodiment, the elastic insulating layer 107 has elasticity, and therefore the surface of the elastic insulating layer 107 facing the wiring board connection pad 109 is stretchable. Furthermore, as the surface of the elastic insulating layer 107 facing the wiring board connection pad 109 stretches and contracts, the second via 108 disposed in the third through hole 107c of the elastic insulating layer 107 deforms obliquely. In this manner, the surface of the elastic insulating layer 107 facing the wiring board connection pad 109 stretches and contracts, causing the second via 108 to deform obliquely, thereby alleviating stress caused by the difference in thermal expansion coefficients between the through electrode substrate 101 and the wiring board 132. Therefore, cracks and breaks in the second joint 131 and the wiring board connection pad 109 can be suppressed.

[0189] 26 is a schematic cross-sectional view showing another example of a through electrode substrate in this embodiment. In the through electrode substrate 101 shown in FIG. 26, an elastic insulating layer 107 also serves as the covering insulating layer 104, and a second via 108 also serves as the first via 105. As shown in FIG. 26, the through electrode substrate 101 has a first surface 102a and a second surface 102b opposite to the first surface 102a, and includes a glass substrate 102 having a first through hole 102c, a through electrode 103 arranged in the first through hole 102c of the glass substrate 102, and an elastic insulating layer 107c arranged on the first surface 102a side of the glass substrate 102 so as to cover the boundary α between the through electrode 103 and the glass substrate 102 and having a third through hole 107c connected to the first through hole 102c. 7 (coating insulating layer 104 having second through hole 104c connected to first through hole 102c), a second via 108 (first via 105) arranged in third through hole 107c (second through hole 104c of coating insulating layer 104) of elastic insulating layer 107 and electrically connected to through electrode 3, and a wiring board connection pad portion 109 arranged on the side of elastic insulating layer 107 opposite glass substrate 102, electrically connected to second via 108, and electrically connected to wiring board.

[0190] In this embodiment, the through electrode substrate shown in FIG. 26 also has the same effects as the through electrode substrate shown in FIG.

[0191] Here, in the manufacture of a semiconductor device in which a through electrode substrate is interposed between an element and a motherboard, heat treatments such as an annealing process and a reflow soldering process are performed. Figures 13(a) and 13(b) are schematic diagrams illustrating the state of the through electrode substrate during heat treatment in the manufacturing process of the semiconductor device. In a through electrode substrate having a through electrode 103 filled in the first through hole 102c as shown in Figure 13(a), a gap G may be generated between the glass substrate 102 and the through electrode 103 during heat treatment due to the difference in thermal expansion coefficients between the glass substrate 102 and the through electrode 103, as shown in Figure 13(b). Furthermore, during heat treatment, the through electrode 103 may rise relative to the first or second surface of the glass substrate 102 due to the difference in thermal expansion coefficients between the glass substrate 102 and the through electrode 103, as shown in Figure 13(b). Furthermore, during heat treatment, gas components such as moisture and hydrogen remaining in the material constituting the through electrode 103 may be released, causing the through electrode 103 to be pushed up. When such gaps or bulges occur, the conductive layer or pad located near the boundary between the through electrode and the glass substrate may be disconnected, and the wiring connected to the pad may be disconnected.

[0192] In this embodiment, a resin is used for the coating insulating layer 104, as described below. As shown in FIG. 23 , when the coating insulating layer 104 is arranged to cover the boundary α between the glass substrate 102 and the through electrode 103, a portion of the coating insulating layer 104 contacts a portion of the through electrode 103. Therefore, even if gas is released from inside the through electrode 103 during heat treatment, the gas can be released to the outside through the coating insulating layer 104. Therefore, swelling of the first conductive layer 106a of the first wiring layer 106 arranged near the boundary α can be suppressed. Furthermore, because the coating insulating layer 104 is arranged to cover the boundary α between the glass substrate 102 and the through electrode 103, even if a gap occurs between the through electrode 103 and the glass substrate 102 during heat treatment, the gap between the through electrode 103 and the glass substrate 102 can be covered by the coating insulating layer 104, thereby suppressing disconnection of the first conductive layer 106a of the first wiring layer 106 located on the boundary α. Furthermore, even if a step occurs between the through electrode 103 and the glass substrate 102 due to a gap or swelling during heat treatment, the covering insulating layer 104 can absorb the step between the through electrode 103 and the glass substrate 102, thereby preventing a sudden step from occurring in the first conductive layer 106a of the first wiring layer 106 located near the boundary α.

[0193] In this embodiment, an elastomer is used for the elastic insulating layer 7, as described below. As shown in FIG. 26 , when the elastic insulating layer 107 also serves as the covering insulating layer 104, if the elastic insulating layer 107 is arranged to cover the boundary α between the glass substrate 102 and the through electrode 103, a portion of the elastic insulating layer 107 contacts a portion of the through electrode 103. Therefore, even if gas is released from inside the through electrode 103 during heat treatment, the gas can be released to the outside through the elastic insulating layer 107. Therefore, swelling of the wiring board connection pad 109 located near the boundary α can be suppressed. Furthermore, since the elastic insulating layer 107 is arranged to cover the boundary α between the glass substrate 102 and the through electrode 103, even if a gap occurs between the through electrode 103 and the glass substrate 102 during heat treatment, the gap between the through electrode 103 and the glass substrate 102 can be covered by the elastic insulating layer 107, thereby suppressing disconnection of the wiring board connection pad 109 located on the boundary α. Furthermore, even if a step occurs between the through electrode 103 and the glass substrate 102 due to a gap or swelling during heat treatment, the elastic insulating layer 107 can absorb the step between the through electrode 103 and the glass substrate 102, thereby preventing a sudden step from occurring in the wiring board connection pad portion 109 located near the boundary α.

[0194] In this way, the covering insulating layer is arranged so as to cover the boundary between the glass substrate and the through electrode, thereby making it possible to prevent disconnection of the conductive layer and pad portion arranged near the boundary between the through electrode and the glass substrate, thereby improving yield.

[0195] Therefore, in this embodiment, the connection reliability can be improved.

[0196] Hereinafter, the through electrode substrate in this embodiment will be described for each configuration.

[0197] 1. Elastic Insulating Layer The elastic insulating layer in this embodiment is disposed on the surface of the covering insulating layer opposite the glass substrate, and has a third through hole that penetrates the covering insulating layer in the thickness direction.

[0198] (1) Physical Properties of the Elastic Insulating Layer The physical properties of the elastic insulating layer in this embodiment are the same as those described in "A. Through-hole electrode substrate intermediate 1. Elastic insulating layer (2) Physical Properties of the Elastic Insulating Layer" in the first embodiment, and therefore will not be described here. The only difference is that the surface of the elastic insulating layer onto which the Berkovich indenter is pressed is the surface of the elastic insulating layer on the wiring board connection pad side.

[0199] (2) Material of the elastic insulating layer The material of the elastic insulating layer in this embodiment is the same as that described in "A. Through electrode substrate intermediate 1. Elastic insulating layer (3) Material of the elastic insulating layer" in the first embodiment above, so the explanation here is omitted.

[0200] (3) Uneven Shape The elastic insulating layer preferably has an uneven shape including multiple convex portions and multiple concave portions on the surface facing the wiring board connection pad portion. For example, in FIG. 27 , elastic insulating layer 107 has an uneven shape 110 including multiple convex portions 110 a and multiple concave portions 110 b on the surface facing wiring board connection pad portion 109. Also, in FIG. 28 , elastic insulating layer 107 also serves as covering insulating layer 104, and has an uneven shape 110 including multiple convex portions 110 a and multiple portions 110 b on the surface facing wiring board connection pad portion 109. Elastic insulating layer 107 has elasticity, and having uneven shape 110 on the surface facing wiring board connection pad portion 109 increases the flexibility of the surface of elastic insulating layer 107 facing wiring board connection pad portion 109. The expansion and contraction of the surface of the elastic insulating layer 107 on the wiring board connection pad 109 side can further reduce stress caused by the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring board, thereby effectively suppressing cracks and breaks in the second joint portion and the wiring board connection pad.

[0201] In the concave-convex shape, the difference in height between adjacent convex and concave portions is preferably smaller than the thickness of the elastic insulating layer. The difference in height is, for example, 50 μm or less, and may be 15 μm or less, or 10 μm or less. If the difference in height is too large, the surface of the elastic insulating layer facing the wiring board connection pad portion may come into contact with the wiring board. On the other hand, the difference in height is, for example, 1 μm or more, or 3 μm or more, or 5 μm or more. If the difference in height is too small, the effect of improving elasticity due to the concave-convex shape may not be fully achieved. Specifically, the difference in height is 1 μm or more to 50 μm or less, or 3 μm or more to 15 μm or less, or 5 μm or more to 10 μm or less. The difference in height between adjacent convex and concave portions is indicated by the symbol H1, as shown in FIG. 29 , and is the distance between adjacent convex portions 110 a and concave portions 110 b in the normal direction of the first surface of the glass substrate.

[0202] The height difference between adjacent convex and concave portions is measured based on an image of the cross section of the through hole electrode substrate taken with a scanning electron microscope (SEM). The height difference between adjacent convex and concave portions is the arithmetic mean value of the height differences at any 10 points.

[0203] In the concave-convex shape, the interval between adjacent convex portions is not particularly limited. The interval is, for example, 2 μm or more, and may be 5 μm or more, or 6 μm or more. On the other hand, the interval is, for example, 20 μm or less, or may be 10 μm or less, or may be 9 μm or less. Specifically, the interval is 2 μm or more and 20 μm or less, or may be 5 μm or more and 10 μm or less, or may be 6 μm or more and 9 μm or less. The interval between adjacent convex portions is indicated by symbol P1, for example, as shown in FIG. 29 , and is the distance between the centers of adjacent convex portions 110 a.

[0204] The distance between adjacent protrusions is measured based on an image of the cross section of the through hole electrode substrate taken with a scanning electron microscope (SEM). The distance between adjacent protrusions is the arithmetic mean value of the distances at any 10 positions.

[0205] In the uneven shape, the convex portions and concave portions may be arranged regularly or irregularly.

[0206] In the cross-sectional shape of the convex portion, it is preferable that the top of the convex portion is rounded. Examples of the cross-sectional shape of the convex portion include a semicircular shape or a semi-elliptical shape. In addition, in the cross-sectional shape of the concave portion, it is preferable that the bottom of the concave portion is rounded. Examples of the cross-sectional shape of the concave portion include a semicircular shape or a semi-elliptical shape. When a wiring board connection pad portion is arranged on the uneven shape of the elastic insulating layer, if the convex portion and the concave portion have the above-mentioned shapes, disconnection of the wiring board connection pad portion can be suppressed.

[0207] The position of the uneven shape on the surface of the elastic insulating layer facing the wiring board connection pads is not particularly limited. The uneven shape may be disposed over the entire surface of the elastic insulating layer facing the wiring board connection pads, or may be disposed partially. For example, in FIGS. 27 and 28 , uneven shapes 110 are partially disposed on the surface of the elastic insulating layer 107 facing the wiring board connection pads 109. For example, in FIGS. 30 and 31 , concave shapes 110 are disposed over the entire surface of the elastic insulating layer 107 facing the wiring board connection pads 109. In particular, as shown in FIGS. 27 , 28 , 30 , and 31 , it is preferable that the uneven shape 110 be disposed at least in the region between adjacent wiring board connection pads 109 on the surface of the elastic insulating layer 107 facing the wiring board connection pads 109. As described above, the uneven shape can further reduce stress caused by the difference in thermal expansion coefficient between the through-hole electrode substrate and the wiring board. Therefore, in a semiconductor device including a through electrode substrate, cracks and breaks in the second bonding portion and the wiring substrate connection pad portion can be effectively suppressed.

[0208] (4) Form of Elastic Insulation Layer In this embodiment, as described above, the elastic insulation layer may or may not also serve as the covering insulation layer. In particular, it is preferable that the elastic insulation layer does not also serve as the covering insulation layer, i.e., that the elastic insulation layer and the covering insulation layer are separately disposed. The covering insulation layer will be described later.

[0209] The thickness of the elastic insulating layer is, for example, 5 μm or more, or may be 15 μm or more, or 50 μm or more. If the thickness of the elastic insulating layer is within the above range, the surface of the elastic insulating layer facing the wiring board connection pad portion is more likely to expand and contract. On the other hand, the thickness of the elastic insulating layer is, for example, 200 μm or less, or may be 100 μm or less, or may be 60 μm or less. If the thickness of the elastic insulating layer is too thick, the thickness of the entire through-hole electrode substrate may become thick. Specifically, the thickness of the elastic insulating layer is 5 μm or more and 200 μm or less, or may be 15 μm or more and 100 μm or less, or may be 50 μm or more and 60 μm or less.

[0210] In this specification, the thickness of each layer is measured based on an image of the cross section of the through hole electrode substrate taken using a scanning electron microscope (SEM). The thickness is the arithmetic average of the thicknesses at any five points.

[0211] (5) Method for Forming Elastic Insulating Layer The elastic insulating layer can be formed by applying the above-mentioned material. The method for forming the third through hole is appropriately selected depending on the material of the elastic insulating layer, and examples thereof include photolithography, laser processing, and shaping using a mold. In the case of photolithography, the material of the elastic insulating layer may be a photosensitive material, and a resist pattern may be formed on the elastic insulating layer. In the case of shaping using a mold, a concave-convex shape may be formed on the surface of the elastic insulating layer by shaping using the mold, and at the same time, a third through hole may be formed in the elastic insulating layer by shaping using the mold. Examples of methods for forming the concave-convex shape include shaping using a mold.

[0212] 2. Second Via The second via in this embodiment is disposed in the third through hole of the elastic insulating layer, and is electrically connected to the first via and the wiring board connection pad portion.

[0213] The material for the second via is not particularly limited as long as it is a conductive material, and conductive materials used for general vias can be used, and is selected appropriately depending on the shape of the via, the formation method, etc.

[0214] The second via can be formed by a common via formation method, which is appropriately selected depending on the shape of the via. In the second via formation method, a third through-hole is first formed in the elastic insulating layer, and then a second via is formed in the third through-hole of the elastic insulating layer. Examples of methods for forming a via in the third through-hole of the elastic insulating layer include PVD methods such as vacuum deposition and sputtering, CVD, and plating. A conductive material may be filled into the third through-hole of the elastic insulating layer to form a via, and simultaneously a wiring board connection pad may be formed using this conductive material. In the plating method, after first forming the third through-hole in the elastic insulating layer, a seed layer is formed on the entire surface of the elastic insulating layer by sputtering or the like, a photoresist layer is then formed on the seed layer, the photoresist layer is subsequently patterned to have an opening for the wiring board connection pad, and the opening in the photoresist layer is then electroplated to form a plating layer, thereby simultaneously forming the second via and the wiring board connection pad. In this case, the second via and the wiring board connection pad have a seed layer and a plating layer.

[0215] 3. Covering Insulating Layer The covering insulating layer in this embodiment is arranged so as to cover at least the boundary between the through electrode and the glass substrate, and has a second through hole that is connected to the first through hole of the glass substrate and penetrates the covering insulating layer in the thickness direction.

[0216] The covering insulating layer is preferably in direct contact with the glass substrate.

[0217] The material of the insulating coating layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0218] 32(a) to 32(c) are schematic cross-sectional views illustrating the arrangement of a first through hole in a glass substrate and a covering insulating layer in a through electrode substrate. In FIGS. 32(a) to 32(c), configurations other than the glass substrate and the covering insulating layer are omitted. As shown in FIG. 32(a), a second through hole 104c in the covering insulating layer 104 is connected to a first through hole 102c in the glass substrate 102. It is preferable that the central axis C1 of the first through hole 102c in the glass substrate 102 substantially coincides with the central axis C2 of the second through hole 104c in the covering insulating layer 104.

[0219] Furthermore, the opening diameter d2 of the second through hole 104c in the coating insulating layer 104 on the glass substrate 102 side is preferably smaller than the opening diameter d1 of the first through hole 102c on the first surface 102a side of the glass substrate 102. The ratio of d2 / d1 may be, for example, 0.5 or greater but less than 1.0, or 0.6 or greater but 0.9 or less. The opening diameter d1 of the first through hole 102c in the glass substrate 102 on the first surface 102a side may be, for example, 50 μm or greater but 100 μm or less, or 60 μm or greater but 90 μm or less. On the other hand, the opening diameter d2 of the second through hole 104c in the coating insulating layer 104 on the glass substrate 102 side is not particularly limited and may be, for example, 40 μm or greater but 85 μm or less, or 50 μm or greater but 80 μm or less.

[0220] Furthermore, it is preferable that an edge E4 of the opening of the second through hole 104c on the surface of the coating insulating layer 104 facing the glass substrate 102 is located more inward than an edge E1 of the opening of the first through hole 102c on the first surface 102c of the glass substrate 102. By arranging the coating insulating layer 104 having such a second through hole 104c, the boundary α between the glass substrate 102 and the through electrode 103 can be covered by the coating insulating layer 104.

[0221] The cross-sectional shape of the second through hole 104c in the coating insulating layer 104 is preferably an inverted tapered shape, as shown in FIG. 32(b), in which the opening diameter d2 of the second through hole 104c on the glass substrate 2 side is smaller than the opening diameter d3 of the second through hole 104c on the side opposite the glass substrate 102. When the second through hole 104c has an inverted tapered shape, the angle θ between the sidewall SS of the second through hole 104c and the surface of the coating insulating layer 104 opposite the glass substrate 102 becomes an obtuse angle in a cross-sectional view in the thickness direction of the coating insulating layer 104. Therefore, even if the through electrode 103 expands and bulges, stress concentration near the edge E3 of the opening of the second through hole 104c on the surface of the coating insulating layer 104 opposite the glass substrate 102 can be suppressed. This suppresses disconnection of the pad portion and the conductive layer arranged on the surface of the coating insulating layer opposite the glass substrate.

[0222] The angle θ is not particularly limited and may be, for example, greater than 90 degrees and less than 130 degrees, or greater than 100 degrees and less than 120 degrees. By keeping the angle θ within the above range, disconnection of the pad portion and conductive layer arranged on the surface of the covering insulating layer opposite the glass substrate can be further suppressed. On the other hand, if the angle θ is too large, the opening diameter d3 of the second through hole 104c on the side opposite the glass substrate 102 becomes large, which may make it unsuitable for high-density mounting.

[0223] 32(c), in a cross-sectional view of the coating insulating layer 104 in the thickness direction, it is preferable that an edge E3 of the opening of the second through hole 104c on the surface of the coating insulating layer 104 opposite to the glass substrate 102 has a curved surface. By having the edge E3 have a curved surface, it is possible to further suppress disconnection of the pad portion and the conductive layer arranged on the surface of the coating insulating layer opposite to the glass substrate.

[0224] The method for forming the second through holes is appropriately selected depending on the material of the covering insulating layer, and examples thereof include photolithography and laser processing. In the case of photolithography, the material of the covering insulating layer may be a photosensitive material, and a resist pattern may be formed on the covering insulating layer.

[0225] 4. First Via The first via in this embodiment is disposed in the second through hole of the covering insulating layer and is electrically connected to the through electrode, the second via, and the wiring board connection pad. The first via is preferably directly connected to the through electrode.

[0226] The first via may be a via that fills the second through hole in the covering insulating layer, a so-called filled via, or may be a via that is arranged only on the side wall of the second through hole in the covering insulating layer, a so-called conformal via.

[0227] The material of the first via is the same as the material of the through electrode, which will be described later. It is preferable that the material of the through electrode and the material of the first via are the same.

[0228] The first via can be formed, for example, by electrolytic plating. When a conductive layer of the first wiring layer (described later) is disposed on the surface of the covering insulating layer opposite the glass substrate, the first via is preferably formed simultaneously with the conductive layer of the first wiring layer. Furthermore, when the elastic insulating layer also serves as the covering insulating layer, the first via can be formed simultaneously with the wiring board connection pad portion.

[0229] 5. Glass Substrate The glass substrate in this embodiment has a first surface and a second surface opposite to the first surface, and has a first through-hole penetrating the glass substrate in the thickness direction.

[0230] Glass substrates have excellent flatness, allowing for the formation of fine wiring at narrow pitches. In addition, the thermal expansion coefficient of glass substrates can be adjusted by changing the composition, allowing for the selection of glass substrates with a desirable thermal expansion coefficient.

[0231] Examples of glass used for the glass substrate include alkali-free glass and quartz.

[0232] The thermal expansion coefficient of the glass substrate is preferably, for example, 2 ppm / ° C. to 9 ppm / ° C. If the thermal expansion coefficient of the glass substrate is within the above range, the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of the element can be sufficiently reduced.

[0233] In this specification, the thermal expansion coefficient refers to a linear expansion coefficient, which is measured by thermomechanical analysis (TMA) in accordance with JIS R3102:1995.

[0234] The shape of the glass substrate in plan view is not particularly limited, but examples thereof include rectangular shapes such as a rectangle and a square.

[0235] The planar shape of the first through hole in the glass substrate is, for example, substantially circular. The cross-sectional shape of the first through hole 102c in the glass substrate 102 can be, for example, a straight shape as shown in FIG. 23 , a reverse tapered shape in which the opening diameter on the first surface 102a side is larger than the opening diameter on the second surface 102b side as shown in FIG. 12(a), a forward tapered shape in which the opening diameter on the first surface 102a side is smaller than the opening diameter on the second surface 102b side as shown in FIG. 12(b), an hourglass shape including a portion where the diameter is minimum at a predetermined position between the first surface 102a and the second surface 102b as shown in FIG. 12(c), or a bowing shape in which the diameter is maximum at a predetermined position between the first surface 102a and the second surface 102b as shown in FIG. 12(d). FIGS. 12(a) to 12(d) are schematic cross-sectional views illustrating examples of the cross-sectional shapes of the first through hole in the glass substrate. The cross-sectional shape of the first through hole in the glass substrate is preferably either an inverted tapered shape or an hourglass shape. Furthermore, in each cross-sectional shape of the first through hole in the glass substrate, the edge E1 of the opening of the first through hole 102c on the first surface 102a of the glass substrate 102, the edge E2 of the opening of the first through hole 102c on the second surface 102b of the glass substrate 102, and the minimum and maximum diameter portions of the first through hole 102c on the glass substrate 102 preferably have curved surfaces. This can prevent disconnection between the through electrode and the via or conductive layer in contact with the through electrode.

[0236] The thickness of the glass substrate is, for example, 100 μm or more, or may be 200 μm or more, 300 μm or more, or 400 μm or more. Having a glass substrate thickness within the above range can prevent the glass substrate from warping too much. This can prevent the glass substrate from being difficult to handle during the manufacturing process or from warping due to internal stress of a thin film or the like disposed on the first or second surface of the glass substrate. On the other hand, the thickness of the glass substrate is, for example, 2000 μm or less, or may be 1000 μm or less, or may be 800 μm or less. A glass substrate thickness within the above range can shorten the time required for the process of forming through holes in the glass substrate. Specifically, the thickness of the glass substrate is 100 μm or more and 2000 μm or less, or may be 200 μm or more and 1000 μm or less, or 300 μm or more and 1000 μm or less, or 400 μm or more and 800 μm or less.

[0237] 6. Through Electrode The through electrode in this embodiment is disposed in the first through hole of the glass substrate.

[0238] The through electrode may be of any shape, as long as it can electrically connect the first and second surfaces of the glass substrate. The through electrode may be, for example, a through electrode filling the first through hole of the glass substrate, a so-called filled via, or a through electrode arranged only on the side wall of the first through hole of the glass substrate, a so-called conformal via. Furthermore, when the through electrode is a conformal via, a hollow portion may be arranged in the first through hole, or the through hole may be filled with a resin portion. In particular, since the above-mentioned problems due to thermal expansion and gas of the through electrode are likely to occur and the effects of this embodiment are fully exhibited, it is preferable that the through electrode be a so-called filled via, in which the first through hole is filled with a conductive material.

[0239] Other points regarding the through electrode are the same as those described in "A. Through electrode substrate intermediate 6. Through electrode" in the first embodiment, and therefore description thereof will be omitted here.

[0240] 7. Wiring Board Connection Pad The wiring board connection pad in this embodiment is disposed on the surface of the elastic insulating layer opposite the glass substrate and is electrically connected to the second via and the wiring board. The wiring board connection pad is directly connected to the second via without a wiring. That is, the wiring board connection pad is in direct contact with the second via. As will be described later, the wiring board connection pad of the through-hole electrode substrate in this embodiment is electrically connected to the wiring board via the second joint, so no wiring is used. That is, on the surface of the elastic insulating layer opposite the glass substrate, there is no wiring for electrically connecting the wiring board connection pad to the second via, nor is there any wiring for electrically connecting the wiring board connection pad to the wiring board.

[0241] The material of the wiring board connection pad portion is not particularly limited as long as it is a conductive material, and conductive materials used in general wiring can be used. Examples of conductive materials that can be used include metals such as copper, molybdenum, titanium, tungsten, tantalum, aluminum, gold, silver, nickel, and palladium, alloys containing at least one selected from these metals, and metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). Among these, copper is preferably used.

[0242] The shape of the wiring board connection pad portion in plan view is not particularly limited, and examples thereof include a circle, an ellipse, a square, and a rectangle.

[0243] The thickness of the wiring board connection pad is the same as that of a general wiring. The thickness of the wiring board connection pad is, for example, 0.05 μm to 100 μm, or 0.1 μm to 50 μm, or 0.2 μm to 10 μm. This allows sufficient conductivity to be obtained.

[0244] The pad portion for connecting to the wiring board can be formed by a general wiring formation method, such as a dry film formation method using PVD methods such as CVD and sputtering, or a plating method, and then patterning the conductive film by photolithography.

[0245] Furthermore, it is preferable that the wiring substrate connection pads are regularly arranged in a plan view, which makes the thermal history of the second joints electrically connecting the through electrode substrate and the wiring substrate uniform during the manufacturing process of the semiconductor device using the through electrode substrate, thereby improving the yield.

[0246] 8. First Wiring Layer The through electrode substrate in this embodiment may have a first wiring layer disposed between the covering insulating layer and the elastic insulating layer and electrically connected to the first via and the second via.

[0247] The first wiring layer includes at least a first conductive layer. The first wiring layer may further include a first interlayer insulating layer and a fourth via. The first conductive layer may be a single layer or two or more layers. When the first wiring layer includes two or more first conductive layers, the first conductive layers are stacked in the thickness direction with the first interlayer insulating layer interposed therebetween. The first conductive layers are electrically connected via the fourth via. For example, in FIG. 33 , the first wiring layer 106 includes, in order from the glass substrate 2 side, a first conductive layer 106 a, a first interlayer insulating layer 106 b, a first conductive layer 106 a, a first interlayer insulating layer 106 b, and a first conductive layer 106 a, and the first conductive layers 106 a are electrically connected by a fourth via 106 c.

[0248] The material for the first conductive layer is not particularly limited as long as it is a conductive material, and a conductive material generally used for wiring of an interposer can be used. Examples of conductive materials include metallic materials such as metals and metal oxides, conductive resins containing conductive fillers and resins, and conductive polymers.

[0249] The thickness of the first conductive layer is, for example, 0.1 μm or more, or may be 0.5 μm or more, 1 μm or more, 3 μm or more, or 5 μm or more. On the other hand, the thickness of the first conductive layer is, for example, 20 μm or less, or may be 15 μm or less. The thickness of the first conductive layer is, for example, 0.1 μm or more to 20 μm or less, or may be 0.5 μm or more to 15 μm or less, or 1 μm or more to 15 μm or less, or may be 3 μm or more to 15 μm or less, or may be 5 μm or more to 15 μm or less. For example, when the first conductive layer is formed by a sputtering method, a relatively thin first conductive layer can be obtained. Furthermore, when the first conductive layer is formed by a plating method, a relatively thick first conductive layer can be obtained.

[0250] The method for forming the first conductive layer may be an additive method or a subtractive method. In the additive method, for example, a resist pattern is formed by photolithography, and a patterned wiring layer is obtained by plating the portions exposed from the resist pattern. When using electrolytic plating, a conductive film may be formed on the first surface of the glass substrate or on the surface of the first interlayer insulating layer opposite the glass substrate before forming the resist pattern. In the subtractive method, for example, a resist pattern is formed on a conductive film formed on the entire first surface of the glass substrate, and the portions exposed from the resist pattern are etched to obtain a patterned first conductive layer.

[0251] The material of the first interlayer insulating layer is preferably an insulating resin. Examples of insulating resins include polyimide, polyamide, polyamideimide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyether ether ketone, polyether sulfone, polycarbonate, polyetherimide, epoxy resin, phenol resin, polyphenylene ether, acrylic resin, polyolefin, polycycloolefin, and liquid crystal polymer compound. Examples of polyolefins include polyethylene and polypropylene. Examples of polycycloolefins include polynorbornene.

[0252] The thickness of the first interlayer insulating layer is, for example, 1.5 μm or more, and may be 2.5 μm or more. On the other hand, the thickness of the first interlayer insulating layer is, for example, 6 μm or less. The thickness of the first interlayer insulating layer is, for example, 1.5 μm or more and 6 μm or less, and may be 2.5 μm or more and 6 μm or less.

[0253] The first interlayer insulating layer may be formed by, for example, photolithography or printing.

[0254] The fourth via is similar to the second via.

[0255] 9. Second Covering Insulating Layer and Third Via The through electrode substrate in this embodiment preferably has a second covering insulating layer disposed on the second surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate and having a fourth through hole connecting to the first through hole, and a third via disposed in the fourth through hole of the second covering insulating layer and electrically connected to the through electrode.

[0256] 34 and 35 , the through electrode substrate 1 includes a second covering insulating layer 113 disposed on the second surface 102b of the glass substrate 102 so as to cover at least the boundary β between the through electrode 103 and the glass substrate 102, the second covering insulating layer 113 having a fourth through hole 113c connected to the first through hole 102c, and a third via 114 disposed in the fourth through hole 113c of the second covering insulating layer 113 and electrically connected to the through electrode 103 and to the element connection pad portion 111. In Figures 34 and 35 , a second wiring layer 112 including a second conductive layer 112a, a second interlayer insulating layer 112b, and a fifth via 112c is disposed on the surface of the second covering insulating layer 113 opposite the glass substrate 102, and the third via 114 is electrically connected to the element connection pad portion 111 via the second conductive layer 112a and the fifth via 112c of the second wiring layer 112.

[0257] The second covering insulating layer has the same effect as the covering insulating layer. The second covering insulating layer and the third via have the same effects as the covering insulating layer and the first via, respectively.

[0258] 10. Second Wiring Layer The through electrode substrate in this embodiment may have a second wiring layer disposed on the second surface side of the glass substrate and electrically connected to the through electrodes.

[0259] The second wiring layer includes at least a second conductive layer. The second wiring layer may further include a second interlayer insulating layer and a fifth via. The second conductive layer may be a single layer or two or more layers. When the second wiring layer includes two or more second conductive layers, the second conductive layers are stacked in the thickness direction via the second interlayer insulating layer. The second conductive layers are electrically connected via the fifth via. For example, in FIGS. 34 and 35 , the second wiring layer 112 includes, in order from the glass substrate 102 side, a second conductive layer 112a, a second interlayer insulating layer 112b, a second conductive layer 112a, a second interlayer insulating layer 112b, a second conductive layer 112a, a second interlayer insulating layer 112b, and a second conductive layer 112a, and the second conductive layers 112a are electrically connected by a fifth via 112c. A second conductive layer 112 a located on the surface of the second wiring layer 112 opposite to the glass substrate 102 includes an element connection pad portion 111 .

[0260] The second conductive layer and the second interlayer insulating layer in the second wiring layer are similar to the first conductive layer and the first interlayer insulating layer in the first wiring layer.

[0261] The shape of the element connection pad portion in plan view is the same as the shape of the wiring board connection pad portion in plan view.

[0262] B. Through-hole electrode substrate with element The through-hole electrode substrate with element in this embodiment has the through-hole electrode substrate described above and an element mounted on the through-hole electrode substrate.

[0263] 24 is a schematic cross-sectional view showing an example of a through hole electrode substrate with elements in this embodiment. As shown in Fig. 24, the through hole electrode substrate with elements 20 has the above-mentioned through hole electrode substrate 101, a first bonding portion 121 electrically connected to the element connection pad portion 111 of the through hole electrode substrate 101, and an element 122 electrically connected to the first bonding portion 121.

[0264] The element-equipped through hole electrode substrate in this embodiment has the above-described through hole electrode substrate, and therefore, can suppress disconnection and improve connection reliability.

[0265] Hereinafter, the element-equipped through hole electrode substrate in this embodiment will be described for each configuration.

[0266] 1. Through-hole electrode substrates Through-hole electrode substrates have been described in detail above in "A. Through-hole electrode substrates," so a detailed description thereof will be omitted here.

[0267] 2. Element The element in this embodiment is the same as that described in "C. Element-equipped through electrode substrate 2. Element" in the first embodiment, and therefore description thereof will be omitted here.

[0268] C. Semiconductor Device The semiconductor device in this embodiment includes the aforementioned element-equipped through hole electrode substrate, and a wiring substrate electrically connected to the wiring substrate connection pads of the through hole electrode substrate.

[0269] 25 is a schematic cross-sectional view showing an example of a semiconductor device according to this embodiment. As shown in Fig. 25, a semiconductor device 130 includes the through electrode substrate 101, a first bonding portion 121 electrically connected to an element connection pad portion 111 of the through electrode substrate 101, an element 122 electrically connected to the first bonding portion 121, a second bonding portion 131 electrically connected to a wiring substrate connection pad 109 of the through electrode substrate 1, and a wiring substrate 132 electrically connected to the second bonding portion 131.

[0270] The semiconductor device in this embodiment has the element-equipped through electrode substrate described above, and therefore can suppress disconnection and improve connection reliability.

[0271] Hereinafter, the semiconductor device according to this embodiment will be described in detail for each of its components.

[0272] 1. Element-Attached Through Electrode Substrate The element-attached through electrode substrate has been described in detail above in "B. Element-Attached Through Electrode Substrate," and therefore a detailed description thereof will be omitted here.

[0273] 2. Wiring Board As the wiring board in this embodiment, a general wiring board can be used.

[0274] The wiring board is electrically connected to the wiring board connection pad portion of the through electrode substrate via a second bonding portion.

[0275] The material of the second joint portion is the same as the material of the first joint portion.

[0276] 3. Applications Applications of the semiconductor device in this embodiment are not particularly limited, and examples thereof include notebook personal computers, tablet terminals, mobile phones, smartphones, digital video cameras, digital cameras, digital clocks, and servers.

[0277] The present disclosure is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present disclosure and that provides similar effects is included within the technical scope of the present disclosure.

[0278] The present disclosure provides the following inventions: [1] A through electrode substrate intermediate comprising: a glass substrate having a first surface and a second surface opposite the first surface and having a through hole, a through electrode arranged in the through hole of the glass substrate, an elastic insulating layer arranged on the first surface side of the glass substrate, a via penetrating the elastic insulating layer and electrically connected to the through electrode, a via pad arranged on the surface of the elastic insulating layer opposite the glass substrate and electrically connected to the via, and a wiring board connection pad arranged on the surface of the elastic insulating layer opposite the glass substrate and electrically connected to a wiring board, wherein the elastic insulating layer has an uneven shape including a plurality of protrusions and a plurality of recesses on the surface facing the via pad and the wiring board connection pad. [2] The through electrode substrate intermediate according to [1], comprising: a covering insulating layer disposed between the glass substrate and the elastic insulating layer so as to cover at least the boundary between the through electrode and the glass substrate, and having a second through hole connected to the through hole; and a second via disposed in the second through hole of the covering insulating layer, electrically connected to the through electrode and electrically connected to a via pad portion. [3] The through electrode substrate intermediate according to [2], wherein the elastic insulating layer also serves as the covering insulating layer, and the via also serves as the second via. [4] The through electrode substrate intermediate according to any of [1] to [3], comprising: an element connection pad portion disposed on the second surface side of the glass substrate, electrically connected to the through electrode, and electrically connected to an element. [5] A through-hole electrode substrate intermediate according to any one of [1] to [4], comprising: a second covering insulating layer disposed on the second surface side of the glass substrate so as to cover at least the boundary between the through-hole and the glass substrate, and having a third through hole connected to the through hole, and a third via disposed in the third through hole of the second covering insulating layer and electrically connected to the through-hole. [6] A through-hole electrode substrate comprising: the through-hole electrode substrate intermediate according to any one of [1] to [5], and a bellows-shaped portion having a plurality of peaks and a plurality of valleys, which is disposed on the surface of the through-hole electrode substrate intermediate facing the elastic insulating layer, and which electrically connects the via pad portion and the wiring board connection pad portion.[7] A through electrode substrate with an element, comprising the through electrode substrate according to [6] and an element mounted on the through electrode substrate. [8] A semiconductor device comprising the through electrode substrate with an element according to [7] and a wiring substrate electrically connected to the wiring substrate connection pads of the through electrode substrate. [9] A through electrode substrate comprising: a glass substrate having a first surface and a second surface opposite the first surface and having a first through hole, a through electrode disposed in the first through hole of the glass substrate, a covering insulating layer disposed on the first surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate and having a second through hole connecting to the first through hole, a first via disposed in the second through hole of the covering insulating layer and electrically connected to the through electrode, an elastic insulating layer disposed on the surface of the covering insulating layer opposite the glass substrate and having a third through hole, a second via disposed in the third through hole of the elastic insulating layer and electrically connected to the first via, and a wiring board connection pad portion disposed on the surface of the elastic insulating layer opposite the covering insulating layer and electrically connected to the second via and to a wiring board.

[10] The through electrode substrate according to [9], wherein the elastic insulating layer has an uneven shape including a plurality of protrusions and a plurality of recesses on a surface facing the wiring board connection pad portion.

[11] The through-hole electrode substrate according to [9] or

[10] , wherein the cross-sectional shape of the second through-hole in the thickness direction of the covering insulating layer is an inverted tapered shape.

[12] The through-hole electrode substrate according to any of [9] to

[11] , wherein, in the cross-sectional view in the thickness direction of the covering insulating layer, the edge of the opening of the second through-hole on the surface of the covering insulating layer opposite to the glass substrate has a curved surface.

[13] The through-hole electrode substrate according to any of [9] to

[12] , wherein the elastic insulating layer also serves as the covering insulating layer, and the second via also serves as the first via.

[14] The through-hole electrode substrate according to any of [9] to

[13] , wherein the through-hole electrode substrate has an element connection pad portion arranged on the second surface side of the glass substrate, electrically connected to the through-hole electrode, and electrically connected to an element.

[15] A through hole electrode substrate according to any of [9] to

[14] , comprising: a second covering insulating layer disposed on the second surface side of the glass substrate so as to cover at least the boundary between the through hole and the glass substrate and having a fourth through hole connected to the first through hole; and a third via disposed in the fourth through hole of the second covering insulating layer and electrically connected to the through hole.

[16] A through hole electrode substrate with an element, comprising: the through hole electrode substrate according to any of [9] to

[15] ; and an element mounted on the through hole electrode substrate.

[17] A semiconductor device comprising: the through hole electrode substrate with an element according to

[16] ; and a wiring board electrically connected to a wiring board connection pad of the through hole electrode substrate.

[0279] REFERENCE SIGNS LIST 1 ... through electrode substrate intermediate 2, 102 ... glass substrate 2a, 102a ... first surface of glass substrate 2b, 102b ... second surface of glass substrate 3, 103 ... through electrode 4 ... first wiring layer 4a ... conductive layer 5 ... elastic insulating layer 6 ... via 7 ... via pad portion 8 ... wiring substrate connection pad portion 9 ... uneven shape 9a ... convex portion 9b ... concave portion 11 ... element connection pad portion 15 ... covering insulating layer 16 ... second via 17 ... second covering insulating layer 18 ... third via 20 ... through electrode substrate 21 ... bellows-shaped portion 21a ... ridge portion 21b ... valley portion 22 ... bellows wiring layer 30 ... through electrode substrate with element 31 ... first bonding portion 32 ... element 40 ... semiconductor device 41 ... second bonding portion 42 ... wiring substrate 101 ... through electrode substrate 104 ... covering insulating layer 104c ... second through hole 105 ... first via 106 ... first wiring layer 106a ... first conductive layer 106b ... first interlayer insulating layer 106c ... fourth via 107 ... elastic insulating layer 107c ... third through hole 108 ... second via 109 ... wiring substrate connection pad portion 110 ... uneven shape 110a ... convex portion 110b ... concave portion 111 ... element connection pad portion 112 ... second wiring layer 112a ... second conductive layer 112b ... second interlayer insulating layer 112c ... fifth via 113 ... second covering insulating layer 113c ... fourth through hole 114 ... third via 120 ... element-attached through electrode substrate 121 ... First bonding portion 122: element 130: semiconductor device 131: second bonding portion 132: wiring substrate

Claims

1. A through electrode substrate intermediate comprising: a glass substrate having a first surface and a second surface opposite to the first surface, the glass substrate having a through hole; a through electrode disposed in the through hole of the glass substrate; an elastic insulating layer disposed on the first surface side of the glass substrate; a via penetrating the elastic insulating layer and electrically connected to the through electrode; a via pad disposed on the surface of the elastic insulating layer opposite to the glass substrate and electrically connected to the via; and a wiring substrate connection pad disposed on the surface of the elastic insulating layer opposite to the glass substrate and electrically connected to a wiring substrate, wherein the elastic insulating layer has an uneven shape including a plurality of convex portions and a plurality of concave portions on the surface facing the via pad portion and the wiring substrate connection pad portion.

2. The through electrode substrate intermediate body according to claim 1, comprising: a covering insulating layer disposed between the glass substrate and the elastic insulating layer so as to cover at least the boundary between the through electrode and the glass substrate, and having a second through hole connected to the through hole; and a second via disposed within the second through hole of the covering insulating layer, electrically connected to the through electrode, and electrically connected to a via pad portion.

3. The through electrode substrate intermediate according to claim 2, wherein the elastic insulating layer also serves as the covering insulating layer, and the via also serves as the second via.

4. The through electrode substrate intermediate according to claim 1, further comprising an element connection pad portion disposed on the second surface side of the glass substrate, electrically connected to the through electrode, and electrically connected to an element.

5. The through electrode substrate intermediate body according to claim 1, comprising: a second covering insulating layer disposed on the second surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate, and having a third through hole connected to the through hole; and a third via disposed within the third through hole of the second covering insulating layer and electrically connected to the through electrode.

6. A through electrode substrate comprising: a through electrode substrate intermediate according to any one of claims 1 to 5; and a bellows wiring layer arranged on the surface of the through electrode substrate intermediate facing the elastic insulating layer, the bellows-shaped portion having a plurality of peaks and a plurality of valleys, and electrically connecting the via pad portion and the wiring substrate connection pad portion.

7. A through electrode substrate with an element, comprising: the through electrode substrate according to claim 6; and an element mounted on the through electrode substrate.

8. A semiconductor device comprising: the element-equipped through electrode substrate according to claim 7; and a wiring substrate electrically connected to the wiring substrate connection pads of said through electrode substrate.

9. A through electrode substrate comprising: a glass substrate having a first surface and a second surface opposite to the first surface, the glass substrate having a first through hole; a through electrode disposed in the first through hole of the glass substrate; a covering insulating layer disposed on the first surface side of the glass substrate so as to cover at least a boundary between the through electrode and the glass substrate and having a second through hole connecting to the first through hole; a first via disposed in the second through hole of the covering insulating layer and electrically connected to the through electrode; an elastic insulating layer disposed on a surface side of the covering insulating layer opposite to the glass substrate, the elastic insulating layer having a third through hole; a second via disposed in the third through hole of the elastic insulating layer and electrically connected to the first via; and a wiring substrate connection pad portion disposed on a surface side of the elastic insulating layer opposite to the covering insulating layer, electrically connected to the second via, and electrically connected to a wiring substrate.

10. The through electrode substrate according to claim 9, wherein the elastic insulating layer has an uneven shape including a plurality of protrusions and a plurality of recesses on the surface facing the wiring board connection pad portion.

11. The through electrode substrate according to claim 9, wherein the cross-sectional shape of the second through hole in the thickness direction of the covering insulating layer is an inverted tapered shape.

12. The through electrode substrate according to claim 9, wherein, in a cross-sectional view in the thickness direction of the covering insulating layer, the edge of the opening of the second through hole on the surface of the covering insulating layer opposite the glass substrate has a curved surface.

13. The through electrode substrate according to claim 9, wherein the elastic insulating layer also serves as the covering insulating layer, and the second via also serves as the first via.

14. The through electrode substrate according to claim 9, further comprising an element connection pad portion disposed on the second surface side of the glass substrate, electrically connected to the through electrode, and electrically connected to an element.

15. A through electrode substrate as described in claim 9, comprising: a second covering insulating layer disposed on the second surface side of the glass substrate so as to cover at least the boundary between the through electrode and the glass substrate and having a fourth through hole connecting to the first through hole; and a third via disposed within the fourth through hole of the second covering insulating layer and electrically connected to the through electrode.

16. A through electrode substrate with an element, comprising: a through electrode substrate according to any one of claims 9 to 15; and an element mounted on the through electrode substrate.

17. A semiconductor device comprising: a through electrode substrate with an element according to claim 16; and a wiring substrate electrically connected to the wiring substrate connection pads of said through electrode substrate.