Phase change material, storage chip, and device

Abstract

Disclosed in embodiments of the present application are a phase change material, a storage chip, and a device, which are used for optimizing the performance of a phase change material, thus improving the product competitiveness of a phase change storage device. The composition of the phase change material comprises GexSbyTez, wherein 2 / 3≤y:x≤6, 0.5*(x+1.5y)≤z<(x+1.5y), a doping element comprises one or more metal elements, the one or more metal elements include M, M comprises at least one element of Zr, Zn, and Sn, and the doping concentration of M is greater than 1% and less than or equal to 18%.

Description

Phase change material, memory chip and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 16, 2023, with application number 202310725887.X and invention name “A phase change material, memory chip and device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a phase change material, a storage chip and a device. Background Art

[0003] With the widespread adoption of technologies such as mobile internet, cloud computing, big data, deep learning, and the Internet of Things, the market demand for low-latency, high-density, and large-capacity storage technologies is rapidly growing. Phase-change storage technology based on phase-change materials has emerged as the answer to this question. Phase-change materials can undergo a reversible phase change driven by thermal effects (such as electric pulses). The resistivity of phase-change materials before and after the phase change varies significantly, allowing them to switch between different resistance states. Phase-change storage technology utilizes the reversible change of phase-change materials between different resistance states to store different data states.

[0004] Phase change materials have the potential for high-density three-dimensional stacking, which is conducive to high-density data storage. However, there is still much room for optimization in terms of the crystallization speed and fatigue performance of phase change materials.

[0005] Summary of the Invention

[0006] The present application provides a phase change material, a memory chip, and a device for optimizing the performance of the phase change material, thereby improving the product competitiveness of the phase change memory device.

[0007] Based on numerous comparative experiments, this application provides phase-change materials and phase-change memory devices with superior performance. To more comprehensively and accurately evaluate the performance of each phase-change material, the aforementioned experiments not only prepared a large number of germanium-antimony-tellurium (Ge-Sb-Te, GST)-based phase-change materials with varying compositions, but also fabricated a large number of phase-change memory devices based on these prepared phase-change materials.

[0008] By testing and comparing the performance of the phase change materials and phase change memory devices prepared in the above experiments, the first aspect provides several GST-based phase change materials with better performance. The composition of the phase change material includes Ge x Sb y Te z, wherein, 2 / 3≤y:x≤6,0.5*(x+1.5y)≤z<(x+1.5y), the doped elements include one or more metal elements, the one or more metal elements include M, M includes at least one element of zirconium (Zr), zinc (Zn) and tin (Sn), and the doping concentration of M is greater than 1% and less than or equal to 18%.

[0009] The phase change material has better performance. For example, the phase change material has a faster phase change speed, and the resistance state conversion delay can be less than 200ns. For example, the phase change material has a longer fatigue life (for example, a fatigue life of the 6th power or even the 7th power or more). The difference between the resistivity of the phase change material in the crystalline state and its resistivity in the amorphous state is greater. For example, the resistivity of the phase change material in the crystalline state is more than 2 orders of magnitude lower than the resistivity in the amorphous state.

[0010] Optionally, 3≤y:x≤5, the phase change material has good comprehensive performance in speed and fatigue.

[0011] Optionally, 0.7*(x+1.5y)≤z≤0.95*(x+1.5y). The phase change material has stronger adhesion to the electrode layer (especially tungsten), which is beneficial for improving the bonding between the phase change material and the electrode in the phase change memory device, thereby improving the yield of the phase change memory device.

[0012] Optionally, the doping concentration of M is greater than 1% and less than 10%. The phase change material can have better performance.

[0013] Optionally, the doping concentration of M is greater than 1% and less than 4%, which is beneficial to reducing the driving voltage required for the phase change of the phase change material.

[0014] Optionally, the doped elements further include one or more non-metallic elements. Continuing to dope one or more non-metallic elements into the M-doped GeXeXbYTez is beneficial to optimizing the performance of the phase change material.

[0015] Optionally, the doping concentration of the one or more non-metallic elements is greater than 1% and less than 4%. Doping with non-metallic elements has a more significant effect on improving the performance of the phase change material.

[0016] Optionally, the one or more non-metallic elements include at least one of nitrogen (N), carbon (C), oxygen (O), silicon (Si), and boron (B). The prepared phase change material is advantageous in having smaller grains, which is advantageous in increasing the phase change speed of the phase change material.

[0017] Optionally, the one or more metal elements further include at least one of the following metal elements: indium (In), hafnium (Hf), gallium (Ga), chromium (Cr), aluminum (Al), scandium (Sc), yttrium (Y), tantalum (Ta), erbium (Er), lutetium (Lu), holmium (Ho), thulium (Tm), dysprosium (Dy), terbium (Tb), calcium (Ca), neodymium (Nd), praseodymium (Pr), ytterbium (Yb), and cerium (Ce). This is beneficial for optimizing the performance of the phase change material.

[0018] Optionally, the phase change material is a thin film with a thickness greater than or equal to 5 nanometers and less than or equal to 200 nanometers.

[0019] In a second aspect, the present application provides a memory chip comprising one or more memory cells; the memory cell comprises a first electrode, a phase change memory structure, and a second electrode stacked in sequence, wherein the phase change memory structure comprises the phase change material as described in the first aspect or any possible implementation of the first aspect.

[0020] In a third aspect, the present application provides a storage device, comprising a controller and at least one storage chip as described in the second aspect, wherein the storage chip is used to store data, and the controller is used to write data to the storage chip or read data from the storage chip.

[0021] In a fourth aspect, the present application provides an electronic device, comprising a processor and at least one storage device as described in the third aspect, wherein the processor is used to write data to the storage device or read data from the storage device.

[0022] The devices provided in the second to fourth aspects of the examples of this application are prepared using the phase change material provided in the first aspect. Therefore, the beneficial effects of the devices provided in the second to fourth aspects of the examples of this application can refer to the beneficial effects of the first aspect or any implementation method of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 schematically shows a cross-sectional view of a phase change material provided by the present application;

[0024] FIG2 schematically shows the resistance-temperature curve of Zn16%-Ge1Sb4Te6.5 thin film heating;

[0025] FIG3 schematically shows the resistance-temperature curve of Sn13%-Ge1Sb4Te6.5 thin film heating;

[0026] FIG4-1 schematically shows a possible cross-sectional view of a storage unit provided in the present application;

[0027] FIG4-2( a ) schematically shows another possible cross-sectional view of a storage unit provided in the present application;

[0028] FIG4-2( b ) schematically shows another possible cross-sectional view of the storage unit provided by the present application;

[0029] FIG5-1 and FIG5-2 schematically illustrate a possible top view and an oblique view of the memory chip provided by the present application, respectively;

[0030] FIG6 schematically illustrates another possible structure of the memory chip provided by the present application;

[0031] FIG7 schematically illustrates a possible structure of a storage device provided by the present application;

[0032] FIG8 schematically illustrates a possible structure of the electronic device provided in this application. DETAILED DESCRIPTION

[0033] The present application provides a phase change material. The phase change material can be used to make a phase change memory device. The phase change memory device utilizes the reversible change of the phase change material between different resistance states to store different data states. In practical applications, phase change memory devices bridge the performance gap between dynamic random access memory (DRAM) and flash memory, offering advantages such as high read speed, high erasable and write cycles, non-volatility, small component size, low power consumption, and resistance to strong vibration and radiation, leading to their widespread use.

[0034] Phase change materials can undergo reversible phase change under the driving force of thermal action. The resistivity of phase change materials before and after the phase change is greatly different, so phase change materials can switch between different resistance states.

[0035] For example, heating a phase-change material with electric pulse 1 can cause it to transform from an amorphous state to a crystalline state. Crystallization refers to the process by which the atomic structure of a material changes from disorder to an ordered arrangement. The resistivity of a phase-change material in the amorphous state is much higher than that in the crystalline state. Heating the phase-change material with electric pulse 1 can cause it to transform from a high-resistance state to a low-resistance state. This process is called set (SET), and the low-resistance state can correspond to the "1" state in a computer. Heating the phase-change material with electric pulse 2 can cause it to transform from a crystalline state to an amorphous state, and from a low-resistance state to a high-resistance state. This process is called reset (RESET), and the high-resistance state can correspond to the "0" state in a computer. The change in the resistance of the phase-change material can represent a single bit of data, "0" or "1."

[0036] This application does not limit the method of thermal action, nor the number of different resistance states that the phase change material can experience. The phase change material can be driven by thermal action to switch between more resistance states (or data states) to represent more bits of data.

[0037] GST-based phase change materials (PCMs) are currently the mainstream phase change materials. The composition of GST-based PCMs affects their performance. Different components of GST-based PCMs can include at least one of the following: different ratios between any two of the three elements Ge, Sb, and Te; different doping elements in the GST-based PCMs; and different doping concentrations in the GST-based PCMs.

[0038] The performance of phase change materials is not only reflected in the performance of the phase change material itself, such as the phase change speed and crystallization temperature of the phase change material, but also in the performance of the phase change memory device it is composed of, such as the operating speed and lifespan of the phase change memory device. The phase change speed of the phase change material is related to the time delay of the phase change material switching between different resistance states (referred to as the resistance state conversion delay). The longer the resistance state conversion delay, the slower the phase change speed. Conversely, the shorter the resistance state conversion delay, the faster the phase change speed. Currently, the set delay of most GST-based phase change materials is over 100 nanoseconds, which restricts the application of phase change memory technology in storage-level memory.

[0039] Based on a large number of comparative experiments, this application provides phase change materials and phase change memory devices with superior performance. In order to more comprehensively and accurately evaluate the performance of each phase change material, in the above experiments, not only a large number of GST-based phase change materials with different components were prepared, but also a large number of phase change memory devices were prepared based on the prepared phase change materials. By testing and comparing the performance of the various phase change materials and phase change memory devices prepared in the above experiments, several GST-based phase change materials with superior performance are provided below.

[0040] The phase change material provided in this application includes GexSbyTez doped with one or more elements. By adjusting the ratio between the three elements Ge, Sb, and Te, and changing the type and concentration of the doped elements, it is found that when 2 / 3≤y:x≤6,0.5*(x+1.5y)≤z<(x+1.5y), at least one metal element (called M) selected from Zr, Zn, and Sn is doped, and the doping concentration of M is greater than 1% and less than or equal to 18%, the phase change material has better performance, for example, the phase change material has a faster phase change speed, and the resistance state conversion delay can be less than 200ns. For example, the resistivity of the phase change material in the crystalline state is more than 2 orders of magnitude lower than its resistivity in the amorphous state. For example, the phase change material has a longer fatigue life (such as a fatigue life of more than 7 times).

[0041] The present application does not limit the preparation method of the phase change material. For example, the GST-based phase change material can be prepared by magnetron sputtering, magnetron reactive sputtering, electron beam evaporation, atomic layer deposition, chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0042] When the phase change material is prepared by magnetron sputtering or magnetron reactive sputtering, a single or multiple targets can be used. Optionally, the phase change material is prepared by using Ge in an inert gas atmosphere. x Sb y Te z Optionally, the phase change material is formed by sputtering an alloy target of Ge in an inert gas atmosphere. x Sb y Te z The alloy target and the elemental target or alloy target are co-sputtered. Alternatively, the phase change material is formed by co-sputtering a GeSb alloy target, a Sb2Te3 alloy target, and an elemental target under an inert gas atmosphere. Alternatively, the phase change material is formed by co-sputtering a Ge elemental target, a Sb elemental target, a Te elemental target, and an elemental target under an inert gas atmosphere.

[0043] This application does not limit the phase change bulk material (such as Ge x Sb y Te z ) doping method, for example, the doping element (such as M) can be doped into the phase change body material through a thermal diffusion process or an ion implantation process to form a phase change material.

[0044] The thermal diffusion process can be understood as the deposition and diffusion of a gaseous impurity source in a high-temperature gas phase environment, allowing the dopant element to be incorporated into the phase-change material. In practice, the higher the concentration of the dopant element, the faster the diffusion; the higher the temperature, the faster the diffusion.

[0045] The ion implantation process can be understood as utilizing the high-energy ion state of impurities to implant into a certain position of the material to be doped (eg, a phase change bulk material), and annealing to activate the implanted atoms, thereby completing the doping.

[0046] When the phase-change material includes multiple doping elements, the multiple doping elements can be doped into the phase-change bulk material using the same or different processes.

[0047] The present application does not limit the morphology of the phase change material. For example, the phase change material is the phase change material layer 101 shown in Figure 1. The phase change material layer 101 can be a continuous film or a discontinuous film. The present application does not limit the thickness of the phase change material layer 101. For example, the phase change material layer 101 is greater than or equal to 5 nm and less than or equal to 200 nm.

[0048] Optionally, 3≤y:x≤5. By further adjusting the ratio of y to x to 3≤y:x≤5, it is found that the phase change speed of the phase change material is increased by at least two times, and the phase change memory device prepared based on the phase change material has a good combination of speed and fatigue resistance.

[0049] Optionally, 0.7*(x+1.5y)≤z≤0.95*(x+1.5y). By further adjusting the ratio of z to 0.7*(x+1.5y)≤z≤0.95*(x+1.5y), more specifically, further adjusting the ratio of z to 0.7*(x+1.5y)≤z≤0.75*(x+1.5y), or 0.77*(x+1.5y)≤z≤0.8*(x+1.5y), or 0.83*(x+1.5y)≤z≤0.88*(x+1.5y), or 0.9*(x+1.5y)≤z≤0.95*(x+1.5y), it is found that the phase change material has stronger adhesion to the electrode layer (especially tungsten), which is beneficial to improving the bonding between the phase change material and the electrode in the phase change memory device, thereby improving the yield of the phase change memory device.

[0050] The following examples introduce several components of the phase change material and the test results of the phase change material.

[0051] For example, the phase change material can be a Zn16%-Ge1Sb4Te6.5 thin film. "Zn16%" means that the doping element in Ge1Sb4Te6.5 is Zn, and the Zn doping concentration is 16%. The following example describes the preparation method of the thin film.

[0052] The Zn16%-Ge1Sb4Te6.5 thin film can be obtained using a magnetron sputtering process. Specifically, a Zn target and a GeSbTe target can be co-sputtered. The sputtering parameters for the Zn target are RF 25W, the sputtering parameters for the GeSbTe target are DC 70W, the argon flow rate is 30sccm, the initial vacuum is 2e-6Torr, and the vacuum during sputtering is 5e-3Torr. After both the Zn and GeSbTe targets are ignited, the shutter is opened for sputtering after one minute. The sputtering time is 5 minutes, and the film thickness is 140nm. Energy dispersive spectrometer (EDS) testing shows that the film composition is Zn16%-Ge1Sb4Te6.5.

[0053] Figure 2 schematically illustrates the resistance-temperature curves of a Zn16%-Ge1Sb4Te6.5 thin film during heating. In Figure 2, Curve 2-1 schematically illustrates the change in resistance of the Zn16%-Ge1Sb4Te6.5 thin film with temperature during heating, and Curve 2-2 schematically illustrates the change in resistance of the Zn16%-Ge1Sb4Te6.5 thin film with temperature during cooling.

[0054] Referring to Figure 2 , during the heating process, the Zn16%-Ge1Sb4Te6.5 film was heated at a rate of 30°C / min, reaching a maximum temperature of 400°C. The as-deposited resistance of the Zn16%-Ge1Sb4Te6.5 film exceeded eight orders of magnitude (i.e., E8). The crystallization temperature of the film is approximately 240°C. After crystallization, the film's resistance decreased by more than three orders of magnitude, ultimately reaching a crystalline resistance of two orders of magnitude (i.e., E2). This demonstrates that the Zn16%-Ge1Sb4Te6.5 film exhibits a superior high-to-low resistance ratio.

[0055] The above test results show that increasing the Sb and Te content in the GST-based phase-change material to obtain Ge1Sb4Te6.5 is beneficial for improving the phase change speed of the phase-change material. On this basis, by doping the low-melting-point element Zn, the phase-change material has a relatively low melting point, thereby reducing its operating power consumption, which is beneficial for reducing element segregation caused by electric fields and temperature, thereby improving its fatigue life. Therefore, Zn-doped Ge1Sb4Te6.5 has both high speed and high fatigue potential.

[0056] For example, the phase change material may be a Sn13%-Ge1Sb4Te6.5 thin film. "Sn13%" means that the doping element in Ge1Sb4Te6.5 is Sn, and the doping concentration of Sn is 13%.

[0057] The Sn13%-Ge1Sb4Te6.5 thin film can be produced using a magnetron sputtering process. Specifically, a Sn target and a GeSbTe target can be co-sputtered. The sputtering parameters for the Sn target are DC 7W, and the sputtering parameters for the GeSbTe target are DC 46W. The initial vacuum level is 2e-6 Torr, and the vacuum level during sputtering is 5e-3 Torr. After both the Sn and GeSbTe targets are ignited, the shutter is opened for one minute before sputtering. The sputtering time is 5 minutes, and the film thickness is 80 nm. EDS testing confirms the film composition is Sn13%-Ge1Sb4Te6.5.

[0058] Figure 3 schematically illustrates the resistance-temperature curves of a Sn13%-Ge1Sb4Te6.5 thin film during heating. In Figure 3, Curve 3-1 schematically illustrates the change in resistance of the Sn13%-Ge1Sb4Te6.5 thin film with temperature during heating, and Curve 3-2 schematically illustrates the change in resistance of the Sn13%-Ge1Sb4Te6.5 thin film with temperature during cooling.

[0059] Referring to Figure 3, the Sn13%-Ge1Sb4Te6.5 film was heated at a rate of 30°C / min, reaching a maximum temperature of 400°C, resulting in a crystallization temperature of approximately 170°C. The as-deposited resistance of the film was approximately six orders of magnitude (i.e., E6). After crystallization, the resistance decreased by more than two orders of magnitude, ultimately reaching a crystalline resistance of two orders of magnitude (i.e., E2), demonstrating that the Sn13%-Ge1Sb4Te6.5 film has a good high-to-low resistance ratio.

[0060] The above test results show that in the GST-based phase change material, Ge1Sb4Te6.5 is obtained by increasing the content of Sb and Te, which is beneficial to improving the phase change speed of the phase change material. On this basis, doping with the low-melting-point element Sn makes Ge1Sb4Te6.5 have a relatively low melting point, thereby reducing its operating power consumption, which is beneficial to reducing the element segregation caused by the electric field and temperature, thereby improving its fatigue life. At the same time, Sn doping can increase the number of four-membered rings in the GeSbTe material system and increase the crystallization speed. Therefore, Sn-doped Ge1Sb4Te6.5 has both high speed and high fatigue potential.

[0061] For example, the phase change material may be a Zr18%-Ge1Sb4Te6.5 thin film. “Zr18%” means that the doping element in Ge1Sb4Te6.5 is Zr, and the doping concentration of Zr is 18%.

[0062] Similarly, Zr18%-Ge1Sb4Te6.5 thin films can be prepared using magnetron sputtering. The sputtering method used is co-sputtering of a Zr target and GeSbTe, with the Zr target sputtering parameters being DC 10W and the GeSbTe target sputtering parameters being DC 23W. The initial vacuum level is 2e-6 Torr, and the vacuum level during sputtering is 5e-3 Torr. After both the Zr and GeSbTe targets are ignited, the shutter is opened for one minute before sputtering. The sputtering time is 10 minutes, and the film thickness is 100 nm. EDS analysis confirms the film composition as Zr18%-Ge1Sb4Te6.5.

[0063] Measurements of the resistance-temperature curves of Zr18%-Ge1Sb4Te6.5 thin films during heating reveal that increasing the Sb and Te content in GST-based phase-change materials to produce Ge1Sb4Te6.5 enhances the phase transition speed of the material. Furthermore, Zr doping increases the number of four-membered rings in the GST-based phase-change material system, accelerating crystallization. Therefore, Zr18%-Ge1Sb4Te6.5 exhibits high-speed potential.

[0064] Optionally, the doping concentration of M is greater than 1% and less than 10%. By adjusting the doping concentration of M in the phase change material to greater than 1% and less than 10%, it is found that the phase change material can have better performance.

[0065] Optionally, the doping concentration of M is greater than 1% and less than 4%. By further reducing the doping concentration of M in the phase change material to greater than 1% and less than 4%, it is beneficial to reduce the driving voltage required for the phase change of the phase change material, for example, reducing the voltage of the electric pulse 2 mentioned above.

[0066] Optionally, the doped elements also include one or more non-metallic elements. By further doping other elements into the M-doped GexSbyTez and testing the properties of the corresponding phase-change materials, it was found that further doping of the M-doped GexSbyTez with one or more non-metallic elements is beneficial for optimizing the performance of the phase-change material.

[0067] Optionally, the one or more non-metallic elements include at least one of N, C, O, Si, and B. When the doped non-metallic element includes at least one of N, C, O, Si, and B, the prepared phase change material is advantageous in having smaller grains, which is advantageous in increasing the phase change speed of the phase change material. When the doped non-metallic element includes N and / or O, in addition to achieving N and / or O doping by doping the corresponding elements into the target material, N and / or O doping can also be achieved by doping the corresponding elements into the sputtering gas environment.

[0068] Optionally, the doping concentration of the one or more non-metallic elements is greater than 1% and less than 4%. By adjusting the doping concentration of the non-metallic elements and testing the performance of the corresponding phase change material, it was found that when the doping concentration of the non-metallic elements is greater than 1% and less than 4%, the effect of doping with the non-metallic elements on improving the performance of the phase change material is more significant.

[0069] Optionally, the one or more metal elements further include at least one of the following metal elements: In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, Ca and Ce.

[0070] By continuing to dope other metal elements into M-doped GexSbyTez and testing the performance of the corresponding phase change materials, it was found that continuing to dope at least one metal element among In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb and Ce into M-doped GexSbyTez is beneficial to optimizing the performance of the phase change material.

[0071] The present application also provides a target material, the composition of which may be the same as that of any of the above-mentioned phase change materials, and the above-mentioned phase change materials may be prepared by using the target material. For example, the composition of the target material is Ge1Sb4Te6, or Zn16%-Ge1Sb4Te6.5.

[0072] The above-mentioned phase change material can be applied to any electronic device. The present application does not limit the type of the electronic device, as long as the electronic device has a storage function. The following examples introduce several possible electronic devices.

[0073] Based on the above-mentioned phase change material with superior performance, the present application provides a storage device with superior performance. Optionally, the storage device is a memory chip. The memory chip includes one or more memory cells. The memory cell includes a phase change memory (PCM) memory cell, which includes a first electrode, a phase change memory structure, and a second electrode stacked in sequence. The phase change memory structure may include any of the phase change materials provided above.

[0074] Taking the phase change memory structure as the phase change material layer shown in Figure 1 as an example, Figure 4-1 schematically shows a possible structure of a memory cell. Referring to Figure 4-1, the memory cell is a PCM memory cell 111, which includes a first electrode 100, a phase change material layer 101, and a second electrode 200 stacked in sequence. The PCM memory cell 111 can be driven by a pulse voltage or a pulse current to switch between at least two resistance states, thereby realizing multi-value storage. In addition, the resistance change amplitude between different resistance states of the PCM memory cell 111 is more than two orders of magnitude, the resistance state conversion delay is less than 200ns, and it has a long fatigue life (e.g., a fatigue life of more than 6).

[0075] The present application does not limit the type of the PCM storage unit 111 . For example, the PCM storage unit 111 may be a T-type storage unit, a μ-type storage unit, or a restricted-type storage unit.

[0076] Optionally, different from the PCM memory cell shown in FIG4-1 , the phase change memory structure may include, in addition to the phase change material layer 101 , a buffer layer between the phase change material layer 101 and the first electrode, and a buffer layer between the phase change material and the second electrode.

[0077] Optionally, the memory cell may be as shown in FIG4-2(a). Unlike the PCM memory cell 111 shown in FIG4-1, as shown in FIG4-2(a), the memory cell 1121 includes, in addition to the PCM memory cell, a gating layer 102 located above the second electrode 200 and a third electrode 300 located above the gating layer 102. Alternatively, the gating layer 102 may be located below the first electrode 100, and the third electrode 300 may be located below the gating layer 102. Continuing with reference to FIG4-2(a), a buffer layer 1011 may be further provided between the phase-change material layer 101 and the first electrode 100, and between the phase-change material layer 101 and the second electrode 200. Similarly, a buffer layer 1021 may be provided between the gating layer 102 and the third electrode 300, and between the gating layer 102 and the second electrode 200.

[0078] Optionally, at least one buffer layer shown in FIG4-2(a) can be removed as needed. For example, the memory cell may also be as shown in FIG4-2(b). Unlike the memory cell 1121 shown in FIG4-2(a), in the memory cell 1122 shown in FIG4-2(b), no buffer layer 1021 is provided between the gate layer 102 and the third electrode 300, or between the gate layer 102 and the second electrode 200.

[0079] The memory cell shown in Figure 4-2(a) or Figure 4-2(b) with a selection layer 102 can also be considered a memory cell + one selection unit (one selector and one memory, 1S1R) integrated unit. In the memory cell 1121 shown in Figure 4-2(a) or the memory cell 1122 shown in Figure 4-2(b), the selection layer corresponds to "S" and the PCM memory cell corresponds to "R." In some cases, the buffer layer in the memory cell can be replaced with another selection unit, such as a diode or a conductive filament selection device.

[0080] The present application does not limit the materials of the first electrode 100, the second electrode 200, and the third electrode 300. For example, the material of any of the above electrodes can be a metal material, a non-metallic material, or a metal nitride, such as tungsten (W), C, Ta, (titanium nitride) TiN, TaN, WN, etc. The materials included in different electrode layers can be the same or different.

[0081] The present application does not limit the material of the buffer layer 1011 or the buffer layer 1021. For example, the material of the buffer layer can be a non-metal, such as C, or a metal or metal nitride, such as W, Ta, TiN, TaN, WN, or a metal telluride such as In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, and Ce.

[0082] The present application does not limit the method for preparing the above-mentioned memory cell. For example, the above-mentioned memory cell can be prepared by at least one method selected from magnetron sputtering, magnetron reactive sputtering, electron beam evaporation, atomic layer deposition, chemical vapor deposition, and plasma-enhanced chemical vapor deposition.

[0083] The above examples, combined with Figures 4-1, 4-2(a), and 4-2(b), illustrate possible structures of a single memory cell. Optionally, a memory chip may include multiple memory cells, and the multiple memory cells are deployed in n memory layers, where n is a positive integer. Two address line layers are provided above and below each memory layer, respectively, one of which includes multiple first address lines parallel to a first direction, and the other includes multiple second address lines parallel to a second direction. The storage density of the memory chip can be 4(F^2)*n, where F is the semiconductor process feature size.

[0084] For ease of description, this application refers to a single address line layer including multiple first address lines as a first address line layer, and a single address line layer including multiple second address lines as a second address line layer. FIG5-1 schematically illustrates a top view of a memory chip along its thickness direction. Referring to FIG5-1 , the first address line layer includes multiple first address lines 210, and the second address line layer includes multiple second address lines 310. The first direction and the second direction are non-parallel, or in other words, the angle α between the two directions is greater than 0 degrees and less than 90 degrees.

[0085] The storage layer being located between two address line layers may mean that the storage layer includes a plurality of storage cells, each of which is located in an overlapping region between the first address line and the second address line. Optionally, a buffer layer may be provided between the storage cell and the adjacent address line.

[0086] FIG5-2 schematically illustrates an oblique view of a memory chip. Referring to FIG5-2 , the memory chip is stacked from bottom to top with a second address line layer, a memory layer, a first address line layer, a memory layer, and a second address line layer. Referring to FIG5-2 , as an example, each first address line layer includes four first address lines 210, each second address line layer includes four second address lines 310, and each memory layer includes 16 memory cells 1122. Each address line layer can include more address lines, and each memory layer can include more memory cells.

[0087] FIG5-2 uses the example of a storage layer including the storage unit 1122 shown in FIG4-2(b), but the storage layer may include other types of storage units. FIG5-2 uses the example of a storage chip including two storage layers and three address line layers. Optionally, the storage chip provided in this application may include a greater number of storage layers and address line layers, or a smaller number of storage layers and address line layers.

[0088] This application does not limit all 1S1R integrated units in a memory chip to facing a single direction. Optionally, in some 1S1R integrated units in the memory chip, the gate layer 102 is located above the second electrode 200, and the third electrode 300 is located above the gate layer 102. In other 1S1R integrated units in the memory chip, the gate layer 102 may be located below the first electrode 100, and the third electrode 300 may be located below the gate layer 102.

[0089] One of the first and second address lines may be referred to as a word line (WL), and the other address line may be referred to as a bit line (BL). Memory cells connected to a WL are referred to as memory cells in a row, and memory cells connected to a BL are referred to as memory cells in a column.

[0090] This application does not limit the preparation method of WL and BL. For example, WL and BL can be formed by 20nm / 20nm equal width lines (L / S) formed after the patterning process. It should be noted that the positions of BL and WL can also be interchanged in the memory chip.

[0091] The present invention also provides a method for manufacturing a memory chip, which can be used to prepare the memory chip shown in FIG. 5-2 . The method may include S1 to S3 .

[0092] S1, forming a second address line layer, the second address line layer including a plurality of second address lines 310 parallel to each other;

[0093] S2, forming a storage layer on the second address line layer, the storage layer including a plurality of storage cells 1122;

[0094] S3. Form a first address line layer on the storage layer, where the first address line layer includes a plurality of first address lines 310 parallel to each other.

[0095] Optionally, the memory chip may include, in addition to a plurality of memory cells and a plurality of address lines, a peripheral control circuit, including a read / write (R / W) circuit, a row control circuit, and a column control circuit.

[0096] FIG6 schematically illustrates another possible structure of a memory chip. Referring to FIG6 , the memory chip includes a plurality of memory cells, a plurality of WLs, a plurality of BLs, a read / write circuit, a row control circuit, and a column control circuit. The read / write circuits are respectively connected to the row control circuit and the column control circuit, and are used to control the row control circuit / column control circuit according to the command of the processor to perform read / write operations on the selected memory cells. The row control circuits are respectively connected to one or more WLs, and are used to apply a different level value to the selected WL than to other WLs under the control of the read / write circuit, so as to select a certain row of memory cells for read / write operations. The column control circuits are respectively connected to one or more BLs, and are used to apply a different level value to the selected BL than to other BLs under the control of the read / write circuit, so as to select a certain column of memory cells for read / write operations.

[0097] Referring to Figure 6 , the row control circuit includes a voltage control circuit (denoted as VS1) and a row selection circuit. The row selection circuit is used to select the WL under the control of the read / write circuit, and the voltage control circuit is used to provide a driving voltage to the WL selected by the row selection circuit. The column control circuit includes a voltage control circuit (denoted as VS2) and a column selection circuit. The column selection circuit is used to select the BL under the control of the read / write circuit, and the voltage control circuit is used to provide a driving voltage to the BL selected by the column selection circuit. When a 1S1R integrated cell is not simultaneously selected by both the WL and the BL, the gating unit in the 1S1R integrated cell is in a closed state to prevent leakage current from affecting other 1S1R integrated cells.

[0098] Based on the aforementioned phase-change material with superior performance, the present application provides a storage device with superior performance. The storage device may include a controller and at least one storage chip described in any of the aforementioned embodiments. The storage chip is used to store data, and the controller is used to write data to the storage chip or read data from the storage chip.

[0099] For example, taking a storage device including a controller and a storage chip as an example, please refer to FIG7 , which is a schematic diagram of the structure of the storage device of the present application example.

[0100] As shown in Figure 7, a storage device 700 includes a controller 701 and at least one storage chip 702 as shown in any of the above examples. The storage chip 702 is used to store data, and the controller 701 is used to write data to the storage chip 702 or read data from the storage chip 702.

[0101] Based on the phase change material with excellent performance, the present application provides an electronic device with excellent performance. Please refer to Figure 8, which is a schematic diagram of the structure of an electronic device exemplified in the present application.

[0102] As shown in Figure 8, an electronic device 800 includes a processor 801 and a storage device 802 as shown in any of the above embodiments. The processor 801 is configured to write data to the storage device 802 or read data from the storage device 802.

[0103] It will be understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0104] In the examples of this application, the terms "first", "second", "third", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0105] In the embodiments of the present application, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower structure or an upper structure, or may have an extent smaller than that of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than that of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0106] It should be noted that the technical solutions described in the examples of this application can be combined arbitrarily unless there is any conflict.

[0107] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Based on actual needs, some or all of these units may be selected to achieve the objectives of the present embodiment, and the specifics are not limited here.

[0108] The above descriptions are merely specific examples of this application, but the scope of protection of this application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A phase change material, characterized in that: The phase change material comprises Ge x Sb y Te z , wherein 2 / 3≤y:x≤6,0.5*(x+1.5y)≤z<(x+1.5y), the doped elements include one or more metal elements, the one or more metal elements include M, M includes at least one element of Zr, Zn and Sn, and the doping concentration of M is greater than 1% and less than or equal to 18%.

2. The phase change material according to claim 1, characterized in that: The doping concentration of M is greater than 1% and less than 10%.

3. The phase change material according to claim 2, characterized in that: The doping concentration of M is greater than 1% and less than 4%.

4. The phase change material according to any one of claims 1 to 3, characterized in that: The doped elements also include one or more non-metallic elements.

5. The phase change material according to claim 4, characterized in that: The doping concentration of the one or more non-metallic elements is greater than 1% and less than 4%.

6. The phase change material according to claim 4 or 5, characterized in that: The one or more non-metallic elements include at least one element of N, C, O, Si and B.

7. The phase change material according to any one of claims 1 to 6, characterized in that: 3≤y:x≤5.

8. The phase change material according to any one of claims 1 to 7, characterized in that: 0.7*(x+1.5y)≤z≤0.95*(x+1.5y).

9. The phase change material according to any one of claims 1 to 8, characterized in that: The one or more metal elements also include at least one of the following metal elements: In, Sn, Zr, Zn, Hf, Ga, Cr, Al, Sc, Y, Ta, Er, Lu, Ho, Tm, Dy, Tb, Ca, Nd, Pr, Yb, Ca and Ce.

10. The phase change material according to any one of claims 1 to 9, characterized in that: The phase change material is a thin film with a thickness greater than or equal to 5 nanometers and less than or equal to 200 nanometers.

11. A memory chip, characterized in that: including one or more storage units; The memory cell comprises a first electrode, a phase-change memory structure, and a second electrode which are sequentially stacked, wherein the phase-change memory structure comprises the phase-change material according to any one of claims 1 to 10.

12. A storage device, characterized in that: The storage device comprises a controller and at least one storage chip as claimed in claim 11, wherein the storage chip is used to store data, and the controller is used to write data to the storage chip or read data from the storage chip.

13. An electronic device, characterized in that: The electronic device comprises a processor and at least one storage device as claimed in claim 12, wherein the processor is configured to write data to the storage device or read data from the storage device.

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