Display substrate, manufacturing method therefor, and display apparatus

Abstract

Provided are a display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a base substrate; a first conductive layer, which is arranged on a side of the substrate, the first conductive layer comprising a first electrode; a second conductive layer, which is arranged on the side of the first conductive layer away from the substrate, the second conductive layer comprising a gate electrode; a semiconductor layer, which is arranged on the side of the second conductive layer away from the base substrate, the orthographic projection of the semiconductor layer on the base substrate being located within the orthographic projection of the second conductive layer on the base substrate; a third conductive layer, which is arranged on the side of the semiconductor layer away from the base substrate, the third conductive layer comprising an adapter part of which the orthographic projection on the base substrate is located within the orthographic projection of the first electrode on the substrate; a passivation layer; and a first electrode via hole passing through the passivation layer, the opening area of the first electrode via hole being gradually reduced in the direction from where is away from the base substrate towards where is close to the base substrate, and the exposed adapter part forming a part of a via hole side wall of the first electrode via hole.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the development of display technology, display devices are increasingly being used in various fields, and the requirements for display technology are becoming increasingly demanding. During the manufacturing process of display devices, multiple vias are used to connect metal traces and metal traces located on different film layers. Electrical connection between metal traces on different film layers is achieved by filling the vias with conductive material. However, during the manufacturing process of existing vias, the metal traces on different film layers have a certain impact on the via etching process. For example, when the via is close to the location of the metal trace, the metal trace collects the charged particles generated by the etching, resulting in defects at the via location, which in turn reduces the product yield.

[0003] Summary of the Invention

[0004] In order to solve at least one aspect of the above problems, the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can at least avoid defects in vias near metal routing positions, improve product yield, and improve the display effect of the display substrate.

[0005] In one aspect, a display substrate is provided, which includes but is not limited to: a base substrate, on which a plurality of sub-pixels are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting, each sub-pixel including at least one control transistor; a first conductive layer, provided on one side of the base substrate, the first conductive layer including first electrodes arranged at intervals in the second direction to constitute the sub-pixels; a second conductive layer, provided on a side of the first conductive layer away from the base substrate, the second conductive layer including first electrodes arranged at intervals in the second direction and extending along the first direction to constitute the gate electrode of the control transistor; a semiconductor layer, provided on a side of the second conductive layer away from the base substrate, the semiconductor layer being on the positive electrode of the base substrate The projection is located within the orthographic projection of the second conductive layer on the substrate; a third conductive layer is arranged on the side of the semiconductor layer away from the substrate, and the third conductive layer includes a transition portion whose orthographic projection on the substrate is located within the orthographic projection of the first electrode on the substrate; a passivation layer is arranged on the side of the third conductive layer away from the substrate; a first electrode via hole penetrates the passivation layer and exposes the first electrode and a portion of the transition portion, the opening area of ​​the first electrode via hole gradually decreases from the direction away from the substrate toward the direction close to the substrate, and the exposed transition portion constitutes a portion of the via hole side wall of the first electrode via hole; and a fourth conductive layer is arranged in the first electrode via hole to electrically connect the first electrode and the transition portion.

[0006] In some exemplary embodiments of the present disclosure, the via side wall of the first electrode via includes a step portion; the step portion includes: a step top surface formed by the surface of the exposed transition portion away from the substrate; and a step side surface formed by the surface of the exposed transition portion facing the inside of the first electrode via; wherein the opening area of ​​the first electrode via corresponding to the step side surface is greater than or equal to the opening area of ​​the first electrode via on the side of the step portion close to the substrate.

[0007] In some exemplary embodiments of the present disclosure, the surface roughness of the unexposed side of the transition portion away from the base substrate is smaller than the surface roughness of the step top surface.

[0008] In some exemplary embodiments of the present disclosure, an angle between the step top surface and the step side surface of the step portion is θ, wherein 90°<θ<180°.

[0009] In some exemplary embodiments of the present disclosure, the first electrode via exposes a portion of the semiconductor layer, and the exposed semiconductor layer constitutes a portion of the via side wall of the first electrode via; the opening area of ​​the first electrode via corresponding to the semiconductor layer is less than or equal to the opening area of ​​the first electrode via corresponding to the step portion.

[0010] In some exemplary embodiments of the present disclosure, the first electrode includes pixel electrodes, which are arranged at intervals in the first direction, and each pixel electrode corresponds to each sub-pixel; the third conductive layer also includes: data signal lines arranged at intervals in the first direction and extending along the second direction; and a first electrode and a second electrode constituting the control transistor; the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the transfer portion.

[0011] In some exemplary embodiments of the present disclosure, the third conductive layer further includes: voltage signal lines arranged at intervals in the first direction and extending along the second direction; the voltage signal lines are located between adjacent data signal lines; and the sub-pixels are located between adjacent voltage signal lines and data signal lines.

[0012] In some exemplary embodiments of the present disclosure, the voltage signal line is electrically connected to the common electrode through a second electrode via.

[0013] In some exemplary embodiments of the present disclosure, the gate electrode is located between adjacent pixel electrodes; the orthographic projections of the first electrode and the second electrode on the base substrate are located within the orthographic projection of the semiconductor layer on the base substrate, and the orthographic projection of the semiconductor layer on the base substrate is located within the orthographic projection of the gate electrode on the base substrate; the gate electrode is configured to control the data signal to be transmitted from the data signal line to the pixel electrode via the control transistor, the transfer portion, and the fourth conductive layer.

[0014] In some exemplary embodiments of the present disclosure, the sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the first direction, the first sub-pixel and the second sub-pixel are located between adjacent data signal lines, and the voltage signal line is located between the first sub-pixel and the second sub-pixel; the gate electrode includes a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are adjacent to each other in the second direction; the first gate electrode is configured to control a control transistor of the first sub-pixel close to the first gate electrode; the second gate electrode is configured to control a control transistor of the second sub-pixel close to the second gate electrode.

[0015] In some exemplary embodiments of the present disclosure, the first electrode includes a common electrode, and a plurality of first electrode vias are provided on a side of each common electrode away from the base substrate; the third conductive layer also includes a connecting portion, and the connecting portion electrically connects the transition portions of the common electrodes adjacent in the second direction, wherein the connecting portion is configured to electrically connect the common electrodes adjacent in the second direction through the fourth conductive layer and the transition portion located in the first electrode via.

[0016] In some exemplary embodiments of the present disclosure, the second conductive layer further includes voltage signal lines arranged at intervals in the second direction and extending along the first direction; the voltage signal lines are electrically connected to the common electrode.

[0017] In some exemplary embodiments of the present disclosure, the gate electrode is disposed adjacent to the voltage signal line, and the gate electrode and the voltage signal line are located between adjacent common electrodes.

[0018] In some exemplary embodiments of the present disclosure, the third conductive layer also includes: data signal lines arranged at intervals in the first direction and extending along the second direction; and a first electrode and a second electrode constituting the control transistor; the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the pixel electrode through a third electrode via.

[0019] Another aspect of the present disclosure provides a method for manufacturing a display substrate, which includes: forming a first conductive layer on one side of a base substrate, the first conductive layer including first electrodes arranged at intervals in a second direction to constitute sub-pixels on the base substrate, the sub-pixels on the base substrate being arranged in an array along a first direction and a second direction, and the first direction and the second direction intersecting; forming a second conductive layer on a side of the first conductive layer away from the base substrate, the second conductive layer including first electrodes arranged at intervals in the second direction and extending along the first direction to constitute a gate electrode of a control transistor; forming a semiconductor layer on a side of the second conductive layer away from the base substrate, the orthographic projection of the semiconductor layer on the base substrate being located within the orthographic projection of the second conductive layer on the base substrate; A third conductive layer is formed on the side of the semiconductor layer away from the base substrate, the third conductive layer includes a transition portion whose orthographic projection on the base substrate is located within the orthographic projection of the first electrode on the base substrate; a passivation layer is formed on the side of the third conductive layer away from the base substrate; a first electrode via is formed, the first electrode via passes through the passivation layer and exposes the first electrode and a portion of the transition portion, the opening area of ​​the first electrode via gradually decreases from the direction away from the base substrate toward the direction close to the base substrate, and the exposed transition portion constitutes a portion of the via side wall of the first electrode via; and a fourth conductive layer is formed in the first electrode via, the fourth conductive layer electrically connecting the first electrode and the transition portion.

[0020] In some exemplary embodiments of the present disclosure, forming the first electrode via includes: forming a first sub-via and forming a second sub-via, wherein the first sub-via exposes a portion of the first electrode, and the orthographic projection of the first sub-via on the base substrate does not overlap with the orthographic projection of the transition portion on the base substrate, and the second sub-via exposes a portion of the transition portion, and the orthographic projection of the second sub-via on the base substrate overlaps with the orthographic projection of the transition portion on the base substrate.

[0021] In some exemplary embodiments of the present disclosure, forming a first sub-via and forming a second sub-via include: coating a photoresist on a side of the passivation layer away from the substrate; fully exposing the photoresist area corresponding to the first sub-via, and half-exposing the photoresist area corresponding to the second sub-via; etching the film layer material in the area corresponding to the first sub-via to expose the first electrode; etching the film layer material in the area corresponding to the second sub-via to expose the transition portion, wherein the exposed transition portion constitutes the via side wall of the first electrode via.

[0022] In some exemplary embodiments of the present disclosure, etching the membrane material in the area corresponding to the first sub-via includes: etching the passivation layer in the area corresponding to the first sub-via through a first dry etching medium and etching the insulating layer in the area corresponding to the first sub-via and located between the passivation layer and the first electrode.

[0023] In some exemplary embodiments of the present disclosure, etching the membrane layer material in the area corresponding to the second sub-via hole includes: etching the photoresist material corresponding to the second sub-hole area through a second dry etching medium; and etching the passivation layer material corresponding to the second sub-hole area through a first dry etching medium.

[0024] In some exemplary embodiments of the present disclosure, the method further comprises: etching the photoresist located on the upper side of the passivation layer by using a second dry etching medium.

[0025] In some exemplary embodiments of the present disclosure, forming a first sub-via and forming a second sub-via include: coating a first photoresist on a side of the passivation layer away from the substrate; fully exposing the first photoresist area corresponding to the first sub-via; etching the film material in the area corresponding to the first sub-via to expose the first electrode; stripping off the first photoresist; coating a second photoresist on a side of the passivation layer away from the substrate so that a portion of the second photoresist fills the first sub-via; fully exposing the second photoresist area corresponding to the second sub-via; etching the film material in the area corresponding to the second sub-via to expose the transition portion, the exposed transition portion constituting the via side wall of the first electrode via; and stripping off the second photoresist.

[0026] According to another aspect of the present disclosure, a display device is provided, comprising: the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0028] FIG1 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure;

[0029] FIG2 is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure;

[0030] FIG3 is a schematic diagram of a partially enlarged structure of area A in FIG2 according to an embodiment of the present disclosure;

[0031] FIG4 is a schematic cross-sectional view of the structure along line BB' in FIG3 according to an embodiment of the present disclosure;

[0032] FIG5 is a schematic planar structural diagram of a display substrate according to another embodiment of the present disclosure;

[0033] FIG6 is a schematic diagram of a partially enlarged structure of area C in FIG5 according to an embodiment of the present disclosure;

[0034] 7 is a flowchart of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure;

[0035] 8A to 8L are schematic cross-sectional views of a method for manufacturing a display substrate during a manufacturing process according to an exemplary embodiment of the present disclosure;

[0036] 9A to 9G are schematic cross-sectional views of a method for manufacturing a display substrate during a manufacturing process according to another exemplary embodiment of the present disclosure;

[0037] FIG10A is a schematic plan view of a first electrode via manufactured by a conventional manufacturing method;

[0038] FIG10B is an actual cross-sectional structural diagram along the dotted line of FIG10A;

[0039] 10C is a schematic plan view of a first electrode via manufactured by a manufacturing method according to an exemplary embodiment of the present disclosure;

[0040] FIG10D is an actual cross-sectional structural diagram along the dotted line of FIG10C.

[0041] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0042] The technical solution of the present disclosure is further described in detail below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of the present disclosure and should not be construed as limiting the present disclosure.

[0043] Furthermore, in the following detailed description, for ease of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent that one or more embodiments can be practiced without these specific details.

[0044] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0045] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0046] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0047] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0048] Those skilled in the art should understand that, herein, unless otherwise specified, the expressions "continuous extension", "integrated structure", "monolithic structure" or similar expressions mean that multiple elements, components, structures and / or parts are located on the same layer and are usually formed by the same patterning process during the manufacturing process. There are no spaces or breaks between these elements, components, structures and / or parts, but they are continuously extended structures.

[0049] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along the pixel region, for example, the longitudinal direction and the transverse direction of the pixel region. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0050] In this document, the term "control transistor" refers to a transistor in a sub-pixel for controlling the transmission of a data signal into the sub-pixel. In this document, a sub-pixel may include one or more transistors, and the one or more transistors may include one or more control transistors.

[0051] In this article, the term "opening area" refers to the area of ​​the positive projection of the opening on a plane parallel to the electrode via opening. As the distance from the substrate changes, the opening area at different positions of the electrode via varies.

[0052] In the related art, different display panel structures correspond to different display modes, such as ADS display mode and iADS display mode. Since the display panel includes multiple different film layers, each of which includes multiple insulating layers and multiple metal wires, even if the display panel has a different structure, since it is necessary to electrically connect the metal wires of multiple different film layers, an exposure process is generally used to manufacture electrode vias, thereby electrically connecting the metal wires located in different film layers. However, when the electrode via is close to the metal wire, the metal wire easily induces a plasma effect during the dry etching process, which makes the etching rate of the insulating layer near the metal higher, resulting in more defects in the electrode via, which easily leads to poor product quality. On the one hand, it reduces the product yield, and on the other hand, it reduces the display effect of the product.

[0053] In order to solve the above problems, an embodiment of the present disclosure provides a display substrate, which includes but is not limited to: a base substrate, on which a plurality of sub-pixels are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting, and each sub-pixel including at least one control transistor; a first conductive layer, arranged on one side of the base substrate, the first conductive layer including first electrodes arranged at intervals in the second direction to constitute the sub-pixels; a second conductive layer, arranged on a side of the first conductive layer away from the base substrate, the second conductive layer including first electrodes arranged at intervals in the second direction and extending along the first direction to constitute the gate electrode of the control transistor; a semiconductor layer, arranged on a side of the second conductive layer away from the base substrate, the semiconductor layer being arranged on the base substrate The orthographic projection on the base substrate is located within the orthographic projection of the second conductive layer on the base substrate; a third conductive layer is arranged on the side of the semiconductor layer away from the base substrate, and the third conductive layer includes a transition portion whose orthographic projection on the base substrate is located within the orthographic projection of the first electrode on the base substrate; a passivation layer is arranged on the side of the third conductive layer away from the base substrate; a first electrode via hole penetrates the passivation layer and exposes the first electrode and a portion of the transition portion, the opening area of ​​the first electrode via hole gradually decreases from the direction away from the base substrate toward the direction close to the base substrate, and the exposed transition portion constitutes a portion of the via side wall of the first electrode via hole; and a fourth conductive layer is arranged in the first electrode via hole to electrically connect the first electrode and the transition portion.

[0054] According to an embodiment of the present disclosure, the first electrode is electrically connected to the transition portion by providing a first electrode via hole that penetrates the passivation layer and exposes a portion of the transition portion in the first electrode and the third conductive layer. The first electrode via is provided so that the opening area gradually decreases from a direction away from the base substrate toward a direction close to the base substrate, thereby avoiding the exposed transition portion from causing defects in subsequent manufacturing processes, thereby improving the yield rate and display effect of the display substrate.

[0055] The structure of the display substrate according to the embodiment of the present disclosure will be described in detail below with reference to FIG. 1 to FIG. 8L .

[0056] 1 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure. Referring to FIG1 , the display substrate according to an exemplary embodiment of the present disclosure may include a base substrate 10 and a pixel unit PX disposed on the base substrate 10.

[0057] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel cells PX displaying an image are located. Each pixel cell PX will be described later. The non-display area NA is an area where pixel cells PX are not located, that is, an area where no image is displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel is determined based on the width of the non-display area NA.

[0058] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0059] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0060] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0061] The pixel cells PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel cells PX, and the pixel cells PX may be arranged in various forms. For example, the pixel cells PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0062] That is, the plurality of pixel units PX are arranged in an array along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.

[0063] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include three sub-pixels, namely a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel.

[0064] It should be noted that, in the embodiment of the present disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the above-mentioned three.

[0065] For example, in the exemplary embodiment shown in FIG1 , signal lines 11 and data lines 12 are schematically illustrated. Specifically, the display substrate may further include: a plurality of signal lines 11 and a plurality of data lines 12 disposed on the base substrate. The plurality of signal lines 11 respectively supply, for example, scan control signals to multiple rows of pixel units, and the plurality of data lines 12 respectively supply data signals to multiple columns of pixel units. The signal lines 11 extend along a first direction X, and the plurality of signal lines 11 are arranged at intervals along a second direction Y. The data lines 12 extend along the second direction Y, and the plurality of data lines 12 are arranged at intervals along the first direction X.

[0066] For example, the signal line 11 may be a representative of a horizontal line, and the data line 12 may be a representative of a vertical line. It should be understood that the horizontal line may also include lines of other types or lines for supplying other signals, and the vertical line may also include lines of other types or lines for supplying other signals.

[0067] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, in an OLED display substrate or display panel, the light-emitting element of a sub-pixel may include a stacked anode, a light-emitting material layer, and a cathode. The anodes of the light-emitting elements of each sub-pixel are spaced apart and arranged in a matrix along rows extending in a first direction X and columns extending in a second direction Y.

[0068] Figure 2 is a schematic diagram of the planar structure of a display substrate according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of a partially enlarged structure of area A in Figure 2 according to an embodiment of the present disclosure. Figure 4 is a schematic diagram of the cross-sectional structure along line BB' in Figure 3 according to an embodiment of the present disclosure.

[0069] The structure of a display substrate according to an embodiment of the present disclosure will be described in detail below with reference to FIG. 2 to FIG. 4 .

[0070] As shown in FIG. 2 to FIG. 4 , the display substrate 100 includes a base substrate 10 , a first conductive layer 20 , a second conductive layer 30 , a semiconductor layer 40 , a third conductive layer 50 , a passivation layer 60 , and a fourth conductive layer 70 .

[0071] As shown in FIG2 , a plurality of sub-pixels px are provided on the base substrate 10 . The plurality of sub-pixels px are arranged in an array along a first direction X and a second direction Y. The first direction X and the second direction Y intersect. Each sub-pixel px includes at least one control transistor TFT.

[0072] For example, sub-pixels arranged in an array can emit light of different colors. For example, three sub-pixels can be referred to as a pixel unit. The first direction X, for example, refers to the lateral direction of the display substrate, and the second direction Y, for example, refers to the longitudinal direction perpendicular to the lateral direction of the display substrate. In an optional embodiment, the first direction X and the second direction Y can be set to form a certain angle to achieve different pixel arrangements and display effects.

[0073] The control transistor TFT may refer to one of the one or more transistors included in each sub-pixel for implementing a specific control function. For example, the control transistor TFT of each sub-pixel is used to control the transmission of a data signal to the pixel electrode of each sub-pixel.

[0074] As shown in FIG4 , a first conductive layer 20 is disposed on one side of the base substrate 10. The first conductive layer 20 includes first electrodes arranged at intervals in the second direction to form the sub-pixels. In this embodiment, the first electrodes include pixel electrodes 21, each pixel electrode 21 being arranged corresponding to a sub-pixel. That is, the pixel electrodes 21 are arranged at intervals in the first direction X and the second direction Y. For example, the pixel electrodes 21 are rectangular in shape, with the length of the rectangle parallel to the second direction Y. In other optional embodiments, the first electrode may also include a common electrode, which will be described in detail below.

[0075] The second conductive layer 30 is disposed on a side of the first conductive layer 20 away from the base substrate. The second conductive layer 30 is arranged at intervals in the second direction Y and extends along the first direction X to form the gate electrode G30 of the control transistor TFT.

[0076] In some embodiments, the first conductive layer 20 may overlap with the positive projection of the gate electrode G30 on the base substrate, and the portion of the first conductive layer 20 overlapping with the gate electrode G30 is insulated and separated from the pixel electrode 21 in the first conductive layer 20, that is, the portion of the first conductive layer 20 overlapping with the gate electrode G30 has no electrical connection with the pixel electrode 21 in the first conductive layer 20.

[0077] As shown in FIG4 , the semiconductor layer 40 is disposed on a side of the second conductive layer 30 away from the base substrate 10 , and the orthographic projection of the semiconductor layer 40 on the base substrate is located within the orthographic projection of the second conductive layer 30 on the base substrate. Specifically, the orthographic projection of the semiconductor layer 40 on the base substrate overlaps with the orthographic projection of the gate electrode G30 of the second conductive layer 30 on the base substrate, meaning that the conduction state of the semiconductor layer 40 is controlled by the gate electrode G30.

[0078] As shown in FIG4 , the third conductive layer 50 is disposed on a side of the semiconductor layer 40 away from the base substrate 10 . The third conductive layer 50 includes a transition portion 51 whose orthographic projection on the base substrate 10 is located within the orthographic projection of the first electrode on the base substrate.

[0079] When the third conductive layer 50 is formed on the side of the semiconductor layer 40 away from the base substrate 10, a portion of the formed third conductive layer 50 is a transition portion 51, and the other portions of the third conductive layer 50 can be structures such as data signal lines and voltage signal lines, which will be described in detail below.

[0080] As shown in Figure 4, a passivation layer 60 is disposed on a side of the third conductive layer 50 away from the base substrate 10. A first electrode via hole VH1 penetrates the passivation layer 60, exposing the first electrode 21 and a portion of the transition portion 51. The opening area of ​​the first electrode via hole VH1 gradually decreases from a direction away from the base substrate 10 toward a direction closer to the base substrate 10. The exposed transition portion 51 constitutes a portion of the via sidewall of the first electrode via hole. A fourth conductive layer 70 is disposed in the first electrode via hole VH1, electrically connecting the first electrode 21 to the transition portion 51.

[0081] In some embodiments of the present disclosure, one or more insulating layers are provided between the first conductive layer 20 and the semiconductor layer 40 , and one or more insulating layers are provided between the second conductive layer 30 and the semiconductor layer 40 . For example, the insulating layer may include a gate insulating layer 101 .

[0082] 3 and 4 , a semiconductor layer 40 is further provided between the transition portion 51 in the third conductive layer 50 and the first electrode 21. In some optional embodiments, no semiconductor layer may be provided between the transition portion in the third conductive layer and the first electrode.

[0083] For example, the first electrode via hole VH1 penetrates the passivation layer 60 and the gate insulating layer 101 .

[0084] As shown in Figure 4, the opening area of ​​the first electrode via hole VH1 refers to the orthographic projection area of ​​the opening of the first electrode via hole on a plane parallel to the upper surface of the substrate. The first electrode via hole VH1 has via sidewalls formed by the passivation layer 60, the transition portion 51 in the third conductive layer 50, the semiconductor layer 40, and the gate insulation layer 101. The exposed portion of the pixel electrode 21 forms the bottom wall of the first electrode via hole VH1, and the exposed portion of the transition portion 51 forms a portion of the via sidewall of the first electrode via hole VH1.

[0085] The fourth conductive layer 70 located in the first electrode via hole VH1 is electrically connected to the exposed portion of the transition portion 51 in the first electrode via hole VH1, and the fourth conductive layer 70 is also electrically connected to the exposed portion of the pixel electrode 21 in the electrode via hole VH1, so that the fourth conductive layer 70 can electrically connect the pixel electrode 21 in the first electrode with the transition portion 51.

[0086] As shown in FIG. 4 , the via sidewall of the first electrode via hole VH1 includes a step portion S1 , and the step portion S1 includes a step top surface S11 and a step side surface S12 .

[0087] The step top surface S11 is formed by the exposed surface of the transition portion 51 facing away from the base substrate 10. The step side surface S12 is formed by the exposed surface of the transition portion 51 facing the first electrode via hole. The opening area of ​​the first electrode via hole corresponding to the step side surface S12 is greater than or equal to the opening area of ​​the first electrode via hole on the side of the step portion S1 closer to the base substrate.

[0088] That is, the closer the opening area of ​​the first electrode via corresponding to the step portion of the first electrode via VH1 is to the base substrate, the smaller the opening area. For example, the opening area of ​​the first electrode via located at the step top surface S11 is larger than the opening area of ​​the first electrode via located at the step side surface S12, and the opening area of ​​the first electrode via corresponding to the step side surface S12 is larger than the opening area of ​​the first electrode via located closer to the base substrate than the step portion S1.

[0089] According to an embodiment of the present disclosure, the opening area of ​​the first electrode via VH1 gradually decreases from the direction away from the base substrate toward the direction close to the base substrate, thereby avoiding the existence of a gap in the direction of the transition portion close to the base substrate, further avoiding the problem of reduced product yield caused by the stripping liquid remaining in the gap during the processing, and at the same time improving the display effect of the display substrate.

[0090] In the embodiment of the present disclosure, the transition portion 51 in the first electrode via VH1 includes an exposed portion and an unexposed portion. During the formation of the first electrode via VH1, dry etching is performed. During the etching process, the surface of the transition portion 51 on the side away from the base substrate 10 is bombarded by plasma, thereby increasing the surface roughness. The unexposed portion is not bombarded by plasma and is unaffected. That is, the surface roughness of the unexposed portion of the transition portion 51 on the side away from the base substrate is less than the surface roughness of the step top surface.

[0091] As shown in FIG4 , the angle between the step top surface S11 and the step side surface S12 of the step portion is θ, where 90°<θ<180°. By setting a certain angle between the step top surface S11 and the step side surface S12, the opening area of ​​the first electrode via hole VH1 gradually decreases from a direction away from the base substrate toward a direction close to the base substrate.

[0092] In some embodiments, a semiconductor layer 40 is further provided on a side of the transition portion 51 that is close to the base substrate 10. The first electrode via hole VH1 exposes a portion of the semiconductor layer 40, and the exposed semiconductor layer 40 constitutes a portion of the via sidewall of the first electrode via hole VH1. The opening area of ​​the first electrode via hole corresponding to the exposed semiconductor layer 40 is less than or equal to the opening area of ​​the first electrode via hole corresponding to the step portion S12.

[0093] In the embodiments shown in FIG. 2 to FIG. 4 , the first electrode includes a pixel electrode, and the pixel electrode provides a data signal for each sub-pixel.

[0094] As shown in FIG. 2 and FIG. 3 , the third conductive layer 50 includes a data signal line 52 and a voltage signal line 53 .

[0095] The data signal lines 52 are arranged at intervals in the first direction X and extend along the second direction Y. The data signal lines 52 are used to transmit data signals VDD. The voltage signal lines 53 are arranged at intervals in the first direction X and extend along the second direction Y. The voltage signal lines 53 are used to transmit voltage signals Vcom.

[0096] The third conductive layer 50 includes a first electrode T1 and a second electrode T2 constituting a control transistor TFT. The first electrode T1 is electrically connected to the data signal line 52 , and the second electrode T2 is electrically connected to the transfer portion 51 .

[0097] One or more sub-pixels are disposed between the data signal lines 52 . For example, two sub-pixels are disposed between the data signal lines 52 , that is, one sub-pixel is disposed on both sides of each data signal line 52 .

[0098] The voltage signal line 53 is located between the adjacent data signal lines 52 , that is, the voltage signal line 53 -data signal line 52 -voltage signal line 53 -data signal line 52 are arranged in an interval manner.

[0099] A second electrode via hole VH2 is provided at a gap between the pixel electrodes 21 of the voltage signal line 53 , and the voltage signal line 53 is electrically connected to the common electrode through the second electrode via hole VH2 .

[0100] As shown in FIG. 2 and FIG. 3 , the gate electrode G30 is located between adjacent pixel electrodes 21 , and the gate electrode G30 extends along a first direction.

[0101] As shown in FIG3 , the orthographic projections of the first electrode T1 and the second electrode T2 on the base substrate 10 are located within the orthographic projection of the semiconductor layer 40 on the base substrate 10, i.e., the semiconductor first electrode T1 and the second electrode T2 are electrically connected to the semiconductor layer 40. The orthographic projection of the semiconductor layer 40 on the base substrate 10 is located within the orthographic projection of the gate electrode G30 on the base substrate 10. The gate electrode G30 is insulated and separated from the semiconductor layer 40 by the gate insulating layer 101. By setting the orthographic projection relationship between the gate electrode G30 and the semiconductor layer 40, the gate electrode G30 controls the semiconductor layer of the control transistor TFT.

[0102] For example, the gate electrode G30 is configured to control the data signal to be transmitted from the data signal line 52 to the pixel electrode 21 via the control transistor TFT, the switching portion 51 , and the fourth conductive layer 70 .

[0103] In some embodiments of the present disclosure, as shown in FIG2 and FIG3 , the sub-pixel includes a first sub-pixel PX1 and a second sub-pixel PX2 adjacent to each other in the first direction X, the first sub-pixel PX1 and the second sub-pixel PX2 are located between adjacent data signal lines 52, and the voltage signal line 53 is located between the first sub-pixel PX1 and the second sub-pixel PX2;

[0104] The gate electrode G30 includes a first gate electrode G301 and a second gate electrode G302, and the first gate electrode G301 and the second gate electrode G302 are adjacent to each other in the second direction Y. The first gate electrode G301 is configured to control the control transistor of the first sub-pixel PX1 adjacent to the first gate electrode G301. The second gate electrode G302 is configured to control the control transistor of the second sub-pixel PX2 adjacent to the second gate electrode G302.

[0105] For example, as shown in FIG3 , the data signal line 52 provides data signal lines for the second subpixel PX2 on the upper side and the first subpixel PX1 on the lower side. Specifically, the data signal line 52 is electrically connected to the first electrode T1 of the control transistor TFT of the second subpixel PX2 on the upper side and the first electrode T1 of the control transistor TFT of the first subpixel PX1 on the lower side, respectively. The first gate electrode G301 controls the conduction state of the control transistor of the first subpixel PX1 on the lower side, and the second gate electrode G302 controls the conduction state of the control transistor of the second subpixel PX2 on the upper side.

[0106] Figure 5 is a schematic diagram of a planar structure of a display substrate according to another embodiment of the present disclosure. Figure 6 is a schematic diagram of a partially enlarged structure of area C in Figure 5 according to an embodiment of the present disclosure.

[0107] As shown in FIG. 5 and FIG. 6 , the first electrode includes a common electrode 21 ′ of a sub-pixel. A plurality of first electrode via holes VH1 ′ are provided on a side of each common electrode 21 ′ away from the base substrate 10 .

[0108] For example, a column of sub-pixels arranged along the first direction X can share a common electrode 21'. The common electrodes 21' are spaced apart in the second direction Y. A second conductive layer 30 is provided between adjacent common electrodes 21' in the second direction Y. The second conductive layer 30 includes gate electrodes G30' and voltage signal lines 31. The voltage signal lines 31 are spaced apart in the second direction Y and extend along the first direction X. The voltage signal lines 31 are electrically connected to the common electrodes 21'. The voltage signal lines 31 are used to transmit voltage signals Vcom to the common electrodes 21'.

[0109] The portion of the third conductive layer 50 whose orthographic projection on the base substrate 10 lies within the orthographic projection of the common electrode 21' on the base substrate 10 is a transition portion 51'. Each common electrode has a corresponding plurality of transition portions 51', which are used to electrically connect adjacent common electrodes in the second direction Y. For example, adjacent common electrodes in the second direction each have a transition portion 51' at a corresponding position. The transition portion 51' is electrically connected to the common electrode 21' through the fourth conductive layer in the first electrode via VH1'. Adjacent transition portions 51' are connected by a connecting portion.

[0110] For example, the third conductive layer also includes a connecting portion 511, which electrically connects the transition portions 51' of the common electrodes adjacent in the second direction Y. The connecting portion 511 is configured to electrically connect the common electrodes 21' adjacent in the second direction Y through the fourth conductive layer 70 and the transition portions 51' located in the first electrode via hole VH1'.

[0111] The gate electrode G30 ′ is disposed adjacent to the voltage signal line 31 , and the gate electrode G30 ′ and the voltage signal line 31 are located between adjacent common electrodes 21 ′.

[0112] In the embodiments of the present disclosure, the voltage signal line 31 is electrically connected to the common electrode 21' to provide a voltage signal to the common electrode. Since the common electrodes 21' are spaced apart in the second direction Y, there is a voltage difference between the spaced common electrodes 21' due to resistance and the like. When displaying, it is easy to cause the display effect of the display substrate to be inconsistent. By setting the connecting portion 511 through the adapter portion 51' and the fourth conductive layer 70 in the first electrode via VH1', the common electrodes 21' spaced apart in the second direction are electrically connected, thereby avoiding the voltage difference between the common electrodes due to resistance and other problems, thereby improving the display uniformity of the display substrate and improving the display effect.

[0113] 6 , the third conductive layer 50 further includes data signal lines 52 ′, which are arranged at intervals in the first direction X and extend along the second direction Y. The third conductive layer 50 further includes a first electrode T1 ′ and a second electrode T2 ′ constituting the control transistor TFT.

[0114] The first electrode T1 ′ is electrically connected to the data signal line 52 ′, and the second electrode T2 ′ is electrically connected to the pixel electrode through the third electrode via hole VH3 .

[0115] In the embodiment of the present disclosure, the second electrode via hole VH2 and the third electrode via hole VH3 are via holes different from the first electrode via hole VH1 , and no metal film layer is exposed on the via hole sidewalls of the second electrode via hole VH2 and the third electrode via hole VH3 .

[0116] In an embodiment of the present disclosure, as shown in Figure 4, the opening area of ​​the first electrode via VH1 gradually decreases from the direction away from the substrate toward the direction close to the substrate. For example, the opening area of ​​the first electrode via in the passivation layer 60 is larger than the opening area of ​​the first electrode via in the gate insulation layer 101.

[0117] For example, the orthographic projection of the opening of the first electrode via hole of the gate insulating layer 101 on the base substrate is located within the orthographic projection of the opening of the first electrode via hole of the passivation layer 60 on the base substrate.

[0118] The first electrode via hole VH1 includes a via sidewall formed by the passivation layer 60 and the gate insulating layer 101. The cross-section of the via sidewall formed by the passivation layer 60 and the gate insulating layer 101 forms an obtuse angle, that is, the via sidewalls have different angles due to different etching rates between the passivation layer 60 and the gate insulating layer 101. For example, the via sidewall formed by the gate insulating layer 101 forms an angle α with the upper surface of the substrate, and the angle is 35°≤α≤45°. Compared with the process of forming the first electrode via by a single exposure, the present disclosure adopts a process of first forming a first sub-via and then forming a second sub-via to form the first electrode via. See the manufacturing method of the display substrate below for details. This can avoid the step formed by the surface of the gate insulating layer away from the base substrate during the formation of the first electrode via due to the different etching rates of the passivation layer and the gate insulating layer in the process of forming the first electrode via by a single exposure. That is, when the first electrode via is formed by the manufacturing process of the present disclosure, the connection between the passivation layer and the gate insulating layer presents an obtuse-angled broken line transition, and does not present a step-like platform.

[0119] FIG. 7 is a flowchart of a method of manufacturing a display substrate according to an exemplary embodiment of the present disclosure.

[0120] As shown in FIG. 7 , the method for manufacturing a display substrate includes operations S1 to S7 .

[0121] In operation S1, a first conductive layer is formed on one side of a base substrate. The first conductive layer includes first electrodes arranged at intervals in a second direction to constitute sub-pixels on the base substrate. The sub-pixels on the base substrate are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0122] In operation S2 , a second conductive layer is formed on a side of the first conductive layer away from the base substrate. The second conductive layer is arranged at intervals in the second direction and extends along the first direction to constitute a gate electrode of the control transistor.

[0123] In operation S3 , a semiconductor layer is formed on a side of the second conductive layer away from the base substrate, and an orthographic projection of the semiconductor layer on the base substrate is located within an orthographic projection of the second conductive layer on the base substrate.

[0124] In operation S4 , a third conductive layer is formed on a side of the semiconductor layer away from the base substrate, wherein the third conductive layer includes a transition portion whose orthographic projection on the base substrate is located within the orthographic projection of the first electrode on the base substrate.

[0125] In operation S5 , a passivation layer is formed on a side of the third conductive layer away from the base substrate.

[0126] In operation S6, a first electrode via is formed, wherein the first electrode via penetrates the passivation layer and exposes the first electrode and a portion of the transition portion. The opening area of ​​the first electrode via gradually decreases from a direction away from the base substrate toward a direction close to the base substrate. The exposed transition portion constitutes a portion of a via side wall of the first electrode via.

[0127] In operation S7 , a fourth conductive layer is formed in the first electrode via hole, where the fourth conductive layer electrically connects the first electrode and the transfer portion.

[0128] 8A to 8L are schematic cross-sectional structural diagrams of a method for manufacturing a display substrate during a manufacturing process according to an exemplary embodiment of the present disclosure.

[0129] The manufacturing method of the display substrate according to the embodiment of the present disclosure will be described in detail below with reference to FIG. 8A to FIG. 8L .

[0130] As shown in FIG8A , a first conductive layer 20 is formed on one side of the display substrate 10 . The first conductive layer 20 includes first electrodes of sub-pixels arranged at intervals in the second direction on the base substrate. The first electrodes can be pixel electrodes or common electrodes.

[0131] As shown in FIG8B , a second conductive layer 30 is formed on a side of the first conductive layer 20 away from the base substrate 10 . The second conductive layer 30 includes gate electrodes arranged at intervals in the second direction and extending along the first direction to form the control transistor.

[0132] As shown in FIG8C , a gate insulating layer 101 is further formed on the second conductive layer 20, and a semiconductor layer 40 is formed on a side of the gate insulating layer 101 away from the base substrate 10. The semiconductor layer 40 includes a portion whose orthographic projection on the base substrate overlaps with the orthographic projection on the base substrate of the second conductive layer 30 forming the gate electrode, and this portion serves as an active layer of the control transistor.

[0133] As shown in Figure 8D, a third conductive layer 50 is formed on the side of the semiconductor layer 40 away from the base substrate 10. The third conductive layer 50 includes a transition portion 51 whose orthographic projection on the base substrate 10 is located within the orthographic projection of the first electrode on the base substrate, that is, the transition portion 51 is a part of the third conductive layer 50.

[0134] As shown in FIG. 8E , a passivation layer 60 is formed on a side of the third conductive layer 50 away from the base substrate 10 .

[0135] Next, a first electrode via is formed, wherein forming the first electrode via includes: forming a first sub-via and forming a second sub-via, wherein the first sub-via exposes a portion of the first electrode, and the orthographic projection of the first sub-via on the base substrate does not overlap with the orthographic projection of the transition portion on the base substrate, and the second sub-via exposes a portion of the transition portion, and the orthographic projection of the second sub-via on the base substrate overlaps with the orthographic projection of the transition portion on the base substrate.

[0136] As shown in FIG. 8F , a photoresist 80 is first coated on the passivation layer 60 .

[0137] As shown in FIG. 8G , the coated photoresist 80 is exposed in segmented regions. The photoresist region corresponding to the first sub-via hole is fully exposed, and the photoresist region corresponding to the second sub-via hole is half exposed.

[0138] For example, the Q1 region is exposed using a full-transmittance exposure process, and the Q2 region is exposed using a semi-transmittance exposure process. The Q1 region is the photoresist region corresponding to the first sub-via hole, and the Q2 region is the photoresist region corresponding to the second sub-via hole. Thus, the structure of the photoresist film layer is formed as shown in FIG8G .

[0139] As shown in FIG8H , the film material in the region of the first sub-via is etched to expose the first electrode in the first conductive layer 20. The passivation layer in the region corresponding to the first sub-via is etched using a first dry etching medium, as well as the insulating layer in the region corresponding to the first sub-via and located between the passivation layer and the first electrode.

[0140] For example, a dry etching process is adopted, and the etching medium adopts a first etching medium, such as N2, to etch the passivation layer material and the gate insulation layer material of the first sub-via area, and finally expose the first electrode in the first conductive layer 20 to form the bottom wall of the first sub-via.

[0141] As shown in FIG8I , the photoresist material corresponding to the second sub-hole region is further etched, for example, by also using a dry etching process and using a second etching medium, such as O 2 , to etch away the photoresist material corresponding to the second sub-hole region.

[0142] As shown in FIG8J , the passivation layer material corresponding to the second sub-hole region is further etched using the first dry etching medium, for example, using O2 to etch away the passivation layer material corresponding to the second sub-hole region, exposing the transition portion 51 in the third conductive layer.

[0143] As shown in FIG8K , the photoresist 80 on the upper side of the passivation layer is etched by a second dry etching medium, and finally a first electrode via hole VH1 is formed, which facilitates subsequent processes.

[0144] In the embodiments disclosed herein, by using a second dry etching medium to etch the photoresist on the upper side of the passivation layer, the wet photoresist stripping process can be omitted, the production steps can be simplified, and the production efficiency can be improved. At the same time, the problem of excessive corrosion of the via caused by residual etching solution in the first electrode via can be solved.

[0145] In another embodiment of the present disclosure, the photoresist 80 on the upper side of the passivation layer 60 may be stripped by a wet stripping process.

[0146] As shown in FIG8L , a fourth conductive layer material 70 is continuously formed in the first electrode via hole VH1 . The fourth conductive layer material electrically connects the first electrode with the transition portion 51 in the third conductive layer.

[0147] 9A to 9G are schematic cross-sectional structural diagrams of a method for manufacturing a display substrate during a manufacturing process according to another exemplary embodiment of the present disclosure.

[0148] Forming the first sub-via and the second sub-via includes: coating a first photoresist on a side of the passivation layer away from the substrate; fully exposing the first photoresist region corresponding to the first sub-via; etching the film material in the region corresponding to the first sub-via to expose the first electrode; stripping the first photoresist; coating a second photoresist on a side of the passivation layer away from the substrate so that a portion of the second photoresist fills the first sub-via; fully exposing the second photoresist region corresponding to the second sub-via; etching the film material in the region corresponding to the second sub-via to expose the transition portion, wherein the exposed transition portion constitutes the via sidewall of the first electrode via hole; and stripping the second photoresist. For example, the first photoresist and the second photoresist can be the same photoresist.

[0149] 9A to 9G , the aforementioned process is the same as that of FIG. 8A to 8E .

[0150] As shown in FIG9A , after forming the passivation layer 60 and coating the photoresist 80 on the passivation layer 60 , the first photoresist region corresponding to the first sub-via hole is fully exposed, thereby determining the region Q1 corresponding to the first sub-via hole.

[0151] As shown in FIG9B , the film material in the region Q1 corresponding to the first sub-via hole is etched to expose the first electrode. For example, the passivation layer 60 and the gate insulating layer 101 are etched to expose the first electrode in the first conductive layer 20 .

[0152] As shown in FIG. 9C , the photoresist 80 is stripped.

[0153] As shown in FIG. 9D , a photoresist 80 is coated on a side of the passivation layer 60 away from the substrate, so that a portion of the photoresist 80 fills the first sub-via hole.

[0154] As shown in FIG. 9E , the region Q2 corresponding to the second sub-via hole is fully exposed, that is, the photoresist corresponding to the second sub-via hole region is exposed.

[0155] As shown in FIG9F , the film material in the region Q2 corresponding to the second sub-via is etched to expose the transition portion, and the exposed transition portion constitutes the via sidewall of the first electrode via hole, for example, by etching the passivation layer, etc., thereby forming the second sub-via hole.

[0156] As shown in FIG. 9G , the photoresist 80 is stripped off, thereby forming a first electrode via hole VH1 composed of the first sub-via hole and the second sub-via hole.

[0157] Figure 10A is a schematic plan view of a first electrode via manufactured using a conventional manufacturing method. Figure 10B is a diagram of an actual cross-sectional structure taken along the dashed line of Figure 10A. Figure 9C is a schematic plan view of a first electrode via manufactured using a manufacturing method according to an exemplary embodiment of the present disclosure. Figure 9D is a diagram of an actual cross-sectional structure taken along the dashed line of Figure 10C.

[0158] As shown in Figures 10A and 10B, the actual cross-sectional structure of the first electrode via manufactured by the existing manufacturing method, in the existing manufacturing method, in the process of forming the first electrode via, the first electrode via area is fully exposed. After the material of the passivation layer is etched, the transition portion 51 of the third conductive layer located on the lower side of the passivation layer is exposed. At this time, the first electrode has not been exposed, and the gate insulating layer needs to be further etched. Due to the "antenna effect" of the exposed third conductive layer, that is, the metal of the exposed transition portion will attract plasma, so that the etching rate near the lower side of the transition portion is accelerated, thereby further etching the gate insulating layer on the lower side of the bottom of the transition portion, that is, the transition portion 51 extends into the first electrode via relative to the side wall of the first electrode via to form a protrusion, and a void defect D is formed at the bottom, as shown in Figure 10B. In addition, if the gate insulating layer on the side of the transition portion close to the substrate is further etched, the exposed transition portion will be bombarded by plasma for a long time, and there is a risk of oxidation on the surface, which can easily cause poor contact problems. In subsequent processes, such as wet stripping of the photoresist on the surface of the passivation layer, the stripping liquid is likely to remain in the defect D, causing corrosion of the electrode via or poor overlap, thereby reducing the product yield.

[0159] In comparison, through the manufacturing method of the display substrate of the embodiment of the present disclosure, as shown in Figures 10C and 10D, the portion of the transition portion 51 in the third conductive layer exposed in the first electrode via constitutes the via side wall of the first electrode via, and the transition portion 51 does not protrude relative to the via side wall, so that the opening area of ​​the first electrode via gradually decreases from the direction away from the base substrate toward the direction close to the base substrate, that is, the defect D in the existing manufacturing method does not exist in the first electrode via. On the one hand, the problem of oxidation caused by the exposed transition portion 51 being bombarded by plasma for a long time is avoided, and the problem of corrosion of the electrode via caused by the defect D is also avoided, thereby effectively improving the product yield of the display substrate.

[0160] Another aspect of the present disclosure provides a display device, which includes the display substrate described above. The display substrate is manufactured according to the manufacturing method described above.

[0161] The beneficial effects that can be achieved by the display device in the above-mentioned embodiment of the present disclosure are the same as the beneficial effects that can be achieved by the above-mentioned display substrate, and will not be described in detail here.

[0162] The display device can be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0163] Although some embodiments of the present general inventive concept have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: include: A base substrate, on which a plurality of sub-pixels are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect, and each sub-pixel includes at least one control transistor; A first conductive layer, disposed on one side of the base substrate, the first conductive layer comprising first electrodes arranged at intervals in the second direction to form the sub-pixels; A second conductive layer is arranged on a side of the first conductive layer away from the base substrate, the second conductive layer includes layers arranged at intervals in the second direction and extending along the first direction to form a gate electrode of the control transistor; A semiconductor layer is arranged on a side of the second conductive layer away from the base substrate, and an orthographic projection of the semiconductor layer on the base substrate is located within an orthographic projection of the second conductive layer on the base substrate; A third conductive layer is disposed on a side of the semiconductor layer away from the substrate, the third conductive layer comprising a transition portion where an orthographic projection on the substrate is within an orthographic projection of the first electrode on the substrate; A passivation layer is disposed on a side of the third conductive layer away from the substrate; a first electrode via hole, penetrating the passivation layer and exposing the first electrode and a portion of the transition portion, wherein an opening area of ​​the first electrode via hole gradually decreases from a direction away from the substrate toward a direction close to the substrate, and the exposed transition portion constitutes a portion of a via hole side wall of the first electrode via hole; as well as The fourth conductive layer is disposed in the first electrode via hole to electrically connect the first electrode with the transition portion.

2. The display substrate according to claim 1, wherein: The via hole sidewall of the first electrode via hole includes a step portion; The step portion comprises: a step top surface formed by a surface of the exposed transition portion away from the substrate; and a step side surface formed by the exposed surface of the transition portion facing the first electrode via hole; The opening area of ​​the first electrode via hole corresponding to the side surface of the step is greater than or equal to the opening area of ​​the first electrode via hole on the side of the step portion close to the base substrate.

3. The display substrate according to claim 2, wherein: The surface roughness of the unexposed transition portion on a side away from the base substrate is smaller than the surface roughness of the step top surface.

4. The display substrate according to claim 2, wherein: The angle between the top surface of the step portion and the side surface of the step is θ, where 90°<θ< 180°。 5. The display substrate according to claim 2, wherein: The first electrode via hole exposes a portion of the semiconductor layer, and the exposed semiconductor layer constitutes a portion of a via hole side wall of the first electrode via hole; The opening area of ​​the first electrode via hole corresponding to the semiconductor layer is smaller than or equal to the opening area of ​​the first electrode via hole corresponding to the step portion.

6. The display substrate according to any one of claims 1 to 5, wherein: The first electrode includes pixel electrodes, the pixel electrodes are arranged at intervals in a first direction, and each pixel electrode corresponds to each sub-pixel; The third conductive layer further comprises: Data signal lines arranged at intervals in the first direction and extending along the second direction; and a first electrode and a second electrode constituting the control transistor; The first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the switching portion.

7. The display substrate according to claim 6, wherein: The third conductive layer further comprises: Voltage signal lines arranged at intervals in the first direction and extending along the second direction; The voltage signal line is located between adjacent data signal lines; The sub-pixel is located between adjacent voltage signal lines and data signal lines.

8. The display substrate according to claim 7, wherein: The voltage signal line is electrically connected to the common electrode through the second electrode via hole.

9. The display substrate according to claim 8, wherein: The gate electrode is located between adjacent pixel electrodes; The orthographic projections of the first electrode and the second electrode on the substrate are located within the orthographic projection of the semiconductor layer on the substrate, and the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the gate electrode on the substrate; The gate electrode is configured to control the data signal to be transmitted from the data signal line to the pixel electrode via the control transistor, the switching portion, and the fourth conductive layer.

10. The display substrate according to claim 9, wherein: The sub-pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the first direction, the first sub-pixel and the second sub-pixel are located between adjacent data signal lines, and the voltage signal line is located in the first sub-pixel. between the pixel and the second sub-pixel; The gate electrode comprises a first gate electrode and a second gate electrode, wherein the first gate electrode and the second gate electrode are adjacently arranged in the second direction; The first gate electrode is configured to control a control transistor of the first sub-pixel proximate to the first gate electrode; The second gate electrode is configured to control a control transistor of the second sub-pixel proximate to the second gate electrode.

11. The display substrate according to any one of claims 1 to 5, wherein: The first electrodes include common electrodes, and a plurality of first electrode via holes are disposed on a side of each common electrode away from the substrate; The third conductive layer further includes a connecting portion, wherein the connecting portion electrically connects the transition portions of the common electrodes adjacent to each other in the second direction. The connecting portion is configured to electrically connect common electrodes adjacent to each other in the second direction through a fourth conductive layer located in the first electrode via hole and the transition portion.

12. The display substrate according to claim 11, wherein: The second conductive layer also includes voltage signal lines arranged at intervals in the second direction and extending along the first direction; The voltage signal line is electrically connected to the common electrode.

13. The display substrate according to claim 12, wherein: The gate electrode is disposed adjacent to the voltage signal line, and the gate electrode and the voltage signal line are located between adjacent common electrodes.

14. The display substrate according to claim 13, wherein: The third conductive layer also includes: Data signal lines arranged at intervals in the first direction and extending along the second direction; and a first electrode and a second electrode constituting the control transistor; The first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the pixel electrode through a third electrode via hole.

15. A method for manufacturing a display substrate, wherein: include: A first conductive layer is formed on one side of the base substrate, wherein the first conductive layer includes first electrodes arranged at intervals in the second direction to form sub-pixels on the base substrate, and the sub-pixels on the base substrate are arranged in the first direction and the second direction. The array is arranged such that the first direction intersects the second direction; Forming a second conductive layer on a side of the first conductive layer away from the substrate, wherein the second conductive layer is arranged at intervals in the second direction and extends along the first direction to form a gate electrode of the control transistor; forming a semiconductor layer on a side of the second conductive layer away from the base substrate, wherein an orthographic projection of the semiconductor layer on the base substrate is located within an orthographic projection of the second conductive layer on the base substrate; Forming a third conductive layer on a side of the semiconductor layer away from the base substrate, the third conductive layer comprising a transition portion whose orthographic projection on the base substrate is located within the orthographic projection of the first electrode on the base substrate; forming a passivation layer on a side of the third conductive layer away from the substrate; forming a first electrode via hole, wherein the first electrode via hole penetrates the passivation layer and exposes the first electrode and a portion of the transition portion, wherein an opening area of ​​the first electrode via hole gradually decreases from a direction away from the substrate toward a direction close to the substrate, and the exposed transition portion constitutes a portion of a via hole side wall of the first electrode via hole; as well as A fourth conductive layer is formed in the first electrode via hole, and the fourth conductive layer electrically connects the first electrode and the transition portion.

16. The method according to claim 15, wherein: Forming the first electrode via hole includes: forming a first sub-via hole and forming a second sub-via hole, The first sub-via hole exposes a portion of the first electrode, and an orthographic projection of the first sub-via hole on the base substrate does not overlap with an orthographic projection of the transition portion on the base substrate. The second sub-via hole exposes a portion of the transition portion, and an orthographic projection of the second sub-via hole on the base substrate overlaps with an orthographic projection of the transition portion on the base substrate.

17. The method according to claim 16, wherein: Forming the first sub-via and forming the second sub-via include: Coating a photoresist on a side of the passivation layer away from the substrate; Fully exposing the photoresist region corresponding to the first sub-via hole, and half exposing the photoresist region corresponding to the second sub-via hole; Etching the film material in the area corresponding to the first sub-via hole to expose the first electrode; etching the film material in the area corresponding to the second sub-via hole to expose the transition portion, The exposed transition portion constitutes a via hole side wall of the first electrode via hole.

18. The method according to claim 17, wherein: Etching the film material in the area corresponding to the first sub-via hole includes: The passivation layer in a region corresponding to the first sub-via hole and the insulating layer in a region corresponding to the first sub-via hole and located between the passivation layer and the first electrode are etched by a first dry etching medium.

19. The method according to claim 17, wherein: Etching the film material in the area corresponding to the second sub-via hole includes: Etching the photoresist material corresponding to the second sub-hole area by a second dry etching medium; The passivation layer material corresponding to the second sub-hole region is etched using a first dry etching medium.

20. The method according to claim 17, wherein: Also includes: The photoresist on the upper side of the passivation layer is etched by a second dry etching medium.

21. The method according to claim 16, wherein: Forming the first sub-via and forming the second sub-via include: Coating a first photoresist on a side of the passivation layer away from the substrate; Fully exposing the first photoresist region corresponding to the first sub-via hole; Etching the film material in the area corresponding to the first sub-via hole to expose the first electrode; stripping the first photoresist; Coating a second photoresist on a side of the passivation layer away from the substrate so that a portion of the second photoresist fills the first sub-via hole; Fully exposing the second photoresist region corresponding to the second sub-via hole; Etching the film material in the area corresponding to the second sub-via hole to expose the transition portion, wherein the exposed transition portion constitutes a via hole side wall of the first electrode via hole; The second photoresist is stripped.

22. A display device, wherein: include: A display substrate according to any one of claims 1 to 14.

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