Data transmission method for chiplet interconnection interface, and chiplet interconnection interface

Abstract

Embodiments of the present disclosure provide a data transmission method for a chiplet interconnection interface, and a chiplet interconnection interface. The data transmission method is applied to a receiving end. The method comprises: receiving N data signals and a first clock signal, wherein the number of periods of the first clock signal is limited, the number of periods of each data signal among the N data signals is less than or equal to that of the first clock signal, and N is a positive integer; and on the basis of the first clock signal, positioning a starting position of data among the N data signals, and obtaining the data among the N data signals. According to the embodiments of the present disclosure, a receiving end uses a first clock signal to obtain data among data signals, and does not use an effective flag bit, so that clock and data alignment training does not need to be performed in advance, and real-time alignment can also be realized.

Description

Data transmission method for chiplet interconnection interface and chiplet interconnection interface

[0001] This application claims priority to Chinese Patent Application No. 202310802966.6 filed on June 30, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a data transmission method, a transmitting end, a receiving end, a chip interconnection interface, a chip, and an electronic device. Background Art

[0003] A chiplet is a unit chip with specific functions and internal interconnect interfaces. It is the latest development in chip design technology. Chiplet technology uses multiple chiplets to implement chip design, which not only reduces costs but also improves chip performance.

[0004] Inter-chiplet interconnection naturally becomes a key factor influencing chip performance. Currently, there are two implementation methods: serial bus and parallel bus. Parallel bus interconnection is currently the mainstream. Parallel buses can provide shorter latency between two chiplets and can also expand the bandwidth between chiplets by increasing bus bandwidth.

[0005] After achieving physical interconnection, chiplet interconnection also requires data link training, where clock-to-data alignment is essential for data transmission. However, clock-to-data alignment is an integral part of data link training. If clock-to-data misalignment occurs after training, the entire data link training must be repeated, severely impacting chip operation.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a data transmission method, a transmitting end, a receiving end, a chip interconnection interface, a chip, and an electronic device.

[0008] In a first aspect, at least one embodiment of the present disclosure provides a data transmission method, applied to a receiving end, comprising: receiving N data signals and a first clock signal, the first clock signal having a limited number of cycles, the number of cycles of each of the N data signals being less than or equal to the number of cycles of the first clock signal, and N being a positive integer; locating the starting position of the data in the N data signals according to the first clock signal, and obtaining the data in the N data signals.

[0009] For example, in a method provided in an embodiment of the present disclosure, the starting position of data in N data signals is located according to a first clock signal, and the data in the N data signals is obtained, including: obtaining N second clock signals according to the first clock signal, the N second clock signals corresponding to the N data signals respectively; locating the starting position of data of each of the N data signals according to the N second clock signals, and converting the data in the N data signals from serial data to parallel data respectively; wherein each of the N second clock signals has the same number of cycles as the first clock signal.

[0010] For example, in a method provided in an embodiment of the present disclosure, after acquiring data in N data signals, the method further includes: saving the data in the N data signals to a buffer memory according to N second clock signals.

[0011] For example, in a method provided in an embodiment of the present disclosure, the method further includes: reading data in N data signals from a buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal of the receiving end.

[0012] For example, in a method provided in an embodiment of the present disclosure, data in a data signal is read from a buffer memory according to a third clock signal, including: accessing a read pointer of the buffer memory according to the third clock signal to read data in N data signals.

[0013] For example, in a method provided in an embodiment of the present disclosure, data in N data signals are correspondingly saved to a buffer memory according to N second clock signals, including: accessing the write pointer of the buffer memory respectively according to the N second clock signals to save the data in the N data signals to the buffer memory.

[0014] For example, in a method provided in an embodiment of the present disclosure, the method further includes: after at least one empty data is read from the buffer memory, stopping reading from the buffer memory.

[0015] For example, in the method provided in one embodiment of the present disclosure, the number of cycles of each data signal in N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

[0016] In a second aspect, at least one embodiment of the present disclosure provides a data transmission method, applied to a transmitting end, comprising: sending N data signals and a first clock signal, wherein N is a positive integer, the number of cycles of the first clock signal is limited, the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.

[0017] For example, in a method provided in an embodiment of the present disclosure, sending N data signals and a first clock signal includes: sending N data signals and the first clock signal at the same time; or, sending the first clock signal first, and then sending N data signals after a preset period.

[0018] For example, in a method provided in an embodiment of the present disclosure, the method further includes: stopping sending the first clock signal when or after the N data signals stop sending.

[0019] For example, in the method provided in one embodiment of the present disclosure, the number of cycles of each data signal in N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

[0020] In a third aspect, at least one embodiment of the present disclosure provides a receiving end, applied to a chip interconnection interface, comprising: N data ports, configured to receive N data signals, where N is a positive integer; a clock port, configured to receive a first clock signal, the first clock signal has a limited number of cycles, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal; a data processing module, connected to the N data ports and the clock port, configured to locate the starting position of the data in the N data signals according to the first clock signal, and obtain the data in the N data signals.

[0021] For example, in the receiving end provided in one embodiment of the present disclosure, the receiving end also includes: a clock acquisition module, connected to the clock port and the data processing module, configured to obtain N second clock signals based on the first clock signal, and send the N second clock signals to the data processing module; the data processing module is configured to convert the data in the N data signals from serial data to parallel data according to the N second clock signals; wherein each of the N second clock signals has the same number of cycles as the first clock signal.

[0022] For example, in a receiving end provided in an embodiment of the present disclosure, the receiving end further includes: a buffer memory connected to the data processing module and configured to store data in N data signals.

[0023] For example, in the receiving end provided in an embodiment of the present disclosure, the data processing module is further configured to access the write pointer of the buffer memory respectively according to N second clock signals to save the data in the N data signals to the buffer memory.

[0024] For example, in the receiving end provided in one embodiment of the present disclosure, the receiving end also includes: a data reading module, connected to the buffer memory, and configured to read data from N data signals from the buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal of the receiving end.

[0025] For example, in the receiving end provided in an embodiment of the present disclosure, the data reading module is further configured to access the read pointer of the buffer memory according to the third clock signal to read data in the N data signals.

[0026] For example, in the receiving end provided in an embodiment of the present disclosure, the data reading module is further configured to stop reading data from the buffer memory after reading at least one empty data from the buffer memory.

[0027] For example, in the receiving end provided in an embodiment of the present disclosure, the buffer memory is an asynchronous FIFO memory.

[0028] For example, in a receiving end provided in an embodiment of the present disclosure, the receiving end further includes: a local clock configured to generate a local clock signal.

[0029] For example, in the receiving end provided in an embodiment of the present disclosure, the number of cycles of each data signal in N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

[0030] In a fourth aspect, at least one embodiment of the present disclosure provides a transmitting end, applied to a chip interconnection interface, comprising: N data ports, configured to correspondingly send N data signals, where N is a positive integer; a clock port, configured to send a first clock signal; a local clock, connected to the clock port and the N data ports, configured to generate a first clock signal; wherein the number of cycles of the first clock signal is limited, the number of cycles of each data signal in the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.

[0031] For example, in the transmitting end provided in one embodiment of the present disclosure, N data ports and clock ports are configured to send N data signals and a first clock signal at the same time; or, the clock port is configured to send the first clock signal first, and the N data ports are configured to send N data signals after a preset period after the first clock signal is sent.

[0032] For example, in the transmitting end provided in one embodiment of the present disclosure, the transmitting end also includes: a clock switch, connected to the local clock and to the clock port, and configured to disconnect the local clock from the clock port when N data signals stop sending or after one cycle of stopping sending.

[0033] For example, in the transmitting end provided in an embodiment of the present disclosure, the number of cycles of each data signal of N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

[0034] In a fifth aspect, at least one embodiment of the present disclosure further provides a chip interconnection interface configured to execute any method as described in the first aspect above.

[0035] In a sixth aspect, at least one embodiment of the present disclosure further provides a chip interconnection interface configured to execute any method as described in the second aspect above.

[0036] In a seventh aspect, at least one embodiment of the present disclosure further provides a chip interconnection interface, comprising a receiving end as described in any one of the third aspects.

[0037] In an eighth aspect, at least one embodiment of the present disclosure further provides a chip interconnection interface, comprising a transmitting end as described in any one of the third aspects.

[0038] In the ninth aspect, at least one embodiment of the present disclosure further provides a chip comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface such as the fifth aspect or the seventh aspect and a core particle interconnection interface such as the sixth aspect or the eighth aspect.

[0039] In a tenth aspect, at least one embodiment of the present disclosure provides an electronic device comprising the chip according to the ninth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0041] FIG1 shows a schematic diagram of a chip interconnection interface in the prior art;

[0042] FIG2 is a schematic diagram showing clock-to-data alignment between chiplets in the prior art;

[0043] FIG3 shows a flowchart of a data transmission method provided according to at least one embodiment of the present disclosure;

[0044] FIG4 shows a flowchart of another data transmission method provided according to at least one embodiment of the present disclosure;

[0045] FIG5 shows a schematic diagram of a receiving end provided by at least one embodiment of the present disclosure;

[0046] FIG6 shows a schematic diagram of a transmitting end provided by at least one embodiment of the present disclosure;

[0047] FIG7 a shows a schematic structural diagram of a clock switch provided by at least one embodiment of the present disclosure;

[0048] FIG7 b shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure;

[0049] FIG7c shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure;

[0050] FIG8 shows a schematic diagram of a chip provided by at least one embodiment of the present disclosure;

[0051] FIG9 shows a timing diagram of a data transmission method after chiplet interconnection according to at least one embodiment of the present disclosure; and

[0052] FIG10 shows a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0055] Data link training typically occurs after the chiplet is initialized. It requires collaboration between the transmitting and receiving chiplets, enabling the receiving chiplet to find the most appropriate data sampling window. Complete data link training includes multiple components, such as offset calibration, reference power supply Vref calibration, data path deskew, clock and data alignment (CDA), parallel data reordering, and data checking. Clock and data alignment adjusts the phase between data and clock to achieve the appropriate sampling phase.

[0056] FIG1 shows a schematic diagram of a chip interconnection interface in the prior art.

[0057] In Figure 1, chiplet A and chiplet B are connected via chiplet interconnect interface 110 and chiplet interconnect interface 120. Chiplet A is the transmitting side, and chiplet B is the receiving side. Chiplet interconnect interface 110 includes multiple data ports 111, clock port 112, and a local clock 113. Chiplet interconnect interface 120 includes multiple data ports 121, clock port 122, a clock receiving module 123, and a data sampling module 124. The multiple data ports 111 and the multiple data ports 121 have the same number of data ports, which are connected via multiple data paths. Clock port 112 is connected to clock port 122 via a clock path. Local clock 113 generates a clock signal and sends the clock signal to the multiple data ports 111 and clock port 112. Clock receiving module 123 receives the clock signal generated by local clock 113, adjusts the clock signal, and sends the adjusted clock signal to data sampling module 124. Data sampling module 124 uses the clock signal to perform data sampling. The clock signal can be a differential clock signal. Clock and data signals are continuously sent to chiplet B. The data signal carries both valid data and null data, meaning that the data signal doesn't carry only valid data. Valid data is what chiplet A wants to send to chiplet B. Chiplet A transmits valid data according to a preset data format. Each transmission of valid data is limited in length, and valid data is not sent continuously, leaving time gaps. Null data is used to fill in the gaps between valid data. Therefore, data transmission between chiplets A and B can result in data misalignment between multiple data channels. In existing technologies, pre-training of clock-to-data alignment is required to receive accurate data.

[0058] FIG. 2 shows a schematic diagram of clock and data alignment between chiplets in the prior art.

[0059] Valid flags are commonly used to train clock-to-data alignment. Cores A and B in Figure 2 can be the same cores A and B shown in Figure 1. The valid flag is vld, which takes a value of 1. The transmitter replicates it three times to create a 3-bit data stream. The first 3 bits of each data channel carry the valid flag. The valid flag indicates the beginning of a valid data segment. Based on the valid flag, core B can accurately locate valid data from each data signal. Valid data has a defined format, including length. Therefore, upon detecting the valid flag, core B can locate a valid data segment. In Figure 2, the three data signals transmitted from core A are aligned. However, there is a phase difference or delay between the three data signals received by core B. This delay is difficult to eliminate and is affected by various factors, including core design, operating environment, temperature, humidity, and manufacturing process. The receiver determines that the data channels are aligned as long as it successfully receives two of the three valid flags.

[0060] Although there is a phase difference between the two lower data paths and the first upper data path in Figure 2, two valid flag bits are still aligned across the three data paths, thus confirming that the three data paths are aligned. This alignment is not absolute; a certain degree of error is tolerated. However, clock-to-data alignment training is included in complete data link training. If misalignment between data signals or between data and clock occurs during normal chip operation, the entire data link training must be repeated, even if other training steps are unnecessary. This can severely impact chip operation and increase power consumption.

[0061] Based on this, the embodiments of the present disclosure provide a data transmission method, a transmitting end, a receiving end, a chip interconnection interface, a chip and an electronic device, which can realize real-time clock and data alignment between chiplets without the need for prior clock-to-data alignment training, and provide a feasible solution for removing clock-to-data alignment from data link training.

[0062] The embodiments provided by the present disclosure are described below with reference to the accompanying drawings.

[0063] FIG3 shows a flowchart of a data transmission method according to at least one embodiment of the present disclosure.

[0064] The data transmission method 300 shown in FIG3 is applied to the receiving end of the chiplet interconnection interface.

[0065] The data transmission method 300 includes the following steps:

[0066] Step S310: Receive N data signals and a first clock signal, where N is a positive integer, the first clock signal has a finite number of cycles, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal.

[0067] Step S320 , locating the starting position of data in the N data signals according to the first clock signal, and acquiring the data in the N data signals.

[0068] In the present disclosure, N data signals correspond to N data paths, and the first clock signal corresponds to a clock path. Each data path transmits one data signal, and each data signal carries serial data. The first clock signal can be a differential clock signal. For example, N is 2, 3, 4, ..., 16, etc. The value of N is related to the bandwidth required by the chiplet interconnect interface. The more data paths, the greater the bandwidth for data transmission between chiplets. The number of data paths can be set according to requirements.

[0069] The data carried by each data signal is of limited length, that is, the number of cycles carrying data in each data signal is limited. The number of cycles of the N data signals or the number of cycles of each data signal involved in the embodiments of the present disclosure refers to the number of cycles carrying valid data. The number of cycles may also be referred to as length or cycle length, and these terms can be interchanged in the present disclosure. It can be understood that data transmission between core particles usually has a fixed data format, that is, the length of data transmitted each time is fixed and equal, for example, the data format stipulates that the data length is 128 bits. The number of cycles of the N data signals in this embodiment is equal, that is, the number of cycles of the N data signals and the number of cycles of each data signal refer to the same number of cycles.

[0070] The data in each data signal does not include a valid flag. The data carried in each data signal can have a predefined data format, such as a predetermined data length or number of cycles. For example, the number of cycles is 8. For ease of description, the length or number of cycles of the data signal mentioned in this disclosure refers to the portion of the data signal that carries valid data, and the data in the data signal also refers to valid data. The data signal in this disclosure is a square wave, and the square wave may be continuously received, but the portion carrying data is the portion of the data signal to be discussed in this disclosure.

[0071] Accordingly, the length of the first clock signal is also limited, which is the length of the valid clock cycle, for example, 4 cycles. The valid clock cycle of the first clock signal is, for example, a cycle with clock transitions, and each valid clock cycle includes one rising edge and one falling edge of the clock. The first clock signal can also be transmitted in the form of a square wave. Unlike the data signal, the first clock signal in the present disclosure is a square wave when valid and can be a continuous low level when invalid.

[0072] The data in the data signal of the present disclosure does not carry a valid flag, but instead utilizes a first clock signal to determine the starting position of the data. The N data signals correspond to the first clock signal, where the difference in the number of cycles is less than or equal to a preset number. For example, the first clock signal has a finite number of cycles and the number of cycles of the first clock signal is greater than or equal to the number of cycles of each data signal. Preferably, the number of cycles of the first clock signal is equal to the number of cycles of each data signal.

[0073] The length of the first clock signal needs to be greater than or equal to the length of each data signal, and the length of each data signal is the same. Only when the length of the first clock signal is greater than or greater than the length of the data signal can the data in the data signal be fully acquired, otherwise data incompleteness may occur. For example, it can be considered that the first clock signal determines the starting position of the data in the data signal. The solution disclosed in this disclosure does not involve a valid flag bit, so the position of the first time period of the first clock signal corresponds to the starting position of the data carried in the data signal, such as Figure 9. For example, the number of N data signal cycles is M, and the number of N first clock signal cycles is M+X, where M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0. X also needs to be less than or equal to a preset number. The preset number is, for example, 1, 2, 3, 4, etc. The preset number can be adjusted according to demand. The smaller the preset number, the shorter the length of the first clock signal, and thus the lower the power consumption of sending and receiving the first clock signal.

[0074] When executing step S320, due to the correspondence between the first clock signal and the N data signals, the data in the data signal can be obtained based on the first clock signal. The data in the data signal here refers to the valid data carried by the data signal. In this embodiment, the opposite of valid data is invalid data or empty data. Invalid data or empty data can be garbled code, preset filler values, etc., so that after reading invalid data or empty data, it is determined that the valid data in the data signal has been received. For example, in this embodiment, the first clock signal does not exist continuously but is of limited length, and the first clock signal is used to locate the position of the data in the data signal.

[0075] According to the method provided in this embodiment, there is a corresponding relationship between the N received data signals and the first clock signal, so that the first clock signal can be used to determine and obtain the data in the data signal. The data does not need to include a valid flag bit, nor does it need to be trained in advance for clock-to-data alignment, and the clock-to-data alignment effect can be obtained in real time.

[0076] In some embodiments, executing step S320 may include: locating the starting position of data in N data signals according to the first clock signal, and obtaining N second clock signals, where the N second clock signals correspond to the N data signals respectively; locating the starting position of data of each of the N data signals according to the N second clock signals, and converting the data in the N data signals from serial data to parallel data respectively; wherein each of the N second clock signals has the same number of cycles as the first clock signal.

[0077] For example, the first clock signal is expanded into N second clock signals without changing the frequency and number of cycles (or length) of the clock signal. Different phase differences may exist between the N second clock signals. For example, when obtaining N second clock signals, different phases are adjusted for each second clock signal, such as the clock signals of multiple lanes in Figure 9 have different phase differences. The phase difference in this embodiment can be understood as a delay. The data in the N data signals is then positioned according to each clock signal in the N second clock signals, for example, the starting position of the positioning data.

[0078] For example, N second clock signals are used to sample N data signals accordingly, thereby converting the data in each data signal from serial to parallel, wherein each second clock signal is used to sample a corresponding data signal. For example, data sampling is performed once at each falling edge or each rising edge of the clock to obtain the data in the data signal.

[0079] In some embodiments, after acquiring the data in the N data signals, the data transmission method further includes: saving the data in the N data signals to a buffer memory according to the N second clock signals.

[0080] Optionally, the data in each data signal can be stored in a portion of the buffer memory's storage area, or in a separate buffer memory. That is, the number of buffer memories can be one or N. For example, after deserializing the data in the data signal, several data blocks are obtained. Each data block can be stored in a storage space in the buffer memory, such as an entry or a segment of the address space. Data from different data signals can be stored in different buffer memories, which simplifies implementation and facilitates subsequent processing.

[0081] When storing data in N data signals in different areas of a buffer memory, the buffer memory reserves a fixed storage area for the data in each data signal. For example, the buffer memory is divided into N storage areas, each storage area including multiple storage spaces.

[0082] In some embodiments, storing data in the N data signals in the buffer memory includes: accessing write pointers of the buffer memory respectively according to N second clock signals to store the data in the N data signals in the buffer memory.

[0083] For example, when there is only one buffer memory, N second clock signals are used to access write pointers of different storage areas to store data in the N data signals into different storage areas. The buffer memory may include N storage areas, each storage area having its own write pointer and read pointer.

[0084] For another example, when there are N buffer memories, N second clock signals are used to access write pointers of different buffer memories to store data in the N data signals into the different buffer memories.

[0085] For example, the buffer memory writes data by accessing a write pointer. Therefore, the second clock signal can be used to count the write pointer. For example, each rising or falling edge of the second clock signal causes the write pointer to increment by 1, pointing to the next storage space. Each write pointer regularly cycles through several storage spaces within a storage area. For example, the write pointer jumps according to the storage space address, from largest to smallest or vice versa.

[0086] In some embodiments, the data transmission method further includes: reading data from the N data signals from the buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal of the receiving end. The data from the N data signals can be read using the same third clock signal.

[0087] The method of reading data from the buffer memory is similar to the method of saving data. For example, the read pointer of the buffer memory can be accessed according to the third clock signal to read the data in N data signals. For example, when there are N buffer memories, the N buffer memories can be accessed according to the third clock signal to obtain the data in the N data signals. After the read pointer of the buffer memory is accessed, the value of the read pointer will also be increased by 1 and point to the next storage space. Optionally, the number of values ​​of the read pointer is limited or the value range is limited, and the value of the read pointer jumps cyclically within the value range. For example, the read pointers of the N buffer memories are accessed and counted according to the rising edge or falling edge of the third clock signal, so that the data in the N data signals can be read out simultaneously.

[0088] Optionally, after the data in the N data signals are saved in the buffer memory, they can be read out simultaneously. For example, after determining that the data in all N data signals are saved in the buffer memory accordingly, a third clock signal can be used to read them simultaneously. The length of the data in the N data signals and the number of data blocks are specified to be the same, and the data blocks can be saved in several similar storage spaces in different buffer memories, or the data blocks can be saved in the same order. Therefore, when reading data, the same signal can be used to trigger, so that the data in different buffer memories or different storage areas can be read simultaneously and in order. The third clock signal can also be a clock signal generated according to the first clock signal, for example, a third clock signal whose length exceeds the first clock signal is generated according to the frequency of the first clock signal, or the first clock signal is delayed to obtain the third clock signal.

[0089] Using the method of this embodiment, the data in the N data signals can be considered "aligned" and stored in a buffer memory. The data in the buffer memory can then be read using the same third clock signal. This reading process is also "aligned." Even if the N data signals are misaligned during transmission (for example, the phase difference between different data signals exceeds 2 cycles), the final data obtained will still be aligned. Therefore, even if misalignment occurs between data channels under normal operation of the core, there is no need to retrain the data link. Furthermore, using the method of this embodiment, clock-to-data alignment training can be eliminated during the data link training phase. Data alignment can be completed directly by correspondingly sending / receiving the N data signals and the first clock signal. Since clock-to-data alignment training and repeated data link training are not required, not only the design complexity is reduced, but also power consumption is reduced.

[0090] In some embodiments, the data transmission method further includes stopping reading the N buffer memories after at least one empty data is read from the buffer memory.

[0091] In this embodiment, the data length of each data signal is limited, so after empty data is read from the buffer memory, it can be considered that the data reading is completed and access to the buffer memory is stopped.

[0092] The data transmission method at the receiving end of the chiplet interconnection interface is described above with reference to the accompanying drawings. The data transmission method at the transmitting end of the chiplet interconnection interface will be described below with reference to FIG. 4 .

[0093] At least one embodiment of the present disclosure also provides a data transmission method, applied to a transmitting end, comprising: sending N data signals and a first clock signal, wherein N is a positive integer, and there is a corresponding relationship between the N data signals and the first clock signal, the corresponding relationship being that the difference in the number of cycles is less than or equal to a preset number, and the first clock signal is used to obtain data in the N data signals.

[0094] 4 shows a flow chart of another data transmission method provided according to at least one embodiment of the present disclosure. The data transmission method 400 is applicable to a transmitting end.

[0095] In FIG4 , the data transmission method 400 includes the following steps:

[0096] Step S410, sending N data signals and a first clock signal, where N is a positive integer, the number of cycles of the first clock signal is limited, the number of cycles of each data signal in the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.

[0097] The definitions of the N data signals and the first clock signal can be found in the relevant description in FIG3 and will not be repeated here. In this embodiment, not any clock signal with the same number of cycles as the number of cycles of the data signal can be used to obtain data in the data signal. There is a corresponding relationship between the first clock signal and the N data signals. For example, when the first clock signal and the N data signals are sent, they are aligned or sent simultaneously, so that the first edge of the first clock signal is aligned with the first cycle of the N data signals that carries valid data. For the receiving end, this corresponding relationship does not change after design or data de-skew training.

[0098] Optionally, the number of cycles of each of the N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

[0099] Each of the N data signals has the same number of cycles. The number of cycles of the first clock signal is greater than or equal to the number of cycles of the data signal, thereby ensuring that the data in the data signal is fully acquired. For example, M is equal to 6, and X is equal to 1 or 2. Optionally, the difference between the number of cycles of the first clock signal and the number of cycles of the data signal is less than a preset value. For example, the preset value is 4 or 3. When the number of cycles of the first clock signal does not exceed the number of cycles of the data signal by a large amount, power used to receive the first clock signal can be saved.

[0100] In a further embodiment, when executing step S410, N data signals and the first clock signal may be sent simultaneously; or, the first clock signal may be sent first, and then the N data signals may be sent after a preset period length.

[0101] For example, when the number of cycles of the first clock signal is equal to or greater than the number of cycles of the data signal, the corresponding data signal and the first clock signal can be sent simultaneously. When the number of cycles of the first clock signal is greater than the number of cycles of the data signal, the first clock signal can be sent first, and then the data signal, so as to ensure that the first clock signal can "cover" all cycles of the data signal.

[0102] Optionally, the sending of the first clock signal is related to the sending of the data signal, for example, the sending of the data signal determines the sending of the first clock signal. For example, the first clock signal can be set to be sent at the same time as the N data signals are sent, so that the starting position of the first clock signal is aligned with the starting position of the data in the N data signals.

[0103] In some embodiments, the data transmission method further includes: stopping sending the first clock signal when or after the N data signals stop sending.

[0104] For example, stopping the transmission of each data signal can also be understood as completing the transmission of each data signal. When all data signals stop being transmitted, you can choose to stop transmitting the first clock signal, or continue transmitting the first clock signal for a few cycles. This ensures that the number of cycles of the first clock signal is greater than or equal to the number of cycles of the data signal, and also stops continuing the clock cycles that will not be used subsequently. In other words, the clock signal is stopped when no data signals are being transmitted, thereby reducing the power consumption caused by transmitting the clock signal.

[0105] At least one embodiment of the present disclosure further provides a chiplet interconnect interface configured to execute any of the methods in the first method embodiment described above. For example, the chiplet interconnect interface includes a processing module that can implement the method in the method embodiment described above.

[0106] At least one embodiment of the present disclosure further provides a chiplet interconnect interface configured to execute any of the methods in the second method embodiment described above. For example, the chiplet interconnect interface includes a processing module that can implement the method in the method embodiment described above.

[0107] Figure 5 shows a schematic diagram of a receiving end provided by at least one embodiment of the present disclosure. The receiving end 500 in this embodiment can execute the data transmission method described with reference to Figure 3 , and its execution method can be found in the relevant description of Figure 3 .

[0108] In Figure 5, a receiving end 500 includes N data ports 510, a clock port 520, and a data processing module 530. The data processing module 530 is connected to each of the N data ports 510, and the data processing module 530 is connected to the clock port 520. The receiving end 500 is connected to N data paths and one clock path, with each data path connected to one data port.

[0109] The N data ports 510 correspondingly receive N data signals. N is a positive integer. The N clock ports 520 correspondingly receive N first clock signals. The N data signals correspond to the first clock signal, where the difference in the number of cycles is less than or equal to a preset number. For example, the first clock signal has a limited number of cycles, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal. The data processing module 530 locates the starting position of the data in the N data signals based on the N first clock signals and obtains the data in the N data signals.

[0110] Optionally, the receiving end further includes: a clock acquisition module connected to the clock port and the data processing module, configured to acquire N second clock signals based on the first clock signal, and send the N second clock signals to the data processing module.

[0111] In this implementation, the clock port is not directly connected to the data processing module, but rather is connected to the data processing module via a clock acquisition module. The clock acquisition module can extend or delay the first clock signal to obtain N second clock signals. In an implementation without a clock acquisition module, the first clock signal can be delayed and extended through circuit design, for example, by adjusting the phase difference between the second clock signals using the length of the connecting wire.

[0112] Further optionally, the data processing module is configured to convert data in the N data signals from serial data to parallel data according to N second clock signals, wherein each of the N second clock signals has the same number of cycles as the first clock signal.

[0113] For example, when the number of data processing modules is N, each data processing module is connected to one second clock signal and is responsible for serial-to-parallel conversion of the data of one corresponding data signal. When the number of data processing modules is one, the data processing module may include multiple processing units, each processing unit being connected to one second clock signal and being responsible for serial-to-parallel conversion of the data of one corresponding data signal.

[0114] For example, the data processing module 530 includes a serial-to-parallel converter, which can convert serial data into parallel data. In another example, the data processing module 530 includes a sampler and a demultiplexer. The sampler can sample the data in the data signal according to the second clock signal to obtain the data in the data signal, and then convert the sampled data into parallel data through the demultiplexer.

[0115] In some embodiments, the receiving end further includes a buffer memory connected to the data processing module and configured to store data in the N data signals. For example, the number of the buffer memories is 1 or N.

[0116] For example, the receiving end 500 further includes N buffer memories 540, which are indicated by dashed boxes in the figure. The N buffer memories 540 respectively store data in the N data signals.

[0117] In some embodiments, the data processing module is further configured to access write pointers of N buffer memories correspondingly according to the N second clock signals to save data in the N data signals.

[0118] For example, data is written to buffer memory 540 by accessing a write pointer. Therefore, the second clock signal can be used to count the write pointer. For example, each rising or falling edge of the second clock signal causes the write pointer to increment by 1, pointing to the next storage space. Because the period of the second clock signal corresponds to the period of the corresponding data signal, the write pointer count is controlled according to the second clock signal, allowing the data in the data signal to be completely written to the N buffer memories 540.

[0119] Optionally, each of the N buffer memories 540 is an asynchronous FIFO memory.

[0120] In some embodiments, the receiving end further includes: a data reading module connected to the buffer memory and configured to read data from the N data signals from the buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal.

[0121] For example, the receiving end 500 further includes a data reading module 550. The number of data reading modules 550 is one. The data reading module 550 is connected to N buffer memories 540. The data reading module 550 can simultaneously read data from N data signals from the N buffer memories 540 according to the third clock signal. It should be noted that the data reading module 550 must wait until all N buffer memories 540 have written data before reading data.

[0122] In some embodiments, the data reading module is further configured to access a read pointer of the buffer memory according to a third clock signal to read data in the N data signals.

[0123] For example, the data reading module 550 can simultaneously access the read pointers of the N buffer memories 540 according to the third clock signal. For example, the read pointers of the N buffer memories 540 are accessed and counted according to the rising edge or falling edge in each cycle of the third clock signal, thereby simultaneously reading data from the N data signals.

[0124] In some embodiments, the data reading module is further configured to stop reading data from the buffer memory after at least one empty data is read from the buffer memory.

[0125] For example, the data reading module 550 is configured to determine that all data has been read after reading empty data from the N buffer memories 540, thereby stopping reading data from the N buffer memories 540. For example, the data reading module 550 reads data from the N buffer memories 540 based on a local clock signal. Because the local clock signal is always present, the data reading module 550 needs to use empty data to determine whether all data has been successfully read. In another example, the data reading module 550 reads data from the N buffer memories 540 based on a first clock signal or a second clock signal. The effective clock cycles of the first clock signal and the second clock signal are limited in length. Therefore, the data reading module 550 can automatically stop reading data from the N buffer memories 540 after all effective clock cycles have elapsed.

[0126] In some embodiments, the receiving end further includes: a local clock configured to generate a local clock signal.

[0127] Figure 6 shows a schematic diagram of a transmitter provided by at least one embodiment of the present disclosure. The transmitter 600 in Figure 6 can execute the method shown in Figure 4. For details on the execution method, please refer to the relevant description of Figure 4.

[0128] In Figure 6, a transmitting end 600 includes N data ports 610, a clock port 620, and a local clock 630. The N data ports 610 correspondingly transmit N data signals, where N is a positive integer. The clock port 620 transmits a first clock signal. The local clock 630 generates the first clock signal. The local clock 630 is connected to the clock port 620 and the N data ports 610. The N data signals correspond to the first clock signal, where the difference in the number of cycles is less than or equal to a preset number. For example, the first clock signal has a finite number of cycles, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal. The first clock signal is used to locate the starting position of data in the N data signals and to retrieve data from the N data signals. Optionally, the local clock 630 may be a phase-locked loop.

[0129] In some embodiments, the number of cycles of the N data signals is M, the number of cycles of the N first clock signals is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

[0130] In some embodiments, the N data ports and clock ports are configured to simultaneously send one data signal among the N data signals and a corresponding first clock signal; or, the clock port is configured to send the first clock signal first, and the N data ports are configured to send the N data signals after a preset period after the first clock signal is sent.

[0131] Different transmission methods can be selected. For example, when the number of cycles of the data signal and the first clock signal is equal, they must be sent at the same time. When the number of cycles of the first clock signal is greater than the number of cycles of the data signal, the first clock signal and the data signal can be sent at the same time, or the first clock signal can be sent first and then the data signal. It should be noted that since the first clock signal will be used to locate the data in the data signal, when the first clock signal is sent first, it is necessary to determine the period difference or phase difference between the first clock signal and the data signal, so as to ensure that the receiving end can use the first clock signal to locate the data.

[0132] In some embodiments, the chip interconnect interface further includes: a clock switch connected to the local clock and the clock port, and configured to disconnect the local clock from the clock port when N data signals stop being sent or one cycle after they stop being sent. Optionally, the clock switch can also disconnect the local clock from the clock port after two cycles or a plurality of cycles after the N data signals stop being sent. Optionally, the clock switch can also control the sending of the first clock signal. For example, if the local clock outputs a clock signal that always exists, the clock switch determines whether to send the first clock signal, when to send the first clock signal, and when to stop sending the first clock signal.

[0133] For example, the clock switch 640 shown in a dotted box in Figure 6 is connected to the local clock 630 and is also connected to the clock port 620. The clock switch 640 can control the clock port 620 to send or stop sending the first clock signal.

[0134] Alternatively, the N clock switches 640 may be implemented using clock gating circuits or switches.

[0135] FIG7 a shows a schematic structural diagram of a clock switch provided by at least one embodiment of the present disclosure.

[0136] In Figure 7a, clock switch 700 is a latch-based clock gating circuit. Clock switch 700 includes latch 701 and AND gate 702. Latch 701 receives clock enable signal ClkEn and clock signal Clock as inputs, while AND gate 702 receives clock signal Clock and the output of latch 701 as inputs. Clock switch 700 can shut off the clock signal when clock enable signal ClkEn is inactive low. That is, the first clock signal is a few clock cycles when clock enable signal ClkEn is active high.

[0137] FIG7 b shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure.

[0138] Figure 7b shows a schematic diagram of the data signal and the first clock signal when the clock switch is not used. In Figure 7b, "Clock" represents the clock signal, and "Data" represents the data signal. The data signal in Figure 7b carries four valid data bits: D0, D1, D2, and D3. The remaining shaded portions represent invalid data. The first clock signal in Figure 7b is persistent.

[0139] FIG7 c shows a schematic diagram of a first clock signal and a data signal provided by at least one embodiment of the present disclosure.

[0140] Figure 7c shows a schematic diagram of the data signal and the first clock signal when using a clock switch. In Figure 7c, ClkEn represents the clock enable signal, Clock represents the clock signal, and Data represents the data signal. The data signal in Figure 7c carries four valid data bits: D0, D1, D2, and D3. The remaining shaded portions represent invalid data. The first clock signal in Figure 7b corresponds to the valid data.

[0141] At least one embodiment of the present disclosure further provides a chip comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface as in any one of the first device embodiments described above and a core particle interconnection interface as in any one of the second device embodiments described above.

[0142] At least one embodiment of the present disclosure further provides a chip comprising a plurality of core particles, wherein any two of the plurality of core particles are connected via a core particle interconnection interface as in any one of the third device embodiments described above and a core particle interconnection interface as in any one of the fourth device embodiments described above.

[0143] FIG8 shows a schematic diagram of a chip provided by at least one embodiment of the present disclosure.

[0144] In Figure 8 , chip 800 includes a core 810 and a core 820. Core 810 is the transmitter, and core 820 is the receiver. Figure 8 shows only the core interconnect interface between cores 810 and 820. Core 810 includes a serial-to-parallel converter 811, a phase-locked loop 812, a clock gating control 813, a data port 814, and a clock port 815. Core 820 includes a serial-to-parallel converter 821, a local clock 822, a data port 823, a clock port 824, and an asynchronous FIFO memory 825.

[0145] Data port 814 is connected to data port 823 via a data path. Clock port 815 is connected to clock port 824 via a clock path. FIG8 shows only one data port for illustration. It is understood that an actual design includes at least one data port.

[0146] Serial-to-parallel converter 811 receives parallel data and converts it into serial data, while serial-to-parallel converter 821 converts the serial data into parallel data. Phase-locked loop 812 receives a clock signal, Clock, as input and outputs it to clock gating 813 and serial-to-parallel converter 811 (only one clock signal is shown in the figure). Another input to clock gating 813 is the clock enable signal, ClkEn.

[0147] The clock port 824 sends the received clock signal to the serial-to-parallel converter 821. The serial-to-parallel converter 821 inputs a clock signal into the asynchronous FIFO memory 825. This clock signal controls the write pointer count of the asynchronous FIFO memory 825. The local clock 822 inputs another clock signal into the asynchronous FIFO memory 825. This clock signal controls the read pointer count of the asynchronous FIFO memory 825.

[0148] Optionally, the core 820 may include multiple serial-to-parallel converters 821 and multiple asynchronous FIFO memories 825. The core 820 may also include a clock acquisition module connected to the clock port 824 and the multiple serial-to-parallel converters 821. The clock acquisition module may expand a single clock signal received from the clock port 824 into multiple clock signals, which are then input into the multiple serial-to-parallel converters 821. Accordingly, the multiple asynchronous FIFOs 825 are connected to the multiple serial-to-parallel converters 821, and each serial-to-parallel converter 821 inputs a clock signal into a corresponding asynchronous FIFO memory 825. The local clock 822 is connected to the multiple asynchronous FIFO memories 825 and provides a local clock signal to the multiple asynchronous FIFO memories 825.

[0149] FIG9 shows a timing diagram of a data transmission method after chiplet interconnection according to at least one embodiment of the present disclosure.

[0150] The chiplet interconnection in Figure 9 can be implemented using the interconnection method shown in Figure 8. In Figure 9, lane represents the control signal from the data path, and FIFO represents the control signal of the buffer memory. LaneY_gated_clock represents the first clock signal of data path Y, where Y is 0-N. LaneY_wrpt represents the write pointer signal to the buffer memory. FIFO_read_clock is the second clock signal, which is a continuously available clock signal. FIFO_rdpt is the read pointer signal for the buffer memory. FIFO_read is the read enable signal. FIFO_read_sync is the synchronous read signal for the buffer memory. FIFO_valid is the valid signal for the buffer memory.

[0151] The first clock signal and read pointer signal of each lane correspond to each other, indicating that the data in the data signal is written to the buffer memory when there is a rising or falling edge of the first clock signal. When all buffer memories have data written, the values ​​of the read pointer and write pointer of each buffer memory are not equal. At this time, the read enable signal FIFO_read is pulled high and becomes valid. The read enable signal FIFO_read is then synchronized to the FIFO_read_clock signal, and data is read out in the next cycle (FIFO_valid becomes high and valid in the next cycle). The values ​​0, 1, 2, and 3 of the pointer signal in the figure represent the pointer values, and the data read is the corresponding value. For example, when the value of FIFO_rdpt is 0, it reads the data corresponding to the value of laneY_wrpt being 0. Therefore, when the value of FIFO_rdpt is 1 to 3, the data at the write pointer values ​​1 to 3 in each lane is read.

[0152] After the transmitter stops sending data signals, laneY_gated_clock is turned off or disconnected. Since FIFO_read_clock is still valid, data will continue to be read, but the data read will be empty. As soon as empty data is read, the read enable signal will be pulled low and become invalid, waiting for the next data signal transmission.

[0153] At least one embodiment of the present disclosure provides an electronic device, including the chip as described in the above embodiments.

[0154] FIG10 shows a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0155] Electronic device 1000 includes chip 1001. Chip 1001 is, for example, chip 800 shown in FIG8. Electronic device 1000 can be any device with computing capabilities, such as a computer, server, smartphone, tablet computer, etc., and the embodiments of the present disclosure are not limited thereto.

[0156] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0157] It is worth noting that the step flow charts and the above method descriptions in this application are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given. Some steps can be performed in parallel, independently of each other, or in other appropriate orders. In addition, words such as "secondly," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods.

[0158] The block diagrams of the devices, apparatuses, equipment, and systems described in this application are intended only as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. It should also be noted that in the apparatuses and methods of this application, the components or steps may be decomposed and / or recombined. Such decompositions and / or recombinations shall be considered equivalents of this application.

[0159] The following points need to be explained: (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures can refer to the general design. (2) In the absence of conflict, the embodiments of the present disclosure and the features therein can be combined with each other to obtain new embodiments. The above description is only an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A data transmission method, applied to a receiving end, comprising: Receive N data signals and a first clock signal, wherein the number of cycles of the first clock signal is limited, the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal, and N is a positive integer; According to the first clock signal, the starting position of the data in the N data signals is located, and the data in the N data signals is acquired.

2. The method according to claim 1, wherein: The step of locating the starting position of the data in the N data signals according to the first clock signal and acquiring the data in the N data signals includes: According to the first clock signal, acquiring N second clock signals, wherein the N second clock signals correspond to the N data signals respectively; Locating the starting position of data of each of the N data signals respectively according to the N second clock signals, and converting the data in the N data signals from serial data to parallel data respectively; Each of the N second clock signals has the same number of cycles as the first clock signal.

3. The method according to claim 2, wherein: After acquiring the data in the N data signals, the method further includes: According to the N second clock signals, data in the N data signals are correspondingly saved in a buffer memory.

4. The method according to claim 3, wherein: The method further comprises: reading data of the N data signals from the buffer memory according to a third clock signal, The third clock signal is a local clock signal of the receiving end.

5. The method according to claim 4, wherein: The step of reading data in the data signal from the buffer memory according to the third clock signal comprises: According to the third clock signal, a read pointer of the buffer memory is accessed to read data in the N data signals.

6. The method according to claim 3, wherein: According to the N second clock signals, correspondingly storing the data in the N data signals into a buffer memory comprises: According to the N second clock signals, the write pointers of the buffer memory are accessed respectively to save the data in the N data signals into the buffer memory.

7. The method according to claim 5, wherein: The method further comprises: After at least one empty data is read from the buffer memory, reading from the buffer memory is stopped.

8. The method according to any one of claims 1 to 7, wherein: The number of cycles of each of the N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

9. A data transmission method, applied to a sending end, comprising: Sending N data signals and a first clock signal, Wherein, N is a positive integer, the number of cycles of the first clock signal is limited, the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.

10. The method according to claim 9, wherein: The sending the N data signals and the first clock signal includes: Send the N data signals and the first clock signal simultaneously; or, The first clock signal is sent first, and then the N data signals are sent after a preset period.

11. The method according to claim 9, further comprising: When or after the N data signals stop being sent, the first clock signal stops being sent.

12. The method according to claim 9, wherein: The number of cycles of each of the N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

13. A receiving end, applied to a chiplet interconnection interface, comprising: N data ports are configured to receive N data signals, where N is a positive integer; A clock port configured to receive a first clock signal, wherein the first clock signal has a limited number of cycles, and the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal; The data processing module is connected to the N data ports and the clock port, and is configured to locate the starting position of the data in the N data signals according to the first clock signal, and obtain the data in the N data signals.

14. The receiving end according to claim 13, further comprising: A clock acquisition module, connected to the clock port and the data processing module, configured to acquire N second clock signals according to the first clock signal, and send the N second clock signals to the data processing module; The data processing module is configured to convert the data in the N data signals from serial data to parallel data respectively according to the N second clock signals; Each of the N second clock signals has the same number of cycles as the first clock signal.

15. The receiving end according to claim 14, further comprising: The buffer memory is connected to the data processing module and is configured to store the data in the N data signals.

16. The receiving end according to claim 15, wherein: The data processing module is further configured to access the write pointer of the buffer memory respectively according to the N second clock signals, so as to save the data in the N data signals into the buffer memory.

17. The receiving end according to claim 15, further comprising: A data reading module is connected to the buffer memory and is configured to read data in the N data signals from the buffer memory according to a third clock signal, wherein the third clock signal is a local clock signal of the receiving end.

18. The receiving end according to claim 17, wherein: The data reading module is further configured to access a read pointer of the buffer memory according to the third clock signal to read data in the N data signals.

19. The receiving end according to claim 17, wherein: The data reading module is further configured to stop reading data from the buffer memory after at least one empty data is read from the buffer memory.

20. The receiving end according to claim 15, wherein: The buffer memory is an asynchronous FIFO memory.

21. The receiving end according to claim 13, wherein: The receiving end also includes: A local clock is configured to generate a local clock signal.

22. The receiving end according to claim 13, wherein: The number of cycles of each of the N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

23. A transmitting end, applied to a chiplet interconnection interface, comprising: N data ports are configured to send N data signals correspondingly, where N is a positive integer; A clock port configured to send a first clock signal; a local clock, connected to the clock port and the N data ports, and configured to generate the first clock signal; The number of cycles of the first clock signal is limited, the number of cycles of each of the N data signals is less than or equal to the number of cycles of the first clock signal, and the first clock signal is used to locate the starting position of the data in the N data signals and obtain the data in the N data signals.

24. The transmitting end according to claim 23, wherein: The N data ports and the clock port are configured to simultaneously transmit the N data signals and the first clock signal; Alternatively, the clock port is configured to send the first clock signal first, and the N data ports are configured to send the N data signals after a preset period after the first clock signal is sent.

25. The transmitting end according to claim 23, further comprising: A clock switch is connected to the local clock and the clock port, and is configured to disconnect the local clock from the clock port when the N data signals stop sending or one cycle after they stop sending.

26. The transmitting end according to claim 23, wherein: The number of cycles of each of the N data signals is M, the number of cycles of the first clock signal is M+X, M is an integer greater than or equal to 2, and X is an integer greater than or equal to 0.

27. A chip interconnection interface, comprising a receiving end as claimed in any one of claims 13 to 22.

28. A chip-to-chip interconnection interface, comprising a transmitting end as claimed in any one of claims 23 to 26.

29. A chip comprising a plurality of core particles, wherein: Any two of the plurality of core particles are connected via the core particle interconnection interface as claimed in claim 27 and the core particle interconnection interface as claimed in claim 28.

30. An electronic device comprising the chip according to claim 29.

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