Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of suppressing deterioration of insulation resistance due to moisture intrusion.　This multilayer ceramic capacitor is characterized by comprising: a laminate 12 having a first surface 12a and a second surface 12b opposite to each other in the lamination direction x, a third surface 12c and a fourth surface 12d opposite to each other in a first direction y orthogonal to the lamination direction x, and a fifth surface 12e and a sixth surface 12f opposite to each other in a second direction z orthogonal to the lamination direction x and to the first direction y; a first external electrode 30a disposed on the third surface 12c of the laminate 12; a second external electrode 30b disposed on the fourth surface 12d of the laminate 12; a third external electrode 30c disposed on the fifth surface 12e of the laminate 12; and a fourth external electrode 30d disposed on the sixth surface 12f of the laminate 12, the laminate 12 comprising an internal layer part 18 and two outer layer parts 20a and 20b disposed so as to sandwich the inner layer part 18 in the lamination direction x, wherein the inner layer part 18 includes an inner layer dielectric layer 14a, a first internal electrode 16a having one end in the first direction y exposed on the third surface 12c and the fourth surface 12d, and a second internal electrode 16b having one end in the second direction z exposed on the fifth surface 12e and the sixth surface 12f, the second internal electrode 16b including a first region 40 disposed inside the laminate 12, and a second region 42 extending from the first region 40 to the fifth surface 12e and the sixth surface 12f, wherein the thickness of the second region 42 in the lamination direction x is less than the thickness of the first region 40 in the lamination direction x.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, electronic devices have become increasingly smaller. Furthermore, the number of electronic components mounted in electronic devices has also increased. Among these, multilayer ceramic capacitors, such as the three-terminal feed-through capacitor disclosed in Patent Document 1, have excellent low impedance characteristics in the high frequency band, and increasing the number of multilayer ceramic capacitors (the number of capacitors connected in parallel) enables the design of low impedance circuits.

[0003] Japanese Patent Application Laid-Open No. 2005-44871

[0004] However, increasing the number of multilayer ceramic capacitors can lead to circuit failure if one of the capacitors fails. Therefore, it is necessary to improve the reliability of multilayer ceramic capacitors. In particular, there is a risk that moisture penetration into a multilayer ceramic capacitor will deteriorate its insulation resistance.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor that can suppress deterioration of insulation resistance due to moisture penetration.

[0006] The multilayer ceramic capacitor according to the present invention comprises a laminate having a first surface and a second surface opposed to each other in the lamination direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the lamination direction and the first direction, a first external electrode arranged on the third surface of the laminate, a second external electrode arranged on the fourth surface of the laminate, a third external electrode arranged on the fifth surface of the laminate, and a fourth external electrode arranged on the sixth surface of the laminate, The laminate comprises a layer portion and two outer layer portions arranged to sandwich the inner layer portion in the stacking direction, the inner layer portion comprising an inner dielectric layer, a first inner electrode having one end in a first direction exposed on the third surface and the fourth surface, and a second inner electrode having one end in a second direction exposed on the fifth surface and the sixth surface, the second inner electrode comprising a first region arranged inside the laminate and a second region drawn out from the first region to the fifth surface and the sixth surface, and the thickness of the second region in the stacking direction is thinner than the thickness of the first region in the stacking direction.

[0007] In the multilayer ceramic capacitor according to the present invention, the second internal electrode comprises a first region disposed inside the laminate and a second region extended from the first region to the fifth and sixth surfaces, and the thickness of the second region in the stacking direction is thinner than the thickness of the first region in the stacking direction, so that moisture penetration from the outer periphery of the second internal electrode can be suppressed, and deterioration of insulation resistance due to moisture penetration can be suppressed.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress deterioration of insulation resistance due to moisture penetration.

[0009] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0010] 1. An external perspective view showing a multilayer ceramic capacitor according to the present invention. 2. A front view showing a multilayer ceramic capacitor according to the present invention. 3. A top view showing a multilayer ceramic capacitor according to the present invention. 4. A cross-sectional view taken along line IV-IV in FIG. 1. 5. A cross-sectional view taken along line VV in FIG. 1. 6. A cross-sectional view taken along line VI-VI in FIG. 4. 7. A cross-sectional view taken along line VII-VII in FIG. 4. 8. An enlarged view of part A in FIG. 5.

[0011] 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor 10 according to the present invention will be described. FIG. 1 is an external perspective view showing a multilayer ceramic capacitor according to the present invention. FIG. 2 is a front view showing a multilayer ceramic capacitor according to the present invention. FIG. 3 is a top view showing a multilayer ceramic capacitor according to the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is an enlarged view of part A in FIG. 5.

[0012] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30 .

[0013] The laminate 12 has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the stacking direction x.

[0014] The laminate 12 has a rectangular parallelepiped shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0015] The laminate 12 has a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 have a first internal electrode 16a and a second internal electrode 16b.

[0016] The laminate 12 also has an inner layer portion 18, a first main surface side outer layer portion 20a located on the first surface 12a side, and a second main surface side outer layer portion 20b located on the second surface 12b side.

[0017] The first main surface side outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer layer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0018] The second main surface side outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer layer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0019] The region sandwiched between the first main surface side outer layer portion 20 a and the second main surface side outer layer portion 20 b is the inner layer portion 18 .

[0020] The inner layer portion 18 has a first inner electrode 16a having one end exposed on the third surface 12c and the other end exposed on the fourth surface 12d, a second inner electrode 16b having one end exposed on the fifth surface 12e and the other end exposed on the sixth surface 12f, and an inner layer dielectric layer 14a.

[0021] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed primarily of BaTiO3, CaTiO3, SrTiO3, and CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material or different dielectric materials.

[0022] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for insulation breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited to this, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the inner dielectric layer 14a be made of a material with a high dielectric constant, such as BaTiO3.

[0023] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 5 to 1000, including the first and second outer layer portions 20 a and 20 b. The thickness of the dielectric layers 14 is preferably, for example, 0.3 μm to 6.0 μm.

[0024] (Internal Electrode) The internal electrode 16 includes a first internal electrode 16a and a second internal electrode 16b.

[0025] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a has a first opposing electrode portion 22a located inside the laminate 12, a first extraction electrode portion 24a connected to the first opposing electrode portion 22a and extending to the third surface 12c, and a second extraction electrode portion 24b extended to the fourth surface 12d.

[0026] The shape of the first opposing electrode portion 22a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 22a may be tapered in plan view, with a slope increasing in either direction.

[0027] The shapes of the first lead electrode portion 24a and the second lead electrode portion 24b of the first internal electrode 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either end.

[0028] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b has a second opposing electrode portion 22b facing the first internal electrode 16a, a third extraction electrode portion 24c connected to the second opposing electrode portion 22b and extending to the fifth surface 12e, and a fourth extraction electrode portion 24d extended to the sixth surface 12f.

[0029] The shape of the second opposing electrode portion 22b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 22b may be tapered in plan view, with a slope increasing in either direction.

[0030] The shapes of the third lead electrode portion 24c and the fourth lead electrode portion 24d of the second internal electrode 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either end.

[0031] The laminate 12 has side portions (W gaps) 26a, 26b of the laminate 12 that are located between one end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the fifth surface 12e, and between one end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the sixth surface 12f, and include the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0032] The laminate 12 also has ends (L gaps) 28a, 28b of the laminate 12 that are located between one end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the third surface 12c, and between one end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b and the fourth surface 12d, and include the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a.

[0033] The second opposing electrode portion 22b of the second internal electrode 16b is defined as a first region 40, and the third lead electrode portion 24c and the fourth lead electrode portion 24d of the second internal electrode 16b are defined as a second region 42. In other words, the first region 40 of the second internal electrode 16b is a region disposed inside the laminate 12. Furthermore, the second region 42 of the second internal electrode 16b is a region drawn from the first region 40 to the fifth surface 12e and the sixth surface 12f.

[0034] In the second internal electrode 16b, the thickness (t1) of the first region 40 in the stacking direction x is different from the thickness (t2) of the second region 42 in the stacking direction x. More specifically, as shown in FIG. 8 , the thickness (t2) of the second region 42 in the stacking direction x is thinner than the thickness (t1) of the first region 40 in the stacking direction x. This reduces the area of ​​the second region 42 exposed to the fifth surface 12e and the sixth surface 12f of the laminate 12, thereby reducing the number of moisture penetration paths and improving moisture resistance. In this case, only the regions of the second region 42 exposed to the fifth surface 12e and the sixth surface 12f may be thin, or the entire second region 42 may be thin.

[0035] When the thickness of the first region 40 in the stacking direction x is t1 and the thickness of the second region 42 exposed on the fifth surface 12e and the sixth surface 12f in the stacking direction x is t2, it is preferable that 0.2t1≦t2≦0.8t1 be satisfied. By setting t2 within the above range, it is possible to suppress a decrease in capacitance due to poor contact while also suppressing deterioration of insulation resistance due to moisture intrusion. If t2 is set smaller than 0.2t1, there is a possibility that the second internal electrode 16b will not be connected to the third external electrode 30c and the fourth external electrode 30d. On the other hand, if t2 is set larger than 0.8t1, there is a risk of moisture intrusion through a portion of the second internal electrode 16b.

[0036] Here, the thickness of the second region 42 in the stacking direction x can be measured, for example, by the following method. First, the side portions (W gaps) 26 a, 26 b of the laminate 12 are polished to ½ of the length in the second direction z. The polished cross section of the second region 42 is observed using a scanning electron microscope (SEM). The average thickness of the second region 42 of any five layers of the second region 42 that are consecutive in the stacking direction x is defined as the thickness of the second region 42 in the stacking direction x. Alternatively, the side portions (W gaps) 26 a, 26 b of the laminate 12 may be polished to ⅓ of the length in the second direction z. The thickness of the first region 40 in the stacking direction x can be measured, for example, by the following method. First, the laminate 12 is polished to ½ of the length in the second direction z. The polished cross section of the first region 40 is observed using a scanning electron microscope (SEM). The average of the thicknesses of any five first regions 40 consecutive in the stacking direction x is defined as the thickness of the first region 40 in the stacking direction x.

[0037] When the length in the first direction y of the second region 42 exposed on the fifth surface 12e and the sixth surface 12f of the laminate 12 is L1 and the length in the first direction y of the laminate 12 is L2, it is preferable that 0.02L2 < L1 < 0.20L2 be satisfied. By setting L1 within the above range, it is possible to suppress a decrease in capacitance due to poor contact while also suppressing deterioration of insulation resistance due to moisture intrusion. Furthermore, if L1 is set to 0.02L2 or less, there is a possibility that the second internal electrode 16b will not be connected to the third external electrode 30c and the fourth external electrode 30d. On the other hand, if L1 is set to 0.20L2 or more, a portion of the second internal electrode 16b will not be covered by the third external electrode 30c and the fourth external electrode 30d, which may allow moisture to infiltrate.

[0038] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0039] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, it is possible to alleviate the electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, leading to an improvement in high-temperature load reliability. In this case, even if Sn is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b, it is possible to achieve a sufficient effect.

[0040] The total number of the first internal electrodes 16 a and the second internal electrodes 16 b is preferably 2 to 1000. The thickness of the first internal electrodes 16 a and the second internal electrodes 16 b is not particularly limited, but is preferably 0.3 μm to 6.0 μm, for example.

[0041] In this embodiment, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0042] (External Electrodes) The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrode 16 a and the second internal electrode 16 b. The external electrodes 30 include a first external electrode 30 a, a second external electrode 30 b, a third external electrode 30 c, and a fourth external electrode 30 d.

[0043] The first external electrode 30a is disposed on the third surface 12c and connected to the first internal electrode 16a. The first external electrode 30a may also be disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0044] The second external electrode 30b is disposed on the fourth surface 12d and connected to the first internal electrode 16a. The second external electrode 30b may also be disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0045] The third external electrode 30c is disposed on the fifth surface 12e and connected to the second internal electrode 16b. The third external electrode 30c may also be disposed on a portion of the first surface 12a and a portion of the second surface 12b.

[0046] The fourth external electrode 30d is disposed on the sixth surface 12f and connected to the second internal electrode 16b. The fourth external electrode 30d may also be disposed on a portion of the first surface 12a and a portion of the second surface 12b.

[0047] Each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d preferably has a base electrode layer 32, a lower plating layer 34, and an upper plating layer 36.

[0048] In other words, the first external electrode 30a preferably has a first base electrode layer 32a, a first lower plating layer 34a, and a first upper plating layer 36a. The second external electrode 30b preferably has a second base electrode layer 32b, a second lower plating layer 34b, and a second upper plating layer 36b. The third external electrode 30c preferably has a third base electrode layer 32c, a third lower plating layer 34c, and a third upper plating layer 36c. The fourth external electrode 30d preferably has a fourth base electrode layer 32d, a fourth lower plating layer 34d, and a fourth upper plating layer 36d.

[0049] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0050] First, a description will be given of the case where the base electrode layer 32 is formed by a baking layer. The baking layer contains a metal component and a glass component. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. Furthermore, the baking layer may be a multi-layer structure.

[0051] The baked layer is formed by applying and baking a conductive paste containing a glass component and a metal component to the laminate 12. The baked layer may be formed by simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip, or by firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 to obtain the laminate 12 and then applying and baking the conductive paste. When simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 and the conductive paste applied to the laminated chip, it is preferable to add a dielectric component instead of the glass component, or to add both components to form the baked layer.

[0052] At the center of the stacking direction x connecting the first surface 12a and the second surface 12b of the first baking layer and the second baking layer located on the third surface 12c and the fourth surface 12d, the thickness in the first direction y connecting the third surface 12c and the fourth surface 12d of the first baking layer and the second baking layer (end surface center thickness) is preferably, for example, 5 μm or more and 55 μm or less.

[0053] Furthermore, when a base electrode layer (baked layer) is provided on a portion of the first surface 12a or a portion of the second surface 12b, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b of the first baked layer and the second baked layer at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first baked layer and the second baked layer located on the first surface 12a or the second surface 12b is preferably, for example, 1 μm or more and 30 μm or less.

[0054] Next, a case where the base electrode layer 32 is formed by a conductive resin layer will be described. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may also completely cover the baked layer, or may cover only a portion of the baked layer. Furthermore, the conductive resin layer may be a multi-layer structure.

[0055] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plating film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0056] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. It is also possible to use a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0057] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0058] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0059] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0060] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0061] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0062] The thickness of the thickest part of the conductive resin layer is preferably, for example, 5 μm or more and 50 μm or less.

[0063] Next, a case where the base electrode layer 32 is formed as a thin film layer will be described. The thin film layer may be formed on the surface of the laminate 12. When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as a sputtering method or a vapor deposition method. The thin film layer is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0064] (Underlayer plating layer) The underlayer plating layer 34 includes a first underlayer plating layer 34a arranged to cover the first underlayer electrode layer 32a, a second underlayer plating layer 34b arranged to cover the second underlayer electrode layer 32b, a third underlayer plating layer 34c arranged to cover the third underlayer electrode layer 32c, and a fourth underlayer plating layer 34d arranged to cover the fourth underlayer electrode layer 32d.

[0065] The lower plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0066] The lower plating layer 34 is preferably Ni plating. When the lower plating layer 34 is Ni plating, the base electrode layer 32 can be prevented from being eroded by solder when the multilayer ceramic capacitor 10 is mounted.

[0067] The thickness of the lower plating layer 34 is preferably, for example, 1 μm or more and 8 μm or less.

[0068] (Upper layer plating layer) The upper layer plating layer 36 includes a first upper layer plating layer 36a arranged to cover the first lower layer plating layer 34a, a second upper layer plating layer 36b arranged to cover the second lower layer plating layer 34b, a third upper layer plating layer 36c arranged to cover the third lower layer plating layer 34c, and a fourth upper layer plating layer 36d arranged to cover the fourth lower layer plating layer 34d.

[0069] The upper plating layer 36 contains at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0070] Furthermore, the upper plating layer 36 is preferably Sn plated. When the upper plating layer 36 is Sn plated, the wettability of the solder when mounting the multilayer ceramic capacitor 10 is improved, making it easier to mount.

[0071] The thickness of the upper plating layer 36 is preferably, for example, 1 μm or more and 8 μm or less.

[0072] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L. The dimension L is preferably 0.51 mm or more and 0.69 mm or less. The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimension W is preferably 0.21 mm or more and 0.39 mm or less. The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T. The dimension T is preferably 0.05 mm or more and 0.55 mm or less. Thus, even with a multilayer ceramic capacitor 10 that is smaller than conventional ones, the above-described configuration makes it possible to suppress a decrease in capacitance due to poor contact between the second internal electrode 16b and the third and fourth external electrodes 30c and 30d, while also suppressing deterioration of insulation resistance due to moisture intrusion.

[0073] 2. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor 10 according to the present invention will now be described.

[0074] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0075] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing, gravure printing, or inkjet printing. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. At this time, the thickness of the second region 42 (the third lead electrode portion 24c and the fourth lead electrode portion 24d) of the second internal electrode 16b is formed to be thinner than the thickness of the first region 40 (the second opposing electrode portion 22b) of the second internal electrode 16b. The sheet on which the first internal electrode is printed and the sheet on which the second internal electrode is printed are then laminated together to form the portion that becomes the inner layer portion 18.

[0076] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first main surface side outer layer portion 20a on the first surface 12a side. Thereafter, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second main surface side outer layer portion 20b on the second surface 12b side. In this way, a laminated sheet is produced.

[0077] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0078] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0079] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0080] A first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the third surface 12c and the fourth surface 12d of the fired laminate 12. Furthermore, a third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the fifth surface 12e and the sixth surface 12f of the fired laminate 12.

[0081] When a baked layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form the base electrode layer 32.

[0082] More specifically, first, the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d are formed on the fifth surface 12e and the sixth surface 12f of the laminate 12 obtained by firing.

[0083] Here, various methods can be used to form the third and fourth base electrode layers 32c and 32d. For example, a method of applying a conductive paste by extruding it through a slit can be used. In this method, by increasing the amount of conductive paste extruded, the third and fourth base electrode layers 32c and 32d can be formed not only on the fifth surface 12e and the sixth surface 12f, but also on a portion of the first surface 12a and a portion of the second surface 12b.

[0084] Alternatively, the electrodes may be formed by a roller transfer method. In the case of the roller transfer method, when the third and fourth base electrode layers 32c and 32d are formed not only on the fifth surface 12e and the sixth surface 12f but also on a part of the first surface 12a and a part of the second surface 12b, the third and fourth base electrode layers 32c and 32d can be formed on a part of the first surface 12a and a part of the second surface 12b by increasing the pressing pressure during the roller transfer.

[0085] Next, the first underlying electrode layer 32a of the first external electrode 30a and the second underlying electrode layer 32b of the second external electrode 30b are formed on the third surface 12c and the fourth surface 12d of the laminate 12 obtained by firing.

[0086] Here, various methods can be used to form the first and second base electrode layers 32 a and 32 b. For example, by using a method such as dipping, the first and second base electrode layers 32 a and 32 b can be formed so as to extend not only to the third surface 12 c and the fourth surface 12 d but also to parts of the first surface 12 a, the second surface 12 b, the fifth surface 12 e, and the sixth surface 12 f.

[0087] In this embodiment, the third base electrode layer 32c and the fourth base electrode layer 32d are fired, and then the first base electrode layer 32a and the second base electrode layer 32b are fired. However, the first base electrode layer 32a and the second base electrode layer 32b, and the third base electrode layer 32c and the fourth base electrode layer 32d may be fired simultaneously.

[0088] When forming a conductive resin layer as the base electrode layer 32, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed alone directly on the laminate without forming a baked layer.

[0089] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal onto the baking layer or the laminate, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0090] The conductive resin paste can be applied by, for example, a method of applying the conductive paste by extruding it through a slit or a roller transfer method, similar to the method of forming the base electrode layer 32 as a baked layer.

[0091] Thereafter, a lower plating layer 34 is formed on the base electrode layer 32 and the surface of the laminate 12, and an upper plating layer 36 is formed to cover the lower plating layer 34. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer 34. Then, a Sn plating layer is formed on the surface of the lower plating layer 34 as the upper plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0092] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 can be manufactured.

[0093] 3. Experimental Examples Multilayer ceramic capacitors were fabricated according to the above manufacturing method and evaluated by a moisture resistance test. As examples, multilayer ceramic capacitors with the following specifications were prepared. As shown in Table 1, the prepared samples of Examples 1 to 7 were varied in thickness in the stacking direction x of the first region 40 of the second internal electrode 16b and in thickness in the stacking direction x of the second region 42. As a comparative example, a multilayer ceramic capacitor was prepared in which the thickness in the stacking direction x of the first region of the second internal electrode was the same as the thickness in the stacking direction x of the second region.

[0094] (1) Multilayer ceramic capacitors used in examples and comparative examples (a) Dimensions of multilayer ceramic capacitors (i) Dimension in stacking direction x (T): 0.30±0.09 mm (ii) Dimension in first direction y (L): 0.60±0.09 mm (iii) Dimension in second direction z (W): 0.30±0.09 mm (b) Main component of dielectric layer: BaTiO3 (c) Main component of internal electrode: Ni (d) Capacitance: 1 μF (e) Structure of external electrode (i) Base electrode layer: Baked layer containing conductive metal (Cu) and glass component (ii) Lower plating layer: Ni plating layer (iii) Upper plating layer: Sn plating layer

[0095] (2) Test Method and Measurement Method First, each multilayer ceramic capacitor was mounted on a wiring board using solder, and the insulation resistance value was measured. Then, each multilayer ceramic capacitor mounted on the wiring board was placed in a high-temperature, high-humidity chamber and maintained for 1,000 hours in an environment of 85°C and 85% RH with a 4 V DC current applied between the first and second external electrodes. The insulation resistance value of each multilayer ceramic capacitor after the humidity test was measured. A capacitor whose insulation resistance value after the humidity test was one order of magnitude lower than the insulation resistance value before the humidity test was considered NG, and the NG rate was calculated by (number of NG capacitors / 77 capacitors) x 100. The capacitance was measured using an LCR meter E4890A manufactured by Agilent, and the capacitance was calculated. The measurement was performed under conditions of 1 kHz and 0.5 Vrms.

[0096] Table 1 shows the results of the humidity resistance test of the multilayer ceramic capacitors produced in the examples and comparative examples.

[0097]

[0098] As shown in Table 1, in each of the samples of Examples 1 to 7, it was confirmed that by making the thickness (t2) of the second region 42 in the stacking direction x smaller than the thickness (t1) of the first region 40 in the stacking direction x, the moisture penetration path is narrowed and a decrease in insulation resistance due to moisture penetration is prevented. In particular, in each of the samples of Examples 2 to 7, it was confirmed that by making the thickness (t2) of the second region 42 in the stacking direction x with respect to the thickness (t1) of the first region 40 in the stacking direction x such that t2≦0.8t1, it was confirmed that a decrease in insulation resistance due to moisture penetration between the second internal electrode 16b and the third external electrode 30c and the fourth external electrode 30d is prevented. Furthermore, in each of the samples of Examples 1 to 5, it was confirmed that by making 0.2t1≦t2, a decrease in capacitance due to poor contact between the second internal electrode 16b and the third external electrode 30c and the fourth external electrode 30d is prevented.

[0099] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0100] In the present embodiment, the second internal electrode 16b includes a first region 40 disposed in an inner layer portion of the second internal electrode 16b, and a second region 42 extended from the first region 40 of the second internal electrode 16b to the fifth surface 12e and the sixth surface 12f of the laminate 12, and is configured so that the thickness in the stacking direction x of the second region 42 is thinner than the thickness in the stacking direction x of the first region 40. However, this is not limited thereto, and a similar effect can be obtained by configuring so that the thickness in the stacking direction x of the region extended from the region of the first internal electrode 16a disposed in an inner layer portion of the first internal electrode 16a to the third surface 12c and the fourth surface 12d of the laminate 12 is thinner than the thickness in the stacking direction x of the region.

[0101] The present invention relates to a multilayer ceramic capacitor, and can be used as a multilayer ceramic capacitor that can suppress deterioration of insulation resistance due to moisture penetration.

[0102] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 14a Inner dielectric layer 14b Outer dielectric layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Internal layer portion 20a First main surface side outer layer portion 20b Second main surface side outer layer portion 22a First opposing electrode portion 22b Second opposing electrode portion 24a First lead electrode portion 24b Second lead electrode portion 24c Third lead electrode portion 24d Fourth lead electrode portion 26a, 26b Side portion of laminate (W gap) 28a, 28b End portion of laminate (L gap) 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 Base plating layer 34a First base plating layer 34b Second base plating layer 34c Third base plating layer 34d Fourth base plating layer 36 Top plating layer 36a First top plating layer 36b Second top plating layer 36c Third top plating layer 36d Fourth top plating layer 40 First region 42 Second region x Stacking direction y First direction z Second direction L Lengthwise dimension of multilayer ceramic capacitor W Widthwise dimension of multilayer ceramic capacitor T Stacking direction dimension t1 of multilayer ceramic capacitor Thickness of the first region in the stacking direction t2 Thickness of the second region in the stacking direction L1 Length of the second region in the first direction L2 Length of the laminate in the first direction

Claims

1. A laminate having a first surface and a second surface opposed to each other in a stacking direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction, a first external electrode arranged on the third surface of the laminate, a second external electrode arranged on the fourth surface of the laminate, a third external electrode arranged on the fifth surface of the laminate, and a fourth external electrode arranged on the sixth surface of the laminate, wherein the laminate comprises an inner layer portion and two outer layer portions arranged to sandwich the inner layer portion in the stacking direction, the inner layer portion comprising: an inner layer dielectric layer; a first internal electrode having one end exposed in the first direction to the third surface and the fourth surface; and a second internal electrode having one end exposed in the second direction to the fifth surface and the sixth surface, wherein the second internal electrode is a first region disposed inside the laminate; and a second region extending from the first region to the fifth surface and the sixth surface, wherein a thickness of the second region in the lamination direction is smaller than a thickness of the first region in the lamination direction.

2. The multilayer ceramic capacitor according to claim 1, wherein, when the thickness of said first region in said lamination direction is t1 and the thickness of said second region in said lamination direction is t2, 0.2t1≦t2≦0.8t1.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, when a dimension of the multilayer ceramic capacitor in a direction connecting the third surface and the fourth surface is L and a dimension of the multilayer ceramic capacitor in a direction connecting the fifth surface and the sixth surface is W, L is 0.51 mm or more and 0.69 mm or less, and W is 0.21 mm or more and 0.39 mm or less.

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