Semiconductor chip and method for manufacturing semiconductor chip

Abstract

A semiconductor chip (10) comprises: an electrode pad (12) provided on a main surface of a base material (11); a passivation film (13) provided on the main surface of the base material (11) and provided with a first opening portion (13a) for partially exposing the electrode pad (12); and a columnar electrode (20) having a pedestal portion (21) and a column portion (22). The pedestal portion (21) is provided on a portion of the electrode pad (12) exposed by the first opening portion (13a), an inner circumferential surface of the first opening portion (13a), and a peripheral portion of the first opening portion (13a) on an upper surface of the passivation film (13). Moreover, the column portion (22) is provided in an upper surface of the pedestal portion (21) and an external shape of the column portion (22) is formed so as to be smaller than an external shape of the pedestal portion (21) in a plan view of the main surface. The pedestal portion (21) and the column portion (22) are formed of the same material.

Description

Semiconductor chip and method for manufacturing the same

[0001] The present disclosure relates to semiconductor chips and methods for manufacturing semiconductor chips.

[0002] Flip-chip mounting is a conventional method for mounting a semiconductor chip on a wiring substrate, in which electrode pads on the semiconductor chip are joined to pads (FC pads: Flip Chip pads) on the wiring substrate using columnar electrodes, solder, or the like.

[0003] Recently, with the increasing performance and integration of semiconductor chips, the arrangement pitch of electrode pads is becoming narrower (fine pitch). As the electrode pad pitch becomes narrower, it becomes necessary to form thinner pillar electrodes on semiconductor chips. Furthermore, as the pillar electrodes become thinner, the bonding area between the pillar electrodes and the electrode pads decreases. As a result, during the manufacturing process of semiconductor devices, defects may occur due to peeling of the pillar electrodes from the electrode pads, tilting of the pillar electrodes, etc., when mounting the semiconductor chip on the wiring substrate or after mounting the semiconductor chip on the wiring substrate.

[0004] Therefore, Patent Document 1 discloses an electronic element in which the adhesion of electrode pads and bumps is improved. In the electronic element described in Patent Document 1, electrode pads and a protective film are arranged on a semiconductor chip, and openings are provided in the protective film to expose the electrode pads. In addition, one metal layer and another metal layer are stacked on the protective film, and columnar electrodes are formed on the other metal layer. In addition, bumps are formed on the columnar electrodes.

[0005] Japanese Patent Application Laid-Open No. 2004-235420

[0006] However, when the arrangement pitch of the electrode pads becomes narrower and it becomes necessary to form the columnar electrodes even thinner, the electronic element described in Patent Document 1 has the problem that the diameter of the columnar electrodes cannot be formed smaller than the opening in the protective film for exposing the electrode pads.

[0007] Furthermore, when forming a columnar electrode by electrolytic plating using a conductive film, which is another metal layer, as a seed layer for electrolytic plating, as in the manufacturing method of an electronic device described in Patent Document 1, the conductive film must be removed by etching after the columnar electrode is formed. In this case, when the conductive film is etched, the corrosion effect of the etching causes the conductive film to narrow into an inverted cone shape, resulting in a smaller base area than the columnar electrode. This reduces the area of ​​contact between the base of the columnar electrode and the conductive film. As a result, the bonding strength between the columnar electrode and the conductive film may be reduced.

[0008] This problem becomes particularly noticeable in highly integrated semiconductor chips where the pitch of the electrode pads is 45 μm to 85 μm.

[0009] Therefore, as the performance and integration of semiconductor chips increases and electrode pads are arranged at finer pitches, it becomes necessary to form thinner pillar electrodes. In this case, it is necessary to prevent a decrease in adhesion strength due to a reduction in the bonding area between the pillar electrodes and the conductive film, and to suppress problems such as defects.

[0010] The present disclosure has been made in view of the above-mentioned problems, and aims to provide a semiconductor chip in which columnar electrodes have good adhesion strength, and a method for manufacturing the semiconductor chip.

[0011] A semiconductor chip according to a first aspect of the present disclosure comprises: an electrode pad provided on a main surface of a substrate; a passivation film provided on the main surface of the substrate and having a first opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the first opening, an inner peripheral surface of the first opening, and a peripheral portion of the first opening on the upper surface of the passivation film; and a pillar electrode having: a pillar portion provided within the upper surface of the pedestal portion, the outer shape of the pillar portion being smaller than the outer shape of the pedestal portion when the main surface is viewed in a plane; and the pedestal portion and the pillar portion are formed from the same material.

[0012] A semiconductor chip according to a second aspect of the present disclosure comprises: an electrode pad provided on a main surface of a substrate; a passivation film provided on the main surface of the substrate, the passivation film having a first opening for partially exposing the electrode pad; an insulating film provided on the passivation film and the electrode pad, the passivation film having a second opening for partially exposing the electrode pad; a pedestal provided on a portion of the electrode pad exposed by the second opening, an inner peripheral surface of the second opening in the insulating film, and a peripheral portion of the second opening on an upper surface of the insulating film; and a pillar electrode having a pillar provided within the upper surface of the pedestal, the outer shape of the pillar being smaller than the outer shape of the pedestal when the main surface is viewed in a plane; and the pedestal and the pillar are formed from the same material.

[0013] A method for manufacturing a semiconductor chip according to a third aspect of the present disclosure includes the steps of: preparing a substrate having an electrode pad on a main surface thereof, and a passivation film on the main surface thereof, the passivation film having a first opening formed therein for partially exposing the electrode pad; forming a seed layer on the passivation film and on the portion of the electrode pad exposed by the first opening; forming a pedestal portion on the seed layer by plating; forming a pillar portion within an upper surface of the pedestal portion by plating; and removing by etching the portion of the seed layer not covered by the pedestal portion; wherein the outer shape of the pillar portion is formed to be smaller than the outer shape of the pedestal portion when the main surface is viewed in a plane; and the pedestal portion and the pillar portion are formed using the same material.

[0014] A method for manufacturing a semiconductor chip according to a fourth aspect of the present disclosure includes the steps of: preparing a substrate having electrode pads on a main surface thereof and a passivation film on the main surface, the passivation film having a first opening for partially exposing the electrode pads; forming an insulating film on the passivation film and the electrode pads, the insulating film having a second opening for partially exposing the electrode pads; forming a seed layer on the insulating film and the portion of the electrode pad exposed by the second opening; forming a pedestal on the seed layer by plating; forming a pillar on the pedestal by plating; and removing by etching the portion of the seed layer not covered by the pedestal; wherein the outer shape of the pillar is smaller than the outer shape of the pedestal when the main surface is viewed in plan; and the pedestal and the pillar are formed using the same material.

[0015] According to the present disclosure, it is possible to provide a semiconductor chip in which columnar electrodes have good adhesion strength, and a method for manufacturing the semiconductor chip.

[0016] 7 is a top view schematically showing a portion of a semiconductor chip according to embodiment 1; FIG. 8 is a cross-sectional view taken along the II-II cutting line shown in FIG. 1; FIG. 9 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 10 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 11 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 12 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 13 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 14 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 15 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 16 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 17 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 18 is a view schematically showing a method for manufacturing a semiconductor chip according to embodiment 1; FIG. 1 is a diagram schematically showing a method for manufacturing a semiconductor chip according to a second embodiment. FIG. 2 is a diagram schematically showing a method for manufacturing a semiconductor chip according to a second embodiment. FIG. 3 is a diagram schematically showing a method for manufacturing a semiconductor chip according to a second embodiment. FIG. 4 is a diagram explaining a structure of a semiconductor chip according to a related art. FIG. 5 is an enlarged view of a bonding portion between an electrode pad and a pillar provided in a semiconductor chip according to a related art.

[0017] Hereinafter, a semiconductor chip and a method for manufacturing the semiconductor chip according to this embodiment will be described with reference to the drawings.

[0018] 1 and 2 show a semiconductor chip 10 according to a first embodiment. As shown in Fig. 1 and 2, the semiconductor chip 10 includes a substrate 11, a plurality of electrode pads 12, and a plurality of passivation films 13. The semiconductor chip 10 also includes a seed layer 14, a pillar-shaped electrode 20, and a solder portion 17, which are provided on each of the electrode pads 12. Furthermore, each of the pillar-shaped electrodes 20 includes a pedestal portion 21 and a pillar portion 22 provided on the pedestal portion 21.

[0019] Circuits and the like (not shown) are formed inside the substrate 11. Electrode pads 12 are provided on the substrate 11 to connect the circuits and the like to external devices.

[0020] The electrode pads 12 are provided on the main surface (top surface shown in FIG. 2) of the substrate 11. The electrode pads 12 are arranged at a pitch of 45 μm to 85 μm. For example, the electrode pads 12 are arranged at a pitch of 50 μm.

[0021] The passivation film 13 is provided on the main surface of the substrate 11. The passivation film 13 is also provided with a first opening 13a for partially exposing the electrode pad 12. The first opening 13a has, for example, a square planar shape. As an example, the first opening 13a has a square shape with each side measuring 35 μm.

[0022] The seed layer 14 is formed of, for example, Ti or W, and is used when forming the columnar electrodes 20 by electroplating, as described below. The seed layer 14 has a thickness of 0.5 μm to 1 μm. The seed layer 14 may have a single-layer structure or a two-layer structure having a layer of Cu on a layer of Ti or W. As shown in FIG. 2 , the seed layer 14 is formed to be slightly larger than the first opening 13 a. Specifically, as shown in FIG. 2 , the seed layer 14 is provided so as to cover the portion of the electrode pad 12 exposed by the first opening 13 a in the passivation film 13, the inner surface of the first opening 13 a, and the periphery of the first opening 13 a on the upper surface of the passivation film 13.

[0023] The columnar electrode 20 includes a pedestal portion 21 and a column portion 22 provided on the pedestal portion 21. The pedestal portion 21 is provided on the seed layer 14 and is provided on the portion of the electrode pad 12 exposed by the first opening 13a, the inner circumferential surface of the first opening 13a, and the periphery of the first opening 13a on the upper surface of the passivation film 13. The pedestal portion 21 is formed from a conductive material, for example, copper. As will be described in detail later, the seed layer 14 is formed by etching using the pedestal portion 21 as a mask. Therefore, the outer shape of the pedestal portion 21 is the same as the outer shape of the seed layer 14. In other words, as shown in FIGS. 1 and 2, when the main surface of the substrate 11 is viewed in plan, the outline of the pedestal portion 21 and the outline of the seed layer 14 have the same shape. As an example, the pedestal portion 21 is formed in a square shape with sides of 45 μm in plan view, as shown in FIG. 1. Since the outer shape of the seed layer 14 is the same as that of the pedestal portion 21, the seed layer 14 is formed into a square with a side length of 45 μm in plan view. In addition, the thickness of the pedestal portion 21 is preferably 5 μm or less to accommodate fine pitch. In this specification, the term "same shape" includes errors that occur during manufacturing.

[0024] The pillar portion 22 has a cylindrical shape. The pillar portion 22 is formed from the same material as the base portion 21, for example, copper. While FIG. 2 shows a boundary between the base portion 21 and the pillar portion 22 for illustrative purposes, the base portion 21 and the pillar portion 22 are formed from the same material and are formed by continuous plating, and therefore, in reality, there is no boundary. Therefore, the base portion 21 and the pillar portion 22 have good bonding strength. Furthermore, when the main surface of the substrate 11 is viewed in plan, the outer shape of the pillar portion 22 is formed smaller than the outer shape of the base portion 21, and the pillar portion 22 is positioned so as to be located within the upper surface of the base portion 21. For example, the diameter of the pillar portion 22 is smaller than the width and length of the base portion 21 when the main surface of the substrate 11 is viewed in plan, and the pillar portion 22 is located within the region of the upper surface of the base portion 21. The diameter of the pillar portion 22 is 5 to 30 μm. The height of the pillar portion 22 is 10 to 30 μm, for example 25 μm. It is preferable that one side of the square in plan view of the pedestal portion 21 is 5 μm to 20 μm larger than the diameter of the pillar portion 22. For example, when the diameter of the pillar portion 22 is 25 μm, it is preferable that the pedestal portion 21 is formed as a square with one side of 45 μm in plan view.

[0025] As shown in FIG. 1 , the pillar portion 22 is disposed directly above the first opening 13a. In other words, the pillar portion 22 is provided so as to be located within the region of the electrode pad 12 exposed by the first opening 13a. The diameter of the pillar portion 22 is smaller than the length of one side of the square first opening 13a in a plan view. The side of the first opening 13a is preferably 5 to 20 μm larger than the diameter of the pillar portion 22. As an example, when the diameter of the pillar portion 22 is 25 μm, the side of the first opening 13a is preferably 35 μm.

[0026] The solder portion 17 is provided on the column portion 22. The solder portion 17 is made of, for example, SnAg. The height of the solder portion 17 is, for example, 10 μm.

[0027] (Method for Manufacturing Semiconductor Chip) Hereinafter, a method for manufacturing the semiconductor chip 10 will be described with reference to the drawings.

[0028] As shown in FIG. 3A, a substrate 11 is prepared with electrode pads 12 and a passivation film 13 formed on its main surface. Circuits and the like (not shown) are formed within the substrate 11. Furthermore, the substrate 11 is not the substrate 11 after being singulated into multiple semiconductor chips as described in FIGS. 1 and 2, but the substrate 11 before being singulated. As a result, multiple semiconductor chips are connected. Therefore, FIGS. 3A to 3C, 4A, 4B, 5A, 5B, 6A, and 6B show an area where one semiconductor chip is formed.

[0029] As shown in FIG. 3B , a seed layer 51 is formed on the main surface side of the substrate 11. The seed layer 51 is formed using a sputtering method. The seed layer 51 is, for example, a thin metal film having a thickness of 0.5 μm to 1 μm. Such a seed layer 51 is formed on the entire surface of the substrate 11. The seed layer 51 is formed using, for example, Ti or W. The seed layer 51 may be composed of a single layer, or may have a two-layer structure including a layer made of Cu on a layer made of Ti or W.

[0030] A first resist layer 52 for forming the pedestal portion 21 is formed on the seed layer 51. A photosensitive material is used for forming the first resist layer 52. The first resist layer 52 is formed by applying a liquid resist material using a coating method such as spin coating.

[0031] Next, the first resist layer 52 is patterned to form resist openings 52a, as shown in FIG. 3C. Specifically, a photomask is used to expose the first resist layer 52 with an exposure device. The first resist layer 52 is then subjected to a development process to harden the first resist layer 52. This results in the first resist layer 52 being patterned. Here, the shape of the resist openings 52a corresponds to the shape of the pedestal portion 21.

[0032] 4A, Cu plating is performed to form the base portion 21. The Cu plating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed so that a Cu layer having a predetermined thickness is formed.

[0033] Next, as shown in FIG. 4B, the first resist layer 52 is dissolved using a stripping solution, and the first resist layer 52 is removed.

[0034] A second resist layer 53 for plating is formed to form the columnar portion 22. A photosensitive material is used as the second resist layer 53. The second resist layer 53 is formed by applying a liquid resist material using a coating method such as spin coating. Alternatively, the second resist layer 53 may be formed by laminating a dry film using a lamination method instead of using a liquid resist material.

[0035] The second resist layer 53 is patterned to form resist openings 53a as shown in FIG. 5A. Specifically, a photomask is used to expose the second resist layer 53 with an exposure device, followed by a development process. The second resist layer 53 is then hardened after the development process. This completes the patterning process. The shape of the resist openings 53a corresponds to the shape of the columnar portions 22. The position of the resist openings 53a is determined so that the columnar portions 22 are located within the first openings 13a of the passivation film 13 when the main surface of the substrate 11 is viewed in plan as shown in FIG. 1.

[0036] 5B, Cu plating is performed to form the columnar portion 22. The Cu plating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed so that a Cu layer of a predetermined thickness is formed.

[0037] 6A, plating is performed to form a solder layer 54. As with Cu plating, electroplating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed so that a solder alloy such as SnAg forms a layer of a predetermined thickness.

[0038] The second resist layer 53 is dissolved using a stripping solution, and the second resist layer 53 is removed.

[0039] Next, the portion of the seed layer 51 that is not covered by the pedestal portion 21 is removed by etching. As a result, as shown in FIG. 6B , only the portion of the seed layer 51 that is located under the pedestal portion 21 remains, and the seed layer 14 is formed. When the seed layer 51 is etched, the pedestal portion 21 functions as an etching mask, so that when the main surface is viewed in plan, the outer shape of the seed layer 14 is formed to be the same as the outer shape of the pedestal portion 21. Here, there is a possibility that part of the outer periphery of the seed layer 14 will be removed during etching. Therefore, the term "same shape" in this specification includes such manufacturing-related errors.

[0040] Subsequently, the solder layer 54 is melted by a reflow process to shape and fix the solder layer 54, thereby forming the solder portion 17. Next, the semiconductor chips formed on the substrate 11 are separated into individual pieces by dicing, thereby manufacturing the semiconductor chips 10.

[0041] According to this embodiment, a semiconductor chip in which the columnar electrodes have good adhesion strength and a method for manufacturing the semiconductor chip are provided.

[0042] First, for comparison, a semiconductor chip 90 according to the related art is shown in FIG. 13A . In this semiconductor chip 90, pillars 98 are provided directly on electrode pads 92 via a seed layer 94. In this semiconductor chip 90, as the performance and integration of the semiconductor chip 90 increase, the pillars 98 must be made thinner. This reduces the bonding area between the pillars 98 and the electrode pads 92, resulting in a decrease in the adhesion strength of the pillars 98. If the adhesion strength of the pillars 98 decreases, defects such as peeling, tilting, or collapse of the pillars 98 may occur during the manufacturing or after mounting of the semiconductor chip 90. Furthermore, as shown in FIG. 13B , if the outer periphery 94 a of the seed layer 94 located between the pillars 98 and the electrode pads 92 is thinned into an inverted cone shape by etching, the bonding area at the bottom of the pillars 98 may decrease, further reducing the strength of the pillars 98.

[0043] In contrast, in the semiconductor chip 10 of embodiment 1, the pedestal 21 and the pillar 22 are formed from the same material and by continuous plating, so there is no boundary between them. Therefore, the pedestal 21 and the pillar 22 have good bonding strength. Furthermore, even if the seed layer 14 is thinned by etching, this does not affect the bond between the pedestal 21 and the pillar 22. Furthermore, compared to related art in which the pedestal and the pillar are formed from different materials, the manufacturing process is simplified, and material costs and manufacturing costs can be reduced in manufacturing the semiconductor chip 10. Additionally, in the semiconductor chip 10 of this embodiment, the pedestal 21 is formed wider than the pillar 22. Therefore, the bonding area between the seed layer 14, which is made of different materials, and the pedestal 21 can be made wider compared to related art in which pillars 98, i.e., pillars, are directly provided on the electrode pad 92 via the seed layer 94. As a result, the semiconductor chip 10 can enhance the bonding strength between the pillar electrodes 20 and the electrode pads 12.

[0044] (Embodiment 2) A semiconductor chip 30 according to embodiment 2 and a method for manufacturing the same will be described with reference to the drawings. The semiconductor chip 30 of this embodiment differs from the semiconductor chip 10 according to embodiment 1 in that it has an insulating film 31 on the passivation film 13. Portions common to embodiment 1 are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0045] 7 and 8 show a semiconductor chip 30 according to the second embodiment. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 7.

[0046] 7 and 8 , the semiconductor chip 30 includes a substrate 11, a plurality of electrode pads 12, a plurality of passivation films 13, and a plurality of insulating films 31. The semiconductor chip 30 also includes a seed layer 14, a pillar-shaped electrode 20, and a solder portion 17, which are provided on each of the electrode pads 12. Furthermore, each of the pillar-shaped electrodes 20 includes a pedestal portion 21 and a pillar portion 22 provided on the pedestal portion 21.

[0047] The electrode pads 12 are provided on the main surface (the upper surface shown in FIG. 8) of the substrate 11, as in the first embodiment. The electrode pads 12 are arranged at a pitch of 45 μm to 85 μm, for example, at a pitch of 50 μm.

[0048] The passivation film 13 is provided on the main surface of the substrate 11. The passivation film 13 is also provided with a first opening 13a for partially exposing the electrode pad 12. The first opening 13a has, for example, a square planar shape. As an example, the first opening 13a has a square shape with each side measuring 35 μm in plan view.

[0049] The insulating film 31 is made of an insulating material, such as polyimide. A second opening 31a is formed in the insulating film 31 to expose the electrode pad 12. The second opening 31a has a circular planar shape when viewed from the main surface of the substrate 11. The inner peripheral surface of the second opening 31a is inclined as shown in FIG. 8, and the inner diameter of the second opening 31a gradually decreases from the top surface to the bottom surface of the insulating film 31. The second opening 31a is formed to expose the electrode pad 12 in a circular shape with a diameter of, for example, 15 μm. The second opening 31a shown in FIG. 7 indicates the shape of the boundary between the insulating film 31 and the electrode pad 12, and indicates the portion of the electrode pad 12 exposed from the insulating film 31.

[0050] The seed layer 14 is formed of, for example, Ti or W, and is used when forming the columnar electrodes 20 by electrolytic plating, as described below. The seed layer 14 has a thickness of 0.5 μm to 1 μm. The seed layer 14 may have a single-layer structure or a two-layer structure. As shown in FIG. 8 , the seed layer 14 is formed to be larger than the second opening 31 a. Specifically, as shown in FIG. 8 , the seed layer 14 is provided so as to cover the portion of the electrode pad 12 exposed by the second opening 31 a in the insulating film 31, the inner surface of the second opening 31 a, and the periphery of the second opening 31 a on the upper surface of the insulating film 31.

[0051] The columnar electrode 20 includes a pedestal portion 21 and a column portion 22 provided on the pedestal portion 21. The pedestal portion 21 is provided on the seed layer 14 and is provided on the portion of the electrode pad 12 exposed by the second opening 31a, the inner circumferential surface of the second opening 31a in the insulating film 31, and the peripheral portion of the second opening 31a on the upper surface of the insulating film 31a. In this embodiment, the outer shape of the pedestal portion 21 is the same as the outer shape of the seed layer 14. That is, as shown in FIGS. 7 and 8, when the main surface of the substrate 11 is viewed in plan, the outline of the pedestal portion 21 and the outline of the seed layer 14 have the same shape. As an example, as shown in FIG. 7, the pedestal portion 21 is formed as a square with sides of 45 μm. Since the outer shape of the seed layer 14 is the same as the outer shape of the pedestal portion 21, it is also formed as a square with sides of 45 μm. Furthermore, the thickness of the pedestal portion 21 is preferably 5 μm or less.

[0052] The pillar portion 22 has a cylindrical shape. The pillar portion 22 is formed from the same material as the base portion 21, for example, copper. The base portion 21 and the pillar portion 22 are formed from the same material and are formed by continuous plating, so there is no actual boundary as shown in FIG. 8 . The pillar portion 22 is provided within the upper surface of the base portion 21. When the main surface of the substrate 11 is viewed from above, the outer shape of the pillar portion 22 is formed smaller than the outer shape of the base portion 21, and the pillar portion 22 is arranged so as to be located within the upper surface of the base portion 21. For example, the diameter of the pillar portion 22 is smaller than the width and length of the base portion 21 when viewed from above from the main surface side of the substrate 11, and the pillar portion 22 is arranged within the upper surface of the base portion 21. The diameter of the pillar portion 22 is 5 to 30 μm, and the height of the pillar portion 22 is 25 μm. It is preferable that one side of the square base 21 in plan view is larger by 5 μm to 20 μm than the diameter of the column 22. As an example, the side of the base 21 is 45 μm, and the diameter of the column 22 is 25 μm.

[0053] 7, the pillar portion 22 is disposed directly above the first opening 13a of the passivation film 13, as in the first embodiment. The diameter of the pillar portion 22 is smaller than the length of one side of the square first opening 13a in a plan view. The side of the first opening 13a is preferably 5 to 20 μm larger than the diameter of the pillar portion 22. As an example, when the diameter of the pillar portion 22 is 25 μm, the side of the first opening 13a is preferably 35 μm.

[0054] The solder portion 17 is provided on the column portion 22. The solder portion 17 is made of, for example, SnAg. The height of the solder portion 17 is, for example, 10 μm.

[0055] (Method for Manufacturing Semiconductor Chip) Hereinafter, a method for manufacturing the semiconductor chip 30 will be described with reference to the drawings.

[0056] First, a substrate 11 is prepared, on the main surface of which the electrode pads 12 and the passivation film 13 are formed. In this embodiment, the substrate 11 is also in a state before being divided into individual pieces.

[0057] An insulating material, for example, photosensitive polyimide, is applied to the electrode pads 12 and the passivation 13 on the substrate 11. Next, the applied insulating material is exposed to light using a photomask in an exposure device, and the insulating material is then subjected to a development process, thereby forming an insulating film 31 in which second openings 31a are formed above the electrode pads 12, as shown in FIG.

[0058] 9B, a seed layer 51 is formed on the main surface side of the base material 11. The seed layer 51 is formed by using a sputtering method.

[0059] A first resist layer 52 for forming the pedestal portion 21 is formed on the seed layer 51. The first resist layer 52 is formed using a photosensitive material. Next, the first resist layer 52 is patterned to form a resist opening 52a, as shown in FIG. 9C . Here, the shape of the resist opening 52a corresponds to the shape of the pedestal portion 21.

[0060] 10A, Cu plating is performed to form the base portion 21. The Cu plating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed so that a Cu layer having a predetermined thickness is formed.

[0061] Next, as shown in FIG. 10B, the first resist layer 52 is dissolved using a stripping solution, and the first resist layer 52 is removed.

[0062] A second resist layer 53 for plating to form the columnar portion 22 is formed, and then the second resist layer 53 is patterned. As a result, a resist opening 53a is formed, as shown in FIG. 11A . The shape of the resist opening 53a corresponds to the shape of the columnar portion 22. The position of the resist opening 53a is determined so that the columnar portion 22 is located within the first opening 13a of the passivation film 13 when viewed in plan from the main surface side of the substrate 11.

[0063] 11B, Cu plating is performed to form the columnar portion 22. The Cu plating is performed using an electrolytic plating method. Specifically, power is supplied from the seed layer 51, and plating is performed so that a Cu layer of a predetermined thickness is formed.

[0064] 11B, plating is performed to form a solder layer 54. As with Cu plating, electrolytic plating is used. Specifically, power is supplied from the seed layer 51, and plating is performed so that a solder alloy such as SnAg has a predetermined thickness.

[0065] As shown in FIG. 12A, the second resist layer 53 is dissolved using a stripping solution, and the second resist layer 53 is removed.

[0066] 12B , the portion of the seed layer 51 that is not covered by the pedestal portion 21 is removed by etching. As a result, only the portion of the seed layer 51 that is located below the pedestal portion 21 remains. As a result, the seed layer 14 is formed. When the seed layer 51 is etched, the pedestal portion 21 functions as an etching mask, so that the outer shape of the seed layer 14 is formed to be the same as the outer shape of the pedestal portion 21.

[0067] Subsequently, the solder layer 54 is melted by a reflow process to shape and fix the solder layer 54. This forms the solder portion 17. Next, the plurality of semiconductor chips formed on the substrate 11 are separated by dicing, thereby manufacturing the semiconductor chip 30 shown in FIG.

[0068] In the semiconductor chip 30 of this embodiment, an insulating film 31 is further provided on the passivation film 13. However, as in the first embodiment, the pedestal portion 21 and the column portion 22 are formed by continuous plating, and therefore have no boundary. Therefore, the pedestal portion 21 and the column portion 22 have good connection strength. As a result, even if the inner circumferential surface of the second opening 31a of the insulating film 31 is inclined, the pedestal portion 21 is formed on the insulating film 31 along the inclination, and therefore, even if the column portion 22 is located on the inclined surface of the insulating film 31, the pedestal portion 21 and the column portion 22 can have good bonding strength.

[0069] The present disclosure is not limited to the above-described embodiments, and various modifications and applications are possible.

[0070] In the above-described embodiments, the solder portion 17 is formed on the column portion 22 of the columnar electrode 20, but the present disclosure is not limited to this. For example, in the present disclosure, a metal layer with a low diffusion coefficient, such as Ni, can be provided between the column portion 22 and the solder portion 17. By providing such a metal layer, when the column portion is made of Cu, the diffusion and alloying of the metal material between the solder portion 17 and the column portion 22 can be suppressed, thereby suppressing electromigration. Alternatively, the bulk strength of the joint of the solder portion 17 can be improved.

[0071] Furthermore, the planar shape of the pedestal portion 21 is not limited to a square shape, but may be a circle, a rectangle, or the like. If the planar shape of the pedestal portion 21 is a circle, the diameter of the pedestal portion 21 is preferably 5 μm to 20 μm larger than the diameter of the column portion 22. If the planar shape of the pedestal portion 21 is a rectangle, the shorter side of the rectangle in plan view of the pedestal portion 21 is preferably 5 μm to 20 μm larger than the diameter of the column portion 22. Similarly, the planar shape of the first opening 13a of the passivation film 13 is not limited to a square shape, but may be a circle, a rectangle, or the like. If the planar shape of the first opening 13a is a circle, the diameter of the first opening 13a is preferably 5 μm to 20 μm larger than the diameter of the column portion 22. If the planar shape of the first opening 13a is a rectangle, the shorter side of the rectangle in plan view of the first opening 13a is preferably 5 μm to 20 μm larger than the diameter of the column portion 22.

[0072] The present disclosure allows various embodiments and modifications without departing from the broad spirit and scope of the present disclosure. Furthermore, the above-described embodiments are intended to explain the present disclosure and do not limit the scope of the present disclosure. That is, the scope of the present disclosure is defined by the claims, not the embodiments. Various modifications made within the scope of the claims and within the meaning of the disclosure equivalent thereto are considered to be within the scope of the present disclosure.

[0073] This application is based on Japanese Patent Application No. 2023-104881 filed on June 27, 2023. The entire specification, claims, and drawings of Japanese Patent Application No. 2023-104881 are incorporated herein by reference.

[0074] 10, 30, 90 Semiconductor chip 11, 91 Base material 12, 92 Electrode pad 13, 93 Passivation film 13a First opening 14, 51, 94 Seed layer 17, 97 Solder portion 20 Column-shaped electrode 21 Pedestal portion 22 Column portion 31 Insulating film 31a Second opening 52 First resist layer 53 Second resist layer 52a, 53a Resist opening 54 Solder layer 91 Base material 93 Passivation film 94a Outer periphery 97 Solder portion 98 Pillar

Claims

1. A semiconductor chip comprising: an electrode pad provided on a main surface of a substrate; a passivation film provided on the main surface of the substrate, the passivation film having a first opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the first opening, an inner circumferential surface of the first opening, and a peripheral portion of the first opening on the upper surface of the passivation film; and a column portion provided within the upper surface of the pedestal portion, the outer shape of the column portion being smaller than the outer shape of the pedestal portion when the main surface is viewed in a plane, wherein the pedestal portion and the column portion are formed from the same material.

2. The semiconductor chip described in claim 1, further comprising a seed layer provided to cover a portion of the electrode pad exposed by the first opening, an inner surface of the first opening, and a peripheral portion of the first opening on the upper surface of the passivation film, wherein the pedestal portion is provided on the seed layer, and the seed layer and the pedestal portion have the same shape when the main surface is viewed in a plane.

3. The semiconductor chip according to claim 1, wherein the pillar portion is provided so as to be located only above a region of the electrode pad exposed by the first opening.

4. The semiconductor chip according to claim 1, wherein the thickness of the base is 5 μm or less.

5. The semiconductor chip according to claim 1, wherein the diameter of said pillar portion is in the range of 5 to 30 μm.

6. The semiconductor chip according to claim 1, further comprising a solder portion provided on an upper portion of said pillar portion.

7. A semiconductor chip comprising: an electrode pad provided on a main surface of a substrate; a passivation film provided on the main surface of the substrate, the passivation film having a first opening for partially exposing the electrode pad; an insulating film provided on the passivation film and the electrode pad, the insulating film having a second opening for partially exposing the electrode pad; a pedestal portion provided on a portion of the electrode pad exposed by the second opening, an inner circumferential surface of the second opening of the insulating film, and a peripheral portion of the second opening on an upper surface of the insulating film; and a columnar electrode having a column portion provided within an upper surface of the pedestal portion, the outer shape of the column portion being smaller than the outer shape of the pedestal portion when the main surface is viewed in a plane, the pedestal portion and the column portion being formed from the same material.

8. A method for manufacturing a semiconductor chip, comprising the steps of: preparing a substrate having an electrode pad on a main surface thereof, and a passivation film on the main surface having a first opening formed therein for partially exposing the electrode pad; forming a seed layer on the passivation film and on a portion of the electrode pad exposed by the first opening; forming a pedestal on the seed layer by plating; forming a pillar within an upper surface of the pedestal by plating; and removing by etching a portion of the seed layer not covered by the pedestal; wherein the outer shape of the pillar is formed to be smaller than the outer shape of the pedestal when the main surface is viewed in a plane; and the pedestal and the pillar are formed using the same material.

9. The method for manufacturing a semiconductor chip according to claim 8, wherein the pillar portion is formed so as to be located only above a region of the electrode pad exposed by the first opening.

10. The method for manufacturing a semiconductor chip according to claim 8, wherein the thickness of the base portion is formed to be 5 μm or less.

11. The method for manufacturing a semiconductor chip according to claim 8, wherein the pillar portion is formed so that the diameter of the pillar portion is in the range of 5 to 30 μm.

12. The method for manufacturing a semiconductor chip according to claim 8, further comprising the step of forming a solder layer on top of the pillars after the step of forming the pillars.

13. A method for manufacturing a semiconductor chip, comprising the steps of: preparing a substrate having an electrode pad on a main surface thereof, and a passivation film having a first opening for partially exposing the electrode pad on the main surface; forming an insulating film having a second opening for partially exposing the electrode pad on the passivation film and the electrode pad; forming a seed layer on the insulating film and on a portion of the electrode pad exposed by the second opening; forming a pedestal portion on the seed layer by plating; forming a pillar portion on the pedestal portion by plating; and removing by etching a portion of the seed layer not covered by the pedestal portion; wherein the outer shape of the pillar portion is formed smaller than the outer shape of the pedestal portion when the main surface is viewed in a plane; and the pedestal portion and the pillar portion are formed using the same material.

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