Semiconductor module

Abstract

The present invention reduces high-frequency noise. This semiconductor module (100) is provided with a semiconductor element (1), a power supply path (3), a first inductor (L1), a capacitor (C1), and a second inductor (L2). The semiconductor element (1) has a power supply terminal (14). The power supply path (3) is connected to the power supply terminal (14) of the semiconductor element (1). The first inductor (L1) is provided in the power supply path (3). The capacitor (C1) has a first end and a second end. In the capacitor (C1), the first end is connected to the power supply path (3), and the second end is connected to the ground. The second inductor (L2) is provided in the power supply path (3) and is connected between the first inductor (L1) and the power supply terminal (14). The first inductor (L1) and the second inductor (L2) are arranged so that a magnetic field generated by the first inductor (L1) and a magnetic field generated by the second inductor (L2) are coupled.

Description

Semiconductor Module

[0001] The present invention relates generally to semiconductor modules, and more particularly to semiconductor modules including semiconductor devices and capacitors.

[0002] Japanese Patent Application Laid-Open No. 2003-124222 discloses a power amplifier (semiconductor module) including an amplifier (semiconductor element), an inductor, and a bypass capacitor (capacitor).

[0003] In the power amplifier disclosed in Patent Document 1, an inductor is connected between the amplifier and a bias power supply (DC power supply), and a bypass capacitor is connected between the connection point between the inductor and the bias power supply and ground.

[0004] International Publication No. 2011 / 092910

[0005] In the power amplifier disclosed in Patent Document 1, the performance of the bypass capacitor may be degraded due to the influence of the ESL (Equivalent Series Inductance) of the bypass capacitor, causing high frequency noise to leak into the amplifier.

[0006] An object of the present invention is to provide a semiconductor module capable of reducing high frequency noise.

[0007] A semiconductor module according to one aspect of the present invention comprises a semiconductor element, a power supply path, a first inductor, a capacitor, and a second inductor. The semiconductor element has a power supply terminal. The power supply path is connected to the power supply terminal of the semiconductor element. The first inductor is provided in the power supply path. The capacitor has a first end and a second end. The first end of the capacitor is connected to the power supply path and the second end is connected to ground. The second inductor is provided in the power supply path and is connected between the first inductor and the power supply terminal. The first inductor and the second inductor are arranged so that a magnetic field generated by the first inductor and a magnetic field generated by the second inductor are coupled.

[0008] The semiconductor module according to the above aspect of the present invention can reduce high frequency noise.

[0009] FIG. 1 is a conceptual diagram of a semiconductor module according to a first embodiment. FIG. 2A is a perspective view of a main portion of the semiconductor module. FIG. 2B is a partially cutaway cross-sectional view of the semiconductor module. FIG. 3A is an explanatory diagram of mutual inductance occurring in the semiconductor module. FIG. 3B is an equivalent circuit diagram of a main portion of the semiconductor module. FIG. 4 is a circuit diagram of the semiconductor module. FIG. 5A is a plan view of a main portion of a semiconductor module according to a first modification of the first embodiment. FIG. 5B is a cross-sectional view of the semiconductor module taken along line X1-X1 in FIG. 5A. FIG. 6 is a conceptual diagram of a semiconductor module according to a second embodiment. FIG. 7A is a perspective view of a main portion of the semiconductor module. FIG. 7B is a partially cutaway cross-sectional view of the semiconductor module. FIG. 8 is an explanatory diagram of mutual inductance occurring in the semiconductor module. FIG. 9 is a circuit diagram of the semiconductor module. FIG. 10 is a conceptual diagram of a semiconductor module according to a second modification of the second embodiment.

[0010] Hereinafter, embodiments 1 and 2 will be described with reference to the drawings. The drawings referred to in the following embodiments 1 and 2 are schematic diagrams, and the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensions, and the size ratios and thickness ratios between the components do not necessarily reflect the actual dimensional ratios.

[0011] First Embodiment A semiconductor module 100 according to a first embodiment will be described with reference to the drawings.

[0012] As shown in FIG. 1, the semiconductor module 100 according to the first embodiment is connected to a DC power supply 7 , and the power supply voltage of the DC power supply 7 is supplied to the power supply terminals of the semiconductor element 1 .

[0013] The semiconductor module 100 is used in, for example, a communication device. The communication device is, for example, a mobile phone (for example, a smartphone), but is not limited to this and may be, for example, a wearable terminal (for example, a smart watch) or the like.

[0014] (1) Circuit Configuration of Semiconductor Module Hereinafter, the circuit configuration of the semiconductor module 100 according to the first embodiment will be described with reference to the drawings.

[0015] 1, the semiconductor module 100 includes a first terminal T1, a second terminal T2, a ground terminal, a semiconductor element 1, a power supply path 3, a first inductor L1, a capacitor C1, and a second inductor L2. The semiconductor element 1 has a power supply terminal 14. The power supply path 3 is connected to the power supply terminal 14 of the semiconductor element 1. The first inductor L1 is provided in the power supply path 3. The capacitor C1 has a first end and a second end. The first end of the capacitor C1 is connected to the power supply path 3 and the second end is connected to the ground terminal. The second inductor L2 is provided in the power supply path 3 and is connected between the first inductor L1 and the power supply terminal 14.

[0016] The semiconductor device 1 is, for example, a power amplifier that power-amplifies a high-frequency signal, and includes a transistor Q1 that power-amplifies the high-frequency signal, as shown in FIG. 4 . The transistor Q1 is an npn-type bipolar transistor. The transistor Q1 has an input terminal 11, an output terminal 12, and a ground terminal 13. The input terminal 11, the output terminal 12, and the ground terminal 13 of the transistor Q1 are the base terminal, the collector terminal, and the emitter terminal, respectively. The input terminal 11 of the transistor Q1 is a terminal to which a high-frequency signal is input. The ground terminal 13 of the transistor Q1 is connected to the ground terminal. The output terminal 12 of the transistor Q1 is connected to a DC power supply 7 via a power supply terminal 14, a second terminal T2, a second inductor L2, a first inductor L1, and a first terminal T1. A power supply voltage is applied to the transistor Q1 (between the output terminal 12 and the ground terminal 13) from the DC power supply 7. The transistor Q1 amplifies the high-frequency signal input to the input terminal 11 and outputs it from the output terminal 12. The bipolar transistor that constitutes the transistor Q1 is, for example, an HBT (Heterojunction Bipolar Transistor).

[0017] An input terminal 11 of the transistor Q1 is connected to a signal processing circuit of the communication device via a signal input terminal. An output terminal 12 of the transistor Q1 is connected to an antenna of the communication device via an antenna terminal. The power amplifier amplifies and outputs a high-frequency signal of a predetermined band output from the signal processing circuit.

[0018] The first inductor L1 and the second inductor L2 each have a first end and a second end. The first end of the first inductor L1 is connected to the first terminal T1. The second end of the first inductor L1 is connected to the first end of the second inductor L2. The second end of the second inductor L2 is connected to the second terminal T2. The second terminal T2 is connected to the power supply terminal 14 of the semiconductor element 1. The first inductor L1 and the second inductor L2 function as a choke coil that reduces high-frequency noise directed from the DC power supply 7 toward the power supply terminal 14 of the semiconductor element 1.

[0019] The capacitor C1 is connected to the second end of the first inductor L1 and the first end of the second inductor L2. The capacitor C1 functions as a bypass capacitor that reduces leakage of high-frequency signals generated in the semiconductor element 1 to the DC power supply 7, for example.

[0020] (2) Structure and Equivalent Circuit of Semiconductor Module As shown in Fig. 2B, the semiconductor module 100 includes a module substrate 5. The module substrate 5 has a main surface 50.

[0021] In a plan view from the thickness direction D1 of the module substrate 5 (see FIG. 2B ), the outer edge of the module substrate 5 is, for example, rectangular, but may have a shape other than rectangular. The module substrate 5 is, for example, a multilayer substrate in which multiple dielectric layers and multiple conductive layers (not shown) are stacked. Each conductive layer is made of, for example, copper. The multiple conductive layers include a ground layer.

[0022] The module substrate 5 is, for example, a low temperature co-fired ceramic (LTCC) substrate. However, the module substrate 5 is not limited to an LTCC substrate, and may be, for example, a printed wiring board, a high temperature co-fired ceramic (HTCC) substrate, a resin multilayer substrate, or a component-embedded substrate.

[0023] The semiconductor element 1 is a semiconductor chip. The semiconductor chip is a GaAs-based chip, but is not limited to a GaAs-based chip and may be a Si-based chip. The semiconductor element 1 is disposed on a module substrate 5. More specifically, the semiconductor element 1 is disposed on a main surface 50 of the module substrate 5. The phrase "the semiconductor element 1 is disposed on the module substrate 5" includes the semiconductor element 1 being mechanically connected to the module substrate 5 and the semiconductor element 1 being electrically connected to the module substrate 5.

[0024] The capacitor C1 is a chip capacitor. The capacitor C1 is disposed on the module substrate 5. More specifically, the capacitor C1 is disposed on the main surface 50 of the module substrate 5. The phrase "the capacitor C1 is disposed on the module substrate 5" includes both the capacitor C1 being mechanically connected to the module substrate 5 and the capacitor C1 being electrically connected to the module substrate 5.

[0025] 2A and 2B, the first inductor L1 and the second inductor L2 are inner layer inductors arranged in the module substrate 5. Note that the module substrate 5 is not shown in FIG. 2A.

[0026] The first inductor L1 is configured to include a wiring portion that is spirally wound when viewed from above in the thickness direction D1 of the module substrate 5. The second inductor L2 is configured to include a wiring portion that is spirally wound when viewed from above in the thickness direction D1 of the module substrate 5.

[0027] 2A and 2B, the first inductor L1 and the second inductor L2 are arranged so that the magnetic field generated by the first inductor L1 and the magnetic field generated by the second inductor L2 are coupled together. The first inductor L1 and the second inductor L2 are arranged so that the first inductor L1 and the second inductor L2 are coupled together.

[0028] In the semiconductor module 100, the winding direction of the first inductor L1 and the winding direction of the second inductor L2 are opposite to each other, and a portion of the first inductor L1 and a portion of the second inductor L2 overlap in the thickness direction D1 of the module substrate 5. In the semiconductor module 100, the first inductor L1 and the second inductor L2 are adjacent to each other in the thickness direction D1 of the module substrate 5. The fact that the first inductor L1 and the second inductor L2 are adjacent to each other means that the first inductor L1 and the second inductor L2 are arranged without any other circuit element being arranged between them. The second end of the first inductor L1 and the first end of the second inductor L2 are connected via a via conductor within the module substrate 5. In the semiconductor module 100, the first inductor L1 and the second inductor L2 are negatively coupled, and in FIG. 3A , the negative mutual inductance is represented by “-M.” FIG. 3B shows an equivalent circuit representation of the negative coupling between the first inductor L1 and the second inductor L2, in which a negative inductance “−M” with respect to ground is generated in the path between the first inductor L1 and the second inductor L2.

[0029] In the equivalent circuit shown in Fig. 3B, in addition to the first inductor L1, the second inductor L2, and the capacitor C1, a negative mutual inductance is illustrated as a circuit element (inductor). The equivalent circuit shown in Fig. 3B also illustrates the ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance) of the capacitor C1.

[0030] In the semiconductor module 100, the negative inductance cancels out the ESL of the capacitor C1, allowing the capacitor C1 to behave more like an ideal capacitor.

[0031] (3) Effects The semiconductor module 100 according to the first embodiment includes a first inductor L1 and a second inductor L2 provided in the power supply path 3, and a capacitor C1 connected between the power supply path 3 and ground. The first inductor L1 and the second inductor L2 are arranged so that the magnetic field generated by the first inductor L1 and the magnetic field generated by the second inductor L2 are coupled. This enables the semiconductor module 100 according to the first embodiment to reduce high-frequency noise. Therefore, the semiconductor module 100 according to the first embodiment can reduce high-frequency noise leaking from the DC power supply 7 to the power supply terminal 14 of the semiconductor element 1.

[0032] (4) Modifications (4.1) Modification 1 As shown in Figures 5A and 5B, the semiconductor module 100 according to Modification 1 of Embodiment 1 differs from the semiconductor module 100 according to Embodiment 1 in that the first inductor L1 is a chip inductor L0. Note that components similar to those in the semiconductor module 100 according to Embodiment 1 are denoted by the same reference numerals and descriptions thereof will be omitted.

[0033] In plan view from the thickness direction D1 of the module substrate 5, the outer edge of the chip inductor L0 has a rectangular shape.

[0034] The chip inductor L0 has a winding portion 9, a rectangular parallelepiped element body 8 covering the winding portion 9, and a pair of external electrodes. The winding portion 9 is disposed within the element body 8. The winding portion 9 is connected between the pair of external electrodes. The winding portion 9 is a coil conductor and is conductive. The shape of the winding portion 9 is, for example, spiral. The material of the element body 8 includes ceramic. The material of each of the pair of external electrodes is, for example, Cu, Ag, or the like. The material of the winding portion 9 includes, for example, the same material as the pair of external electrodes, but is not limited to this. The chip inductor L0 is a vertically wound inductor and is disposed on the main surface 50 of the module substrate 5 so that the winding axis A1 (see FIG. 5B ) of the winding portion 9 is parallel to the thickness direction D1 of the module substrate 5.

[0035] In the semiconductor module 100 according to the first modification, the first inductor L1 is a chip inductor L0, and the second inductor L2 is a spiral inner layer inductor disposed within the module substrate 5. The winding axis A1 of the winding portion 9 in the chip inductor L0 is parallel to the thickness direction D1 of the module substrate 5.

[0036] In the semiconductor module 100 according to the first modification, the first inductor L1 and the second inductor L2 overlap in a plan view in the thickness direction D1 of the module substrate 5. In the examples of Figures 5A and 5B, a portion of the first inductor L1 overlaps a portion of the second inductor L2, but the entire first inductor L1 may overlap the entire second inductor L2, or a portion of the first inductor L1 may overlap the entire second inductor L2.

[0037] (4.2) Modification 2 In the semiconductor module 100 according to modification 2, the first inductor L1 is a spiral inner layer inductor arranged within the module substrate 5, and the second inductor L2 is a chip inductor arranged on the module substrate 5.

[0038] The semiconductor module 100 according to the first and second modifications of the first embodiment achieves the same effects as the semiconductor module 100 according to the first embodiment.

[0039] Second Embodiment A semiconductor module 100A according to a second embodiment will be described with reference to Figures 6 to 9. Regarding the semiconductor module 100A according to the second embodiment, components that are the same as those in the semiconductor module 100 according to the first embodiment (see Figures 1 to 4) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0040] (1) Circuit Configuration of Semiconductor Module Hereinafter, the circuit configuration of the semiconductor module 100A according to the second embodiment will be described with reference to the drawings.

[0041] As shown in FIG. 6 , the semiconductor module 100A includes a first terminal T1, a second terminal T2, a ground terminal, a semiconductor element 1 (hereinafter also referred to as the first semiconductor element 1), a power supply path 3 (hereinafter also referred to as the first power supply path 3), a first inductor L1, a capacitor C1 (first capacitor C1), and a second inductor L2, similar to the semiconductor module 100 according to the first embodiment. The semiconductor module 100A also includes a third terminal T3, a second semiconductor element 2, a second power supply path 4, a third inductor L3, a first matching circuit MN1 (see FIG. 9 ), a second matching circuit MN2 (see FIG. 9 ), and a second capacitor C2 (see FIG. 9 ). The second semiconductor element 2 has a power supply terminal 24. The second power supply path 4 is connected between the connection point of the first inductor L1 and the second inductor L2 in the first power supply path 3 and the power supply terminal 24 of the second semiconductor element 2. The third inductor L3 is provided in the second power supply path 4. The third inductor L3 is connected to the power supply terminal 24 of the second semiconductor element 2 via the third terminal T3.

[0042] As shown in FIG. 9 , the first semiconductor element 1 includes a transistor Q1 (hereinafter also referred to as the first transistor Q1) that power-amplifies a high-frequency signal. The second semiconductor element 2 includes a second transistor Q2 that power-amplifies a high-frequency signal. The first transistor Q1 and the second transistor Q2 are each an npn-type bipolar transistor. The first transistor Q1 has an input terminal 11 (hereinafter also referred to as the first input terminal 11), an output terminal 12 (hereinafter also referred to as the first output terminal 12), and a ground terminal 13 (hereinafter also referred to as the first ground terminal 13). In the first transistor Q1, the first input terminal 11, the first output terminal 12, and the first ground terminal 13 are a base terminal, a collector terminal, and an emitter terminal, respectively. The second transistor Q2 has an input terminal 21 (hereinafter also referred to as the second input terminal 21), an output terminal 22 (hereinafter also referred to as the second output terminal 22), and a ground terminal 23 (hereinafter also referred to as the second ground terminal 23). In the second transistor Q2, the second input terminal 21, the second output terminal 22, and the second ground terminal 23 are the base terminal, the collector terminal, and the emitter terminal, respectively. The second output terminal 22 of the second semiconductor element 2 is connected to the DC power supply 7 via the power supply terminal 24, the third terminal T3, the third inductor L3, the first inductor L1, and the first terminal T1. A power supply voltage is applied to the second transistor Q2 (between the second output terminal 22 and the second ground terminal 23) from the DC power supply 7. The bipolar transistors constituting each of the first transistor Q1 and the second transistor Q2 are HBTs.

[0043] The first matching circuit MN1 is connected to the first input terminal 11 of the first transistor Q1 of the first semiconductor element 1. The second matching circuit MN2 is connected between the first output terminal 12 of the first transistor Q1 of the first semiconductor element 1 and the second input terminal 21 of the second transistor Q2 of the second semiconductor element 2.

[0044] The first input terminal 11 of the first transistor Q1 is connected to a signal processing circuit of the communication device via a first matching circuit MN1 and a signal input terminal, and the second output terminal 22 of the second transistor Q2 is connected to an antenna of the communication device via a filter and an antenna terminal.

[0045] The third inductor L3 has a first end and a second end. The first end of the third inductor L3 is connected to the second end of the first inductor L1 and the first end of the second inductor L2. The second end of the third inductor L3 is connected to the third terminal T3. The third terminal T3 is connected to the power supply terminal 24 of the second semiconductor element 2. The first inductor L1 and the second inductor L2 function as a choke coil that reduces high-frequency noise directed from the DC power supply 7 to the power supply terminal 24 of the second semiconductor element 2. The first inductor L1 and the third inductor L3 also function as a choke coil that reduces high-frequency noise directed from the DC power supply 7 to the power supply terminal 24 of the second semiconductor element 2.

[0046] (2) Structure and Equivalent Circuit of Semiconductor Module As shown in Fig. 7B, the semiconductor module 100A includes a module substrate 5. The module substrate 5 has a main surface 50.

[0047] The first semiconductor element 1 and the second semiconductor element 2 are disposed on a module substrate 5. More specifically, the first semiconductor element 1 and the second semiconductor element 2 are disposed on a main surface 50 of the module substrate 5. More specifically, an IC chip including the first semiconductor element 1 and the second semiconductor element 2 is disposed on the main surface 50 of the module substrate 5.

[0048] The capacitor C1 is a chip capacitor and is disposed on the module substrate 5.

[0049] 7A and 7B, the first inductor L1, the second inductor L2, and the third inductor L3 are inner layer inductors arranged in the module substrate 5. Note that the module substrate 5 is not shown in FIG. 7A.

[0050] The first inductor L1 has a spiral shape when viewed from above in the thickness direction D1 of the module substrate 5. The second inductor L2 has a spiral shape when viewed from above in the thickness direction D1 of the module substrate 5. The third inductor L3 has a spiral shape when viewed from above in the thickness direction D1 of the module substrate 5.

[0051] In the semiconductor module 100A, the first inductor L1 and the second inductor L2 are arranged so that the magnetic field generated by the first inductor L1 and the magnetic field generated by the second inductor L2 are coupled, and the second inductor L2 and the third inductor L3 are arranged so that the magnetic field generated by the second inductor L2 and the magnetic field generated by the third inductor L3 are coupled. Also, in the semiconductor module 100A, the first inductor L1 and the third inductor L3 are arranged so that the first inductor L1 and the third inductor L3 are negatively coupled to each other, generating negative mutual inductance.

[0052] In the semiconductor module 100A, the first inductor L1, the second inductor L2, and the third inductor L3 are arranged in the thickness direction D1 of the module substrate 5 in the order of the first inductor L1, the second inductor L2, and the third inductor L3 from the main surface 50 side of the module substrate 5.

[0053] In the semiconductor module 100A, the winding directions of the first inductor L1 and the second inductor L2 are the same, and a portion of the first inductor L1 and a portion of the second inductor L2 overlap in the thickness direction D1 of the module substrate 5. In the semiconductor module 100A, the first inductor L1 and the second inductor L2 are adjacent to each other in the thickness direction D1 of the module substrate 5. The second end of the first inductor L1 and the first end of the second inductor L2 are connected via a first via conductor within the module substrate 5. In the semiconductor module 100A, the first inductor L1 and the second inductor L2 are positively coupled, so that a positive mutual inductance with respect to ground is generated in the path between the first inductor L1 and the second inductor L2. In FIG. 8, the positive mutual inductance is represented by "M."

[0054] In the semiconductor module 100A, the winding direction of the second inductor L2 and the winding direction of the third inductor L3 are opposite to each other, and a portion of the second inductor L2 and a portion of the third inductor L3 overlap in the thickness direction D1 of the module substrate 5. In the semiconductor module 100A, the second inductor L2 and the third inductor L3 are adjacent to each other in the thickness direction D1 of the module substrate 5. A first end of the second inductor L2 and a first end of the third inductor L3 are connected via a second via conductor within the module substrate 5. In the semiconductor module 100A, the second inductor L2 and the third inductor L3 are negatively coupled, and therefore a negative mutual inductance with respect to ground occurs in the path between the second inductor L2 and the third inductor L3. In FIG. 8, the negative mutual inductance is represented by "-M."

[0055] In the semiconductor module 100A according to the second embodiment, the first inductor L1 and the third inductor L3 are not adjacent to each other in the thickness direction D1 of the module substrate 5.

[0056] (3) Effects The semiconductor module 100A according to the second embodiment includes the second power supply path 4 connected between the connection point of the first inductor L1 and the second inductor L2 in the first power supply path 3 and the power supply terminal 24 of the second semiconductor element 2, and includes the third inductor L3 provided in the second power supply path 4. This makes it possible to reduce high-frequency noise leaking from the second power supply path 4 to the second semiconductor element 2.

[0057] Furthermore, the semiconductor module 100A according to the second embodiment can ensure isolation between the first power supply path 3 and the second power supply path 4. More specifically, the semiconductor module 100A according to the second embodiment can ensure isolation between the path between the first terminal T1 and the second terminal T2 and the path between the third terminal T3 and the first terminal T1.

[0058] 10, the semiconductor module 100A according to the modification of the second embodiment may be configured such that the first inductor L1 and the second inductor L2 are negatively coupled, the second inductor L2 and the third inductor L3 are negatively coupled, and the first inductor L1 and the third inductor L3 are positively coupled. In this case, the winding direction of the first inductor L1 and the second inductor L2 are opposite to each other, the winding directions of the second inductor L2 and the third inductor L3 are opposite to each other, and the winding direction of the first inductor L1 and the third inductor L3 are the same.

[0059] The semiconductor module 100A according to the modified example of the second embodiment has the same effects as the semiconductor module 100A according to the second embodiment.

[0060] The above-described first and second embodiments are merely examples of various embodiments of the present invention. The above-described first and second embodiments can be modified in various ways depending on the design, etc., as long as the object of the present invention can be achieved.

[0061] Each of the first transistor Q1 included in the first semiconductor element 1 and the second transistor Q2 included in the second semiconductor element 2 is not limited to a bipolar transistor, and may be, for example, a MOSFET.

[0062] Each of the first semiconductor element 1 and the second semiconductor element 2 may be any semiconductor element that operates based on the power supply voltage supplied from the DC power supply 7, and is not limited to a power amplifier, but may also be, for example, a low-noise amplifier or a switch.

[0063] (Aspects) The present specification discloses the following aspects.

[0064] A semiconductor module (100; 100A) according to a first aspect includes a semiconductor element (1), a power supply path (3), a first inductor (L1), a capacitor (C1), and a second inductor (L2). The semiconductor element (1) has a power supply terminal (14). The power supply path (3) is connected to the power supply terminal (14) of the semiconductor element (1). The first inductor (L1) is provided in the power supply path (3). The capacitor (C1) has a first end and a second end. The first end of the capacitor (C1) is connected to the power supply path (3) and the second end is connected to ground. The second inductor (L2) is provided in the power supply path (3) and is connected between the first inductor (L1) and the power supply terminal (14). The first inductor (L1) and the second inductor (L2) are arranged so that a magnetic field generated in the first inductor (L1) and a magnetic field generated in the second inductor (L2) are coupled.

[0065] According to this aspect, it is possible to reduce high frequency noise.

[0066] In the semiconductor module (100; 100A) according to the second aspect, in the first aspect, the first end of the capacitor (C1) is connected to the connection point between the first inductor (L1) and the second inductor (L2).

[0067] A semiconductor module (100A) according to a third aspect is the same as that according to the first or second aspect, and further includes a second semiconductor element (2), a second power supply path (4), and a third inductor (L3). The second semiconductor element (2) is different from the first semiconductor element (1), which is the semiconductor element (1). The second semiconductor element (2) has a power supply terminal (24). The second power supply path (4) is connected between the connection point of the first inductor (L1) and the second inductor (L2) in the first power supply path (3), which is the power supply path (3), and the power supply terminal (24) of the second semiconductor element (2). The third inductor (L3) is provided in the second power supply path (4).

[0068] According to this aspect, it is possible to reduce high frequency noise leaking from the second power supply path (4) to the second semiconductor element (2).

[0069] A semiconductor module (100; 100A) according to a fourth aspect is the same as that of the first aspect, but further includes a module substrate (5). The semiconductor element (1) is disposed on the module substrate (5). The first inductor (L1) and the second inductor (L2) are inner layer inductors disposed within the module substrate (5). The first inductor (L1) includes a wiring portion wound in a spiral shape when viewed from a plane in the thickness direction (D1) of the module substrate (5). The second inductor (L2) includes a wiring portion wound in a spiral shape when viewed from a plane in the thickness direction (D1) of the module substrate (5). The first inductor (L1) and the second inductor (L2) are disposed so that a magnetic field generated in the first inductor (L1) and a magnetic field generated in the second inductor (L2) are coupled.

[0070] A semiconductor module (100; 100A) according to a fifth aspect is the fourth aspect, in which the first inductor (L1) and the second inductor (L2) are adjacent to each other in the thickness direction (D1) of the module substrate (5).

[0071] According to this aspect, it is easy to couple the magnetic field generated by the first inductor (L1) with the magnetic field generated by the second inductor (L2).

[0072] A semiconductor module (100A) according to a sixth aspect is the third aspect, further comprising a module substrate (5). The first semiconductor element (1) and the second semiconductor element (2) are arranged on the module substrate (5). The first inductor (L1), the second inductor (L2), and the third inductor (L3) are inner layer inductors arranged within the module substrate (5). The first inductor (L1) includes a wiring portion wound spirally in a planar view from the thickness direction (D1) of the module substrate (5). The second inductor (L2) includes a wiring portion wound spirally in a planar view from the thickness direction (D1) of the module substrate (5). The third inductor (L3) includes a wiring portion wound spirally in a planar view from the thickness direction (D1) of the module substrate (5). The second inductor (L2) and the third inductor (L3) are arranged so that a magnetic field generated in the second inductor (L2) and a magnetic field generated in the third inductor (L3) are coupled. The first inductor (L1) and the third inductor (L3) are arranged so that the magnetic field generated by the first inductor (L1) and the magnetic field generated by the third inductor (L3) cancel each other out.

[0073] According to this aspect, it is possible to improve the isolation between the first power supply path (3) and the second power supply path (4).

[0074] A semiconductor module (100A) according to a seventh aspect is based on the sixth aspect. In the semiconductor module (100A), the wiring portion of the first inductor (L1) and the wiring portion of the second inductor (L2) are adjacent to each other in the thickness direction (D1) of the module substrate (5). The wiring portion of the second inductor (L2) and the wiring portion of the third inductor (L3) are adjacent to each other. The wiring portion of the first inductor (L1) and the wiring portion of the third inductor (L3) are not adjacent to each other.

[0075] According to this aspect, it is possible to achieve miniaturization.

[0076] A semiconductor module (100; 100A) according to an eighth aspect is any one of the first to third aspects, further comprising a module substrate (5). The semiconductor element (1) is disposed on the module substrate (5). One of the wiring portion of the first inductor (L1) and the wiring portion of the second inductor (L2) is a chip inductor (L0). The chip inductor (L0) is disposed on the module substrate (5). The chip inductor (L0) has a winding portion (9). The remaining one of the wiring portion of the first inductor (L1) and the wiring portion of the second inductor (L2) is a spiral-shaped inner layer inductor disposed within the module substrate (5). The winding axis (A1) of the winding portion (9) of the wiring portion of the chip inductor (L0) is parallel to the thickness direction (D1) of the module substrate (5). In a plan view in the thickness direction (D1) of the module substrate (5), at least a part of the wiring portion of the first inductor (L1) and the wiring portion of the second inductor (L2) overlap.

[0077] REFERENCE SIGNS LIST 1 Semiconductor element (first semiconductor element) 11 Input terminal (first input terminal) 12 Output terminal (first output terminal) 13 Ground terminal (first ground terminal) 14 Power supply terminal 2 Second semiconductor element 21 Input terminal (second input terminal) 22 Output terminal (second output terminal) 23 Ground terminal (second ground terminal) 24 Power supply terminal 3 Power supply path (first power supply path) 4 Second power supply path 5 Module substrate 50 Main surface 7 DC power supply 8 Element body 9 Winding portion 100, 100A Semiconductor module A1 Winding axis L0 Chip inductor L1 First inductor L2 Second inductor L3 Third inductor C1 Capacitor (first capacitor) C2 Second capacitor MN1 First matching circuit MN2 Second matching circuit T1 First terminal T2 Second terminal T3 Third terminal

Claims

1. A semiconductor module comprising: a semiconductor element having a power supply terminal; a power supply path connected to the power supply terminal of the semiconductor element; a first inductor provided in the power supply path; a capacitor having a first end and a second end, the first end being connected to the power supply path and the second end being connected to ground; and a second inductor provided in the power supply path and connected between the first inductor and the power supply terminal, the first inductor and the second inductor being arranged so that a magnetic field generated by the first inductor and a magnetic field generated by the second inductor are coupled.

2. The semiconductor module according to claim 1, wherein the first end of the capacitor is connected to a connection point between the first inductor and the second inductor.

3. The semiconductor module according to claim 1 or 2, further comprising: a second semiconductor element having a power supply terminal different from the first semiconductor element, which is the semiconductor element; a second power supply path connected between a path between the first inductor and the second inductor in the first power supply path, which is the power supply path, and the power supply terminal of the second semiconductor element; and a third inductor provided in the second power supply path.

4. The semiconductor module described in claim 1, further comprising a module substrate, wherein the semiconductor element is disposed on the module substrate, the first inductor and the second inductor are inner layer inductors disposed within the module substrate, the first inductor includes a wiring portion wound in a spiral shape when viewed in a plane in the thickness direction of the module substrate, and the second inductor includes a wiring portion wound in a spiral shape when viewed in a plane in the thickness direction of the module substrate, and the first inductor and the second inductor are disposed such that a magnetic field generated in the first inductor and a magnetic field generated in the second inductor are coupled to each other.

5. The semiconductor module according to claim 4, wherein the first inductor and the second inductor are adjacent to each other in the thickness direction of the module substrate.

6. The semiconductor module according to claim 3, further comprising a module substrate, wherein the first semiconductor element and the second semiconductor element are disposed on the module substrate, the first inductor, the second inductor and the third inductor are inner layer inductors disposed within the module substrate, the first inductor includes a wiring portion wound in a spiral shape when viewed in a plan view from the thickness direction of the module substrate, the second inductor includes a wiring portion wound in a spiral shape when viewed in a plan view from the thickness direction of the module substrate, and the third inductor includes a wiring portion wound in a spiral shape when viewed in a plan view from the thickness direction of the module substrate, the second inductor and the third inductor are disposed such that a magnetic field generated in the second inductor and a magnetic field generated in the third inductor are coupled to each other, and the first inductor and the third inductor are disposed such that a magnetic field generated in the first inductor and a magnetic field generated in the third inductor cancel each other out.

7. The semiconductor module described in claim 6, wherein, in the thickness direction of the module substrate, a wiring portion of the first inductor and a wiring portion of the second inductor are adjacent to each other, a wiring portion of the second inductor and a wiring portion of the third inductor are adjacent to each other, and a wiring portion of the first inductor and a wiring portion of the third inductor are not adjacent to each other.

8. The semiconductor module according to any one of claims 1 to 3, further comprising a module substrate, the semiconductor element being disposed on the module substrate, one of the wiring portion of the first inductor and the wiring portion of the second inductor being a chip inductor disposed on the module substrate and having a winding portion, the remaining one of the wiring portion of the first inductor and the wiring portion of the second inductor being a spiral inner layer inductor disposed within the module substrate, the winding axis of the winding portion in the wiring portion of the chip inductor being parallel to the thickness direction of the module substrate, and at least a portion of the wiring portion of the first inductor and the wiring portion of the second inductor overlapping in a plan view from the thickness direction of the module substrate.

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