Ceramic circuit board, manufacturing method therefor, and double-sided cooling type power module having same

Abstract

The present invention provides: a ceramic circuit board comprising a copper structure, and thus has excellent heat dissipation performance; a manufacturing method therefor; and a double-sided cooling type power module having same. The ceramic circuit board according to one embodiment of the present invention comprises: a ceramic substrate including a ceramic layer and a first base copper layer arranged on a first surface of the ceramic layer; a first copper structure, which is arranged in a region of a part of the first base copper layer, is formed by printing, compressing, and sintering a copper-containing paste, has a differential porosity, and includes, on the top side thereof, a region having a porosity lower than the porosity of the bottom side thereof that is relatively adjacent to the first base copper layer; and an element attachment layer which is locally arranged on the surface of the first copper structure, and which is formed by printing, drying, compressing, and sintering a silver-containing paste.

Description

Ceramic circuit board, manufacturing method thereof, and double-sided cooling power module having the same

[0001] The technical idea of ​​the present invention relates to a ceramic circuit board, and more specifically, to a ceramic circuit board having a copper structure having a component attachment layer, a method for manufacturing the same, and a double-sided cooling power module having the same.

[0002] Power semiconductor devices, widely used in mobile devices, home appliances, and automobiles, play a role in converting, processing, and controlling power. Power semiconductor devices, which require high current and voltage for power supply, generate a significant amount of heat, and therefore use ceramic circuit boards made of ceramic materials such as Al2O3, AlN, Zirconia Toughened Alumina (ZTA), and Si3N4. Ceramics have high insulation, mechanical strength, and relatively high heat dissipation performance, making them suitable as substrates for high-power power semiconductor devices. In addition, ceramic circuit boards may include conductive patterns made of aluminum (Al) or copper (Cu), which have high thermal conductivity, on the ceramic material.

[0003] In order to easily dissipate heat generated from power semiconductor devices, a double-sided cooling type power module is being used, which can cool both sides by placing ceramic circuit boards on both sides of the power semiconductor devices. In addition, to dissipate heat from the power module, cooling fins are placed on the outside of the ceramic circuit board, and heat can be transferred to a water cooler installed externally through the cooling fins.

[0004] Conventional techniques for manufacturing such ceramic circuit boards use an etching process to form a conductive layer pattern, which limits the shape of the pattern. In particular, conventional techniques using an etching process have difficulty forming patterns with step thicknesses or multilayer patterns to accommodate various types of power semiconductor devices. Therefore, conventionally, conductive spacers made of a Mo-Cu alloy have been used to secure the step thicknesses of the patterns. However, the Mo-Cu alloy conductive spacers have low thermal conductivity and require an additional process of individually mounting small spacers on the ceramic circuit board, which is a limitation. In addition, attaching cooling fins to the outer surface of the ceramic circuit board has the limitation that sufficient heat transfer between the ceramic circuit board and the cooling fins is not achieved. A method of applying thermal grease to the contact surface to ensure smooth heat transfer between them is also available, but this has limitations in improving heat dissipation performance.

[0005] In addition, if a silver plating layer is formed across the entire surface as an adhesion layer of a power semiconductor device, a peeling defect may occur at the adhesive interface between the silver plating layer and the mold layer.

[0006] <Prior Art Document> Korean Patent Publication No. 2014-0127228

[0007] The technical problem to be achieved by the technical idea of ​​the present invention is to provide a ceramic circuit board having excellent heat dissipation performance including a copper structure, a method for manufacturing the same, and a double-sided cooling power module having the same.

[0008] However, these tasks are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0009] According to one aspect of the present invention, a ceramic circuit board having excellent heat dissipation performance including a copper structure, a method for manufacturing the same, and a double-sided cooling power module having the same are provided.

[0010] According to one embodiment of the present invention, the ceramic circuit board may include a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; a first copper structure disposed on a portion of the first base copper layer, the first copper structure formed by printing, pressing, and sintering a copper-containing paste, the first copper structure having a differential porosity and including a region on an upper side having a lower porosity than a lower side relatively adjacent to the first base copper layer; and an element attachment layer locally disposed on a surface of the first copper structure and formed by printing, drying, pressing, and sintering a silver-containing paste.

[0011] According to one embodiment of the present invention, the porosity of the first copper structure may decrease from the lower side relatively adjacent to the first base copper layer toward the upper side.

[0012] According to one embodiment of the present invention, the first copper structure may include a first base portion; and a first surface portion disposed on the first base portion and having a lower porosity than the first base portion.

[0013] According to one embodiment of the present invention, the first base portion may have a porosity in a range of more than 5% by volume and less than or equal to 20% by volume, and the first surface portion may have a porosity in a range of more than 0% by volume and less than or equal to 5% by volume.

[0014] According to one embodiment of the present invention, the first base portion may be formed using a paste containing copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm, and the first surface portion may be formed using a paste containing copper particles having an average particle diameter in a range of 100 nm to 3 μm.

[0015] According to one embodiment of the present invention, a second copper structure may be further included, which is disposed on at least a portion of the first copper structure, is formed by printing, pressing, and sintering a copper-containing paste, has a differential porosity, and includes a region on an upper side having a lower porosity than a lower side relatively adjacent to the first copper structure.

[0016] According to one embodiment of the present invention, the second copper structure may further include an element attachment layer locally disposed on the surface.

[0017] According to one embodiment of the present invention, the porosity of the second copper structure may decrease from the lower side relatively adjacent to the first copper structure toward the upper side.

[0018] According to one embodiment of the present invention, the second copper structure may include a second base portion; and a second surface portion disposed on the second base portion and having a lower porosity than the second base portion.

[0019] According to one embodiment of the present invention, the second base portion may have a porosity in a range of more than 5% by volume and less than or equal to 20% by volume, and the second surface portion may have a porosity in a range of more than 0% by volume and less than or equal to 5% by volume.

[0020] According to one embodiment of the present invention, the second base portion may be formed using a paste containing copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm, and the second surface portion may be formed using a paste containing copper particles having an average particle diameter in a range of 100 nm to 3 μm.

[0021] According to one embodiment of the present invention, the first base copper layer may be formed of a TPC copper layer formed by printing, pressing, and sintering a copper-containing paste on the ceramic layer, a DBC copper layer formed by bonding a copper foil on the ceramic layer through a high-temperature oxidation process, a DPC copper layer formed by forming a seed layer on the ceramic layer and then plating the seed layer with copper, or an AMB copper layer formed by bonding a copper foil using an active metal foil to the ceramic layer.

[0022] According to one embodiment of the present invention, the first base copper layer may include at least one of a bonding copper layer, a laminated copper layer, and a surface copper layer.

[0023] According to one embodiment of the present invention, the bonding copper layer may be formed using a copper-containing bonding paste including glass frit, inorganic particles, copper oxide particles, copper particles, a solvent, and a binder, the laminated copper layer may be formed using a copper-containing laminated paste including inorganic particles, copper particles, a solvent, and a binder, and the surface copper layer may be formed using a copper-containing surface paste including copper oxide particles, copper particles, a solvent, and a binder.

[0024] According to one embodiment of the present invention, the ceramic substrate may further include a second base copper layer disposed on a second surface of the ceramic layer.

[0025] According to one embodiment of the present invention, a method for manufacturing the ceramic circuit board includes the steps of: providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; forming a first copper structure on a portion of the ceramic substrate; forming one or more second copper structures on at least a portion of the first copper structure; and locally forming a device attachment layer on a surface of at least one of the first copper structure and the second copper structure, wherein the step of forming the device attachment layer may include: a printing step of locally printing a silver-containing paste on a surface of at least one of the first copper structure and the second copper structure to form a silver-containing paste layer; a pressing step of pressing the silver-containing paste layer; and a sintering step of sintering the silver-containing paste layer at a temperature in a range of 500°C to 700°C to form the device attachment layer.

[0026] According to one embodiment of the present invention, the double-sided cooling power module comprises: a lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; a lower second copper structure disposed on a portion of the lower first copper structure; and a lower component attachment layer locally disposed on a surface of at least one of the lower first copper structure and the lower second copper structure; an upper ceramic circuit board including an upper ceramic layer and an upper first base copper layer; an upper first copper structure disposed on a portion of the upper ceramic substrate; an upper second copper structure disposed on a portion of the upper first copper structure; and an upper component attachment layer locally disposed on a surface of at least one of the upper first copper structure and the upper second copper structure; a first semiconductor element disposed between the lower first copper structure and the upper first copper structure and attached by the lower component attachment layer and the upper component attachment layer; A second semiconductor element disposed between the lower second copper structure and the upper second copper structure, attached by the lower element attachment layer and the upper element attachment layer, and having a smaller thickness than the first semiconductor element; and a mold layer filling a space between the lower ceramic circuit board and the upper ceramic circuit board to cover the first semiconductor element and the second semiconductor element; wherein at least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure has a differential porosity, and may include a region on the upper side having a lower porosity than a lower side relatively adjacent to the lower first base copper layer or the upper first base copper layer.

[0027] According to one embodiment of the present invention, the lower ceramic substrate may further include a lower active metal brazing layer interposed between the lower ceramic layer and the lower first base copper layer, and the upper ceramic substrate may further include an upper active metal brazing layer interposed between the upper ceramic layer and the upper first base copper layer.

[0028] According to one embodiment of the present invention, the double-sided cooling power module comprises: a lower ceramic circuit board including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; a lower second copper structure disposed on a portion of the lower first copper structure; and a lower component attachment layer locally disposed on a surface of at least one of the lower first copper structure and the lower second copper structure; an upper ceramic substrate including an upper ceramic layer; an upper first base copper layer; and an upper component attachment layer locally disposed on a portion of the upper first base copper layer; a first semiconductor element disposed between the lower first copper structure and the upper first base copper layer and attached by the lower component attachment layer and the upper component attachment layer; a second semiconductor element disposed between the lower second copper structure and the upper first base copper layer and attached by the lower component attachment layer and the upper component attachment layer, the second semiconductor element having a smaller thickness than the first semiconductor element; And a mold layer that fills the space between the lower ceramic circuit board and the upper ceramic substrate to cover the first semiconductor element and the second semiconductor element; and at least one of the lower first copper structure and the lower second copper structure may include a region on the upper side having a differential porosity and having a lower porosity than the lower side relatively adjacent to the lower first base copper layer.

[0029] According to one embodiment of the present invention, the lower ceramic substrate may include a lower active metal brazing layer interposed between the lower ceramic layer and the lower first base copper layer, and the upper ceramic substrate may include an upper active metal brazing layer interposed between the upper ceramic layer and the upper first base copper layer.

[0030] The ceramic circuit board according to the present invention can form a three-dimensional pattern on a ceramic substrate by using a copper structure formed by printing, pressing, and sintering as a spacer, so as to be compatible with various types of semiconductor devices mounted on the substrate. Furthermore, the use of the copper structure improves electrical and thermal conductivity, and enhances durability against thermal cycles.

[0031] In addition, since the above copper structure is a sintered material rather than a rolled material, there are differences in the microstructure, such as not having the directionality that appears in a rolled material, and there are differences in the degree of inclusion and distribution of pores.

[0032] While the Mo-Cu spacer according to the prior art has a porosity of about 0% and thus has high thermal stress and low thermal fatigue characteristics, the copper structure according to the present invention includes a lower layer having a high porosity, thereby providing low thermal stress and improved resistance to thermal fatigue destruction, and further includes an upper layer having a low porosity, thereby preventing bonding defects in power semiconductor devices.

[0033] In addition, since the copper structure has a pyramidal shape, a power semiconductor element can be stably mounted.

[0034] In addition, in the ceramic circuit board according to the present invention, instead of forming a silver layer by plating on the entire surface of the ceramic board, a component attachment layer formed of a silver layer is locally formed in an area where a power semiconductor device is mounted, so that the mold layer composed of EMC only contacts the base copper structure composed of copper and does not contact the component attachment layer, thereby preventing a delamination defect occurring between the silver layer and the mold layer.

[0035] The method for manufacturing a ceramic circuit board according to the present invention can prevent the formation of defects due to heat by performing sintering of a copper structure at a temperature ranging from 500°C to 800°C. In addition, by performing surface blasting treatment, copper oxide formed on the surface of the copper structure during sintering can be removed to provide a smooth surface, thereby ensuring stable bonding of power semiconductor devices mounted on the copper structure.

[0036] The effects of the present invention described above are illustrative, and the scope of the present invention is not limited by these effects.

[0037] Figures 1 to 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0038] FIGS. 5A and 5B are cross-sectional views illustrating a base copper layer and a copper body of a ceramic circuit board according to one embodiment of the present invention.

[0039] FIG. 6 is a photograph showing the microstructure of a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0040] FIGS. 7a and 7b are cross-sectional views and photographs showing a pyramid-shaped copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0041] Figure 8 is a flowchart illustrating a method for manufacturing a ceramic circuit board according to one embodiment of the present invention.

[0042] Figure 9 is an ultrasonic inspection result showing whether a defect occurs depending on the sintering temperature of a ceramic circuit board according to an embodiment of the present invention.

[0043] FIG. 10 is a photograph showing the surface state of a copper structure of a ceramic circuit board before and after blasting treatment according to an embodiment of the present invention.

[0044] FIG. 11 is a photograph showing the surface state of a ceramic circuit board's element attachment layer before and after blasting treatment according to one embodiment of the present invention.

[0045] FIG. 12 is a perspective view illustrating a pair of ceramic circuit boards for forming a double-sided cooling power module according to one embodiment of the present invention.

[0046] Figures 13 to 16 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.

[0047] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Embodiments of the present invention are provided to more completely explain the technical idea of ​​the present invention to those skilled in the art. The following embodiments may be modified in various different forms, and the scope of the technical idea of ​​the present invention is not limited to the following embodiments. Rather, these embodiments are provided to more faithfully and completely convey the technical idea of ​​the present invention to those skilled in the art. Like reference numerals throughout this specification denote like elements. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the technical idea of ​​the present invention is not limited by the relative sizes or intervals drawn in the attached drawings.

[0048] In this specification, a layer formed "on" another layer may refer to a layer formed directly above the other layer, or may refer to an intermediate layer or layers formed on another layer. It should be noted that the meanings of "upper" and "lower" in this specification are relative, and the direction upward from the ceramic substrate is described as "upper", and the direction downward is described as "lower."

[0049] In this specification, power semiconductor devices are exemplary, and cases composed of other semiconductor devices are also included in the technical concept of the present invention.

[0050] Figures 1 to 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0051] Referring to FIGS. 1 to 4, a ceramic circuit board (1) may include a ceramic substrate (110), a first copper structure (150), and an element attachment layer (170). A ceramic circuit board (1a) may include a ceramic substrate (110a), a first copper structure (150), and an element attachment layer (170). A ceramic circuit board (100) may include a ceramic substrate (110), a first copper structure (150), a second copper structure (160), and an element attachment layer (170). A ceramic circuit board (100a) may include a ceramic substrate (110a), a first copper structure (150), a second copper structure (160), and an element attachment layer (170).

[0052] Hereinafter, components of a ceramic circuit board will be described in detail with reference to FIGS. 1 to 4.

[0053] The ceramic substrate (110) may include a ceramic layer (120), a first base copper layer (130), and a second base copper layer (140).

[0054] The ceramic substrate (110a) may include a ceramic layer (120), a first active metal brazing layer (125), a second active metal brazing layer (126), a first base copper layer (130), and a second base copper layer (140). Compared to the ceramic substrate (110), the ceramic substrate (110a) has a difference in that it further includes a first active metal brazing layer (125) and a second active metal brazing layer (126).

[0055] The ceramic layer (120) may have a first surface (121) and a second surface (122) that face each other. In FIGS. 1 to 4, the first surface (121) is illustrated as the upper surface and the second surface (122) is illustrated as the lower surface with respect to the ceramic layer (120). The ceramic layer (120) may have excellent thermal conductivity and electrical insulation. The ceramic layer (120) may be formed of a ceramic material, and may include, for example, at least one of Al2O3, AlN, Zirconia Toughened Alumina (ZTA), and Si3N4.

[0056] A first base copper layer (130) may be disposed on a first surface (121) of a ceramic layer (120). The first base copper layer (130) may be formed using TPC technology, DBC technology, DPC technology, or AMB technology. The first base copper layer (130) may have a total thickness in the range of, for example, 100 μm to 1000 μm, and may have a total thickness of, for example, about 300 μm.

[0057] The second base copper layer (140) may be disposed on the second surface (122) opposite to the first surface (121) of the ceramic layer (120). The second base copper layer (140) may function as a warpage prevention layer that prevents the ceramic layer (120) from warping during the sintering process for forming the first base copper layer (130) and the sintering process for forming the first copper structure (150) and the second copper structure (160). In addition, the second base copper layer (140) may provide a path for dissipating heat generated from the power semiconductor device to the outside. For this purpose, a heat dissipation structure (not shown) may be attached to the second base copper layer (140). The second base copper layer (140) may be formed as a single layer or as a plurality of layers.

[0058] The second base copper layer (140) can be formed in the same manner as the first base copper layer (130). The second base copper layer (140) can be formed using the above-described TPC technology, DBC technology, DPC technology, or AMB technology. The second base copper layer (140) can include the same material as the first base copper layer (130) and can be formed simultaneously.

[0059] The first base copper layer (130) and the second base copper layer (140) may be formed as TPC (thick printed copper) copper layers using TPC technology. The TPC technology may refer to a technology of forming a copper layer having a predetermined thickness by printing, pressing, and sintering using a copper-containing paste. The TPC copper layer may be formed by printing a copper-containing paste on one or both sides of a ceramic layer (120) to form a paste layer, and pressing and sintering the paste layer. Since the TPC technology forms the TPC copper layer using a screen printing method, it does not require an additional etching process and can freely implement various patterning shapes. In addition, the TPC technology may allow a layer formed in one process cycle of printing, pressing, and sintering to have a very small thickness, and the layer may have a thickness in the range of, for example, 10 μm to 100 μm. In addition, since the thickness of the TPC copper layer can be increased by repeatedly performing the above process cycle to form multiple layers, thickness control can be facilitated. In addition, the TPC copper layer can secure overall uniformity in thickness, surface quality, etc. In addition, nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the TPC copper layer.

[0060] In addition, the first base copper layer (130) and the second base copper layer (140) may be formed as DBC copper layers formed using DBC (direct bonded copper) technology. The DBC technology may refer to a technology of forming a copper layer by directly attaching a copper foil to a ceramic layer. The DBC copper layer may be formed by placing a copper foil on one or both sides of a ceramic layer (120), performing a high-temperature oxidation process at a temperature in the range of 1000°C to 1080°C, and bonding the copper foil to the ceramic layer using a copper-oxygen eutectic liquid. The bonding may be performed in a nitrogen atmosphere containing about 30 ppm of oxygen at a temperature lower than 1083°C, which is the melting point of copper, and forming a copper oxide layer on the surface of the copper foil to implement bonding with the ceramic layer (120). Subsequently, if necessary, the DBC copper layer may be patterned using an etching process. Additionally, nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the DBC copper layer.

[0061] In addition, the first base copper layer (130) and the second base copper layer (140) may be formed as DPC copper layers formed using DPC (direct plating copper) technology. The DPC technology may refer to a technology for forming a copper layer by using a thin film process, an etching process, and a plating process. The DPC copper layer may be formed by forming a seed layer of titanium (Ti), titanium-tungsten (TiW), or the like on one or both sides of a ceramic layer (120), and then plating copper (Cu) on the seed layer. In addition, a photoresist pattern may be formed on the seed layer, and then copper (Cu) may be plated on the photoresist pattern, and the photoresist pattern may be removed to form the DPC copper layer having a desired pattern. Subsequently, if necessary, the DPC copper layer may be patterned using an etching process.

[0062] In addition, the first base copper layer (130) and the second base copper layer (140) may be formed as active metal brazing (AMB) copper layers formed using an AMB technology. The AMB technology may refer to a technology for bonding a ceramic layer and a copper layer using an active metal foil. An active metal foil and a copper foil are sequentially placed on one or both sides of a ceramic layer (120), and heated to melt the active metal foil. As illustrated in FIG. 2, a first active metal brazing layer (125) and a second active metal brazing layer (126) are formed, thereby bonding the ceramic layer (120) and the copper foil to each other. Therefore, the first active metal brazing layer (125) may serve to bond the ceramic layer (120) and the first base copper layer (130). The second active metal brazing layer (126) may serve to bond the ceramic layer (120) and the second base copper layer (140). Next, if necessary, the AMB copper layer can be patterned using an etching process.

[0063] The first active metal brazing layer (125) and the second active metal brazing layer (126) may include a metal or metal alloy having a lower melting point than the copper constituting the copper foil, and may include, for example, an active metal alloy in which copper, aluminum, nickel, or silver is added to titanium, hafnium, nickel, molybdenum, or zirconium, which are active against oxygen, to lower the melting point. The first active metal brazing layer (125) and the second active metal brazing layer (126) may include, for example, an alloy including at least one of silver (Ag), copper (Cu), and titanium (Ti). However, this is exemplary, and the first active metal brazing layer (125) and the second active metal brazing layer (126) may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), niobium (Nb), and molybdenum (Mo).

[0064] As illustrated in FIG. 2, the first active metal brazing layer (125) may be disposed on the first surface (121) of the ceramic layer (120). The first base copper layer (130) may be disposed on the first active metal brazing layer (125). That is, the first active metal brazing layer (125) may be interposed between the ceramic layer (120) and the first base copper layer (130), thereby bonding the ceramic layer (120) and the first base copper layer (130) to each other.

[0065] The second active metal brazing layer (126) may be disposed on the second surface (122) of the ceramic layer (120). The second base copper layer (140) may be disposed on the second active metal brazing layer (126). That is, the second active metal brazing layer (126) may be interposed between the ceramic layer (120) and the second base copper layer (140), thereby bonding the ceramic layer (120) and the second base copper layer (140) to each other.

[0066] In order to form a pattern on the first base copper layer (130), an additional etching process may be required when applying the DBC technology, DPC technology, or AMB technology. Therefore, when using such an etching process, there is a limitation in that there is a limitation in the pattern shape, and it may be difficult to make a difference in thickness between patterns or to form secondary and tertiary patterns on the pattern in order to respond to various types of semiconductor devices. On the other hand, when applying the TPC technology to form the first base copper layer (130), the pattern can be easily formed during printing, and an additional etching process may not be required.

[0067] Referring to FIGS. 1 to 4, the first copper structure (150) may be disposed on a portion of the ceramic substrate (110), for example, on a portion of the first base copper layer (130). The first copper structures (150) may all have substantially the same height. The height may refer to the height from the ceramic substrate (110).

[0068] Referring to FIGS. 3 and 4, the second copper structure (160) may be disposed on at least a portion of the first copper structure (150). As the second copper structure (160) is formed on at least a portion of the first copper structure (150), the portion where the second copper structure (160) is additionally formed may have a higher height than the portion where only the first copper structure (150) is formed.

[0069] The first copper structure (150) and the second copper structure (160) can be formed using the above-described TPC technology that forms copper layers by printing, pressing, and sintering. Therefore, the first structure (150) and the second copper structure (160) can be sintered bodies made of substantially the same material. The second copper structure (160) can be laminated one or more times on the first copper structure (150). As an example, in FIGS. 3 and 4, a single layer of the second copper structure (160) is laminated on a portion of the first copper structure (150). However, the present invention is not limited thereto, and the second copper structure (160) can be formed in two or more layers in order to adjust the height of the copper structure as needed.

[0070] The first copper structure (150) and the second copper structure (160) can provide a space in which the power semiconductor element is mounted, and can function as a spacer that corrects a thickness deviation of the power semiconductor element. The height at which the power semiconductor element is disposed can be changed by the arrangement of the first copper structure (150) and the second copper structure (160). That is, as the second copper structure (160) is selectively formed on a portion of the first copper structure (150), the height provided when the first copper structure (150) and the second copper structure (160) are included can be greater than the height provided when only the first copper structure (150) is included. The height can refer to the height from the ceramic substrate (110). Copper structures having different heights are formed, and thus, the thickness deviation of power semiconductor elements having different thicknesses can be corrected.

[0071] The first copper structure (150) and the second copper structure (160) may have the same planar area, or the second copper structure (160) may have a smaller planar area than the first copper structure (150).

[0072] In addition, the first copper structure (150) and the second copper structure (160) can additionally perform the function of wiring that provides an electrical passage. The first copper structure (150) and the second copper structure (160) can be applied with a high current or high voltage from the power semiconductor element.

[0073] The first copper structure (150) and the second copper structure (160) can be integrated by sintering.

[0074] At least one of the first copper structure (150) and the second copper structure (160) may have a surface from which oxides have been removed by blasting treatment.

[0075] In order to attach a power semiconductor element, when silver is plated on the first copper structure (150), the second copper structure (160), and the ceramic substrate (110), a silver plating layer is formed on the entire exposed surface. However, since the silver plating layer formed entirely on the ceramic substrate (110) does not adhere to the mold layer formed in a subsequent process and a defect occurs in which it separates at the interface, it is necessary to configure the silver plating layer so that it does not come into contact with the mold layer.

[0076] Accordingly, the technical idea of ​​the present invention is to include an element attachment layer (170) that is locally disposed on the surface of at least one of the first copper structure (150) and the second copper structure (160) and includes silver.

[0077] The element attachment layer (170) can be locally disposed on the surface of at least one of the first copper structure (150) and the second copper structure (160). A power semiconductor element can be attached and mounted on the element attachment layer (170).

[0078] The device attachment layer (170) may be locally disposed on at least one surface of the first copper structure (150) and the second copper structure (160). In addition, the device attachment layer (170) may be locally disposed on a portion of the surface of the first base copper layer (130) of the ceramic substrate (110) to which the power semiconductor device is attached. The device attachment layer (170) may include silver (Ag), a silver alloy, copper, or a copper alloy. The thickness of the device attachment layer (170) may be, for example, in the range of 1 μm to 100 μm, and may be, for example, in the range of 1 μm to 20 μm.

[0079] FIGS. 5A and 5B are cross-sectional views illustrating a base copper layer and a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0080] Referring to FIG. 5a, the first base copper layer (130) may be a copper foil formed by DBC technology or AMB technology, or a copper plating layer formed by DPC technology. The first copper structure (150) and the second copper structure (160) may be sintered bodies of copper-containing paste formed by TPC technology.

[0081] Hereinafter, the first base copper layer (130), the first copper structure (150), and the second copper structure (160) formed using TPC (thick printed copper) technology will be described in detail.

[0082] Referring to FIG. 5b, the first base copper layer (130) may be a sintered body of a copper-containing paste formed by TPC technology. The first copper structure (150) and the second copper structure (160) may be sintered bodies of a copper-containing paste formed by TPC technology.

[0083] The first base copper layer (130), the first copper structure (150), and the second copper structure (160) can be formed by commonly printing a copper-containing paste to form a paste layer and pressing and sintering the paste layer.

[0084] The first base copper layer (130) may be disposed on a portion of the ceramic layer (120). The first base copper layer (130) may be formed using the TPC technology described above.

[0085] The first base copper layer (130) may be composed of a plurality of layers. The first base copper layer (130) may include, for example, at least one of a bonding copper layer (131), a laminated copper layer (132), and a surface copper layer (133).

[0086] The thickness of the first base copper layer (130) can be varied by controlling the thickness of the relatively thick laminated copper layer (132). The laminated copper layer (132) can have a greater thickness than the bonded copper layer (131) and the surface copper layer (133). The bonded copper layer (131) and the surface copper layer (133) can have the same thickness or different thicknesses. The bonded copper layer (131) can have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 20 μm. The laminated copper layer (132) can have a thickness in the range of, for example, 100 μm to 1000 μm. The surface copper layer (133) can have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 30 μm.

[0087] The bonding copper layer (131) may be disposed on at least a portion of the ceramic layer (120). The laminated copper layer (132) may be disposed on the bonding copper layer (131). The surface copper layer (133) may be disposed on the laminated copper layer (132). However, this is exemplary and the technical idea of ​​the present invention is not limited thereto. For example, when the thickness of the first base copper layer (130) is not thick, the first base copper layer (130) may be configured to include the bonding copper layer (131) and the surface copper layer (133), excluding the laminated copper layer (132). Alternatively, when the power semiconductor element is not bonded on the base copper layer (140), the first base copper layer (130) may be configured to include the bonding copper layer (131) and the laminated copper layer (132), excluding the surface copper layer (133).

[0088] The bonding copper layer (131) can be formed by forming a bonding paste layer by printing a copper-containing bonding paste on the ceramic layer (120) using a screen printing method or the like, drying to remove the solvent, pressing the dried bonding paste layer, and then heating to sinter it.

[0089] The laminated copper layer (132) can be formed by printing a copper-containing laminated paste on the bonding copper layer (131) using a screen printing method or the like to form a laminated paste layer, then drying to remove the solvent, pressing the dried laminated paste layer, and then heating to sinter it.

[0090] The surface copper layer (133) can be formed by printing a copper-containing surface paste on the laminated copper layer (132) using a screen printing method or the like to form a surface paste layer, then drying to remove the solvent, pressing the dried surface paste layer, and then heating to sinter it.

[0091] By the above pressing, the internal pores of the bonding paste layer, the laminated paste layer, and the surface paste layer can be reduced and the uniformity of height can be secured.

[0092] The above-described printing, pressing, and sintering steps may be performed repeatedly. For example, after forming one paste layer in one cycle of the printing and pressing, the printing and pressing may be performed again to form a subsequent paste layer on the previously formed paste layer, and this may be repeated to form a plurality of paste layers. The plurality of paste layers may be sintered together. In addition, by repeatedly performing the sintering, the copper layer may be formed. That is, sintering may be performed one or more times for one copper layer constituting the first base copper layer (130). The number of times of the printing, pressing, and sintering may vary.

[0093] Below, the materials constituting the above-described paste forming the first base copper layer (130) will be described.

[0094] The copper-containing bonding paste may include, for example, copper particles, glass frit, inorganic particles, copper oxide particles, a solvent, and a binder.

[0095] The copper-containing laminate paste may include, for example, copper particles, inorganic particles, a solvent, and a binder. Compared to the copper-containing bonding paste, the copper-containing laminate paste may not include glass frit and copper oxide particles.

[0096] The copper-containing surface paste may include copper particles, copper oxide particles, a solvent, and a binder. Compared to the copper-containing bonding paste, the copper-containing surface paste may not include glass frit and inorganic particles.

[0097] The above glass frit is a sintering aid that helps sintering of copper (Cu) particles and can provide better bonding between the ceramic layer (120) and the bonding copper layer (131).

[0098] The above inorganic particles may include powder of at least one of Al2O3, CaO, and ZrO2. The above inorganic particles may function to reduce the shrinkage rate of the paste. For reference, the shrinkage rate can be measured by printing the paste into a disk shape, drying and sintering it, and comparing the diameter of the disk after drying and after sintering.

[0099] The above copper oxide particles may include at least one of CuO and Cu2O, and may perform a function of improving bonding properties with the components to be bonded. The above copper oxide particles may form a process liquid phase during the sintering process. For example, when the ceramic layer (120) includes alumina (Al2O3), the copper oxide may react with alumina to form CuAlO2, CuAl2O4, etc., thereby improving bonding properties.

[0100] The above copper particles may be composed of copper and may be a main component constituting the first base copper layer (130). The copper particles may include fine copper particles having an average particle diameter in the range of 1 μm to 10 μm and may be included in an amount of 60 wt% to 95 wt% of the paste.

[0101] The shrinkage rate of the copper-containing laminate paste may be higher than the shrinkage rate of the copper-containing bonding paste. The shrinkage rate of the copper-containing surface paste may be higher than the shrinkage rate of the copper-containing bonding paste and the shrinkage rate of the copper-containing bonding paste. The shrinkage rate of the copper-containing bonding paste may be, for example, 0% to 3%. The shrinkage rate of the copper-containing laminate paste may be, for example, 3% to 9%. The shrinkage rate of the copper-containing surface paste may be, for example, 10% to 15%.

[0102] The copper-containing bonding paste, the copper-containing laminate paste, and the copper-containing surface paste can change the types and contents of glass frit, inorganic particles, copper oxide particles, copper particles, solvent, and binder in order to achieve a desired thermal expansion coefficient and shrinkage rate.

[0103] The description of the composition and paste for the first base copper layer (130) described above can be equally applied to the second base copper layer (140).

[0104] The first copper structure (150) may be placed on a portion of the first base copper layer (130). The first copper structure (150) may be placed on a portion of the first base copper layer (130) to reduce the difference in thermal expansion coefficient with respect to the power semiconductor element mounted thereon, for example, 5 x 10 -6 / ℃ to 20 x 10 -6 / ℃ can have a coefficient of thermal expansion in the range.

[0105] The first copper structure (150) may be a porous structure having pores within it. The first copper structure (150) may have a differential porosity. This means that the first copper structure (150) includes a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first base copper layer (130).

[0106] For example, the porosity of the first copper structure (150) may decrease from the lower side relatively adjacent to the first base copper layer (130) toward the upper side.

[0107] For example, the first copper structure (150) may be composed of a plurality of layers and may include a first base portion (151) and a first surface portion (152) disposed on the first base portion (151) and having a lower porosity than the first base portion (151). The first base portion (151) may have a porosity in a range of, for example, more than 5% by volume and less than or equal to 20% by volume. The first surface portion (152) may have a porosity in a range of, for example, more than 0% by volume and less than or equal to 5% by volume.

[0108] Since the first base (151) has a relatively high porosity, the pores perform a buffer function against thermal shock, thereby reducing thermal stress and increasing resistance to thermal fatigue destruction due to thermal stress under repeated thermal history.

[0109] On the other hand, since the first surface portion (152) has a relatively low porosity, it can have a smooth surface, and thus the bonding of the power semiconductor element mounted thereon can be improved. If the first surface portion (152) has a high porosity, void defects may remain on the bonding surface due to the pores, which may result in poor bonding of the power semiconductor element. Therefore, it is preferable to control the first surface portion (152) so that there are no pores or the porosity is low.

[0110] To control this porosity, the particle size and fraction of copper particles included in the paste can be controlled. If the particle size of the copper particles is large or the fraction is low, the porosity can increase, and if the particle size of the copper particles is small or the fraction is large, the porosity can decrease.

[0111] The first paste forming the first base portion (151) may include copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm. The second paste forming the first surface portion (152) may include copper particles having an average particle diameter in a range of 100 nm to 3 μm. That is, the average particle diameter of the copper particles included in the second paste may be smaller than the average particle diameter of the copper particles included in the first paste. Due to this difference in the average particle diameter of the copper particles, the first surface portion (152) may have a denser microstructure and a lower porosity than the first base portion (151).

[0112] The first copper structure (150) may have an overall thickness in the range of, for example, 100 μm to 2000 μm. The first base portion (151) may have a greater thickness than the first surface portion (152). The first base portion (151) may have a thickness in the range of, for example, 100 μm to 1900 μm. The first surface portion (152) may have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 20 μm.

[0113] The first copper structure (150) can be formed using the TPC technology described above. The first copper structure (150) can be formed using a copper-containing paste including copper particles, inorganic particles, a solvent, and a binder. The copper-containing paste may further include copper oxide particles. The first copper structure (150) can be formed by printing the copper-containing paste using a screen printing method or the like to form a paste layer, then drying to remove the solvent, pressing the dried paste layer, and then heating to sinter it.

[0114] The above-described printing, pressing, and sintering steps may be performed repeatedly. For example, after forming one paste layer in one cycle of the printing and pressing, the printing and pressing may be performed again to form one more subsequent paste layer on the previously formed paste layer, and this may be repeated a plurality of times to form a plurality of paste layers. The plurality of paste layers may be sintered together. In addition, by repeatedly performing the sintering, the copper layer may be formed. That is, sintering may be performed one or more times for one copper layer constituting the first copper structure (150). The number of times of the printing, pressing, and sintering may vary.

[0115] The second copper structure (160) may be disposed on at least a portion of the first copper structure (150). The second copper structure (160) may be formed using the TPC technology described above. The second copper structure (160) may be formed to reduce the difference in thermal expansion coefficient with respect to the power semiconductor element mounted thereon, for example, by 5 x 10 -6 / ℃ to 20 x 10 -6 / ℃ can have a coefficient of thermal expansion in the range.

[0116] The second copper structure (160) may be a porous structure having pores within it. The second copper structure (160) may have a differential porosity. This means that the second copper structure (160) includes a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first copper structure (150).

[0117] For example, the porosity of the second copper structure (160) may decrease from the lower side relatively adjacent to the first copper structure (150) toward the upper side.

[0118] For example, the second copper structure (160) may be composed of a plurality of layers and may include a second base portion (161) and a second surface portion (162) disposed on the second base portion (161) and having a lower porosity than the second base portion (161). The second base portion (161) may have a porosity in a range of, for example, more than 5% by volume and less than or equal to 20% by volume. The second surface portion (162) may have a porosity in a range of, for example, more than 0% by volume and less than or equal to 5% by volume.

[0119] The first paste forming the second base portion (161) may include copper particles having an average particle diameter in the range of more than 3 μm and less than or equal to 10 μm. The second paste forming the second surface portion (162) may include copper particles having an average particle diameter in the range of 100 nm to 3 μm.

[0120] The second copper structure (160) may have an overall thickness in the range of, for example, 100 μm to 2000 μm. The second base portion (161) may have a greater thickness than the second surface portion (162). The second base portion (161) may have a thickness in the range of, for example, 100 μm to 1900 μm. The second surface portion (162) may have a thickness in the range of, for example, 1 μm to 100 μm, for example, about 20 μm.

[0121] The second copper structure (160) can be formed using the TPC technology described above. The second copper structure (160) can be formed using a copper-containing paste including copper particles, inorganic particles, a solvent, and a binder.

[0122] The second base portion (161) may be identical or similar to the first base portion (151), and the second surface portion (162) may be identical or similar to the first surface portion (152).

[0123] However, this is exemplary, and the technical idea of ​​the present invention also includes cases where the second copper structure (160) has a different structure than the first copper structure (150), has a different constituent material, or is formed by a different manufacturing method.

[0124] FIG. 6 is a photograph showing the microstructure of a copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0125] Referring to Fig. 6, the internal pores of the first base portion (151) and the first surface portion (152) of the first copper structure (150) are shown. Compared to the first base portion (151), the first surface portion (152) has a low porosity, and the size of each pore is also small. That is, the first surface portion (152) has a dense microstructure.

[0126] When the porosity was 0%, it exhibited a high thermal stress of 220 MPa, whereas when the porosity was 7.7%, it exhibited a thermal stress of 136 MPa, and when the porosity was 17.2%, it exhibited a thermal stress of 114 MPa. In other words, it can be seen that as the porosity increases, the thermal stress decreases. In addition, when the porosity was 7.7%, it exhibited thermal fatigue failure characteristics of 1000 cycles, and when the porosity was 17.2%, it exhibited improved thermal fatigue failure characteristics of 2000 cycles. In other words, it can be seen that as the porosity increases, the resistance to thermal fatigue failure improves.

[0127] The Mo-Cu spacer according to the prior art is a metalworking material that substantially does not contain pores inside and has a porosity of approximately 0%, thereby exhibiting high thermal stress and low thermal fatigue fracture characteristics. In contrast, the copper structure according to the present invention comprises a lower layer having a high porosity, thereby providing low thermal stress and improved resistance to thermal fatigue fracture, and further comprises an upper layer having a low porosity, thereby preventing bonding defects in power semiconductor devices.

[0128] FIGS. 7a and 7b are cross-sectional views and photographs showing a pyramid-shaped copper structure of a ceramic circuit board according to one embodiment of the present invention.

[0129] Referring to FIG. 7a, the first copper structure (150) may have a truncated pyramid shape in which the planar area of ​​the upper side is smaller than that of the lower side as the planar area decreases from the lower side relatively adjacent to the first base copper layer (130) toward the upper side. That is, the first copper structure (150) may have a trapezoidal vertical cross-sectional shape. In addition, the first copper structure (150) may have a horizontal cross-sectional shape that is a polygon such as a triangle, a square, a pentagon, a hexagon, or a circle such as a square, an ellipse, a semicircle, or the like.

[0130] Since the first copper structure (150) has a pyramidal shape, it can stably mount a power semiconductor element. In addition, it can prevent an undercut phenomenon formed by etching.

[0131] These pyramidal shapes can be formed as follows.

[0132] After printing and pressing the first layer (151_1) of the first base portion (151) and then sintering, it can naturally shrink due to volume reduction caused by evaporation of the solvent and sintering of the copper particles. At this time, the lower side of the first layer (151_1) is attached to the first base copper layer (130), so the shrinkage is small, whereas the upper side shrinks greatly. Then, when the second layer (151_2) is printed, the area of ​​the upper side that has shrunk corresponds to the area of ​​the upper side, so the lower area of ​​the second layer (150_2) is reduced. When the second layer (151_2) is sintered, the upper side shrinks more than the lower side, similar to the first layer (150_1). In this manner, a plurality of layers having an upper side having a smaller area than the lower side are formed. Next, a first surface portion (152) having an upper side having a smaller area than a lower side is formed on the n-th layer (150_n). Accordingly, a first copper structure (150) having a pyramidal shape can be formed.

[0133] In addition, in the step of forming the first copper structure (150), the application area of ​​the paste applied during printing can be reduced from the bottom to the top using TPC technology to implement the pyramidal shape. When forming a subsequent layer based on the first layer formed first, for example, a second layer (151_2) based on the first layer (151_1), the application area can be reduced to 1 area% to 10 area%, for example, 3 area% to 5 area%.

[0134] Additionally, similar to the first copper structure (150), the second copper structure (160) may have a pyramidal shape in which the planar area decreases from the lower side relatively adjacent to the first copper structure (150) toward the upper side.

[0135] Referring to Fig. 7b, photographs of a copper structure in the shape of a pyramid are shown.

[0136] Hereinafter, a method for manufacturing a ceramic circuit board according to one embodiment of the present invention will be described.

[0137] Figure 8 is a flowchart illustrating a method for manufacturing a ceramic circuit board according to one embodiment of the present invention.

[0138] Referring to FIG. 8, a method for manufacturing a ceramic circuit board (S100) may include a step of providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer (S110); a step of forming a first copper structure on a portion of the ceramic substrate (S120); and a step of forming one or more second copper structures on at least a portion of the first copper structure (S130).

[0139] In addition, the method for manufacturing a ceramic circuit board (S100) may further include a step (S140) of locally forming an element attachment layer on the surface of at least one of the first copper structure and the second copper structure. The element attachment layer may have a flat surface or may have a trench.

[0140] In addition, the method for manufacturing a ceramic circuit board (S100) may further include a step (S150) of blasting the surface of the element attachment layer. In addition, the blasting step may also be performed on the surface of the base copper layer, the surface of the first copper structure, or the surface of the second copper structure.

[0141] The step of providing the ceramic substrate (S110) may be performed by providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer. In addition, the ceramic substrate may further include a second base copper layer disposed on a second surface of the ceramic layer opposite to the first surface.

[0142] Hereinafter, the base copper layer should be understood to mean the first base copper layer and the second base copper layer.

[0143] In the step (S110) of providing the above ceramic substrate, the first base copper layer may be a TPC copper layer, a DBC copper layer, a DPC copper layer, or an AMB copper layer.

[0144] The step (S120) of forming the first copper structure may include a printing step of forming a paste layer by printing a copper-containing paste on a portion of the first base copper layer; a pressing step of pressing the paste layer; and a sintering step of forming the first copper structure by sintering the paste layer.

[0145] In the above printing step, a copper-containing paste may be screen-printed onto the ceramic layer to form a paste layer. The printing step may include a drying step that is intentionally performed to remove all or part of the solvent contained in the paste layer by maintaining the temperature in the air at a range of 10°C to 100°C. Alternatively, the drying may be performed unintentionally through natural drying.

[0146] In the above pressing step, the paste layer can be pressed to form a uniform thickness. The boundary of the paste layer may have a higher viscosity than the center due to a reduced flow rate of the copper-containing paste, and may be formed to a thicker thickness. By pressing the paste layer, this thickness variation can be reduced. In addition, internal pores in the paste layer can be eliminated or reduced.

[0147] In the above sintering step, the copper particles contained in the paste layer can be sintered. The sintering step can be performed in an inert atmosphere, such as a nitrogen atmosphere or an argon atmosphere, or can be performed in an air atmosphere. The sintering step can be performed in a continuous heat treatment furnace, such as a muffle-type heat treatment furnace, or in a batch-type heat treatment furnace, such as a box oven.

[0148] The step (S130) of forming the second copper structure may include a printing step of forming a paste layer by printing a copper-containing paste on a portion of the first copper structure; a pressing step of pressing the paste layer; and a sintering step of forming the second copper structure by sintering the paste layer.

[0149] At least one of the sintering step for forming the first copper structure and the sintering step for forming the second copper structure may be performed at a temperature of, for example, less than 900°C, and may be performed at a temperature in the range of, for example, 500°C to 800°C for 10 minutes to 120 minutes.

[0150] For example, when the ceramic substrate includes an active metal brazing layer, it is important to prevent the active metal brazing layer from melting during the sintering step of forming the first copper structure or the second copper structure, and therefore, the sintering temperature is preferably lower than the melting temperature of the active metal brazing layer, and is preferably lower, for example, in the range of 50°C to 100°C.

[0151] In addition, the sintering may be performed by including a bake out step at a temperature ranging from 300°C to 500°C by supplying a small amount of water vapor or oxygen in a nitrogen atmosphere to remove the binder contained in the paste layer, and a liquid phase sintering step of the copper particles contained in the paste layer. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto, and the bake out step may be omitted.

[0152] The step (S120) of forming the first copper structure may be performed so that the first copper structure has a differential porosity. The first copper structure may include a region on the upper side having a lower porosity than a region on the lower side that is relatively adjacent to the first base copper layer.

[0153] The step of forming the first copper structure (S120) may include: forming a first base portion; and forming a first surface portion having a lower porosity than the first base portion on the first base portion. The step of forming the first base portion may be performed using a paste including copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm. The step of forming the first surface portion may be performed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 μm on the first base portion. The first base portion may have a porosity in a range of more than 5 vol% and less than or equal to 20 vol%. The first surface portion may have a porosity in a range of more than 0 vol% and less than or equal to 5 vol%.

[0154] The step (S130) of forming the second copper structure may be performed so that the second copper structure has a differential porosity. The second copper structure may include a region on the upper side having a lower porosity than a region on the lower side relatively adjacent to the first copper structure.

[0155] The step of forming the second copper structure (S130) may include: forming a second base portion; and forming a second surface portion having a lower porosity than the second base portion on the second base portion. The step of forming the second base portion may be performed using a paste including copper particles having an average particle diameter in a range of more than 3 μm and less than or equal to 10 μm. The step of forming the second surface portion may be performed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 μm on the second base portion. The second base portion may have a porosity in a range of more than 5 vol% and less than or equal to 20 vol%. The second surface portion may have a porosity in a range of more than 0 vol% and less than or equal to 5 vol%.

[0156] The printing step, the pressing step, and the sintering step for forming the first copper structure and the second copper structure may be performed repeatedly. For example, after the printing step and the pressing step are performed in one cycle to form one paste layer, the printing step and the pressing step are performed again to further form a subsequent paste layer on the previously formed paste layer, thereby forming a plurality of paste layers. The plurality of paste layers may be sintered together. In addition, by repeatedly performing the sintering step, the copper layer may be formed. That is, the sintering step may be performed one or more times for one copper layer constituting the first copper structure and the second copper structure. The number of times of the printing step, the pressing step, and the sintering step may vary.

[0157] In addition, if a paste layer is formed on only one side of the ceramic layer and sintered, the ceramic layer may warp during sintering. To prevent this, paste layers may be formed on both sides of the ceramic layer and sintered together to form the first base copper layer and the second base copper layer simultaneously. In addition, the second base copper layer may be additionally formed simultaneously with the first copper structure and the second copper structure. It is preferable that the paste layers formed on both sides of the ceramic layer and sintered simultaneously have the same volume, or the volume ratio may be, for example, 90% to 100%. The volume ratio may be a percentage obtained by dividing the volume of the paste layer having a small volume by the volume of the paste layer having a large volume. In addition, the volume may be calculated from the weight of the paste layer.

[0158] The step (S120) of forming the first copper structure can cause the first copper structure to have a pyramidal shape by reducing the application area of ​​the copper-containing paste from the lower side relatively adjacent to the first base copper layer toward the upper side when performing the printing step.

[0159] In the step (S130) of forming the second copper structure, when performing the printing step, the application area of ​​the copper-containing paste is reduced from the lower side relatively adjacent to the first copper structure toward the upper side, thereby allowing the second copper structure to have a pyramidal shape.

[0160] The step (S140) of forming the element attachment layer may include a printing step of locally printing a silver-containing paste on at least one surface of the first copper structure and the second copper structure to form a silver-containing paste layer; a pressing step of pressing the silver-containing paste layer; and a sintering step of sintering the silver-containing paste layer at a temperature in the range of 500°C to 700°C to form the element attachment layer. The sintering step may be a step in which the silver-containing paste is metallized.

[0161] In the above printing step, a silver-containing paste layer may be formed by locally screen-printing a silver-containing paste on at least one surface of the first copper structure and the second copper structure. The printing step may include a drying step that is intentionally performed by maintaining a temperature in the air range of 10°C to 100°C to remove all or part of the solvent contained in the silver-containing paste layer. Alternatively, the drying may be performed unintentionally through natural drying.

[0162] In the above pressing step, the silver-containing paste layer can be pressed to form a uniform thickness. The boundary of the silver-containing paste layer may have a higher viscosity than the center due to a reduced flow rate of the copper-containing paste, and may be formed to a thicker thickness. By pressing the silver-containing paste layer, such thickness variation can be reduced. In addition, internal pores of the silver-containing paste layer can be eliminated or reduced.

[0163] The sintering step may be performed at a temperature of, for example, less than 900°C, and may be performed at a temperature in the range of, for example, 500°C to 700°C for 10 to 120 minutes. The sintering step may be performed in an inert atmosphere, such as a nitrogen atmosphere or an argon atmosphere, or may be performed in an air atmosphere.

[0164] The silver-containing paste may include silver or a silver alloy. Conventionally, sintering of the silver paste was performed in an oxidizing atmosphere. However, when sintering in an oxidizing atmosphere, the copper constituting the first copper structure and the second copper structure is oxidized and loses its metallic properties. On the other hand, when sintering in a nitrogen atmosphere to prevent such copper oxidation, the silver may lose its metallic properties. On the other hand, when a silver paste composed of fine silver particles is used, the silver can maintain its metallic properties even when sintered in a nitrogen atmosphere. Therefore, the silver-containing paste may include silver particles having a particle size ranging from 100 nm to 10 μm, for example.

[0165] In the step (S140) of forming the above-mentioned element attachment layer, the printing step, the pressing step, and the sintering step for forming the above-mentioned element attachment layer may be performed repeatedly. This repetition is as described above.

[0166] For reference, in the past, a silver plating layer was formed on a molybdenum-copper (Mo-Cu) spacer on a ceramic circuit board used in a double-sided cooling power module, and then the spacer was attached to the ceramic circuit board by sintering the silver plating layer. In this case, since the spacers must be attached individually, the process is complicated and may take a lot of time. In addition, the ceramic circuit board according to the present invention has an integral structure in which the first copper structure and the second copper structure performing the spacer function are formed on the ceramic substrate. When silver plating is performed on the ceramic circuit board, a silver plating layer is formed over the entire surface, and is not limited to the first copper structure and the second copper structure. When an EMC molding layer is formed in a subsequent process, layer separation occurs in the area where the silver plating layer and the EMC molding layer come into contact, thereby reducing reliability. In addition, a silver layer can be formed limited to the first copper structure and the second copper structure using a lithography process commonly used in semiconductor processes, but the photoresist process and the masking process require expensive equipment and have high process costs, and furthermore, since protrusions are formed by the first copper structure and the second copper structure, it may be difficult to apply the photoresist process.

[0167] The above blasting treatment step (S150) may be performed by blasting the surface of at least one of the base copper layer, the first copper structure, the second copper structure, and the element attachment layer with ceramic particles such as sand.

[0168] The element attachment layer is formed on the first copper structure and the second copper structure, and a power semiconductor element is mounted. The process of sintering the base copper layer, the first copper structure, the second copper structure, and the element attachment layer, etc., is heat-treated at a high temperature in the air, so impurities such as a copper oxide layer or a silver oxide layer may be formed on the surface. In addition, even when the sintering is performed in an inert atmosphere, oxidation by oxygen may occur. The copper oxide layer or the silver oxide layer may reduce the adhesion of the element attachment layer to the first copper structure and the second copper structure, and may also reduce the adhesion of the power semiconductor element to the element attachment layer. Therefore, after forming the first copper structure and the second copper structure, the copper oxide layer may be removed by blasting fine-diameter ceramic particles onto the surfaces of the first copper structure and the second copper structure. In addition, after forming the element attachment layer, the silver oxide layer can be removed by blasting fine-diameter ceramic particles onto the surface of the element attachment layer. The blasting may be referred to as sandblasting. In addition, the case of blasting the base copper layer is also included in the technical concept of the present invention.

[0169] Figure 9 is an ultrasonic inspection result showing whether a defect occurs depending on the sintering temperature of a ceramic circuit board according to an embodiment of the present invention.

[0170] Referring to Fig. 9, when the sintering of the copper structure was performed at 900°C to form a ceramic circuit board, an adhesion defect occurred between the ceramic layer and the base copper layer, as indicated by the arrow. It is analyzed that the adhesion defect occurred due to exposure to a high temperature of 900°C during the sintering process of the copper structure, and the occurrence became more pronounced as this high-temperature exposure was repeated. In particular, when the ceramic circuit board includes an active metal brazing layer, since the sintering temperature of 900°C approaches or exceeds the melting point of the active metal brazing layer, the adhesion defect occurs more as the active metal brazing layer melts.

[0171] On the other hand, when the sintering of the copper structures was performed at 600°C, the above-mentioned adhesion defect did not occur. Therefore, the sintering temperature of the base copper layer, the first copper structure, and the second copper structure is preferably lower than 900°C, and for example, a temperature in the range of 500°C to 800°C is preferable.

[0172] FIG. 10 is a photograph showing the surface state of a copper structure of a ceramic circuit board before and after blasting treatment according to an embodiment of the present invention.

[0173] Referring to Fig. 10, the surface condition of a copper structure before and after blasting is shown. When blasting is not performed, it can be seen that copper oxide exists on the surface of the copper structure, resulting in a rough surface. On the other hand, it can be seen that the copper oxide is removed by blasting, resulting in a smooth surface, and that the surface becomes even smoother as the number of blasting cycles increases. Therefore, after blasting, power semiconductor devices mounted on the copper structure can be more stably bonded.

[0174] FIG. 11 is a photograph showing the surface state of a ceramic circuit board's element attachment layer before and after blasting treatment according to one embodiment of the present invention.

[0175] Referring to Fig. 11, the surface condition of the element attachment layer composed of silver before and after blasting treatment is shown. In the case of before blasting treatment (No blasting), the surface of the element attachment layer composed of silver is not plated, but is formed by printing, drying, pressing, and firing a paste formed by mixing silver powder, so that the particle boundaries of the silver powder appear distinct. On the other hand, in the case of after blasting treatment (Blasting treated), it can be seen that most of the particle boundaries of the silver powder are removed by blasting.

[0176] FIG. 12 is a perspective view illustrating a pair of ceramic circuit boards for forming a double-sided cooling power module according to one embodiment of the present invention.

[0177] Referring to Fig. 12, a lower ceramic circuit board (100_D) and an upper ceramic circuit board (100_U) forming a double-sided cooling power module are illustrated. In Fig. 12, the component attachment layer is omitted.

[0178] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0179] The upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first copper structure (150_U), and an upper second copper structure (160_U). The upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0180] Figures 13 to 16 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.

[0181] Referring to FIG. 13, a double-sided cooling power module (10) may include a lower ceramic circuit board (100_D), an upper ceramic circuit board (100_U), a first power semiconductor element (20), a second power semiconductor element (30), and a mold layer (50).

[0182] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), a lower second copper structure (160_D), and a lower component attachment layer (170_D). The lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0183] The upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first copper structure (150_U), an upper second copper structure (160_U), and an upper component attachment layer (170_U). The upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0184] The lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U) can be placed facing each other.

[0185] A first power semiconductor element (20) and a second power semiconductor element (30) may be disposed between a lower ceramic circuit board (100_D) and an upper ceramic circuit board (100_U). The lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U) may perform a function of dissipating heat generated in the first power semiconductor element (20) and the second power semiconductor element (30) to the outside. For such heat dissipation, a heat dissipation structure (not shown) may be disposed on the outer surface of at least one of the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U).

[0186] The first power semiconductor element (20) and the second power semiconductor element (30) may be, for example, a GTO (gate turn-off thyristor) semiconductor element or an IGBT (insulated gate bipolar mode transistor) semiconductor element, and may perform an operation of converting power supplied from a power supply unit such as a battery into power for driving a motor through a switching operation and supplying the converted power. In addition, the first power semiconductor element (20) and the second power semiconductor element (30) may include electrode members formed on the upper or lower portions.

[0187] The first power semiconductor element (20) may be placed between the lower first copper structure (150_D) and the upper first copper structure (150_U). The first power semiconductor element (20) may be attached by the lower element attachment layer (170_D) and the upper element attachment layer (170_U). One side of the first power semiconductor element (20) may be attached to the lower first copper structure (150_D) by the lower element attachment layer (170_D), and the other side may be attached to the upper first copper structure (150_U) by the upper element attachment layer (170_U).

[0188] The second power semiconductor element (30) may be placed between the lower second copper structure (160_D) and the upper second copper structure (160_U). The second power semiconductor element (30) may be attached by the lower element attachment layer (170_D) and the upper element attachment layer (170_U). One side of the second power semiconductor element (30) may be attached to the lower second copper structure (160_D) by the lower element attachment layer (170_D), and the other side may be attached to the upper second copper structure (160_U) by the upper element attachment layer (170_U).

[0189] The second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20). Therefore, by further arranging a second copper structure (160) on the upper and lower sides of the second power semiconductor element (30), the thickness difference between the second power semiconductor element (30) and the first power semiconductor element (20) can be corrected.

[0190] The lower element attachment layer (170_D) and the upper element attachment layer (170_U) can be attached to the first power semiconductor element (20) and the second power semiconductor element (30) by heat treatment at a temperature of, for example, less than 900°C, for example, at a temperature in the range of 500°C to 700°C, for example, at about 600°C.

[0191] The mold layer (50) can fill the space between the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U). Accordingly, the first power semiconductor element (20) and the second power semiconductor element (30) can be covered by the mold layer (50). The mold layer (50) can insulate the first power semiconductor element (20) and the second power semiconductor element (30). The mold layer (50) can be composed of, for example, EMC (epoxy molding compound).

[0192] The mold layer (50) is in contact with the lower first base copper structure (130_D) and the upper first base copper structure (130_U) made of copper, and since copper and EMC have excellent affinity, peeling defects can be prevented. In addition, the mold layer (50) made of EMC does not contact the lower element attachment layer (170_D) and the upper element attachment layer (170_U) made of silver, or contacts them minimally at the level of side contact, and thus peeling defects of the mold layer (50) can be prevented.

[0193] At least one of the lower first copper structure (150_D), the upper first copper structure (150_U), the lower second copper structure (160_D) and the upper second copper structure (160_U) may have a differential porosity and include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D) or the upper first base copper layer (130_U).

[0194] The double-sided cooling power module (10) may have a symmetrical structure based on the first power semiconductor element (20) and the second power semiconductor element (30). That is, the lower first copper structure (150_D), the lower second copper structure (160_D), the upper first copper structure (150_U), and the upper second copper structure (160_U) may be arranged symmetrically. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto. For example, the lower first copper structure (150_D) and the upper first copper structure (150_U) may have different heights. In addition, the lower second copper structure (160_D) and the upper second copper structure (160_U) may have different heights.

[0195] Hereinafter, descriptions of components identical or similar to those in the embodiment of Fig. 13 will be omitted.

[0196] Referring to FIG. 14, a double-sided cooling power module (10a) may include a lower ceramic circuit board (100a_D), an upper ceramic circuit board (100a_U), a first power semiconductor element (20), a second power semiconductor element (30), and a mold layer (50).

[0197] The lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110a_D), a lower first copper structure (150_D), a lower second copper structure (160_D), and a lower component attachment layer (170_D). The lower ceramic substrate (110a_D) may include a lower ceramic layer (120_D), a lower first active metal brazing layer (125_D), a lower second active metal brazing layer (126_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0198] The upper ceramic circuit board (100a_U) may include an upper ceramic substrate (110a_U), an upper first copper structure (150_U), an upper second copper structure (160_U), and an upper component attachment layer (170_U). The upper ceramic substrate (110a_U) may include an upper ceramic layer (120_U), an upper first active metal brazing layer (125_U), an upper second active metal brazing layer (126_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).

[0199] The lower ceramic circuit board (100a_D) and the upper ceramic circuit board (100a_U) can be placed facing each other.

[0200] The first power semiconductor element (20) may be placed between the lower first copper structure (150_D) and the upper first copper structure (150_U). The second power semiconductor element (30) may be placed between the lower second copper structure (160_D) and the upper second copper structure (160_U). The second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20).

[0201] At least one of the lower first copper structure (150_D), the upper first copper structure (150_U), the lower second copper structure (160_D) and the upper second copper structure (160_U) may have a differential porosity and include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D) or the upper first base copper layer (130_U).

[0202] The double-sided cooling power module (10a) may have a symmetrical structure based on the first power semiconductor element (20) and the second power semiconductor element (30). That is, the lower first copper structure (150_D), the lower second copper structure (160_D), the upper first copper structure (150_U), and the upper second copper structure (160_U) may be symmetrically arranged. However, this is exemplary and the technical idea of ​​the present invention is not limited thereto. For example, the lower first copper structure (150_D) and the upper first copper structure (150_U) may have different heights. In addition, the lower second copper structure (160_D) and the upper second copper structure (160_U) may have different heights.

[0203] Compared with the double-sided cooling power module (10) of FIG. 13, the double-sided cooling power module (10a) of FIG. 14 has a difference in that it further includes a lower first active metal brazing layer (125_D) interposed between the lower ceramic layer (120_D) and the lower first base copper layer (130_D), a lower second active metal brazing layer (126_D) interposed between the lower ceramic layer (120_D) and the lower second base copper layer (140_D), an upper first active metal brazing layer (125_U) interposed between the upper ceramic layer (120_U) and the upper first base copper layer (130_U), and an upper second active metal brazing layer (126_U) interposed between the upper ceramic layer (120_U) and the upper second base copper layer (140_U).

[0204] Referring to FIG. 15, a double-sided cooling power module (10b) may include a lower ceramic circuit board (100_D), an upper ceramic board (110_U), a first power semiconductor element (20), a second power semiconductor element (30), and a mold layer (50).

[0205] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), a lower second copper structure (160_D), and a lower component attachment layer (170_D). The lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0206] The upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U). The upper ceramic substrate (110_U) may further include an upper device attachment layer (170_U) locally disposed on a portion of the surface of the upper first base copper layer (130_U).

[0207] The lower ceramic circuit board (100_D) and the upper ceramic board (110_U) can be placed facing each other.

[0208] The first power semiconductor element (20) may be disposed between the lower first copper structure (150_D) and the upper first base copper layer (130_U). The second power semiconductor element (30) may be disposed between the lower second copper structure (160_D) and the upper first base copper layer (130_U). The second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20).

[0209] At least one of the lower first copper structure (150_D) and the lower second copper structure (160_D) may have a differential porosity and may include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D).

[0210] Compared with the double-sided cooling power module (10) of Fig. 13, the double-sided cooling power module (10b) of Fig. 15 has a difference in that it includes an upper ceramic substrate (110_U) instead of an upper ceramic circuit substrate (100_U). That is, the double-sided cooling power module (10b) does not include an upper first copper structure (150_U) and an upper second copper structure (160_U). In addition, an upper element attachment layer (170_U) is locally disposed on a portion of the surface of the upper first base copper layer (130_U). Therefore, the double-sided cooling power module (10b) may have an asymmetrical structure with respect to the first power semiconductor element (20) and the second power semiconductor element (30).

[0211] Referring to FIG. 16, a double-sided cooling power module (10c) may include a lower ceramic circuit board (100a_D), an upper ceramic board (110a_U), a first power semiconductor element (20), a second power semiconductor element (30), and a mold layer (50).

[0212] The lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110a_D), a lower first copper structure (150_D), and a lower second copper structure (160_D). The lower ceramic substrate (110a_D) may include a lower ceramic layer (120_D), a lower first active metal brazing layer (125_D), a lower second active metal brazing layer (126_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).

[0213] The upper ceramic substrate (110a_U) may include an upper ceramic layer (120_U), an upper first active metal brazing layer (125_U), an upper second active metal brazing layer (126_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U). The upper ceramic substrate (110_U) may further include an upper device attachment layer (170_U) locally disposed on a portion of the surface of the upper first base copper layer (130_U).

[0214] The lower ceramic circuit board (100a_D) and the upper ceramic board (110a_U) can be placed facing each other.

[0215] The first power semiconductor element (20) may be disposed between the lower first copper structure (150_D) and the upper first base copper layer (130_U). The second power semiconductor element (30) may be disposed between the lower second copper structure (160_D) and the upper first base copper layer (130_U). The second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20).

[0216] At least one of the lower first copper structure (150_D) and the lower second copper structure (160_D) may have a differential porosity and may include a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer (130_D).

[0217] Compared with the double-sided cooling power module (10b) of FIG. 15, the double-sided cooling power module (10c) of FIG. 16 has a difference in that it further includes a lower first active metal brazing layer (125_D) interposed between the lower ceramic layer (120_D) and the lower first base copper layer (130_D), a lower second active metal brazing layer (126_D) interposed between the lower ceramic layer (120_D) and the lower second base copper layer (140_D), an upper first active metal brazing layer (125_U) interposed between the upper ceramic layer (120_U) and the upper first base copper layer (130_U), and an upper second active metal brazing layer (126_U) interposed between the upper ceramic layer (120_U) and the upper second base copper layer (140_U).

[0218] Compared with the double-sided cooling power module (10a) of Fig. 14, the double-sided cooling power module (10c) of Fig. 16 has a difference in that it includes an upper ceramic substrate (110a_U) instead of an upper ceramic circuit substrate (100a_U). That is, the double-sided cooling power module (10c) does not include an upper first copper structure (150_U) and an upper second copper structure (160_U). In addition, the upper element attachment layer (170_U) is locally disposed on a portion of the surface of the upper first base copper layer (130_U). Therefore, the double-sided cooling power module (10c) may have an asymmetrical structure with respect to the first power semiconductor element (20) and the second power semiconductor element (30).

[0219] According to one embodiment of the present invention, a method for manufacturing a double-sided cooling power module comprises the steps of: providing a lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; one or more lower second copper structures disposed on at least a portion of the lower first copper structure; and a lower device attachment layer disposed on a surface of at least one of the lower first copper structure and the lower second copper structure; mounting a first power semiconductor device on the lower first copper structure; mounting a second power semiconductor device having a smaller thickness than the first power semiconductor device on the lower second copper structure; providing an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer on the lower ceramic circuit board; an upper first copper structure disposed on a portion of the upper ceramic substrate; one or more upper second copper structures disposed on at least a portion of the upper first copper structure; And the step of arranging an upper ceramic circuit board including an upper element attachment layer disposed on at least one surface of the upper first copper structure and the upper second copper structure so as to face the lower ceramic circuit board; and the step of forming a mold layer that fills a space between the lower ceramic circuit board and the upper ceramic circuit board to cover the first power semiconductor element and the second power semiconductor element.

[0220] According to one embodiment of the present invention, a method for manufacturing a double-sided cooling power module comprises the steps of: providing a lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; one or more lower second copper structures disposed on at least a portion of the lower first copper structure; and a lower component attachment layer disposed on a surface of at least one of the lower first copper structure and the lower second copper structure; mounting a first power semiconductor device on the lower first copper structure; mounting a second power semiconductor device having a smaller thickness than the first power semiconductor device on the lower second copper structure; disposing an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer on the lower ceramic circuit board; and an upper component attachment layer disposed on a portion of the surface of the upper first base copper layer, the upper ceramic substrate facing the lower ceramic circuit board; and a step of forming a mold layer covering the first power semiconductor element and the second power semiconductor element by filling the space between the lower ceramic circuit substrate and the upper ceramic substrate.

[0221] At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure can be formed by printing, pressing, and sintering of a copper-containing paste at a temperature ranging from 500°C to 800°C.

[0222] The lower element attachment layer and the upper element attachment layer can be formed by printing, drying, pressing, and sintering of a silver-containing paste at a temperature ranging from 500°C to 700°C.

[0223] The surface of at least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure may be blasted. In addition, at least one of the surface of the lower element attachment layer and the surface of the upper element attachment layer may be blasted.

[0224] At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure may have a differential porosity, and may include a region on the upper side having a lower porosity than a lower side relatively adjacent to the upper first base copper layer or the lower first base copper layer.

[0225] It will be apparent to a person skilled in the art to which the technical idea of ​​the present invention pertains that the technical idea of ​​the present invention described above is not limited to the above-described embodiments and the attached drawings, and that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical idea of ​​the present invention.

Claims

1. A ceramic substrate comprising a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; A first copper structure disposed on a portion of the first base copper layer, formed by printing, pressing, and sintering a copper-containing paste, having a differential porosity, and including a region on the upper side having a lower porosity than the lower side relatively adjacent to the first base copper layer; and A device attachment layer locally disposed on the surface of the first copper structure and formed by printing, drying, pressing and sintering a silver-containing paste, Ceramic circuit board.

2. In paragraph 1, The above first copper structure is, The porosity decreases from the lower side relatively adjacent to the first base copper layer toward the upper side, Ceramic circuit board.

3. In paragraph 1, The above first copper structure is, First base; and A first surface portion disposed on the first base portion and having a lower porosity than the first base portion, Ceramic circuit board.

4. In paragraph 3, The above first base has a porosity in the range of more than 5% by volume and less than or equal to 20% by volume, The above first surface portion has a porosity in a range of more than 0 volume% and less than or equal to 5 volume%, Ceramic circuit board.

5. In paragraph 3, The above first base is formed using a paste containing copper particles having an average particle diameter in the range of more than 3 μm and less than 10 μm, The first surface portion is formed using a paste containing copper particles having an average particle diameter in the range of 100 nm to 3 μm. Ceramic circuit board.

6. In paragraph 1, A second copper structure is further included, which is disposed on at least a portion of the first copper structure, is formed by printing, pressing and sintering a copper-containing paste, has a differential porosity, and includes a region on the upper side having a lower porosity than the lower side relatively adjacent to the first copper structure. Ceramic circuit board.

7. In paragraph 6, Further comprising a device attachment layer locally disposed on the surface of the second copper structure; Ceramic circuit board.

8. In paragraph 6, The above second copper structure is, The porosity decreases from the lower side relatively adjacent to the first copper structure toward the upper side, Ceramic circuit board.

9. In paragraph 6, The above second copper structure is, Second base; and A second surface portion disposed on the second base portion and having a lower porosity than the second base portion, Ceramic circuit board.

10. In paragraph 9, The above second base has a porosity in the range of more than 5% by volume and less than or equal to 20% by volume, The second surface portion has a porosity in a range of more than 0 volume% and less than or equal to 5 volume%. Ceramic circuit board.

11. In paragraph 9, The second base is formed using a paste containing copper particles having an average particle diameter in the range of 3 μm to 10 μm, The second surface portion is formed using a paste containing copper particles having an average particle diameter in the range of 100 nm to 3 μm. Ceramic circuit board.

12. In paragraph 1, The above first base copper layer is, A TPC copper layer formed by printing, pressing and sintering a copper-containing paste on the above ceramic layer, A DBC copper layer formed by bonding copper foil on the above ceramic layer through a high-temperature oxidation process, After forming a seed layer on the above ceramic layer, a DPC copper layer formed by plating copper on the seed layer, Or, it is made of an AMB copper layer formed by a copper foil bonded using an active metal foil to the above ceramic layer. Ceramic circuit board.

13. In paragraph 1, The above first base copper layer is, Comprising at least one of a bonding copper layer, a laminated copper layer, and a surface copper layer, Ceramic circuit board.

14. In paragraph 13, The above bonding copper layer is formed using a copper-containing bonding paste including glass frit, inorganic particles, copper oxide particles, copper particles, a solvent, and a binder, The above laminated copper layer is formed using a copper-containing laminate paste including inorganic particles, copper particles, a solvent, and a binder, The above surface copper layer is formed using a copper-containing surface paste containing copper oxide particles, copper particles, a solvent, and a binder. Ceramic circuit board.

15. In paragraph 1, The above ceramic substrate, Further comprising a second base copper layer disposed on the second surface of the ceramic layer; Ceramic circuit board.

16. A step of providing a ceramic substrate comprising a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; A step of forming a first copper structure on a portion of the ceramic substrate; A step of forming one or more second copper structures on at least a portion of the first copper structure; and A step of locally forming an element attachment layer on the surface of at least one of the first copper structure and the second copper structure, The step of forming the above-mentioned element attachment layer is: A printing step of locally printing a silver-containing paste on the surface of at least one of the first copper structure and the second copper structure to form a silver-containing paste layer; A pressing step of pressing the silver-containing paste layer; and A sintering step comprising sintering the silver-containing paste layer at a temperature ranging from 500°C to 700°C to form the element attachment layer. Method for manufacturing ceramic circuit boards.

17. A lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; a lower second copper structure disposed on a portion of the lower first copper structure; and a lower component attachment layer locally disposed on a surface of at least one of the lower first copper structure and the lower second copper structure; An upper ceramic circuit board comprising: an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; an upper first copper structure disposed on a portion of the upper ceramic substrate; an upper second copper structure disposed on a portion of the upper first copper structure; and an upper device attachment layer locally disposed on a surface of at least one of the upper first copper structure and the upper second copper structure; A first semiconductor element disposed between the lower first copper structure and the upper first copper structure, and attached by the lower element attachment layer and the upper element attachment layer; A second semiconductor element disposed between the lower second copper structure and the upper second copper structure, attached by the lower element attachment layer and the upper element attachment layer, and having a smaller thickness than the first semiconductor element; and A mold layer covering the first semiconductor element and the second semiconductor element by filling the space between the lower ceramic circuit board and the upper ceramic circuit board; At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure and the upper second copper structure has a differential porosity and includes a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer or the upper first base copper layer. Double-sided cooled power module.

18. In paragraph 17, The lower ceramic substrate further includes a lower active metal brazing layer interposed between the lower ceramic layer and the lower first base copper layer, The upper ceramic substrate further comprises an upper active metal brazing layer interposed between the upper ceramic layer and the upper first base copper layer. Double-sided cooled power module.

19. A lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; a lower second copper structure disposed on a portion of the lower first copper structure; and a lower component attachment layer locally disposed on a surface of at least one of the lower first copper structure and the lower second copper structure; An upper ceramic substrate comprising an upper ceramic layer; an upper first base copper layer; and an upper device attachment layer locally disposed on a portion of the upper first base copper layer; A first semiconductor element disposed between the lower first copper structure and the upper first base copper layer, and attached by the lower element attachment layer and the upper element attachment layer; A second semiconductor element disposed between the lower second copper structure and the upper first base copper layer, attached by the lower element attachment layer and the upper element attachment layer, and having a smaller thickness than the first semiconductor element; and A mold layer covering the first semiconductor element and the second semiconductor element by filling the space between the lower ceramic circuit board and the upper ceramic substrate; At least one of the lower first copper structure and the lower second copper structure has a differential porosity and includes a region on the upper side having a lower porosity than the lower side relatively adjacent to the lower first base copper layer. Double-sided cooled power module.

20. In paragraph 19, The lower ceramic substrate includes a lower active metal brazing layer interposed between the lower ceramic layer and the lower first base copper layer, The upper ceramic substrate comprises an upper active metal brazing layer interposed between the upper ceramic layer and the upper first base copper layer. Double-sided cooled power module.

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