Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, the at least one of which comprises a pixel driving circuit, the pixel driving circuit at least comprising a compensation transistor (T2) made of an oxide and a driving transistor (T3) made of polycrystalline silicon, wherein a gate electrode of the compensation transistor (T2) is connected to a compensation scanning signal line (24), which is configured to control the turning-on and turning-off of the compensation transistor (T2); and a first electrode of the compensation transistor (T2) is arranged at the side of the compensation scanning signal line (24) close to the driving transistor (T3), and is connected to a gate electrode of the driving transistor (T3) by means of a first connecting electrode (51), and a second electrode of the compensation transistor (T2) is arranged at the side of the compensation scanning signal line (24) away from the driving transistor (T3), and is connected to a second electrode of the driving transistor (T3) by means of a second connecting electrode (52).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising multiple circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least an oxide compensation transistor and a polysilicon driving transistor, the gate electrode of the compensation transistor being connected to a compensation scanning signal line, and the compensation scanning signal line being configured to control the conduction and disconnection of the compensation transistor; the first electrode of the compensation transistor being arranged on a side of the compensation scanning signal line close to the driving transistor, and being connected to the gate electrode of the driving transistor through a first connecting electrode, the second electrode of the compensation transistor being arranged on a side of the compensation scanning signal line away from the driving transistor, and being connected to the second electrode of the driving transistor through a second connecting electrode.

[0006] In an exemplary embodiment, an orthographic projection of the first connection electrode on the plane of the display substrate does not overlap with an orthographic projection of the compensation scan signal line on the plane of the display substrate.

[0007] In an exemplary embodiment, the compensation transistor includes at least a compensation active layer, the first connecting electrode and the compensation active layer are both strip-shaped extending toward the driving transistor, and the extension length of the first connecting electrode is smaller than the extension length of the compensation active layer.

[0008] In an exemplary embodiment, the second connecting electrode includes at least a first sub-electrode and a second sub-electrode, the first end of the first sub-electrode is connected to the second electrode of the driving transistor, the second end of the first sub-electrode extends in a direction away from the driving transistor, the first end of the second sub-electrode is connected to the first sub-electrode, the second end of the second sub-electrode extends in the direction of the compensation transistor and then connected to the second electrode of the compensation transistor, the first connecting electrode is in the shape of a strip extending in the direction of the driving transistor, and the extension length of the first connecting electrode is smaller than the extension length of the first sub-electrode.

[0009] In an exemplary embodiment, at least one circuit unit further includes a first power line, which is connected to the pixel driving circuit, and the first power line is configured to provide a first power signal to the pixel driving circuit, and the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the first connecting electrode on the display substrate plane.

[0010] In an exemplary embodiment, the compensation transistor includes at least a compensation active layer, and an orthographic projection of the first power line on the display substrate plane at least partially overlaps with an orthographic projection of the compensation active layer on the display substrate plane.

[0011] In an exemplary embodiment, the pixel driving circuit further includes a polysilicon data writing transistor, a gate electrode of the data writing transistor being connected to the first scanning signal line, a first electrode of the data writing transistor being connected to the data signal line, and a second electrode of the data writing transistor being connected to the first electrode of the driving transistor; the first electrode of the data writing transistor being arranged on a side of the compensation scanning signal line away from the driving transistor, or the first electrode of the data writing transistor being arranged on a side of the compensation scanning signal line close to the driving transistor.

[0012] In an exemplary embodiment, the first scan signal line is disposed on a side of the compensation scan signal line away from the driving transistor.

[0013] In an exemplary embodiment, an orthographic projection of the first connecting electrode on the plane of the display substrate does not overlap with an orthographic projection of the first scan signal line on the plane of the display substrate.

[0014] In an exemplary embodiment, the compensation scan signal line is disposed on a side of the first scan signal line away from the driving transistor.

[0015] In an exemplary embodiment, an orthographic projection of the first connecting electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the first scan signal line on the plane of the display substrate.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a first initialization transistor and a second initialization transistor of polysilicon; a gate electrode of the first initialization transistor is connected to a third scanning signal line, a first electrode of the first initialization transistor is connected to the first initial signal line, and a second electrode of the first initialization transistor is connected to the second electrode of the driving transistor; a gate electrode of the second initialization transistor is connected to a second scanning signal line, a first electrode of the second initialization transistor is connected to the second initial signal line, and a second electrode of the second initialization transistor is connected to an anode of the light-emitting device; an orthographic projection of the second initialization signal line on the plane of the display substrate at least partially overlaps with an orthographic projection of the second scanning signal line on the plane of the display substrate.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a third initialization transistor of polysilicon, a gate electrode of the third initialization transistor being connected to the second scanning signal line, a first electrode of the third initialization transistor being connected to the third initial signal line, and a second electrode of the third initialization transistor being connected to the first electrode of the driving transistor; an orthographic projection of the third initial signal line on the plane of the display substrate at least partially overlaps with an orthographic projection of the third scanning signal line on the plane of the display substrate.

[0018] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a plurality of conductive layers sequentially arranged on a base, the first initial signal line and the second initial signal line are arranged in different conductive layers, and the second initial signal line and the third initial signal line are arranged in the same conductive layer.

[0019] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0020] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of circuit units, and the preparation method includes:

[0021] A pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit including at least an oxide compensation transistor and a polysilicon driving transistor, the gate electrode of the compensation transistor being connected to a compensation scanning signal line, the compensation scanning signal line being configured to control the on and off of the compensation transistor; a first electrode of the compensation transistor being arranged on a side of the compensation scanning signal line close to the driving transistor and being connected to the gate electrode of the driving transistor through a first connecting electrode, and a second electrode of the compensation transistor being arranged on a side of the compensation scanning signal line away from the driving transistor and being connected to the second electrode of the driving transistor through a second connecting electrode.

[0022] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0024] FIG1 is a schematic structural diagram of a display device;

[0025] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0026] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0027] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0028] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0029] FIG6 is a schematic diagram of a display substrate after a shielding layer pattern is formed thereon according to the present disclosure;

[0030] 7A and 7B are schematic diagrams of a display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0031] 8A and 8B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0032] 9A and 9B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0033] 10A and 10B are schematic diagrams of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0034] 11A and 11B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0035] FIG12 is a schematic diagram of a display substrate after a sixth insulating layer pattern is formed according to the present disclosure;

[0036] 13A and 13B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0037] FIG14 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure;

[0038] 15A and 15B are schematic diagrams of a display substrate after a fifth conductive layer pattern is formed thereon according to the present disclosure;

[0039] FIG16 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0040] FIG17 is a schematic diagram of another display substrate after forming a shielding layer pattern according to the present disclosure;

[0041] 18A and 18B are schematic diagrams of another display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0042] 19A and 19B are schematic diagrams of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0043] 20A and 20B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0044] 21A and 21B are schematic diagrams of another display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0045] 22A and 22B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0046] FIG23 is a schematic diagram of another display substrate after forming a sixth insulating layer pattern according to the present disclosure;

[0047] 24A and 24B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure.

[0048] Description of the accompanying drawings:

[0049] 11—first active layer; 12—second active layer; 13—third active layer;

[0050] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0051] 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line;

[0052] 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line;

[0053] 25—light-emitting signal line; 26—first electrode plate; 31—first initial signal line;

[0054] 32—shielding line; 33—second electrode plate; 34—opening;

[0055] 35—plate connecting strip; 42—second initial signal line; 43—third initial signal line;

[0056] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0057] 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode;

[0058] 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode;

[0059] 61—first power line; 62—data signal line; 63—anode connection electrode;

[0060] 91—first shielding electrode line; 92—second shielding electrode line; 93—shielding electrode;

[0061] 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer;

[0062] 104—Encapsulation structure layer. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0064] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0065] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0066] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0067] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0068] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0069] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0070] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0071] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0072] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0073] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0074] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0075] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to the data signal lines DATA1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines DATA1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to the scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit the scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission driver can generate emission signals to be supplied to the emission signal lines EM1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines EM1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0076] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0077] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0078] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0079] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0080] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG4 , the pixel driving circuit may include 8 transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor C. The pixel driving circuit is respectively connected to 10 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power line VDD).

[0081] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively; the third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fourth node N4 is further connected to the anode of the light emitting device EL.

[0082] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0083] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor. A gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is connected to the third node N3. The second transistor T2 may be referred to as a compensation transistor. A gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. A gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The fourth transistor T4 may be referred to as a data write transistor. A gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2. The fifth transistor T5 can be referred to as a first emission control transistor. A gate electrode of the fifth transistor T5 is connected to the emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. The sixth transistor T6 can be referred to as a second emission control transistor. A gate electrode of the sixth transistor T6 is connected to the emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. The seventh transistor T7 can be referred to as a second initialization transistor. A gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. The eighth transistor T8 can be referred to as a third initialization transistor. A gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0084] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked anode (first pole), an organic light-emitting layer and a cathode (second pole), or can be a QLED, including a stacked anode (first pole), a quantum dot light-emitting layer and a cathode (second pole).

[0085] In an exemplary embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, the second electrode of the light emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0086] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0087] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0088] In an exemplary embodiment, the second transistor T2 may be a metal oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low temperature polysilicon transistors.

[0089] In an exemplary embodiment, the operation process of the pixel driving circuit shown in FIG4 may include:

[0090] The first stage is called the reset stage of the second node N2 and the fourth node N4. The signal of the second scanning signal line S2 is a low level signal, and the signals of the first scanning signal line S1, the third scanning signal line S3, the fourth scanning signal line S4 and the light emitting signal line EM are high level signals.

[0091] The signal on the second scan signal line S2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The signal on the second initialization signal line INIT2 is supplied to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device EL and clearing any existing charge therein, setting the potential of the fourth node N4 to Vinit2. The signal on the third initialization signal line INIT3 is supplied to the second node N2, initializing (resetting) the second node N2 and clearing any existing charge therein, setting the potential of the second node N2 to Vinit3. During this phase, the third transistor T3 is turned on. The signal on the fourth scan signal line S4 is a high-level signal, turning on the second transistor T2. The signal on the second node N2 is supplied to the first node N1 and the third node N3, initializing them. The signals on the first scan signal line S1, the third scan signal line S3, and the emission signal line EM are high-level signals, turning off the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0092] The second stage is called the first node N1 reset stage. The signal of the third scan signal line S3 is a low level signal, and the signals of the first scan signal line S1, the second scan signal line S2, the fourth scan signal line S4 and the light emitting signal line EM are high level signals.

[0093] The signal on the third scan signal line S3 becomes a low-level signal, turning on the first transistor T1. Since the signal on the fourth scan signal line S4 is a high-level signal at this stage, the second transistor T2 is turned on. Therefore, the signal on the first initial signal line INIT1 is provided to the first node N1 via the third node N3, resetting the first node N1 to a potential of Vinit1. The signals on the first scan signal line S1, the second scan signal line S2, and the emission signal line EM are high-level signals, turning off the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0094] The third stage is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, and the signals of the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4 and the luminescence signal line EM are high level signals.

[0095] The signal on the first scan signal line S1 is a low-level signal, turning on the fourth transistor T4. Since the third transistor T3 is continuously turned on during this stage, the signal on the fourth scan signal line S4 is a high-level signal, turning on the second transistor T2. Therefore, the data voltage output by the data signal line DATA is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the capacitor C. The voltage at the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line DATA and Vth is the threshold voltage of the third transistor T3. The signals on the second scan signal line S2, the third scan signal line S3, and the emission signal line EM are high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0096] The fourth stage is called the continuous compensation stage. The signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4 and the light emitting signal line EM are high level signals.

[0097] The signal on the fourth scan signal line S4 is a high-level signal, the second transistor T2 is continuously turned on, the signals on the first scan signal line S1, the third scan signal line S3, the second scan signal line S2, and the light-emitting signal line EM are high-level signals, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Although the signal on the data signal line DATA stops being written, the second node N2 is still provided to the first node N1 through the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, thereby continuously compensating for the threshold voltage of the third transistor T3.

[0098] The fifth stage is called the second node N2 and the fourth node N4 point reset stage. The signals of the second scanning signal line S2 and the fourth scanning signal line S4 are low level signals, and the signals of the first scanning signal line S1, the third scanning signal line S3 and the light emitting signal line EM are high level signals.

[0099] The signals on the first scan signal line S1, the third scan signal line S3, and the light-emitting signal line EM are high-level signals, while the signal on the fourth scan signal line S4 is low-level. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all off. The signal on the second scan signal line S2 is low-level, and the seventh transistor T7 and the eighth transistor T8 are on. Since the third transistor T3 is continuously on during this stage, the signal on the third initial signal line INIT3 is written to the second node N2 and the third node N3, and the signal on the second initial signal line INIT2 is written to the fourth node N3. This resets the second node N2, the third node N3, and the fourth node N4, respectively. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. Resetting the second node N2, the third node N3, and the fourth node N4 can eliminate hysteresis caused by grayscale differences between adjacent pixels, reducing hysteresis deviation. It can also periodically reset the OLED anode, improving low-frequency flicker.

[0100] The sixth phase is called the light-emitting phase. The signals on the emission signal line EM and the fourth scan signal line S4 are low-level signals, while the signals on the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are high-level signals. The low-level signal on the emission signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device EL to emit light.

[0101] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0102] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0103] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0104] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0105] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0106] In an exemplary embodiment, the display substrate of the present disclosure may include multiple circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes at least an oxide compensation transistor and a polysilicon driving transistor, the gate electrode of the compensation transistor is connected to a compensation scanning signal line, and the compensation scanning signal line is configured to control the conduction and disconnection of the compensation transistor; the first electrode of the compensation transistor is arranged on a side of the compensation scanning signal line close to the driving transistor, and is connected to the gate electrode of the driving transistor through a first connecting electrode, and the second electrode of the compensation transistor is arranged on a side of the compensation scanning signal line away from the driving transistor, and is connected to the second electrode of the driving transistor through a second connecting electrode.

[0107] In an exemplary embodiment, an orthographic projection of the first connection electrode on the plane of the display substrate does not overlap with an orthographic projection of the compensation scan signal line on the plane of the display substrate.

[0108] In an exemplary embodiment, the compensation transistor includes at least a compensation active layer, the first connecting electrode and the compensation active layer are both strip-shaped extending toward the driving transistor, and the extension length of the first connecting electrode is smaller than the extension length of the compensation active layer.

[0109] In an exemplary embodiment, the second connecting electrode includes at least a first sub-electrode and a second sub-electrode, the first end of the first sub-electrode is connected to the second electrode of the driving transistor, the second end of the first sub-electrode extends in a direction away from the driving transistor, the first end of the second sub-electrode is connected to the first sub-electrode, the second end of the second sub-electrode extends in the direction of the compensation transistor and then connected to the second electrode of the compensation transistor, the first connecting electrode is in the shape of a strip extending in the direction of the driving transistor, and the extension length of the first connecting electrode is smaller than the extension length of the first sub-electrode.

[0110] In an exemplary embodiment, at least one circuit unit further includes a first power line, which is connected to the pixel driving circuit, and the first power line is configured to provide a first power signal to the pixel driving circuit, and the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the first connecting electrode on the display substrate plane.

[0111] In an exemplary embodiment, the compensation transistor includes at least a compensation active layer, and an orthographic projection of the first power line on the display substrate plane at least partially overlaps with an orthographic projection of the compensation active layer on the display substrate plane.

[0112] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, the display substrate may include a plurality of circuit units, which may form a plurality of unit rows and a plurality of unit columns. The plurality of circuit units in each unit row are sequentially arranged along a first direction X, and the plurality of unit rows are sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0113] In an exemplary embodiment, at least one circuit unit may include a pixel driving circuit, the pixel driving circuit includes at least a storage capacitor and a plurality of transistors, the storage capacitor may include at least a first plate and a second plate, and the plurality of transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, wherein the second transistor is an oxide transistor, and the first transistor, the third transistor to the eighth transistor are low-temperature polysilicon transistors.

[0114] In an exemplary embodiment, the first transistor T1 can serve as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line 23, a first electrode of the first transistor T1 is connected to the first initialization signal line 31, and a second electrode of the first transistor T1 is connected to the second electrode of the third transistor T3.

[0115] In an exemplary embodiment, the second transistor T2 can serve as a compensation transistor, the gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, the fourth scan signal line 24 can serve as a compensation scan signal line, the first electrode of the second transistor T2 is connected to the gate electrode of the third transistor T3, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3.

[0116] In an exemplary embodiment, the third transistor T3 may serve as a driving transistor, and the gate electrode of the third transistor T3 and the first plate of the storage capacitor may be an integrated structure connected to each other.

[0117] In an exemplary embodiment, the fourth transistor T4 can be used as a data writing transistor, the gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 62, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3.

[0118] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can serve as light-emitting control transistors, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are connected to the light-emitting signal line 25, the first electrode of the fifth transistor T5 is connected to the first power line 61, the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.

[0119] In an exemplary embodiment, the seventh transistor T7 can serve as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, a first electrode of the seventh transistor T7 is connected to the second initialization signal line 42, and a second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6.

[0120] In an exemplary embodiment, the eighth transistor T8 can serve as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line 22, a first electrode of the eighth transistor T8 is connected to the third initialization signal line 43, and a second electrode of the eighth transistor T8 is connected to the first electrode of the third transistor T3.

[0121] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 31, the second initial signal line 42 and the third initial signal line 43 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 61 and the data signal line 62 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0122] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0123] In an exemplary embodiment, the second transistor T2 of the oxide may include at least a gate electrode, a first electrode, and a second electrode. The fourth scan signal line 24 may serve as the gate electrode of the second transistor T2. The first electrode T2-1 of the second transistor may be located on a side of the fourth scan signal line 24 close to the gate electrode T3-g of the third transistor. The second electrode T2-2 of the second transistor may be located on a side of the fourth scan signal line 24 away from the gate electrode T3-g of the third transistor.

[0124] In example embodiments, the first electrode T2 - 1 of the second transistor may be connected to the gate electrode T3 - g of the third transistor through the first connection electrode 51 , and the second electrode T2 - 2 of the second transistor may be connected to the second electrode T3 - 2 of the third transistor through the second connection electrode 52 .

[0125] In an exemplary embodiment, the shape of the first connection electrode 51 can be a strip shape extending along the second direction Y (towards the third transistor T3), the first end of the first connection electrode 51 is connected to the first electrode T2-1 of the second transistor, and the second end of the first connection electrode 51 extends along the second direction Y and is connected to the gate electrode T3-g of the third transistor.

[0126] In an exemplary embodiment, the second connecting electrode 52 may include at least a first sub-electrode 52-1 and a second sub-electrode 52-2, the first end of the first sub-electrode 52-1 is connected to the second electrode T3-2 of the third transistor, the second end of the first sub-electrode 52-1 extends in the opposite direction of the second direction Y (towards the direction away from the third transistor T3), the first end of the second sub-electrode 52-2 is connected to the first sub-electrode 52-1, and the second end of the second sub-electrode 52-2 extends along the first direction X (towards the direction of the second transistor T2) and is connected to the second electrode T2-2 of the second transistor.

[0127] In an exemplary embodiment, an extension length of the first connection electrode 51 may be smaller than an extension length of the first sub-electrode 52 - 1 , where the extension length refers to a length in the second direction Y.

[0128] In an exemplary embodiment, the second transistor T2 may further include a second active layer 12, which may serve as a compensation active layer. The second active layer 12 may be shaped like a strip extending along the second direction Y (the direction toward the third transistor T3), and the extension length of the first connection electrode 51 may be less than the extension length of the second active layer 12.

[0129] In an exemplary embodiment, the first connection electrode 51 may be located on a side of the fourth scan signal line 24 close to the gate electrode T3-g of the third transistor, and the orthographic projection of the first connection electrode 51 on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line 24 on the display substrate plane.

[0130] In an exemplary embodiment, an orthographic projection of the first power line 61 on the display substrate plane at least partially overlaps with an orthographic projection of the first connection electrode 51 on the display substrate plane.

[0131] In an exemplary embodiment, an orthographic projection of the first power supply line 61 on the display substrate plane at least partially overlaps with an orthographic projection of the second active layer 12 on the display substrate plane.

[0132] In an exemplary embodiment, the first scan signal line 21 can be set on a side of the fourth scan signal line 24 away from the gate electrode T3-g of the third transistor, and the first electrode T4-1 of the fourth transistor can be set on a side of the fourth scan signal line 24 away from the gate electrode T3-g of the third transistor, and the orthographic projection of the first connecting electrode 51 on the plane of the display substrate does not overlap with the orthographic projection of the first scan signal line 21 on the plane of the display substrate.

[0133] In an exemplary embodiment, an orthographic projection of the second preliminary signal line 42 on the display substrate plane at least partially overlaps with an orthographic projection of the second scan signal line 22 on the display substrate plane.

[0134] In an exemplary embodiment, an orthographic projection of the third preliminary signal line 43 on the display substrate plane at least partially overlaps with an orthographic projection of the third scan signal line 23 on the display substrate plane.

[0135] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a plurality of conductive layers sequentially arranged on a base, the first initial signal line 31 and the second initial signal line 42 may be arranged in different conductive layers, and the second initial signal line 42 and the third initial signal line 43 may be arranged in the same conductive layer.

[0136] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0137] In an exemplary embodiment, taking three circuit units (one unit row and three unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0138] (11) Forming a blocking layer pattern. In an exemplary embodiment, forming a blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG6 .

[0139] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a first shielding electrode line 91 , a second shielding electrode line 92 , and a shielding electrode 93 .

[0140] In an exemplary embodiment, the shielding electrode 93 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first shielding electrode line 91 may be straight and extend along the first direction X. The first shielding electrode line 91 may be disposed on both sides of the shielding electrode 93 in the first direction X and connected to the shielding electrode 93. The second shielding electrode line 92 may be zigzag-line shaped and extend along the second direction Y. The second shielding electrode line 92 may be disposed on both sides of the shielding electrode 93 in the second direction Y and connected to the shielding electrode 93.

[0141] In an exemplary embodiment, the first shielding electrode line 91 of each circuit unit is connected to the first shielding electrode line 91 of the circuit unit adjacent in the first direction X, so that the multiple shielding electrodes 93 and the first shielding electrode line 91 in a unit row are connected into one, forming an interconnected integrated structure.

[0142] In an exemplary embodiment, the second shielding electrode line 92 of each circuit unit is connected to the second shielding electrode line 92 of the circuit unit adjacent in the second direction Y, so that the shielding electrode 93 and the second shielding electrode line 92 in a unit column are connected into one, forming an interconnected integrated structure.

[0143] In an exemplary embodiment, the shielding layers in the unit rows and unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0144] In an exemplary embodiment, the positions and shapes of the shielding layers of adjacent cell columns may be substantially the same.

[0145] (12) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a plan view schematic diagram of the first semiconductor layer in FIG7A .

[0146] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0147] In an exemplary embodiment, an orthographic projection of the third active layer 13 on the substrate at least partially overlaps with an orthographic projection of the shielding electrode 93 on the substrate.

[0148] In an exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 may be located on a side of the third active layer 13 in the present circuit unit opposite to the first direction X, and the fourth active layer 14 and the eighth active layer 18 may be located on a side of the third active layer 13 in the present circuit unit in the first direction X. In the second direction Y, the first active layer 11 and the fourth active layer 14 may be located on a side of the third active layer 13 in the present circuit unit opposite to the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on a side of the third active layer 13 in the present circuit unit in the second direction Y.

[0149] In an exemplary embodiment, the third active layer 13 may have an inverted Ω shape, and the first active layer 11 and the fourth to eighth active layers 14 to 18 may have an I shape.

[0150] In an exemplary embodiment, the first active layer 11 and the third active layers 13 to 18 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be provided separately.

[0151] In example embodiments, positions and shapes of the first semiconductor layers of adjacent cell columns may be substantially the same.

[0152] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the first transistor, the third transistor, the fourth transistor, the fifth transistor, and the eighth transistor are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0153] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the first conductive layer in FIG8A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0154] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 25 and a first plate 26 of a storage capacitor.

[0155] In an exemplary embodiment, the first electrode plate 26 may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate 26 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 26 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0156] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a zigzag shape with the main portion extending along the first direction X. The first scanning signal line 21 can be located on the side of the first electrode 26 in the opposite direction of the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0157] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scanning signal line 22 can be located on one side of the first electrode 26 in the second direction Y. The area where the second scanning signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the second scanning signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0158] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X. The third scan signal line 23 can be located on a side of the first scan signal line 21 away from the first electrode 26. The area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0159] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line with the main portion extending along the first direction X. The light-emitting signal line 25 can be located between the second scanning signal line 22 and the first electrode 26. The area where the light-emitting signal line 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 25 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0160] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 25 can be designed with equal width or unequal width, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0161] In an exemplary embodiment, the first scan signal line 21 and the third scan signal line 23 may include an area overlapping with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the signal line in the area overlapping with the first semiconductor layer may be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.

[0162] In example embodiments, positions and shapes of the first conductive layers of adjacent cell columns may be substantially the same.

[0163] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all conductorized.

[0164] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the second conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0165] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a first initial signal line 31 , a shielding line 32 , and a second plate 33 of a storage capacitor.

[0166] In an exemplary embodiment, the first preliminary signal line 31 may be in a straight line or a zigzag shape with a main portion extending along the first direction X. The first preliminary signal line 31 may be located between the first scan signal line 21 and the third scan signal line 23 .

[0167] In an exemplary embodiment, a first preliminary connection block 31-1 is provided on a side of the first preliminary signal line 31 of each circuit unit close to the first scan signal line 21. The first preliminary connection block 31-1 may be in a block shape (e.g., a rectangle), with a first end of the first preliminary connection block 31-1 connected to the first preliminary signal line 31, and a second end of the first preliminary connection block 31-1 extending toward the first scan signal line 21. The first preliminary connection block 31-1 is configured to be connected to the first region of the first active layer via a seventh connection electrode formed subsequently.

[0168] In an exemplary embodiment, a shielding bar 31-2 may be provided on a side of the first initial signal line 31 of each circuit unit that is adjacent to the first scan signal line 21. The shielding bar 31-2 may be in the shape of a bar extending along the second direction Y. A first end of the shielding bar 31-2 is connected to the first initial signal line 31, and a second end of the shielding bar 31-2 extends toward the first scan signal line 21. The shielding bar 31-2 is configured to be provided between the first region of the fourth active layer and the second region of the second active layer, providing shielding between the first electrode of the fourth transistor T4 and the second electrode of the second transistor T2, thereby preventing data voltage jumps from affecting the performance of the second transistor T2.

[0169] In an exemplary embodiment, the first preliminary signal line 31 , the first preliminary connection block 31 - 1 , and the shielding bar 31 - 2 may be an integral structure connected to each other.

[0170] In an exemplary embodiment, the shape of the shielding line 32 can be a straight line or line shape with the main part extending along the first direction X. The shielding line 32 can be located between the first scanning signal line 21 and the first electrode 26. The shielding line 32 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and at the same time being configured as the bottom gate electrode of the second transistor T2.

[0171] In an exemplary embodiment, the shielding lines 32 may be designed with unequal widths, which not only improves the shielding effect but also facilitates the layout of the pixel structure and reduces the parasitic capacitance between signal lines.

[0172] In an exemplary embodiment, the outline of the second electrode plate 33 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 33 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 26 on the substrate. The second electrode plate 33 can serve as another electrode plate of the storage capacitor, and the first electrode plate 26 and the second electrode plate 33 constitute the storage capacitor of the pixel driving circuit.

[0173] In an exemplary embodiment, an opening 34 is provided on the second electrode plate 33. Opening 34 can be rectangular and located in the middle of the second electrode plate 33, forming an annular structure. Opening 34 exposes the third insulating layer covering the first electrode plate 26, and the orthographic projection of the first electrode plate 26 on the substrate includes the orthographic projection of opening 34 on the substrate. In an exemplary embodiment, opening 34 is configured to accommodate a thirteenth via hole to be formed later. The thirteenth via hole is located within opening 34 and exposes the first electrode plate 26, allowing a first connecting electrode to be formed later to connect to the first electrode plate 26.

[0174] In an exemplary embodiment, a plate connecting bar 35 is provided on one side of the second electrode plate 33 in the first direction X or on a side opposite to the first direction X. The plate connecting bar 35 can be in the shape of a bar extending along the first direction X. The first end of the plate connecting bar 35 is connected to the second electrode plate 33 in the current circuit unit, and the second end of the plate connecting bar 35 is connected to the second electrode plate 33 in the adjacent circuit unit in the first direction X. This allows the second electrode plates 33 in adjacent circuit units in a row of cells to form an interconnected, integrated structure. Because the second electrode plates 33 in each circuit unit are connected to a subsequently formed first power line, by forming the second electrode plates 33 of adjacent circuit units into an interconnected, integrated structure, the second electrode plates of the integrated structure can be reused as power signal lines. This ensures that multiple second electrode plates in a row of cells have the same potential, which helps improve panel uniformity, prevents display defects on the display substrate, and ensures the display quality of the display substrate.

[0175] In example embodiments, positions and shapes of the second conductive layers of adjacent cell columns may be substantially the same.

[0176] (15) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second semiconductor layer in FIG10A .

[0177] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .

[0178] In an exemplary embodiment, the second active layer 12 may be in the shape of a strip extending along the second direction Y, and may be located between the first initial signal line 31 and the second electrode plate 33 , with the orthographic projection of the second active layer 12 on the substrate at least partially overlapping with the orthographic projection of the shielding line 32 on the substrate.

[0179] In an exemplary embodiment, the first region 12-1 of the second active layer may be located on a side of the shielding line 32 close to the first and second plates 26 and 33, and the second region 12-2 of the second active layer may be located on a side of the shielding line 32 away from the first and second plates 26 and 33.

[0180] In example embodiments, positions and shapes of the second semiconductor layers of adjacent cell columns may be substantially the same.

[0181] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0182] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the third conductive layer in FIG11A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0183] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a fourth scan signal line 24 , a second preliminary signal line 42 , and a third preliminary signal line 43 .

[0184] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main portion extending along the first direction X. The fourth scan signal line 24 can be located between the first scan signal line 21 and the first electrode 26. The orthographic projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the orthographic projection of the shielding line 32 on the substrate. The area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0185] In an exemplary embodiment, the fourth scan signal line 24 can serve as a compensation scan signal line, the first region 12-1 of the second active layer can be located on a side of the fourth scan signal line 24 close to the first electrode plate 26 and the second electrode plate 33, and the second region 12-2 of the second active layer can be located on a side of the fourth scan signal line 24 away from the first electrode plate 26 and the second electrode plate 33.

[0186] In an exemplary embodiment, the fourth scan signal line 24 and the shielding line 32 can be connected to the same signal source, so that the shielding line 32 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0187] In an exemplary embodiment, the first region of the fourth active layer (the first electrode of the fourth transistor T4 ) may be located on a side of the fourth scan signal line 24 away from the storage capacitor.

[0188] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 42 can be located on the side of the light-emitting signal line 25 away from the second electrode plate 33. A second initial connection block 42-1 is provided on the second initial signal line 42 of each circuit unit. The first end of the second initial connection block 42-1 is connected to the second initial signal line 42, and the second end of the second initial connection block 42-1 extends in a direction away from the second electrode plate 33. The second initial connection block 42-1 is configured to be connected to the first area of ​​the seventh active layer through the subsequently formed eighth connection electrode.

[0189] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate, and the second initial signal line 42 with a constant voltage can act as a shield, reducing the impact of the second scanning signal line 22 on the pixel driving circuit.

[0190] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main portion extending along the first direction X. The third initial signal line 43 can be located on the side of the first initial signal line 31 away from the second electrode plate 33. A third initial connection block 43-1 is provided on the third initial signal line 43 of each circuit unit. The first end of the third initial connection block 43-1 is connected to the third initial signal line 43, and the second end of the third initial connection block 43-1 extends in a direction away from the second electrode plate 33. The third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through a ninth connection electrode formed subsequently.

[0191] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line 23 on the substrate. The third initial signal line 43 with a constant voltage can play a shielding role, reducing the influence of the third scanning signal line 23 on the pixel driving circuit.

[0192] In exemplary embodiments, positions and shapes of the third conductive layers of adjacent cell columns may be substantially the same.

[0193] (17) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of via holes, as shown in FIG. 12 .

[0194] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0195] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed seventh connecting electrode to the first region of the first active layer through the via hole.

[0196] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0197] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0198] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the fifth via hole V5 is configured to connect the subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0200] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the fifth active layer, and the eighth via V8 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the fifth active layer (also the first area of ​​the third active layer and the second area of ​​the fourth active layer) through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the ninth via hole V9 is configured to connect the subsequently formed sixth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect the subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer. The twelfth via hole V12 is configured to connect the subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the opening 34 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first electrode 26. The thirteenth via hole V13 is configured to connect the subsequently formed first connecting electrode to the first electrode 26 through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second electrode plate 33 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second electrode plate 33, and the fourteenth via hole V14 is configured to connect the subsequently formed fourth connecting electrode to the second electrode plate 33 through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first initial connection block 31-1 of the first initial signal line 31 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifteenth via V15 are etched away to expose the surface of the first initial connection block 31-1, and the fifteenth via V15 is configured to connect the subsequently formed seventh connection electrode to the first initial connection block 31-1 through the via.

[0210] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the second initial connection block 42-1, and the sixteenth via V16 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 42-1 through the via.

[0211] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the sixth insulating layer in the seventeenth via V17 is etched away, exposing the surface of the third initial connection block 43-1, and the seventeenth via V17 is configured to connect the subsequently formed ninth connection electrode to the third initial connection block 43-1 through the via.

[0212] In an exemplary embodiment, positions and shapes of the plurality of via holes of adjacent cell columns may be substantially the same.

[0213] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 13A and FIG. 13B , where FIG. 13B is a plan view schematic diagram of the fourth conductive layer in FIG. 13A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0214] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0215] In an exemplary embodiment, the first connection electrode 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the first region of the second active layer via a third via hole V3. The second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 26 via a thirteenth via hole V13. In an exemplary embodiment, because the first electrode plate 26 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 26 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0216] In an exemplary embodiment, since the first region of the second active layer (the first electrode of the second transistor) is arranged on the side of the fourth scanning signal line 24 close to the storage capacitor, and the second region of the second active layer (the second electrode of the second transistor) is arranged on the side of the fourth scanning signal line 24 away from the storage capacitor, the first connecting electrode 51 connecting the first region of the second active layer and the first electrode plate 26 has a smaller extension length, and there is a larger distance between the first connecting electrode 51 and the subsequently formed data signal line. Moreover, the orthographic projection of the first connecting electrode 51 on the substrate does not overlap with the orthographic projection of the first scanning signal line 21 and the fourth scanning signal line 24 on the substrate, which can effectively reduce the capacitance between the first node N1 of the pixel driving circuit and the data signal line and the scanning signal line, thereby minimizing crosstalk and improving the display effect and display quality.

[0217] In an exemplary embodiment, the second active layer 12 of the second transistor T2 and the first connection electrode 51 may both be strip-shaped with the main portion extending along the second direction Y, and the extension length of the first connection electrode 51 may be smaller than the extension length of the second active layer 12 .

[0218] In an exemplary embodiment, the second connection electrode 52 may include a first sub-electrode 52-1 with a strip-shaped main portion extending along the second direction Y, and a second sub-electrode 52-2 with a strip-shaped main portion extending along the first direction X. The first end of the first sub-electrode 52-1 is connected to the second region of the first active layer via a second via V2. The second end of the first sub-electrode 52-1 extends along the second direction Y and is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fifth via V5. The first end of the second sub-electrode 52-2 is connected to the first sub-electrode 52-1. The second end of the second sub-electrode 52-2 extends along the first direction X toward the second region of the second active layer and is connected to the second region of the second active layer via a fourth via V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrodes of the first transistor T1, the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0219] In exemplary embodiments, an extension length of the first connection electrode 51 may be smaller than an extension length of the first sub-electrode 52 - 1 .

[0220] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0221] In an exemplary embodiment, the fourth connection electrode 54 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer of the power supply in the current circuit via a seventh via V7. A second end of the fourth connection electrode 54 extends in a direction opposite to the second direction Y and is connected to the second electrode plate 33 of the power supply in the adjacent circuit via a fourteenth via V14. Because multiple second electrode plates 33 in a cell row are interconnected, the first electrode of the fifth transistor T5 and the second electrode plate 33 of the storage capacitor in each circuit cell have the same potential.

[0222] In an exemplary embodiment, the fifth connection electrode 55 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the second region of the fifth active layer via an eighth via hole V8. A second end of the fifth connection electrode 55 extends along the second direction Y and is connected to the second region of the eighth active layer via a twelfth via hole V12. In an exemplary embodiment, because the second region of the fifth active layer serves as both the first region of the third active layer and the second region of the fourth active layer, the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, thereby forming a second node N2 of the pixel driving circuit.

[0223] In an exemplary embodiment, the sixth connection electrode 56 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 56 is configured to be connected to an anode connection electrode formed subsequently.

[0224] In an exemplary embodiment, the seventh connection electrode 57 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the seventh connection electrode 57 is connected to the first region of the first active layer via a first via V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 31-1 via a fifteenth via V15. In an exemplary embodiment, the seventh connection electrode 57 may serve as the first electrode of the first transistor T1. Because the first initial connection block 31-1 is connected to the first initial signal line 31, the seventh connection electrode 57 enables the first initial signal transmitted by the first initial signal line 31 to be written into the first electrode of the first transistor T1.

[0225] In an exemplary embodiment, the eighth connection electrode 58 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer via a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 via a sixteenth via hole V16. In an exemplary embodiment, the eighth connection electrode 58 may serve as the first electrode of the seventh transistor T7. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 causes the second initial signal transmitted by the second initial signal line 42 to be written into the first electrode of the seventh transistor T7.

[0226] In an exemplary embodiment, the ninth connection electrode 59 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer of the present circuit unit via an eleventh via hole V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 of the next cell row via a seventeenth via hole V17. The ninth connection electrode 59 may serve as the first electrode of the eighth transistor T8. Since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 enables the third initial signal transmitted by the third initial signal line 43 to be written into the first electrode of the eighth transistor T8.

[0227] In example embodiments, positions and shapes of the fourth conductive layers of adjacent cell columns may be substantially the same.

[0228] (19) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 14 .

[0229] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0230] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connecting electrode 53, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0231] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer within the twenty-second via hole V22 is etched away to expose the surface of the fourth connecting electrode 54, and the twenty-second via hole V22 is configured to connect a subsequently formed power connection line to the fourth connecting electrode 54 through the via hole.

[0232] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer within the twenty-third via hole V23 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.

[0233] In an exemplary embodiment, positions and shapes of the plurality of via holes on the first planar layer of adjacent cell columns may be substantially the same.

[0234] (20) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG15A and FIG15B , where FIG15B is a planar schematic diagram of the fifth conductive layer in FIG15A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0235] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a first power line 61 , a data signal line 62 , and an anode connection electrode 63 .

[0236] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 61 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is respectively connected to the first region of the fifth active layer and the second plate 33 of the storage capacitor, the first power line 61 writes the first power signal to the fifth transistor T5 and the second plate 33 of the storage capacitor.

[0237] In an exemplary embodiment, the first power line 61 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0238] In an exemplary embodiment, a power connection block 61 - 1 is connected to the first power line 61 , and the power connection block 61 - 1 is connected to the fourth connection electrode 54 through the twenty-second via hole V22 .

[0239] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 62 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4.

[0240] In an exemplary embodiment, the anode connection electrode 63 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 63 is connected to the sixth connection electrode 56 via a twenty-third via hole V23. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer via the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0241] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. The first power line 61 having a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.

[0242] In an exemplary embodiment, an orthographic projection of the first power line 61 on the substrate may include an orthographic projection of the first connection electrode 51 on the substrate.

[0243] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the first power line 61 can block the second active layer, thereby blocking the light emission of the light-emitting device and the light reflected by the film layer from irradiating the second transistor T2 of the oxide, preventing the characteristics of the oxide transistor from drifting due to light, and improving the electrical characteristics of the oxide transistor.

[0244] In an exemplary embodiment, an orthographic projection of the first power line 61 on the substrate may include an orthographic projection of the second active layer on the substrate.

[0245] In example embodiments, positions and shapes of the fifth conductive layers of adjacent cell columns may be substantially the same.

[0246] Subsequently, a second flat layer pattern covering the fifth conductive layer pattern is formed, and a plurality of anode vias are formed on the second flat layer using a patterning process. The anode vias expose the surface of the anode connecting electrode, and the anode vias are configured to connect the subsequently formed anode to the anode connecting electrode through the vias.

[0247] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, a second initial signal line, and a third initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer sequentially arranged on the substrate. The blocking layer may include at least a blocking electrode, the first semiconductor layer may include at least the active layers of the first transistor, the third transistor to the eighth transistor, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the third scanning signal line, the light-emitting signal line and the first plate of the storage capacitor, the second conductive layer may include at least the first initial signal line, the blocking line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the second transistor, the third conductive layer may include at least the second initial signal line, the third initial signal line and the fourth scanning signal line, the fourth conductive layer may include at least a plurality of connecting electrodes, and the fifth conductive layer may include at least the first power line, the data signal line and the anode connecting electrode.

[0248] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0249] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin.

[0250] In an exemplary embodiment, after the driving circuit layer is prepared, the subsequent preparation process may include preparing a light-emitting structure layer on the driving circuit layer and preparing an encapsulation structure layer on the light-emitting structure layer. In an exemplary embodiment, the preparation process of the light-emitting structure layer may include: forming an anode conductive layer, the anode conductive layer includes at least a plurality of anodes, and the plurality of anodes can be respectively connected to the anode connection electrode of the circuit unit through anode vias. A pixel definition layer covering the anode conductive layer is formed, and a plurality of pixel openings exposing the anodes are provided on the pixel definition layer. An organic light-emitting layer is formed by evaporation or inkjet printing, and then a cathode is formed on the organic light-emitting layer. The formation of the encapsulation structure layer may include sequentially forming a first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0251] With the continuous development of display technology, the resolution of display devices (Pixels Per Inch, PPI) continues to increase, the size of pixel units continues to decrease, and the space for pixel driver circuits continues to shrink. As the size of pixel units decreases, the distances between nodes within the pixel driver circuit and the distances between each node and the signal lines decrease, resulting in an increase in inter-signal capacitance.

[0252] In a display substrate, the capacitance between the first node N1 of the pixel driving circuit and the data signal line is relatively large, about 0.157 (fF), resulting in poor crosstalk and even deterioration of the display effect. Research has shown that the problem of large capacitance in this display substrate is caused by an unreasonable design of the connection position between the nodes. In the pixel driving circuit structure of this display substrate, since the first electrode of the oxide compensation transistor is set on the side of the fourth scanning signal line away from the storage capacitor, and the second electrode of the oxide compensation transistor is set on the side of the fourth scanning signal line close to the storage capacitor, the first connecting electrode connecting the first electrode of the oxide compensation transistor and the first electrode plate of the storage capacitor needs to avoid the second electrode of the oxide compensation transistor by bending the wiring. The bending wiring structure not only increases the extension length of the first connecting electrode, but also reduces the distance between the first connecting electrode and the data signal line, resulting in a larger capacitance between the first node N1 of the pixel driving circuit and the data signal line. In addition, since the first electrode of the oxide compensation transistor is set on the side of the fourth scanning signal line away from the storage capacitor, the first connecting electrode needs to cross the fourth scanning signal line, so that there is a large capacitance between the first connecting electrode and the fourth scanning signal line, which is about 3.324 (fF), which increases power consumption.

[0253] The display substrate provided by the embodiment of the present disclosure effectively reduces the capacitance between the first node N1 of the pixel driving circuit and the data signal line by adjusting the data signal writing path. In the pixel driving circuit structure of the present disclosure, the first electrode of the oxide second transistor (i.e., the compensation transistor) is arranged on the side of the fourth scan signal line close to the storage capacitor, the first electrode of the second transistor is connected to the first plate of the storage capacitor (i.e., the gate electrode of the driving transistor) via the first connecting electrode (i.e., the first node N1), and the second electrode of the second transistor is arranged on the side of the fourth scan signal line away from the storage capacitor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor via the second connecting electrode. The adjusted data signal writing path is as follows: after the data signal provided by the data signal line passes through the third transistor, it first passes through the second connecting electrode (SD1 layer) along the opposite direction of the second direction Y (from bottom to top) to reach the second electrode of the second transistor, then passes through the second transistor along the second direction Y (from top to bottom), and then passes through the first connecting electrode (SD1 layer) along the second direction Y (from top to bottom) to reach the first plate of the storage capacitor (i.e., the gate electrode of the third transistor). This effectively shortens the extension length of the first connection electrode and avoids a zigzag routing structure, increasing the distance between the first connection electrode and the data signal line. Because the capacitance between the first connection electrode and the data signal line is positively correlated with the extension length of the first connection electrode and the distance between the first connection electrode and the data signal line, the disclosed structure effectively reduces the capacitance between the first node N1 of the pixel driver circuit and the data signal line. In this embodiment, the capacitance between the first node N1 and the data signal line is only approximately 0.010 (fF), a reduction of over 90% compared to existing structures. This minimizes crosstalk and improves display effects and quality.

[0254] The present disclosure effectively reduces the capacitance between the first node N1 and the fourth scan signal line by positioning the first electrode of the second oxide transistor on the side of the fourth scan signal line near the storage capacitor. This ensures that the orthographic projection of the first connecting electrode on the substrate does not overlap with the orthographic projection of the fourth scan signal line on the substrate. Research has shown that after the data signal is written, the fourth scan signal line undergoes a voltage jump from a high voltage to a low voltage to turn off the compensation transistor. This voltage jump on the fourth scan signal line lowers the voltage of the first node N1 through capacitive coupling. Therefore, the setting of the black screen (L0) data signal needs to take into account the effects of capacitive coupling. In this embodiment, the capacitance between the first node N1 and the scan signal line is only approximately 1.634 (fF), which is approximately 50% smaller than that of existing structures. Therefore, the setting of the black screen data signal does not need to consider the effects of capacitive coupling. This reduces the black screen voltage, effectively reduces power consumption, and further avoids crosstalk, thereby improving display quality and performance.

[0255] The present disclosure sets a first power line to cover the first connection electrode, which can effectively shield the influence of data voltage jumps and other signals on the first node in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node, and effectively avoid the deterioration of crosstalk. The present disclosure sets a first power line to cover the second active layer, which can effectively block the light emission of the light-emitting device and the light reflected by the film layer from irradiating the oxide transistor, prevent the oxide transistor from drifting due to light, and improve the electrical characteristics of the oxide transistor. The preparation process of the present disclosure is well compatible with existing preparation processes, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0256] Figure 16 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, the main structure of the display substrate of this embodiment is substantially the same as that of the aforementioned embodiment, except that in this embodiment, the fourth scan signal line 24 can be located on the side of the first scan signal line 21 away from the gate electrode T3-g of the third transistor, and the first electrode T4-1 of the fourth transistor can be located on the side of the fourth scan signal line 24 closer to the gate electrode T3-g of the third transistor.

[0257] In an exemplary embodiment, the first connection electrode 51 may be located on a side of the fourth scan signal line 24 close to the gate electrode T3-g of the third transistor, and the orthographic projection of the first connection electrode 51 on the display substrate plane does not overlap with the orthographic projection of the fourth scan signal line 24 on the display substrate plane.

[0258] In an exemplary embodiment, an orthographic projection of the first connection electrode 51 on the display substrate plane at least partially overlaps with an orthographic projection of the first scan signal line 21 on the display substrate plane.

[0259] In an exemplary embodiment, taking three circuit units (one unit row and three unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0260] (21) Forming a shielding layer pattern. In an exemplary embodiment, the process of forming the shielding layer pattern and the structure of the shielding layer are substantially the same as those in the previous embodiment, as shown in FIG. 17 .

[0261] (22) Forming a first semiconductor layer pattern. In the exemplary embodiment, the process of forming the first semiconductor layer and the structure of the first semiconductor layer are substantially the same as those in the aforementioned embodiment, except that the fourth active layer 14 of this embodiment has a shorter extension length, that is, the distance in the second direction Y between the first region of the fourth active layer and the second region of the first active layer is larger, as shown in FIG18A and FIG18B , where FIG18B is a plan view schematic diagram of the first semiconductor layer in FIG18A .

[0262] (23) Forming a first conductive layer pattern. In the exemplary embodiment, the process of forming the first conductive layer and the structure of the first conductive layer are substantially the same as those in the aforementioned embodiment, except that the spacing between the first scan signal line 21 and the first electrode plate 26 is smaller in this embodiment, as shown in FIG19A and FIG19B . FIG19B is a plan view schematically illustrating the first conductive layer in FIG19A .

[0263] (24) Forming a second conductive layer pattern. In the exemplary embodiment, the process of forming the second conductive layer and the structure of the second conductive layer are substantially the same as those in the aforementioned embodiment, except that, in this embodiment, the shielding line 32 is located on the side of the first scanning signal line 21 away from the first electrode plate 26, as shown in Figures 20A and 20B. Figure 20B is a plan view schematic diagram of the second conductive layer in Figure 20A.

[0264] In an exemplary embodiment, the first scanning signal line 21 of the aforementioned embodiment is located between the first initial signal line 31 and the shielding line 32, and the shielding line 32 of this embodiment is located between the first initial signal line 31 and the first scanning signal line 21, that is, the positions of the first scanning signal line 21 and the shielding line 32 are interchanged in this embodiment.

[0265] (25) Forming a second semiconductor layer pattern. In an exemplary embodiment, the process of forming the second semiconductor layer and the structure of the second semiconductor layer are substantially the same as those in the aforementioned embodiment, as shown in FIG21A and FIG21B , where FIG21B is a schematic plan view of the second semiconductor layer in FIG21A .

[0266] In an exemplary embodiment, the orthographic projection of the second region of the second active layer of the aforementioned embodiment on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line 21 on the substrate, and the orthographic projection of the first region of the second active layer of this embodiment on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line 21 on the substrate.

[0267] (26) Forming a third conductive layer pattern. In an exemplary embodiment, the process of forming the third conductive layer and the structure of the third conductive layer are substantially the same as those in the aforementioned embodiment. The fourth scan signal line 24 is located on a side of the first scan signal line 21 away from the first electrode plate 26. The orthographic projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the orthographic projection of the shielding line 32 on the substrate, as shown in FIG22A and FIG22B. FIG22B is a plan view schematic diagram of the third conductive layer in FIG22A.

[0268] In an exemplary embodiment, the first scanning signal line 21 of the aforementioned embodiment is located between the first initial signal line 31 and the fourth scanning signal line 24, and the fourth scanning signal line 24 of this embodiment is located between the first initial signal line 31 and the first scanning signal line 21, that is, the positions of the first scanning signal line 21 and the fourth scanning signal line 24 are interchanged in this embodiment.

[0269] In an exemplary embodiment, the first region of the fourth active layer (the first electrode of the fourth transistor T4 ) may be located on a side of the fourth scan signal line 24 close to the storage capacitor.

[0270] (27) Forming a Sixth Insulation Layer Pattern In an exemplary embodiment, the process of forming the sixth insulation layer and the structure of the plurality of via holes are substantially the same as those in the previous embodiment, as shown in FIG. 23 .

[0271] (28) Forming a fourth conductive layer pattern. In the exemplary embodiment, the process of forming the fourth conductive layer and the structure of the fourth conductive layer are substantially the same as those in the aforementioned embodiment, except that the shape of the second connection electrode 52 in this embodiment is slightly changed, as shown in Figures 24A and 24B. Figure 24B is a plan view schematic diagram of the fourth conductive layer in Figure 24A.

[0272] In an exemplary embodiment, since the first region of the second active layer (the first electrode of the second transistor) is arranged on the side of the fourth scanning signal line 24 close to the storage capacitor, and the second region of the second active layer (the second electrode of the second transistor) is arranged on the side of the fourth scanning signal line 24 away from the storage capacitor, the first connecting electrode 51 connecting the first region of the second active layer and the first electrode plate 26 has a smaller extension length, and there is a larger distance between the first connecting electrode 51 and the subsequently formed data signal line. Moreover, the orthographic projection of the first connecting electrode 51 on the substrate does not overlap with the orthographic projection of the fourth scanning signal line 24 on the substrate, which can effectively reduce the capacitance between the first node N1 of the pixel driving circuit and the data signal line, and can effectively reduce the capacitance between the first node N1 of the pixel driving circuit and the fourth scanning signal line, thereby avoiding crosstalk to the greatest extent and improving the display effect and display quality.

[0273] (29) Sequentially forming patterns of the first planar layer and the fifth conductive layer. In an exemplary embodiment, the process and structure of forming the first planar layer and the fifth conductive layer are substantially the same as those of the aforementioned embodiment, as shown in FIG16 .

[0274] Subsequently, a second planar layer pattern is formed overlying the fifth conductive layer pattern, completing the drive circuit layer on the substrate. After the drive circuit layer is completed, subsequent fabrication steps may include fabricating a light-emitting structure layer on the drive circuit layer and an encapsulation structure layer on the light-emitting structure layer, which will not be detailed here.

[0275] The display substrate provided in the disclosed embodiments also effectively reduces the capacitance between the first node N1 of the pixel driver circuit and the data signal line by adjusting the data signal write path. In this embodiment, the capacitance between the first node N1 and the data signal line is only approximately 0.058 (fF), a 65% reduction compared to existing structures. This reduces crosstalk and improves display quality.

[0276] In this embodiment, the orthographic projection of the first connecting electrode on the substrate does not overlap with the orthographic projection of the fourth scanning signal line on the substrate, thus effectively reducing the capacitance between the first connecting electrode and the fourth scanning signal line. Although the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the substrate, the capacitance between the first connecting electrode and the scanning signal line is only approximately 1.367 (fF). Compared with existing structures, this capacitance is reduced by approximately 60%, effectively reducing power consumption and further preventing crosstalk, thereby improving display effects and quality.

[0277] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0278] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0279] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, and the preparation method may include:

[0280] A pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit including at least an oxide compensation transistor and a polysilicon driving transistor, the gate electrode of the compensation transistor being connected to a compensation scanning signal line, the compensation scanning signal line being configured to control the on and off of the compensation transistor; a first electrode of the compensation transistor being arranged on a side of the compensation scanning signal line close to the driving transistor and being connected to the gate electrode of the driving transistor through a first connecting electrode, and a second electrode of the compensation transistor being arranged on a side of the compensation scanning signal line away from the driving transistor and being connected to the second electrode of the driving transistor through a second connecting electrode.

[0281] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units, at least one of which comprises a pixel driving circuit, wherein the pixel driving circuit comprises at least an oxide compensation transistor and a polysilicon driving transistor, wherein a gate electrode of the compensation transistor is connected to a compensation scanning signal line, and the compensation scanning signal line is configured to control the on and off of the compensation transistor; a first electrode of the compensation transistor is arranged on a side of the compensation scanning signal line close to the driving transistor, and is connected to the gate electrode of the driving transistor through a first connecting electrode, and a second electrode of the compensation transistor is arranged on a side of the compensation scanning signal line away from the driving transistor, and is connected to the second electrode of the driving transistor through a second connecting electrode.

2. The display substrate according to claim 1, wherein: The orthographic projection of the first connecting electrode on the display substrate plane does not overlap with the orthographic projection of the compensation scanning signal line on the display substrate plane.

3. The display substrate according to claim 1, wherein: The compensation transistor at least includes a compensation active layer, the first connection electrode and the compensation active layer are both in the shape of strips extending toward the driving transistor, and the extension length of the first connection electrode is smaller than the extension length of the compensation active layer.

4. The display substrate according to claim 1, wherein: The second connecting electrode at least includes a first sub-electrode and a second sub-electrode, the first end of the first sub-electrode is connected to the second electrode of the driving transistor, the second end of the first sub-electrode extends in a direction away from the driving transistor, the first end of the second sub-electrode is connected to the first sub-electrode, the second end of the second sub-electrode extends in the direction of the compensation transistor and then connected to the second electrode of the compensation transistor, the shape of the first connecting electrode is a strip shape extending in the direction of the driving transistor, and the extension length of the first connecting electrode is less than the extension length of the first sub-electrode.

5. The display substrate according to claim 1, wherein: At least one circuit unit also includes a first power line, which is connected to the pixel driving circuit, and the first power line is configured to provide a first power signal to the pixel driving circuit, and the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the first connecting electrode on the display substrate plane.

6. The display substrate according to claim 5, wherein: The compensation transistor at least includes a compensation active layer, and an orthographic projection of the first power line on the plane of the display substrate at least partially overlaps with an orthographic projection of the compensation active layer on the plane of the display substrate.

7. The display substrate according to any one of claims 1 to 6, wherein: The pixel driving circuit also includes a polysilicon data writing transistor, a gate electrode of the data writing transistor is connected to the first scanning signal line, a first electrode of the data writing transistor is connected to the data signal line, and a second electrode of the data writing transistor is connected to the first electrode of the driving transistor; the first electrode of the data writing transistor is arranged on a side of the compensation scanning signal line away from the driving transistor, or the first electrode of the data writing transistor is arranged on a side of the compensation scanning signal line close to the driving transistor.

8. The display substrate according to claim 7, wherein: The first scanning signal line is arranged at a side of the compensation scanning signal line away from the driving transistor.

9. The display substrate according to claim 8, wherein: The orthographic projection of the first connecting electrode on the plane of the display substrate does not overlap with the orthographic projection of the first scanning signal line on the plane of the display substrate.

10. The display substrate according to claim 7, wherein: The compensation scanning signal line is arranged at a side of the first scanning signal line away from the driving transistor.

11. The display substrate according to claim 10, wherein: The orthographic projection of the first connecting electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first scanning signal line on the display substrate plane.

12. The display substrate according to claim 7, wherein: The pixel driving circuit further includes a first initialization transistor and a second initialization transistor of polysilicon; a gate electrode of the first initialization transistor is connected to a third scanning signal line, a first electrode of the first initialization transistor is connected to a first initial signal line, and a second electrode of the first initialization transistor is connected to a second electrode of the driving transistor; a gate electrode of the second initialization transistor is connected to a second scanning signal line, a first electrode of the second initialization transistor is connected to a second initial signal line, and a second electrode of the second initialization transistor is connected to an anode of the light-emitting device; The orthographic projection of the second initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second scanning signal line on the display substrate plane.

13. The display substrate according to claim 12, wherein: The pixel driving circuit also includes a third initialization transistor of polysilicon, a gate electrode of the third initialization transistor is connected to the second scanning signal line, a first electrode of the third initialization transistor is connected to the third initial signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor; an orthographic projection of the third initial signal line on the plane of the display substrate at least partially overlaps with an orthographic projection of the third scanning signal line on the plane of the display substrate.

14. The display substrate according to claim 13, wherein: On a plane perpendicular to the display substrate, the display substrate includes a plurality of conductive layers sequentially arranged on a base, the first initial signal line and the second initial signal line are arranged in different conductive layers, and the second initial signal line and the third initial signal line are arranged in the same conductive layer.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

16. A method for preparing a display substrate, wherein the display substrate comprises a plurality of circuit units, the method comprising: A pixel driving circuit is formed in at least one circuit unit, the pixel driving circuit at least comprising an oxide compensation transistor and a polysilicon driving transistor, a gate electrode of the compensation transistor being connected to a compensation scanning signal line, and the compensation scanning signal line being configured to control the on and off of the compensation transistor; The first electrode of the compensation transistor is arranged on a side of the compensation scanning signal line close to the driving transistor, and is connected to the gate electrode of the driving transistor through a first connecting electrode. The second electrode of the compensation transistor is arranged on a side of the compensation scanning signal line away from the driving transistor, and is connected to the second electrode of the driving transistor through a second connecting electrode.

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