Clock signal generation circuit and method, and memory

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a clock signal generation circuit and method, and a memory. The circuit comprises: a command pre-decoding circuit used for decoding some of command bits in a command to obtain a pre-decoded command signal; a command decoding circuit used for decoding the command to obtain an internal command signal; a counting circuit used for counting a clock cycle on the basis of an initial clock signal to generate a first counting signal and a second counting signal; and a clock signal intercepting circuit connected to the command pre-decoding circuit, the command decoding circuit, and the counting circuit and used for intercepting the initial clock signal on the basis of the pre-decoded command signal, the internal command signal, the first counting signal, and the second counting signal to obtain a target clock signal. Embodiments of the present disclosure can reduce the dynamic loss of the memory.

Description

Clock signal generation circuit, method and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 19, 2023, with application number 202310887357.5 and application name “Clock Signal Generation Circuit, Method and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a clock signal generation circuit, method, and memory. Background Art

[0003] With the continuous development of semiconductor technology, memory technology has become an important research direction. For memories such as Dynamic Random Access Memory (DRAM), they often need to perform various functions according to commands transmitted by the memory controller.

[0004] However, the dynamic power consumption of existing memories is often high when performing functions. Therefore, how to reduce the dynamic power consumption of memories has become a technical problem that needs to be solved urgently.

[0005] Summary of the Invention

[0006] The present disclosure provides a clock signal generation circuit, method, and memory, which at least to some extent overcome the problem of high dynamic power consumption of memories in related technologies.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to one aspect of the present disclosure, there is provided a clock signal generating circuit, comprising:

[0009] A command pre-decoding circuit, used for decoding part of the command bits in the command to obtain a pre-decoded command signal;

[0010] A command decoding circuit, used for decoding the command to obtain an internal command signal;

[0011] a counting circuit, configured to count clock cycles based on the initial clock signal and generate a first counting signal and a second counting signal;

[0012] The clock signal interception circuit is connected to the command pre-decoding circuit, the command decoding circuit and the counting circuit, and is used to intercept the initial clock signal according to the pre-decoding command signal, the internal command signal, the first counting signal and the second counting signal to obtain the target clock signal.

[0013] According to another aspect of the present disclosure, a memory is provided, characterized in that it includes the above-mentioned clock signal generating circuit

[0014] According to another aspect of the present disclosure, a clock signal generating method is provided, comprising:

[0015] The command decoding circuit decodes the input command to obtain an internal command signal;

[0016] The counting circuit counts clock cycles based on the initial clock signal to generate a counting signal;

[0017] The clock signal interception circuit intercepts the initial clock signal according to the internal command signal and the counting signal to obtain the target clock signal.

[0018] According to another aspect of the present disclosure, a clock signal generating method is provided, comprising:

[0019] Decoding part of the command bits in the command to obtain a pre-decoded command signal;

[0020] Counting clock cycles based on the initial clock signal to generate a first counting signal;

[0021] intercepting the initial clock signal according to the pre-decoding command signal and the first counting signal to obtain a first intercepted clock signal;

[0022] Decode the command to obtain the internal command signal;

[0023] Counting clock cycles based on the initial clock signal to generate a second counting signal;

[0024] The first intercepted clock signal is intercepted according to the internal command signal and the second counting signal to obtain a target clock signal.

[0025] The clock signal generation circuit, method, and memory provided by the embodiments of the present disclosure, after decoding a portion of the command bits of a command based on a command pre-decoding circuit to obtain a pre-decoding command, parsing the command decoding circuit to obtain an internal command signal, and counting the clock cycles of the initial clock signal by a counting circuit to generate a first count signal and a second count signal, because the pre-decoding command signal and the internal command signal are related to the command, and because the first count signal and the second count signal are obtained by counting the initial clock signal, a portion of the initial clock signal can be intercepted based on the pre-decoding command signal, the internal command signal, and the counting results of the first count signal and the second count signal to obtain a target clock signal that matches the command. Since the target clock signal of each command can match the operation time of each command, compared to the technical solution of using the same clock signal for each command, the dynamic loss of the memory caused by the constant flipping of the redundant cycle clock due to the mismatch between the clock cycle and the command during the command operation is avoided, thereby reducing the dynamic loss of the memory.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] FIG1 shows an exemplary command timing diagram provided by an embodiment of the present disclosure;

[0029] FIG2 shows a timing diagram of an exemplary clock signal provided by an embodiment of the present disclosure;

[0030] FIG3 shows a system architecture diagram of a storage system provided by an embodiment of the present disclosure;

[0031] FIG4 shows a circuit diagram of a clock signal generating circuit provided by an embodiment of the present disclosure;

[0032] FIG5 shows a circuit diagram of a command pre-decoding circuit provided by an embodiment of the present disclosure;

[0033] FIG6 shows a circuit diagram of an exemplary command pre-decoding circuit provided by an embodiment of the present disclosure;

[0034] FIG7 shows a circuit diagram of an exemplary pre-decoding command sub-signal processing circuit provided by an embodiment of the present disclosure;

[0035] FIG8 shows an exemplary signal timing diagram provided by an embodiment of the present disclosure;

[0036] FIG9 shows a schematic diagram of a counting circuit provided by an embodiment of the present disclosure;

[0037] FIG10 shows an exemplary timing diagram of output signals of the first triggers at each stage;

[0038] FIG11 shows a circuit diagram of a counting circuit;

[0039] FIG12 shows a circuit diagram of another counting circuit provided by an embodiment of the present disclosure;

[0040] FIG13 shows a circuit diagram of a clock signal interception circuit provided by an embodiment of the present disclosure;

[0041] FIG14 shows a circuit diagram of an exemplary clock signal interception circuit provided by an embodiment of the present disclosure;

[0042] FIG15 shows a circuit diagram of a circuit for generating an intercepted pulse signal provided by an embodiment of the present disclosure;

[0043] FIG16 shows a schematic diagram of an exemplary target pulse signal processing logic according to an embodiment of the present disclosure;

[0044] FIG17 shows a circuit diagram of an exemplary intercepted clock signal generation circuit provided by an embodiment of the present disclosure;

[0045] FIG18 shows a circuit diagram of an exemplary signal shielding circuit provided by an embodiment of the present disclosure;

[0046] FIG19 shows a schematic diagram of a first circuit portion of a clock signal generating circuit provided by an embodiment of the present disclosure;

[0047] FIG20 shows a schematic diagram of a second circuit portion of a clock signal generating circuit provided by an embodiment of the present disclosure;

[0048] FIG21 is a schematic flow chart showing a method for generating a clock signal according to an embodiment of the present disclosure;

[0049] FIG22 is a flow chart showing another clock signal generating method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0051] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0052] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0053] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0054] It should be noted that the modifications of "one" and "plurality" mentioned in this disclosure are illustrative and non-restrictive. Those skilled in the art will understand that, unless the context clearly indicates otherwise, they should be understood as "one or more." Furthermore, unless otherwise expressly specified or limited, the terms "connected" and "connected" should be understood broadly, for example, to mean fixedly connected, detachably connected, or integrally connected; directly connected, or indirectly connected through an intermediary. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0055] Before describing the technical solutions provided by the embodiments of the present disclosure, the technical terms involved in the embodiments of the present disclosure are first described.

[0056] (1) CAS Write Latency (CWL): After the memory controller sends a write command, it needs to wait for CWL before sending the write data.

[0057] (2) Write Recovery Time (tWR), which is the delay between writing data and the precharge command. tWR is used to indicate how many clock cycles must be waited before a valid write operation and precharge are completed in an active memory array (bank). This required number of clock cycles is used to ensure that the data in the write buffer can be written to the memory cell before precharge occurs.

[0058] (3) Unit clock cycle (Clock Time, tCK), which can be used as the basic unit of memory clock.

[0059] (4) Command / Address (CA) bus, which is used to transmit address signals and command signals between the chip and external devices.

[0060] After introducing the above technical terms, the technical solutions provided by the embodiments of the present disclosure are described below.

[0061] As mentioned in the background art, how to reduce the dynamic power consumption of memory has become a technical problem that needs to be solved urgently.

[0062] The inventors have found through research that in command transmission scenarios of memories such as DRAM, when the memory receives a command (Command, CMD), the command, after being decoded, often requires a clock signal to complete the operation corresponding to the command. For example, FIG1 shows an exemplary command timing diagram provided by an embodiment of the present disclosure. After the receiver receives the clock signal CK_t / CK_c as shown in FIG1, it can be divided into an odd-even clock PCLK_E / O as a clock signal to complete the operations corresponding to each command within the clock cycle corresponding to the odd-even clock PCLK_E / O.

[0063] However, the inventors found through further research that the operation time required for different commands is different. For example, when the burst length (Burst Length, BL) requires 16 tCKs, CWL is equal to 64 tCKs, and tWR is equal to 96 tCKs, the generation time required for the Write with Auto Precharge (WRA) command with automatic precharge is CWL+BL / 2+tWR, which requires 168 (i.e., 64+16 / 2+96) tCKs. Among them, BL is the burst length (Burst Length, BL). For another example, the clock cycle required for the Write (WR) command can be CWL+BL / 2, which requires 72 (i.e., 64+16 / 2) tCKs. It should be noted that when CWL, BL, and tWR are specified as other cycle lengths, the clock cycle required for each command can be other values, and there is no specific limitation on this.

[0064] Accordingly, Figure 2 shows a timing diagram of an exemplary clock signal provided by an embodiment of the present disclosure. As shown in Figure 2, clock signal C0 has a unit clock cycle as its period. If a command requires an operation time of T1, then the unit clock cycle corresponding to the required operation time T1 is the unit clock cycle required for the command operation. Unit clock cycles beyond the unit clock cycle required for the command operation are excess clock cycles.

[0065] If operations related to the decoded command are performed based on the clock signal C0, the clock signal will be continuously flipped in excess clock cycles, causing dynamic loss of the memory and consuming power.

[0066] Based on this, the embodiments of the present disclosure provide a clock signal generation circuit, method and memory, which can be applied to the field of semiconductor technology, especially the field of clock signal generation. In the embodiments of the present disclosure, since the target clock signal of each command can match the operation time required for each command, for example, the target clock signal Cx shown in Figure 2 contains a unit clock cycle whose number of cycles is equal to the number of clock cycles required for the command. Compared with the technical solution of using the same clock signal for each command, it avoids the dynamic loss of the memory caused by the constant flipping of the excess cycle clock generated by the mismatch between the clock cycle and the command during the command operation, thereby reducing the dynamic loss of the memory. Optionally, in order to further reduce the dynamic loss of the memory, as shown in Figure 2, the target clock signal Cx can be in a low level state during the time period corresponding to the excess cycle clock.

[0067] Next, the technical solutions provided by the embodiments of the present disclosure will be described and introduced.

[0068] Before introducing the technical solutions provided by the embodiments of the present disclosure, the storage system involved in the embodiments of the present disclosure is first described.

[0069] FIG3 shows a system architecture diagram of a storage system provided by an embodiment of the present disclosure. As shown in FIG2 , the storage system may include a storage controller 1 and a semiconductor memory 2 .

[0070] The memory controller 1 can send commands to the semiconductor memory 2 to enable the semiconductor memory 2 to perform various functions. For example, the memory controller 1 and the semiconductor memory 2 can transmit various commands via a command / address (CA) bus.

[0071] In the embodiment of the present disclosure, the storage controller 1 may be a host device (Host), for example, a system on a chip (SOC), etc. It should be noted that the host device may also be other host devices such as a processor (Central Processing Unit, CPU), and there is no specific limitation on this.

[0072] The semiconductor memory 2 may include a clock signal generating circuit 20 , which may generate a target clock signal matching a command, so as to execute operations related to the command based on the target clock signal after the command is decoded.

[0073] In the embodiment of the present disclosure, the semiconductor memory 2 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), or a flash memory. For example, the semiconductor memory may be a dual data rate synchronous dynamic random access memory (DDR SDRAM) or a low power dual data rate synchronous dynamic random access memory (LPDDR SDRAM). For example, the semiconductor memory may be DDR3, DDR4, DDR5, DDR6, LPDDR4, LPDDR5, LPDDR6, etc. However, the present disclosure does not limit the form of the semiconductor memory.

[0074] After a preliminary introduction to the storage system provided by the embodiment of the present disclosure, the commands involved in the embodiment of the present disclosure are explained next.

[0075] The command may be a command for controlling the semiconductor memory 2 to perform various functions. In the disclosed embodiment, the command may require clock signal generation. For example, Table 1 shows a truth table for the command. "H" indicates a high level, and "L" indicates a low level.

[0076] Table 1

[0077] As can be seen from Table 1, for the Write Pattern (WRP) command and the Write Pattern with Auto Precharge (WRPA) command, the command bits CA0-CA4 are “HLLHL”.

[0078] In addition, the mode register write (Mode Register Write, MRW) command, the mode register read (Mode Register Read, MRR) command, the write (Write, WR) command, the write with auto precharge (Write with Auto Precharge, WRA) command, the read command (Read, RD) and the read with auto precharge (Read with Auto Precharge, RDA) command are all "HLH" in the command bits CA0-CA2.

[0079] After a preliminary introduction to the commands, this example implementation is described in detail below with reference to the accompanying drawings and examples.

[0080] Figure 4 shows a schematic circuit diagram of a clock signal generation circuit provided in an embodiment of the present disclosure. As shown in Figure 4, the clock signal generation circuit 20 provided in an embodiment of the present disclosure may include a command pre-decoding circuit 21, a command decoding circuit 22, a counting circuit 23, and a clock signal interception circuit 24. The components of the clock signal generation circuit 20 are described below.

[0081] The command pre-decoding circuit 21 is used to decode part of the command bits in the command X0 to obtain a pre-decoded command signal X1.

[0082] The command X0 may refer to a pending command sent by the storage controller 1 to the semiconductor memory 2. For example, the command X0 may include, but is not limited to, one or more of an MRW command, an MRR command, a WR command, a WRA command, an RD command, and an RDA command, and is not specifically limited thereto.

[0083] In some embodiments, command X0 can be divided into multiple categories of commands with different command characteristics. Each category of commands has the same partial command bits, and the positions / numbers of the same command bits of different categories of commands are different. For example, the first category of commands with command bits CA0-CA4 being "HLLHL". Another example is the second category of commands with command bits CA0-A2 being "HLH". The specific contents of the first category of commands and the second category of commands can be found in the above-mentioned embodiments of the present disclosure in conjunction with the relevant description of Table 1, which will not be repeated here.

[0084] In some embodiments, FIG5 shows a circuit diagram of a command pre-decoding circuit provided by an embodiment of the present disclosure. As shown in FIG5 , the command pre-decoding circuit 21 may include multiple command pre-decoding sub-circuits 211 and a pre-decoding command signal processing sub-circuit 212 .

[0085] Among them, for multiple command pre-decoding sub-circuits 211, different command pre-decoding sub-circuits 211 decode different numbers / positions of command bits, and each command pre-decoding sub-circuit is used to pre-decode the command to obtain a pre-decoded command sub-signal. For example, one command pre-decoding sub-circuit 211 can decode command bits CA0-CA2, while another command pre-decoding sub-circuit 211 decodes command bits CA0-CA4, and the number of command bits decoded by the two is different. For another example, one command pre-decoding sub-circuit 211 can decode command bits CA0-CA2, while another command pre-decoding sub-circuit 211 decodes command bits CA0, CA1, and CA4, and the number of command bits decoded by the two is different.

[0086] Exemplarily, each command predecoding sub-circuit is configured to adjust the output predecoded command sub-signal to a third level when the decoded command bit is at the preset level corresponding to each command bit. Furthermore, when one or more decoded command bits are not at the preset level corresponding to each command bit, the output predecoded command sub-signal is adjusted to a fourth level. One of the third and fourth levels is a high-level signal, and the other is a low-level signal. In one embodiment, the command predecoding circuit 21 may include a first command predecoding circuit 211_1 and a second command predecoding circuit 211_2.

[0087] The first command pre-decoding circuit 211_1 can decode the command bits CA0_CA4, and when the command bits CA0_CA4 are “HLLHL”, the output pre-decoding command sub-signal PRE_CMD1 is pulled high.

[0088] In one example, a circuit diagram of an exemplary command pre-decoding circuit provided by an embodiment of the present disclosure is shown in Figure 6. As shown in Figure 6, the first command pre-decoding circuit 211_1 may include a first NAND gate NAND1, a second NAND gate NAND2, and a first NOR gate NOR1.

[0089] The first NAND gate NAND1 includes a first input terminal A1, a second input terminal B1, a third input terminal C1, and an output terminal Y1. The first input terminal A1 of the first NAND gate NAND1 is used to receive the chip select signal CS_E / O, the second input terminal B1 is used to receive the original value signal CA0T_E / O of the command bit CA0, and the third input terminal C1 is used to receive the negated signal CA1B_E / O of the command bit CA1. When the chip select signal CS_E / O is high (high level, corresponding to a logical value of 1), the command bit C0 is high, and the command bit C1 is low (low level, corresponding to a logical value of 0), the first input terminal A1, the second input terminal B1, and the third input terminal C1 all receive high-level signals, and the output terminal Y1 outputs a low-level signal.

[0090] The second NAND gate NAND2 includes a first input terminal A2, a second input terminal B2, a third input terminal C2, and an output terminal Y2. The first input terminal A2 is used to receive the negated signal CA2B_E / O of the command bit CA2, the second input terminal B2 is used to receive the original value signal CA3T_E / O of the command bit CA3, and the third input terminal C2 is used to receive the negated signal CA4B_E / O of the command bit CA4. When command bit C2 is low, command bit C3 is high, and command bit C4 is low, the first input terminal A2, the second input terminal B2, and the third input terminal C2 all receive a high level, and the output terminal Y2 outputs a low level. In other words, when command bits C2-C4 are low-high, the output terminal Y2 outputs a low level.

[0091] The first NOR gate NOR1 includes a first input terminal A3, a second input terminal B3, and an output terminal Y3. The first input terminal A3 is connected to the output terminal Y1, and the second input terminal B3 is connected to the output terminal Y2. When the output terminals Y1 and Y2 both output a low level, the output terminal Y3 outputs a high level.

[0092] That is, through the first command pre-decoding circuit 211_1 shown in FIG. 6 , when the command bit CS is H and the command bits C0 - C4 are HLLHL, the first command pre-decoding circuit 211_1 outputs a high-level pre-decoding command sub-signal PRE_CMD1 .

[0093] The second command pre-decoding circuit 211_2 can decode the command bit CA0_CA2, and when the command bit CA0_CA2 is “HLH”, the output pre-decoding command sub-signal PRE_CMD2 is pulled high.

[0094] In one example, referring to FIG. 6 , the second command pre-decoding circuit 211_2 includes a third NAND gate NAND3 , a fourth NAND gate NAND4 , and a second NOR gate NOR2 .

[0095] The third NAND gate NAND3 includes a first input terminal A4, a second input terminal B4, and an output terminal Y4. The first input terminal A4 is used to receive the chip select signal CS_E / O, and the second input terminal B4 is used to receive the original value signal CA0T_E / O of the command bit CA0. When the chip select signal CS_E / O is high and the command bit C0 is high, the first input terminal A4 and the second input terminal B4 both receive high-level signals, and the output terminal Y4 outputs a low-level signal.

[0096] The fourth NAND gate NAND4 includes a first input terminal A5, a second input terminal B5, and an output terminal Y5. The first input terminal A5 is used to receive the negated signal CA1B_E / O of the command bit CA1, and the second input terminal B5 is used to receive the original value signal CA2T_E / O of the command bit CA2. When the command bit C1 is low and the command bit C2 is high, the first input terminal A5 and the second input terminal B5 both receive a high level, and the output terminal Y5 outputs a low level.

[0097] The second NOR gate NOR2 includes a first input terminal A6 and an output terminal Y6. The first input terminal A6 is connected to the output terminal Y4, and the second input terminal B6 is connected to the output terminal Y5. When the output terminals Y4 and Y5 both output low levels, the output terminal Y6 outputs a high level.

[0098] That is, through the second command pre-decoding circuit 211_2 shown in FIG. 6 , when the command bit CS is H and the command bits C0 - C2 are HLH, the second command pre-decoding circuit 211_2 outputs a high-level pre-decoding command sub-signal PRE_CMD2 .

[0099] It should be noted that the command pre-decoding sub-circuit 211 can also implement other circuits, devices, and functional modules that can adjust the pre-decoded command sub-signal to the third level when the decoded command bit receives the preset level corresponding to each command bit according to decoding needs. There is no specific limitation on this.

[0100] The pre-decoding command sub-signal processing circuit 212 is connected to the multiple command pre-decoding sub-circuits 211 and is configured to combine the multiple pre-decoding command sub-signals to generate a pre-decoding command signal. Exemplarily, the pre-decoding command sub-signal processing circuit 212 is configured to output a pre-decoding command signal corresponding to a fifth level when one or more pre-decoding command sub-signals are at a third level. Similarly, when all of the multiple pre-decoding command sub-signals are at a fourth level, the pre-decoding command signal is output at a sixth level. One of the fifth and sixth levels is a high level, and the other is a low level.

[0101] In one example, referring to FIG. 6 , the pre-decoding command sub-signal processing circuit 212 may include a third NOR gate NOR3 and a first NOT gate NOT1 .

[0102] The third NOR gate NOR3 includes a first input terminal A7, a second input terminal B7, and an output terminal Y7. The first NOT gate NOT1 includes an input terminal A8 and an output terminal Y8. When the first input terminal A7 and / or the second input terminal B8 receives a high level, the output terminal Y8 outputs a high level.

[0103] It should be noted that the command pre-decoding circuit 21 may also be implemented as other circuits capable of combining multiple pre-decoding command sub-signals, such as an AND gate, etc., and there is no specific limitation on this.

[0104] In one embodiment, the predecoding command sub-signal processing circuit 212 may also receive a predecoding control signal. The predecoding control signal is used to indicate whether predecoding is to be enabled or disabled. Furthermore, when the predecoding control signal indicates enabling predecoding, the circuit may combine multiple predecoding command sub-signals to generate a predecoding command signal.

[0105] In one example, FIG7 shows a circuit diagram of an exemplary pre-decoding command sub-signal processing circuit provided by an embodiment of the present disclosure. As shown in FIG7 , the difference between FIG7 and the pre-decoding command sub-signal processing circuit 212 shown in FIG6 is that the third NOR gate NOR3 may further include a third input terminal C7, which is used to receive the pre-decoding control signal TMF_CLK_GATING_OFF. A high level of the pre-decoding control signal TMF_CLK_GATING_OFF indicates that pre-decoding is turned on, and a low level indicates that pre-decoding is turned off. Since the pre-decoding control signal TMF_CLK_GATING_OFF can indicate whether pre-decoding is turned on or off, accordingly, in this example, flexible control of pre-decoding can be achieved, thereby improving flexible control of the clock signal generation process.

[0106] In the command predecoding circuit 21 provided in the embodiment of the present disclosure, multiple types of commands with different command characteristics can be accurately pre-decoded in advance through the above-mentioned multiple command predecoding sub-circuits 211, so that when any type of command among the multiple types of commands is received, the counter can be accurately and quickly triggered to generate target clock signals corresponding to the commands, thereby improving the generation rate and accuracy of the target clock signal.

[0107] Furthermore, since multiple commands often have the same command bits, the command pre-decoding circuit can be used to effectively pre-decode multiple commands with a small number of command pre-decoding sub-circuits 211, thereby ensuring pre-decoding accuracy while reducing circuit costs.

[0108] Furthermore, it should be noted that the command pre-decoding circuit 21 may also be implemented as other circuits, devices or functional modules that can have a command decoding function, and there is no specific limitation on this.

[0109] After introducing the command pre-decoding circuit 21 , the command decoding circuit 22 will be described next.

[0110] The command decoding circuit 22 is configured to decode the command X0 to generate an internal command signal X2. For example, the internal command signal X2 can be an internal command signal X2 obtained by decoding the command X0 and capable of being processed by the semiconductor memory 2. For example, the internal command signal X2 can be a valid pulse signal for the command X0. For example, FIG8 shows an exemplary signal timing diagram provided by an embodiment of the present disclosure. Taking a write command as an example, the internal command signal X2 can be WR_E / O as shown in FIG8 .

[0111] The command decoding circuit 22 may be implemented as a circuit, a functional module or a device having a command decoding function, and no specific limitation is imposed on this.

[0112] After the command decoding circuit 22 has been introduced, the counter circuit 23 will be described next.

[0113] The counting circuit 23 is used to count clock cycles based on the initial clock signal C0 to generate a first counting signal X3 and a second counting signal X4.

[0114] To facilitate understanding of the counting circuit 23 , before introducing the specific circuit of the counting circuit 23 , the technical terms related to the counting circuit 23 are explained below.

[0115] The initial clock signal C0 may be a periodic clock signal with a unit clock period tCK as a period. For example, the initial clock signal C0 may be the initial clock signal PCLK_E / O output in FIG8 .

[0116] Among them, for the first counting signal X3, the duration of its effective level can be 2 M-1 The unit clock cycle tCK can be obtained by intercepting the active level to obtain 2 M-1 The effective level is the level used to intercept the clock signal, for example, it can be a high level or a low level, and there is no specific limitation on this. In one embodiment, the first counting signal X3 can be at the p×2th level of the initial clock signal. M-1 +1 trigger edge causes a signal flip, and P is a positive integer. For example, taking M=9 as an example, the first counting signal X3 causes a signal flip at the 1st, 257th, 513th, ... trigger edge of the initial clock signal. Accordingly, a clock signal of 256 unit clock cycles can be intercepted through the first counting signal X3. Wherein, M is an integer greater than or equal to 1, 2 M-1 Greater than or equal to the number of clock cycles required by the command.

[0117] For the second counting signal X4, the duration of the effective level can be 2 N-1 The unit clock cycle tCK can be obtained by intercepting the active level to obtain 2 N-1 The effective level is the level used to intercept the clock signal, for example, it can be a high level or a low level, and there is no specific limitation on this. In one embodiment, the first counting signal X3 can be at the p×2th level of the initial clock signal. N-1 +1 trigger edge causes a signal flip, and P is a positive integer. For example, taking N=8 as an example, the first counting signal X3 causes a signal flip at the 1st, 129th, 257th, 385th, ... trigger edge of the initial clock signal. Correspondingly, a clock signal of 128 unit clock cycles can be intercepted through the second counting signal X4. Wherein, N is an integer greater than or equal to 1, N is less than or equal to M, 2 N-1 Greater than or equal to the number of clock cycles required by the command.

[0118] After introducing the technical terms related to the counting circuit 23 , the specific circuit of the counting circuit 23 will be described next.

[0119] In some embodiments, the first counting signal X3 and the second counting signal X4 may be generated by the same counting circuit. For example, the first counting signal X3 and the second counting signal X4 may be obtained by an asynchronous counter formed by cascading multiple stages of DFFs.

[0120] Accordingly, the counting circuit 23 may include: a first counting circuit for generating a first counting signal X3 and a second counting signal X4.

[0121] In one example, FIG9 shows a schematic diagram of a counting circuit provided by an embodiment of the present disclosure. As shown in FIG9 , the first counting circuit 231 may include M stages of first flip-flops DFF11 to DFF1M, wherein the output signal of the first flip-flop of the i-th stage undergoes a signal flip at the p×2i-1+1th trigger edge of the initial clock signal. i is any positive integer less than or equal to M. The output signal of the first flip-flop of the M-th stage is the first counting signal X3, the output signal of the first flip-flop of the N-th stage is the second counting signal, and M and N are integers greater than or equal to 1. Exemplarily, the output signal of the first flip-flop of the M-th stage may be the output signal of the positive output terminal Q of the first flip-flop of the M-th stage, or the output signal of the negative output terminal Q. For example, it can be the output signal of the inverting output terminal. Exemplarily, the trigger edge of the initial clock signal can be a rising edge or a falling edge, which is not specifically limited.

[0122] In one example, for any two adjacent first flip-flops, the positive phase output terminal Q of the previous flip-flop is connected to the clock input terminal of the next flip-flop, and the negative phase output terminal of each flip-flop is connected to the clock input terminal of the next flip-flop. Connected to its own input terminal D, the clock input terminal of the first stage trigger receives the initial clock signal, and the inverting output terminal of the Nth stage trigger The second counting signal X4 is output, and the inverting output terminal Q of the M-th stage trigger outputs the first counting signal X3.

[0123] In a specific example, referring to FIG8 , the output signals from the trigger signal of the first flip-flop DFF11 of the first stage to the positive-phase output terminal of the first flip-flop DFF19 of the ninth stage are Q11 to Q19, respectively. The inverted output signal outputted from the inverting output terminal of the first flip-flop DFF19 of the ninth stage is Q19B.

[0124] Optionally, the first flip-flop of the next stage can undergo a signal flip-flop at each triggering edge of the output signal of the first flip-flop of the previous stage. In a specific example, Figure 10 shows an exemplary timing diagram of the output signals of the first flip-flops of each stage. As shown in Figure 10, the output signal Q1 of the first flip-flop of the first stage can undergo a signal flip-flop at each triggering edge of the initial clock signal C0; the output signal Q2 of the first flip-flop of the second stage can undergo a signal flip-flop at each triggering edge of the output signal Q1; and so on.

[0125] In the embodiment of the present disclosure, the first counting signal X3 and the second counting signal X4 can be generated by different levels of first triggers of the first counting circuit 231, thereby improving the integration of the counting circuit, optimizing the circuit structure, and reducing the circuit cost.

[0126] In one embodiment, the counting circuit 23 may further include a first counting control circuit 232 connected to the first counting circuit 231 .

[0127] The first counting control circuit 232 is configured to receive the initial clock signal C0 and the output signal of the first flip-flop of the Mth stage (the first counting signal X3 or the inverted signal of the first counting signal X3), and to start the first counting circuit to count based on the initial clock signal C0 when the output signal of the first flip-flop of the Mth stage is at a first level. Furthermore, when the output signal of the first flip-flop of the Mth stage is at a second level, the first counting circuit is controlled to stop counting. One of the first level and the second level is a high level, and the other is a low level. For example, the first level may be a high level, and the second level may be a low level.

[0128] In one example, a circuit diagram of a counting circuit is shown in FIG11 . As shown in FIG11 , the first counting control circuit 232 may include a second NOT gate NOT2 , a fifth NAND gate NAND5 , and a third NOT gate NOT3 .

[0129] The second NOT gate NOT2 is used to invert the initial clock signal C0 to obtain a negated signal of the initial clock signal C0. A fifth NAND gate NAND5 receives the negated signal of the initial clock signal C0 at one end and the output signal of the first flip-flop of the Mth stage at the other end. When the output signal of the first flip-flop of the Mth stage is at a high level, the negated signal of the initial clock signal C0 is input to the clock input of the first flip-flop of the first stage. For example, when counting is started at a low level and ended at a high level, the first counting control circuit 232 may not include the third NOT gate NOT3.

[0130] It should be noted that the first counting control circuit 232 can also be implemented as other circuits, devices or functional modules that can control the first counting circuit 231 to start or end counting according to the output signal of the first trigger of the Mth level, and there is no specific limitation on this.

[0131] Through the first counting control circuit 232 provided in this embodiment, the counting process can be accurately controlled according to the level of the output signal of the first trigger of the Mth level. Through the output signal of the first trigger of the Mth level, the counting function can be quickly turned off after the counting requirement is completed, thereby improving the counting efficiency and reducing the power consumption of the memory.

[0132] In one embodiment, in order to optimize the signal quality of the output signal of the M-th stage first trigger received by the first counting control circuit 232 , the counting circuit may further include an output signal adjustment circuit 233 and / or a signal driving module 234 .

[0133] As for the output signal adjustment circuit 233, it is used to use the initial clock signal C0 to adjust the output signal QOUTED_E / O_1 of the first trigger of the Mth stage, so that the signal edge of the output signal QOUTED_E / O_2 of the adjusted first trigger of the Mth stage is aligned with the signal edge of the initial clock signal C0, and the output signal QOUTED_E / O_2 of the adjusted first trigger of the Mth stage is provided to the first counting control circuit 232.

[0134] In one example, referring again to FIG11 , the output signal conditioning circuit 233 may include multiple fourth flip-flops, such as a fourth flip-flop DFF21 and a fourth flip-flop DFF22. The clock inputs of the multiple fourth flip-flops are configured to receive an initial clock signal C0, the positive phase output of the preceding flip-flop of any two adjacent fourth flip-flops is connected to the input of the succeeding flip-flop, the input of the first fourth flip-flop is configured to receive the output signal QOUTED_E / O_1 of the first flip-flop of the Mth stage, and the positive phase output of the last fourth flip-flop is configured to output the conditioned output signal QOUTED_E / O_2 of the first flip-flop of the Mth stage.

[0135] Through the output signal adjustment circuit 233, the output signal QOUTED_E / O_2 aligned with the edge of the initial clock signal C0 can be provided to the first counting control circuit 232, so that the first counting control circuit can provide the first counting circuit with a complete initial clock cycle C0 under the control of the output signal QOUTED_E / O_2, thereby further improving the counting accuracy.

[0136] It should be noted that the output signal adjustment circuit 233 may also be other circuits, devices or functional modules that align the edges of two signals, and there is no specific limitation on this.

[0137] The signal driving circuit 234 is used to increase the driving capability of the output signal QOUTED_E / O_1 of the first flip-flop of the Mth stage. In one example, referring to FIG11 , the signal driving circuit 234 may include a fourth NOT gate NOT4 and a fifth NOT gate NOT5.

[0138] It should be noted that the signal driving circuit 234 may also be other circuits, devices or functional modules that can enhance the signal driving capability, and there is no specific limitation on this.

[0139] In some other embodiments, the first counting signal X3 and the second counting signal X4 may be generated by different counting circuits. Accordingly, the counting circuit 23 may include a second counting circuit 235 and a third counting circuit 236 .

[0140] In one example, FIG12 shows a circuit diagram of another counting circuit provided by an embodiment of the present disclosure. As shown in FIG12 , the second counting circuit 235 may include M stages of second flip-flops DFF31 to DFF3M. The output signal of the j-th stage second flip-flop is at the p×2-th stage of the initial clock signal. j-1+1 trigger edge causes a signal flip, and the output signal of the second flip-flop of the Mth stage (the inverting output signal or the non-inverting output signal of the second flip-flop of the Mth stage) is the first counting signal X3, where j is any positive integer less than or equal to M, and p is any positive integer. The connection method of the second flip-flops DFF31 to DFF3M of the Mth stage is similar to that of the first flip-flops DFF11 to DFF1M of the Mth stage, and a detailed description thereof is omitted.

[0141] 12, the third counting circuit 236 may include N stages of third flip-flops DFF41 to DFF4N, wherein the output signal of the k-th stage third flip-flop is at the p×2-th stage of the initial clock signal. k-1 A signal flip occurs after +1 trigger edge, and the output signal of the third counter of the Nth stage (the inverting output signal or the non-inverting output signal of the third counter of the Nth stage) becomes the second counting signal, where k is any positive integer less than or equal to N. The connection method of the third flip-flops DFF41 to DFF4N of the Nth stage is similar to that of the first flip-flops DFF11 to DFF1M of the Mth stage, and a detailed description thereof is omitted.

[0142] The second counting circuit 235 and the third counting circuit 236 described above can independently and accurately generate the first counting signal X3 and the second counting signal X4, thereby improving the accuracy of the counting signal generation. Optionally, to reduce circuit costs, different commands can share the same second counting circuit 235 to generate the same first counting signal. Optionally, to further reduce semiconductor dynamic power consumption and provide flexibility in the generated target counting signal, different commands can use their own third counting circuit 236 to generate their respective required second counting signal X4.

[0143] Optionally, the counting circuit may further include a second counting control circuit connected to the second counting circuit 235 and / or a third counting control circuit connected to the third counting circuit 236 .

[0144] The second counting control circuit can be configured to receive an initial clock signal and an output signal of the second flip-flop of the Mth stage, and to start the second counting circuit to count based on the initial clock signal when the output signal of the second flip-flop of the Mth stage is at a first level; and to control the second counting circuit to stop counting when the output signal of the second flip-flop of the Mth stage is at a second level. The second counting control circuit is similar to the first counting control circuit described above, and reference can be made to the description of the first counting control circuit in the above-mentioned embodiments of the present disclosure, which will not be repeated here.

[0145] A third counting control circuit is connected to the third counting circuit and is configured to receive the first intercepted clock signal and the output signal of the third flip-flop of the Nth stage. The third counting control circuit is configured to start the third counting circuit to count based on the first intercepted clock signal when the output signal of the third flip-flop of the Nth stage is at a first level; and to control the third counting circuit to stop counting when the output signal of the third flip-flop of the Nth stage is at a second level. The third counting control circuit is similar to the first counting control circuit described above. Please refer to the description of the first counting control circuit in the above-mentioned embodiments of the present disclosure, and no further description will be given. Optionally, the third counting control circuit can also count based on the initial clock signal C0, which is not specifically limited.

[0146] The second counting control circuit provided in this embodiment can accurately control the counting process based on the level of the output signal of the second flip-flop of the Mth stage. The output signal of the second flip-flop of the Mth stage can quickly shut down the counting function after the counting requirement is met, thereby improving counting efficiency and reducing memory power consumption. Furthermore, the third counting control circuit provided in this embodiment can accurately control the counting process based on the level of the output signal of the third flip-flop of the Nth stage. The output signal of the third flip-flop of the Nth stage can quickly shut down the counting function after the counting requirement is met, thereby improving counting efficiency and reducing memory power consumption.

[0147] In one embodiment, an output signal conditioning circuit and / or a signal driving circuit may be included between the output terminal of the second trigger of the Mth stage of the second counting circuit and the second counting control circuit. For details, please refer to the description of the signal conditioning circuit and the signal driving circuit in the above-mentioned embodiments of the present disclosure, and will not be repeated here.

[0148] In one embodiment, an output signal adjustment circuit and / or a signal driving circuit may be further included between the output end of the third trigger of the Nth stage of the third counting circuit and the third counting control circuit. In one example, the output signal adjustment circuit can be used to adjust the output signal QOUTED_E / O of the third trigger of the Nth stage using a first intercepted clock signal (such as PCLK_E / O_1 shown in FIG8 ). In addition, the signal driving circuit can enhance the driving capability of the output signal QOUTED_E / O of the third trigger of the Nth stage. It should be noted that other contents of the output signal adjustment circuit and the signal driving circuit can refer to the relevant description of the signal adjustment circuit and the signal driving circuit in the above part of the embodiment of the present disclosure, and will not be repeated here.

[0149] It should be noted that the counting circuit 23 may also be implemented as other circuits, devices or functional modules that can generate the first counting signal X3 and the second counting signal X4, and there is no specific limitation on this.

[0150] After introducing the counting circuit 23 , the clock signal interception circuit 24 will be described next.

[0151] The clock signal interception circuit 24 is connected to the command pre-decoding circuit 21, the command decoding circuit 22 and the counting circuit 23, and is used to intercept the initial clock signal C0 according to the pre-decoding command signal X1, the internal command signal X2, the first counting signal X3 and the second counting signal X4 to obtain the target clock signal Cx.

[0152] The target clock signal Cx may refer to a clock signal used to execute the corresponding functional operation of command X0. For example, the target clock signal Cx may be a clock signal having a unit clock cycle as a period, and a number of cycles greater than or equal to the required number of clock cycles. For example, taking the WR command as an example, the target clock signal Cx may be the signal PCLK_WR_E / O shown in FIG8 .

[0153] In some embodiments, FIG13 shows a circuit diagram of a clock signal interception circuit provided by an embodiment of the present disclosure. As shown in FIG13 , the clock signal interception circuit 24 may include a first clock signal interception circuit 241 and a second clock signal interception circuit 242 .

[0154] The first clock signal interception circuit 241 is connected to the command pre-decoding circuit 21 and the counting circuit 23, and is used to intercept at least part of the initial clock signal C0 (the clock signal to be intercepted by the first clock signal interception circuit 241) according to the pre-decoding command signal X1 and the first counting signal X3 to generate a first intercepted clock signal C2. For example, the first intercepted clock signal C2 can be a signal including 2 M-1 A clock signal having a unit clock cycle. For example, when M is equal to 9, the first intercepted clock signal C2 can be a clock signal having 256 tCKs, such as PCLK_E / O_1 shown in FIG8 . Optionally, to improve clock signal utilization, the number of cycles per unit clock cycle of the first intercepted clock signal C2 is greater than or equal to the number of clock cycles required for each command. Exemplarily, the number of cycles per unit clock cycle of the first intercepted clock signal C2 can be 256 tCKs.

[0155] In one embodiment, FIG14 shows a circuit diagram of an exemplary clock signal interception circuit provided by an embodiment of the present disclosure. As shown in FIG14 , the first clock signal interception circuit 241 may include an intercepted pulse signal generation circuit 2411 and an intercepted clock signal generation circuit 2412 .

[0156] For the intercepted pulse signal generating circuit 2411 in the first clock signal intercepting circuit 241, it includes a command signal input terminal, a counting signal input terminal and an intercepted pulse output terminal. Among them, the command signal input terminal is used to obtain the pre-decoding command signal X1, and the counting signal input terminal is used to obtain the first counting signal X3. The intercepted pulse signal generating circuit 2411 is used to generate the intercepted pulse signal P1 according to the signal obtained by the command signal input terminal (i.e., the pre-decoding command signal X1) and the signal obtained by the counting signal input terminal (i.e., the first counting signal X3). Exemplarily, the effective level starting moment (first effective signal edge) of the intercepted pulse signal P1 can be generated according to the transition edge of the pre-decoding command signal X1, and the effective level ending moment (second effective signal edge) of the intercepted pulse signal P1 can be generated based on the transition edge of the first counting signal. In one example, referring to Figure 8, the intercepted pulse signal net2_1 can be generated according to the pre-decoding command signal CMD_GATING and the first counting signal Q19B.

[0157] In one example, a circuit diagram of an intercept pulse signal generation circuit provided by an embodiment of the present disclosure is shown in Figure 15. As shown in Figure 15, the intercept pulse signal generation circuit 2411 may include a pulse generation circuit 2411A and a pulse signal adjustment circuit 2411B.

[0158] The pulse generating circuit 2411A can be used to generate a target pulse signal net1 based on the signal obtained from the command signal input terminal of the intercepted pulse signal generating circuit 2411 (i.e., the pre-decoding command signal X1) and the signal obtained from the counting signal input terminal of the intercepted pulse signal generating circuit (i.e., the first counting signal X3).

[0159] The effective level start time of the target pulse signal net1 is based on the transition edge of the signal (i.e., the pre-decoding command signal X1) obtained at the command signal input terminal of the intercepted pulse signal generating circuit, and the effective level end time of the target pulse signal is based on the transition edge of the signal (i.e., the first counting signal X3) obtained at the count signal input terminal of the intercepted pulse signal generating circuit. For example, the first effective signal edge of the target pulse signal net1 can be aligned with the transition edge (rising edge or falling edge) of the pre-decoding command signal X1 or there is a preset allowable deviation; the second effective signal edge of the target pulse signal net1 can be aligned with the transition edge of the first counting signal or there is a preset allowable deviation. Continuing to refer to Figure 8, the rising edge of the target pulse signal net1 is aligned with the pre-decoding command signal CMD_GATING, and the falling edge of the target pulse signal net1 is aligned with the rising edge of the first counting signal Q19B.

[0160] In a specific example, referring to Figure 15, the pulse generating circuit 2411A may include an SR trigger. Among them, the set end of the SR trigger is used to receive the negation signal of the pre-decoding command signal (when the pre-decoding command signal uses the rising edge as the trigger edge), and the reset end of the SR trigger is used to receive the negation signal of the first counting signal (when the first counting signal uses the low level as the valid level signal). Through this embodiment, referring to Figure 8, when the pre-decoding command signal CMD_GATING is pulled up to a high level (i.e., a rising edge), the set end of the SR trigger is set low, so that the output end of the SR trigger can be pulled up to a high level. And, when the first counting signal Q19B is pulled up to a high level, the reset end of the SR trigger is set low, and at this time the output end of the SR trigger can be pulled down to a low level. Thus, the target pulse signal net1 can be accurately generated by the SR trigger. It should be noted that when the pre-decoding command signal uses the rising edge as the trigger edge, the set end of the SR trigger is used to receive the original value signal of the pre-decoding command signal, and when the first counting signal uses a high level as the valid level signal, the reset end of the SR trigger is used to receive the original value signal of the first counting signal.

[0161] Optionally, when the set end of the SR trigger receives the inverted signal of the pre-decoding command signal, the pulse generating circuit 2411A may further include a sixth NOT gate NOT6 to receive the pre-decoding command signal and invert it to obtain the inverted signal of the pre-decoding command signal.

[0162] Optionally, when the reset terminal of the SR flip-flop receives the negation signal of the first count signal, the pulse generating circuit 2411A may further include a fourth NOR gate NOR4, which may receive the reset signal RESET and the first count signal X3 and output the negation signal of the first count signal X3 when the reset signal is at a low level. Alternatively, the reset terminal of the SR flip-flop may be connected to an odd number of NOT gates to provide the negation signal of the first count signal X3 to the reset terminal of the SR flip-flop.

[0163] It should be noted that the pulse generating circuit 2411 can also be implemented as other circuits, devices, functional modules, etc. that can generate a target pulse signal based on the pre-decoding command signal X1 and the first counting signal X3, and there is no specific limitation on this.

[0164] As for the pulse signal adjustment circuit 2411B, it can be connected to the pulse generation circuit 2411, and is used to adjust the pulse width of the target pulse signal according to the initial clock signal C0 (the clock signal to be intercepted by the first clock signal interception circuit 241), and use the target pulse signal after width adjustment as the intercepted pulse signal.

[0165] In one example, the pulse signal adjustment circuit 2411B may include a pulse extension sub-circuit 2411B_1 and a pulse adjustment sub-circuit 2411B_2 .

[0166] For the pulse extension sub-circuit 2411B_1, it can be used to use the pulse extension signal (such as the pulse extension signal CS_MASK_E / O in Figure 15) to pre-adjust the effective level starting time of the target pulse signal to generate a target pulse signal after the time is pre-adjusted. Among them, the effective level starting time of the target pulse signal can refer to the starting time of the level used for clock signal interception. Exemplarily, the pulse extension signal CS_MASK_E / O can be a pulse signal with a duration of 8tCK, and the command / address (C / A) information can be collected within the duration of the pulse extension signal CS_MASK_E / O.

[0167] In a specific example, referring again to FIG15 , pulse stretching subcircuit 2411B_1 can include a fifth NOR gate NOR5. For example, FIG16 illustrates an exemplary logic diagram for processing a target pulse signal according to an embodiment of the present disclosure. As shown in FIG16 , the fifth NOR gate NOR5 can be used to pre-adjust the effective level start time of target pulse signal net1 using pulse stretching signal CS_MASK_E / O, resulting in a pre-adjusted target pulse signal net2_0.

[0168] It should be noted that the pulse expansion sub-circuit 2411B_1 can also be implemented as other circuits, devices, functional modules, etc. that can pre-adjust the effective level starting time of the target pulse signal based on the pulse expansion signal CS_MASK_E / O, and there is no specific limitation on this.

[0169] The pulse adjustment sub-circuit 2411B_2 is connected to the pulse expansion sub-circuit 2411B_1 and is used to adjust the pulse width of the target pulse signal after the moment is advanced according to the clock signal to be intercepted (the initial clock signal C0 in the first clock signal interception circuit 241) to obtain an intercepted pulse signal with a complete cycle.

[0170] For example, referring again to FIG. 15 , the pulse adjustment sub-circuit 2411B_2 may include a half-latch H1. The input of half-latch H1 is used to receive the target pulse signal net2_0 after time adjustment, and the clock trigger terminal of half-latch H1 is used to receive the negated signal of the clock signal to be intercepted (initial clock signal C0 in the first clock signal interception circuit 241). By reversely connecting the clock signal to be intercepted to half-latch H1, that is, latching the clock signal to be intercepted at an active low level, and subsequently performing a negative OR operation with the output of half-latch H1 and the clock signal to be intercepted, the intercepted signal is guaranteed to be a continuous pulse clock signal with a complete cycle of rising edges after the clock signal to be intercepted is initially latched at a low level, thus avoiding the phenomenon of an incomplete first valid clock pulse cycle.

[0171] It should be noted that the pulse adjustment sub-circuit 2411B_2 can also be implemented as other circuits, devices or functional modules that can adjust the pulse width of the clock signal, and there is no specific limitation on this.

[0172] The pulse stretching subcircuit 2411B_1 provided in this example can pre-adjust the effective level start time of the target pulse signal, allowing the effective level start time of the intercepted pulse signal to be earlier than the earliest operation time of the command. This ensures that the intercepted target clock signal fully covers the required operation time of the command, thereby ensuring normal use of the memory. Furthermore, the pulse adjustment subcircuit 2411B_2 ensures the cycle integrity of the intercepted target clock signal, improving the quality of the generated clock signal.

[0173] In another example, the pulse signal adjustment circuit 2411B may include one of a pulse extension subcircuit 2411B_1 and a pulse adjustment subcircuit 2411B_2. For example, when the pulse extension subcircuit 2411B_1 is included, the target pulse signal after the time advance can be used as the intercepted pulse signal. For another example, when the pulse adjustment subcircuit 2411B_2 is included, the pulse width of the target pulse signal that has not been forward-adjusted can be adjusted according to the clock signal to be intercepted (the initial clock signal C0 in the first clock signal interception circuit 241) to obtain an intercepted pulse signal with a complete period. It should be noted that its specific content can be found in the relevant description of the above part of this embodiment, and will not be repeated here.

[0174] It should be noted that the pulse signal adjustment circuit 2411B can also be implemented as other circuits, devices, functional modules, etc. that can adjust the target pulse signal, and there is no specific limitation on this.

[0175] In this embodiment, the pulse generating circuit 2411A and the pulse signal adjusting circuit 2411B can accurately generate an intercepted pulse signal that meets the requirements, and then accurately intercept the target clock signal, thereby improving the quality of the generated clock signal.

[0176] In another example, the intercepted pulse signal generating circuit 2411 can be specifically implemented as a pulse generating circuit 2411A. Accordingly, the target pulse signal net1 can be used as the intercepted pulse signal. This example allows for rapid generation of the intercepted pulse signal, thereby increasing the speed of generating the target clock signal. It also simplifies the circuit structure and reduces circuit cost.

[0177] It should be noted that the intercepted pulse signal generating circuit 2411 can also be implemented as other circuits, devices or functional modules that can generate intercepted pulse signals for clock signal interception, and there is no specific limitation on this.

[0178] The intercepted clock signal generation circuit 2412 in the first clock signal interception circuit 241 includes an intercepted pulse signal input terminal, a clock signal to be intercepted input terminal, and an intercepted clock output terminal. The intercepted pulse signal input terminal is connected to the intercepted pulse output terminal. The clock signal to be intercepted input terminal is used to obtain the clock signal to be intercepted (the initial clock signal C0 in the first clock signal interception circuit 241). The intercepted clock signal generation circuit is used to intercept at least a portion of the initial clock signal C0 (the clock signal to be intercepted in the first clock signal interception circuit 241) based on the intercepted pulse signal P1 to generate a first intercepted clock signal C2, and output the first intercepted clock signal C2 through the intercepted clock output terminal.

[0179] In one example, FIG17 shows a circuit diagram of an exemplary intercepted clock signal generating circuit provided by an embodiment of the present disclosure. As shown in FIG17 , the intercepted clock signal generating circuit 2412 in the first clock signal intercepting circuit 241 may include a sixth NOR gate NOR6 and an eighth NOT gate NOT8. Among them, one end of the sixth NOR gate receives the inverted signal of the intercepted pulse signal P1 (when the effective level of the intercepted pulse signal P1 is a low level), and the other end receives the initial clock signal C0 (the clock signal to be intercepted of the first clock signal intercepting circuit 241). When the inverted signal of the intercepted pulse signal P1 is a high level, the eighth NOT gate NOT8 outputs the intercepted clock signal. It should be noted that when the effective level of the intercepted pulse signal P1 is a high level, one end of the sixth NOR gate of the first clock signal intercepting circuit receives the original value signal of the intercepted pulse signal P1.

[0180] It should be noted that the intercepted clock signal generating circuit 2412 can also be implemented as other circuits, devices or functional modules that can have a signal interception function, and there is no specific limitation on this.

[0181] By intercepting the pulse signal generating circuit 2411 and the intercepting clock signal generating circuit 2412, the clock signal can be accurately intercepted, thereby improving the accuracy of the target clock signal.

[0182] In another embodiment, Figure 18 shows a circuit diagram of an exemplary signal shielding circuit provided by an embodiment of the present disclosure. As shown in Figure 18, the first clock signal interception circuit 241 may further include a signal shielding circuit 2413. The input end of the signal shielding circuit 2413 is connected to the output end of the intercepted pulse signal generating circuit, for receiving the mode signal CONTI_MODE and the intercepted pulse signal P1. The output end of the signal shielding circuit is used to connect the input end of the clock signal interception circuit, for shielding or outputting the intercepted pulse signal based on the mode signal CONTI_MODE. Exemplarily, when the mode signal CONTI_MODE is at a valid level, the intercepted pulse signal can be shielded. When the mode signal CONTI_MODE is at an invalid level, the inverted signal or the original value signal of the intercepted pulse signal can be output.

[0183] In a specific example, referring to FIG18 , the signal shielding circuit 2413 may include a seventh NOR gate NOR7. Accordingly, the valid level of the mode signal CONTI_MODE is a high level, and the invalid level is a low level. For example, when the mode signal CONTI_MODE is at a low level, a negated signal of the intercepted pulse signal may be output. Through the signal shielding circuit 2414, the interception process of the clock signal may be effectively controlled by the mode signal CONTI_MODE, thereby improving the control accuracy of the clock signal generation process.

[0184] It should be noted that the signal shielding circuit 2413 may also adopt other circuits, devices or functional modules with signal shielding functions, and there is no specific limitation on this.

[0185] After introducing the first clock signal interception circuit 241 , the second clock signal interception circuit 242 will be described next.

[0186] The second clock signal interception circuit 242 is connected to the first clock signal interception circuit 241, the command decoding circuit 22 and the counting circuit 23, and is used to intercept at least part of the first intercepted clock signal C2 according to the internal command signal X2 and the second counting signal X4 to generate the target clock signal Cx.

[0187] As for the target clock signal Cx, in one example, the first intercepted clock signal C2 may be intercepted to generate the target clock signal Cx. In another example, the initial clock signal C0 may be intercepted to generate the target clock signal Cx.

[0188] In some embodiments, different commands have different target clock signal Cx cycles, and accordingly, different commands have different N cycles. For example, for a WRA command requiring 168 tCK, its target clock signal may include 256 tCK, and accordingly, N may be 9. For another example, for an MRW command requiring 16 tCK, its target clock signal may include 16 tCK or 32 tCK, and accordingly, N may be 5 or 6.

[0189] In one embodiment, the second clock signal interception circuit 242 may include an intercepted pulse signal generation circuit 2411 and an intercepted clock signal generation circuit 2412 .

[0190] The intercepted pulse signal generation circuit 2411 in the second clock signal interception circuit 242 includes a command signal input terminal, a count signal input terminal, and an intercepted pulse output terminal. The command signal input terminal is used to obtain the internal command signal X2, and the count signal input terminal is used to obtain the second count signal X4. The intercepted pulse signal generation circuit 2411 is configured to generate an intercepted pulse signal P1 based on the signal obtained from the command signal input terminal (i.e., the internal command signal X2) and the signal obtained from the count signal input terminal (i.e., the second count signal X4).

[0191] The intercepted clock signal generating circuit 2412 in the second clock signal intercepting circuit 242 includes an intercepted pulse signal input terminal, a clock signal to be intercepted input terminal, and an intercepted clock output terminal. The intercepted pulse signal input terminal is connected to the intercepted pulse output terminal, the clock signal to be intercepted input terminal is used to obtain the first intercepted clock signal C2 (or the initial clock signal C0 can be obtained), and the intercepted clock signal generating circuit is used to intercept at least part of the first intercepted clock signal C2 (or the initial clock signal C0 can be obtained) obtained by the clock signal to be intercepted input terminal according to the intercepted pulse signal P1, generate a target clock signal Cx, and output the target clock signal Cx through the intercepted clock output terminal. It should be noted that the specific contents of the intercepted pulse signal generating circuit 2411 and the intercepted clock signal generating circuit 2412 can be found in the relevant description of the above part of the embodiment of the present disclosure, and will not be repeated here.

[0192] Through the first clock signal interception circuit 241 and the second clock signal interception circuit 242 of the embodiment of the present disclosure, the target clock signal can be further intercepted using the second count signal X4 based on the first intercepted clock signal intercepted by the first count signal X3, which can further reduce the redundant cycle clocks in the target clock signal, thereby further avoiding the dynamic loss of the memory caused by the redundant cycle clocks constantly flipping due to the mismatch between the clock cycle and the command during the command operation, thereby further reducing the dynamic loss of the memory. It should be noted that the clock signal interception circuit of the embodiment of the present disclosure can also be implemented as other circuits, devices or functional modules that can intercept and obtain the target clock signal, which will not be described in detail.

[0193] In some embodiments, the clock signal generating circuit further includes a set signal generating circuit 25 .

[0194] When the set signal generation circuit 25 is used to set the second flip-flop of the second counting circuit, the set signal generation circuit 25 is used to generate a set signal for the second flip-flop based on the pre-decoded command signal and the reset signal RESET. For example, FIG19 shows a schematic diagram of the first portion of the clock signal generation circuit provided in an embodiment of the present disclosure. As shown in FIG19 , the set signal generation circuit 25 may include a seventh NOR gate NOR7 and a ninth NOT gate NOT9 to generate the second flip-flop set signal RESD_E / O_1.

[0195] When the set signal generation circuit 25 is used to set the third flip-flop of the third counting circuit, the set signal generation circuit 25 is used to generate a set signal for the third flip-flop based on the internal command signal and the reset signal RESET. For example, FIG20 shows a schematic diagram of the second portion of the clock signal generation circuit provided in an embodiment of the present disclosure. As shown in FIG20 , the set signal generation circuit 25 can generate the third flip-flop set signal RESD_E / O based on the internal command signal.

[0196] The clock signal generating circuit provided by the embodiment of the present disclosure, after decoding a part of the command bits of the command based on the command pre-decoding circuit to obtain the pre-decoding command, parsing the command decoding circuit to obtain the internal command signal, and counting the clock cycles of the initial clock signal by the counting circuit to generate the first counting signal and the second counting signal, because the pre-decoding command signal and the internal command signal are related to the command, and because the first counting signal and the second counting signal are obtained by counting the initial clock signal, a part of the initial clock signal can be intercepted according to the pre-decoding command signal, the internal command signal, and the counting results of the first counting signal and the counting results of the second counting signal to obtain the target clock signal that matches the command. Since the target clock signal of each command can match each command, compared with the technical solution of using the same clock signal for each command, the dynamic loss of the memory caused by the constant flipping of the redundant cycle clock due to the mismatch between the clock cycle and the command during the command operation is avoided, thereby reducing the dynamic loss of the memory.

[0197] In some embodiments, referring to Figures 19 and 20 , taking the WR command as an example, the first circuit section is used to generate a first intercepted clock signal PCLK_E / O_1 based on the initial clock signal PCLK_E / O. A second count control circuit 237 is connected to a second count circuit 235. A second circuit section is used to generate a target clock signal PCLK_WR_E / O based on the first intercepted clock signal PCLK_E / O_1. A third count control circuit 238 is connected to a third count circuit 236. The components of the first and second circuit sections can be found in the above description of the embodiments of the present disclosure, and will not be further elaborated upon.

[0198] It should be noted that Figures 19 and 20 illustrate circuit diagrams in which the first and second count signals are generated by different counter circuits. When the first and second count signals are generated by the same counter circuit, the second circuit portion may not include the third counter circuit 236, the third count control circuit 238 connected to the third counter circuit 236, the output signal conditioning circuit 233, and the signal driver module 234. Accordingly, the second counter circuit 235 may provide the second count signal to the second clock signal interception circuit 242.

[0199] In one embodiment, the command decoding circuit may further include a decoding control circuit 221. The decoding control circuit 221 may also receive a decoding control signal. The decoding control signal is used to indicate whether decoding should be enabled or disabled. Furthermore, when the decoding control signal indicates enabling decoding, the circuit provides an internal command signal to the clock signal interception circuit. For example, the decoding control signal may be the same as the pre-decoding control signal, such as the control signal TMF_CLK_GATING_OFF.

[0200] In one example, referring again to FIG. 20 , the decoding control circuit 221 may include an eighth NOR gate NOR8 and a tenth NOT gate NOT10. A first input of the eighth NOR gate NOR8 is configured to receive a decoding control signal, and a second input of the eighth NOR gate NOR8 is configured to receive an internal command signal WR_E / O. An output of the eighth NOR gate NOR8 is connected to an input of the tenth NOT gate NOT10.

[0201] Based on the same inventive concept, an embodiment of the present disclosure further provides a clock signal generation method, as shown in the following embodiment.

[0202] FIG21 shows a flow chart of a clock signal generating method in an embodiment of the present disclosure. As shown in FIG21 , the clock signal generating method includes S2110 to S2130 .

[0203] S2110 , the command decoding circuit decodes the input command to obtain an internal command signal.

[0204] S2120: The counting circuit counts clock cycles based on the initial clock signal to generate a counting signal.

[0205] S2130: The clock signal interception circuit intercepts the initial clock signal according to the internal command signal and the counting signal to obtain a target clock signal.

[0206] In some embodiments, before step S2110, the clock signal generation method may further include step D1. In step D1, the command pre-decoding circuit decodes part of the command bits in the command to obtain a pre-decoded command signal.

[0207] In one embodiment, step D1 includes step D11 and step D12.

[0208] In step D11 , each command pre-decoding sub-circuit pre-decodes the command to obtain a pre-decoded command sub-signal.

[0209] Step D12: The pre-decoding command sub-signal processing circuit combines the multiple pre-decoding command sub-signals to generate a pre-decoding command signal.

[0210] In some embodiments, S2120 may specifically include: a counting circuit counting clock cycles based on the initial clock signal to generate a first count signal and a second count signal. Accordingly, S2130 may specifically include: intercepting the initial clock signal based on the pre-decoded command signal, the internal command signal, the first count signal, and the second count signal to obtain a target clock signal.

[0211] In some embodiments, S2130 includes step D21 and step D22.

[0212] In step D21 , the first clock signal interception circuit intercepts at least a portion of the initial clock signal according to the pre-decoding command signal and the first counting signal to generate a first intercepted clock signal.

[0213] In step D22 , the second clock signal interception circuit intercepts at least a portion of the first intercepted clock signal according to the internal command signal and the second counting signal to generate a target clock signal.

[0214] In some embodiments, step D21 includes steps D211 to D213.

[0215] Step D211 , intercepting the pulse signal generating circuit to obtain the pre-decoding command signal and the first counting signal.

[0216] In step D212 , the interception pulse signal generating circuit generates an interception pulse signal according to the pre-decoding command signal and the first counting signal.

[0217] In step D213, the intercepted clock signal generation circuit obtains the initial clock signal, intercepts at least part of the initial clock signal according to the intercepted pulse signal, generates a first intercepted clock signal, and outputs the first intercepted clock signal through the intercepted clock output terminal.

[0218] In one embodiment, step D212 includes step D2121 and step D2122.

[0219] In step D2121 , the pulse generating circuit generates a target pulse signal according to the pre-decoding command signal and the first counting signal.

[0220] In step D2122 , the pulse signal adjustment circuit adjusts the pulse width of the target pulse signal according to the initial clock signal, and uses the target pulse signal after the width adjustment as the intercepted pulse signal.

[0221] In one example, step D2122 includes: the pulse expansion sub-circuit uses the pulse expansion signal to advance the effective level starting time of the target pulse signal to generate the target pulse signal after the time is advanced; the pulse adjustment sub-circuit adjusts the pulse width of the target pulse signal after the time is advanced according to the initial clock signal to obtain an intercepted pulse signal with a complete period.

[0222] In one embodiment, step D214 is further included between step D212 and step D213.

[0223] In step D214 , the signal shielding circuit receives the mode signal and the intercepted pulse signal to shield or output the intercepted pulse signal to the clock signal intercepting circuit based on the mode signal.

[0224] In some embodiments, step D22 includes steps D221 to D223.

[0225] Step D221 , intercepting the pulse signal generating circuit to obtain the internal command signal and the second counting signal.

[0226] Step D222: The interception pulse signal generating circuit generates an interception pulse signal according to the internal command signal and the second counting signal.

[0227] In step D223, the intercepted clock signal generation circuit obtains the first intercepted clock signal (or initial clock signal), intercepts at least part of the first intercepted clock signal (or initial clock signal) according to the intercepted pulse signal, generates a target clock signal, and outputs the target clock signal through the intercepted clock output terminal.

[0228] In one embodiment, step D222 includes step D2221 and step D2222.

[0229] In step D2221 , the pulse generating circuit generates a target pulse signal according to the internal command signal and the second counting signal.

[0230] In step D2222, the pulse signal adjustment circuit adjusts the pulse width of the target pulse signal according to the first intercepted clock signal (or the initial clock signal), and uses the target pulse signal after the width adjustment as the intercepted pulse signal.

[0231] In one example, step D2222 includes: the pulse extension sub-circuit uses the pulse extension signal to advance the effective level starting time of the target pulse signal to generate the target pulse signal after the time is advanced; the pulse adjustment sub-circuit adjusts the pulse width of the target pulse signal after the time is advanced according to the first intercepted clock signal (or initial clock signal) to obtain an intercepted pulse signal with a complete period.

[0232] In one embodiment, step D224 is further included between step D222 and step D223. In step D224, the signal shielding circuit receives the mode signal and the intercepted pulse signal to shield or output the intercepted pulse signal to the clock signal intercepting circuit based on the mode signal.

[0233] In some embodiments, S2130 includes step D23. In step D23, the first clock signal interception circuit intercepts at least a portion of the initial clock signal according to the pre-decoding command signal and the first counting signal to obtain a target clock signal.

[0234] In some embodiments, when the counting circuit includes a first counting circuit, the clock signal generating method further includes step D31. In step D31, the first counting control circuit receives an initial clock signal and an output signal of a first flip-flop of the Mth stage, and when the output signal of the first flip-flop of the Mth stage is at a first level, starts the first counting circuit to count based on the initial clock signal; and when the output signal of the first flip-flop of the Mth stage is at a second level, controls the first counting circuit to stop counting.

[0235] In some embodiments, when the counting circuit includes a second counting circuit, the clock signal generating method further includes step D32. In step D32, the second counting control circuit receives the initial clock signal and the output signal of the second flip-flop of the Mth stage, and when the output signal of the second flip-flop of the Mth stage is at a first level, starts the second counting circuit to count based on the initial clock signal; and when the output signal of the second flip-flop of the Mth stage is at a second level, controls the second counting circuit to stop counting.

[0236] In some embodiments, when the counting circuit includes a third counting circuit, the clock signal generating method further includes step D33. In step D33, the third counting control circuit receives the first intercepted clock signal and the output signal of the third flip-flop of the Nth stage, and when the output signal of the third flip-flop of the Nth stage is at a first level, starts the output signal of the third flip-flop of the Nth stage to count based on the first intercepted clock signal; and when the output signal of the third flip-flop of the Nth stage is at a second level, controls the second counting circuit to stop counting.

[0237] It should be noted that the clock signal generation method shown in Figure 21 can be implemented by various embodiments of the device embodiments shown in Figures 4 to 20, and realize various effects in the device embodiments shown in Figures 4 to 20, which will not be repeated here.

[0238] The clock signal generation method provided in the embodiment of the present disclosure, after decoding a portion of the command bits of a command based on a command pre-decoding circuit to obtain a pre-decoded command, parsing the command decoding circuit to obtain an internal command signal, and counting the clock cycles of an initial clock signal by a counting circuit to generate a first count signal and a second count signal, can intercept a portion of the initial clock signal based on the pre-decoded command signal, the internal command signal, and the counting results of the first count signal and the second count signal to obtain a target clock signal that matches the command. Since the target clock signal of each command can match the operation time of each command, compared to the technical solution of using the same clock signal for each command, the dynamic loss of the memory caused by the constant flipping of the redundant clock cycle generated by the mismatch between the clock cycle and the command during command operation is avoided, thereby reducing the dynamic loss of the memory.

[0239] Based on the same inventive concept, another clock signal generation method is also provided in the embodiments of the present disclosure, such as the following embodiments.

[0240] FIG22 shows a flow chart of another clock signal generating method in an embodiment of the present disclosure. As shown in FIG22 , the clock signal generating method includes S2210 to S2260 .

[0241] S2210, decoding some command bits in the command to obtain a pre-decoded command signal. It should be noted that S2210 can be implemented by the above-mentioned command decoding circuit. The specific content of S2210 can be found in the above-mentioned description of the above-mentioned command decoding circuit in the embodiment of the present disclosure, which will not be repeated here.

[0242] S2220: Count clock cycles based on the initial clock signal to generate a first count signal. It should be noted that S2220 can be implemented by the first counting circuit or the second counting circuit. For details of S2220, please refer to the description of the first counting circuit and the second counting circuit in the above-mentioned embodiments of the present disclosure, and will not be repeated here.

[0243] S2230: The initial clock signal is intercepted according to the pre-decoding command signal and the first count signal to obtain a first intercepted clock signal. It should be noted that S2230 can be implemented by the first clock signal interception circuit described above. The details of S2230 can be found in the description of the first clock signal interception circuit in the above embodiments of the present disclosure, and will not be further described.

[0244] S2240, decoding the command to obtain an internal command signal. It should be noted that S2240 can be implemented by the above-mentioned command decoding circuit. The specific content of S2240 can be found in the above-mentioned description of the command decoding circuit in the embodiment of the present disclosure, which will not be repeated here.

[0245] S2250 counts clock cycles based on the initial clock signal to generate a second count signal. It should be noted that S2250 can be implemented by the first counting circuit or the third counting circuit described above. For details of S2250, please refer to the description of the first counting circuit and the third counting circuit in the above-mentioned embodiments of the present disclosure, and will not be repeated here.

[0246] S2260: The first intercepted clock signal is intercepted according to the internal command signal and the second count signal to obtain a target clock signal. It should be noted that S2260 can be implemented by the second clock signal interception circuit described above. The details of S2260 can be found in the description of the first clock signal interception circuit in the above embodiments of the present disclosure, and will not be further described.

[0247] The clock signal generation method provided by the embodiment of the present disclosure is based on the pre-decoding command obtained by decoding part of the command bits of the command based on the command pre-decoding circuit, and the internal command signal obtained by parsing the command decoding circuit, and the counting circuit counts the clock cycle of the initial clock signal to generate the first count signal and the second count signal. Since the pre-decoding command signal and the internal command signal are related to the command, and since the first count signal and the second count signal are obtained by counting the initial clock signal, part of the initial clock signal can be intercepted according to the pre-decoding command signal, the internal command signal, and the counting results of the first count signal and the second count signal to obtain the target clock signal that matches the command. Since the target clock signal of each command can match the operation time of each command, compared with the technical solution of using the same clock signal for each command, the dynamic loss of the memory caused by the constant flipping of the redundant cycle clock due to the mismatch between the clock cycle and the command during the command operation is avoided, thereby reducing the dynamic loss of the memory.

[0248] Based on the same inventive concept, a semiconductor memory is also provided in an embodiment of the present disclosure. The semiconductor memory may include a memory module and a clock signal generation circuit. The memory module may include multiple memory arrays (banks). And the clock signal generation circuit 20 provided in any of the above embodiments of the present disclosure. The specific content of the clock signal generation circuit 20 can be found in the above-mentioned description of the embodiment of the present disclosure in conjunction with Figures 4 to 8, and will not be repeated here. The specific content of the semiconductor memory can be found in the above-mentioned description of the embodiment of the present disclosure, and will not be repeated here.

[0249] The semiconductor memory provided by the embodiments of the present disclosure obtains a pre-decoded command by decoding a portion of the command bits of the command based on a command pre-decoding circuit, obtains an internal command signal based on parsing by the command decoding circuit, and generates a first count signal and a second count signal by counting the clock cycles of the initial clock signal through a counting circuit. Since the pre-decoded command signal and the internal command signal are related to the command, and since the first count signal and the second count signal are obtained by counting the initial clock signal, a portion of the initial clock signal can be intercepted based on the pre-decoded command signal, the internal command signal, and the counting results of the first count signal and the second count signal to obtain a target clock signal that matches the command. Since the target clock signal of each command can match the operation time of each command, compared to the technical solution of using the same clock signal for each command, the dynamic loss of the memory caused by the constant flipping of the redundant clock cycles due to the mismatch between the clock cycle and the command during the command operation is avoided, thereby reducing the dynamic loss of the semiconductor memory.

[0250] Based on the same inventive concept, an electronic device is also provided in an embodiment of the present disclosure. The electronic device may include the memory provided in any of the above embodiments of the present disclosure. The specific content of the memory can be found in the relevant description of the above embodiments of the present disclosure, and will not be repeated here. Among them, the electronic device of the embodiment of the present disclosure may be an electronic device equipped with a memory. For example, the electronic device may be a mobile terminal, a computer, a server, a virtual reality device, an Internet of Things device, etc.

[0251] The electronic device provided by the embodiment of the present disclosure can obtain a pre-decoded command by decoding part of the command bits of the command based on the command pre-decoding circuit, obtain an internal command signal based on the analysis of the command decoding circuit, and generate a first count signal and a second count signal by counting the clock cycles of the initial clock signal through the counting circuit. Since the pre-decoded command signal and the internal command signal are related to the command, and since the first count signal and the second count signal are obtained by counting the initial clock signal, a portion of the initial clock signal can be intercepted based on the pre-decoded command signal, the internal command signal, and the counting results of the first count signal and the second count signal to obtain a target clock signal that matches the command. Since the target clock signal of each command can match the operation time of each command, compared with the technical solution of using the same clock signal for each command, the dynamic loss of the memory caused by the constant flipping of the redundant cycle clock due to the mismatch between the clock cycle and the command during the command operation is avoided, thereby reducing the dynamic loss of the memory.

[0252] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. The method embodiment is described relatively simply, and for relevant details, please refer to the description of the system embodiment. The present disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications and additions, or change the order of the steps after understanding the spirit of the present disclosure. In addition, for the sake of brevity, a detailed description of known method technologies is omitted here.

[0253] The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this disclosure, and they should all be covered by the protection scope of the present disclosure.

[0254] Therefore, the scope of protection of the present disclosure shall be based on the scope of protection of the claims. The present disclosure is intended to cover any modifications, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A clock signal generating circuit (20), characterized in that: The clock signal generating circuit comprises: A command pre-decoding circuit (21) is used for decoding part of the command bits in the command (X0) to obtain a pre-decoded command signal (X1); A command decoding circuit (22), used for decoding the command (X0) to obtain an internal command signal (X2); A counting circuit (23) for counting clock cycles based on an initial clock signal (C0) to generate a first counting signal (X3) and a second counting signal (X4); A clock signal interception circuit (24) is connected to the command pre-decoding circuit (21), the command decoding circuit (22) and the counting circuit (23), and is used to intercept the initial clock signal (C0) according to the pre-decoding command signal (X1), the internal command signal (X2), the first counting signal (X3) and the second counting signal (X4) to obtain a target clock signal (Cx).

2. The clock signal generating circuit according to claim 1, characterized in that: The counting circuit (23) comprises: The first counting circuit (231) comprises M stages of first flip-flops (DFF11-DFF1M), wherein the output signal of the i-th stage first flip-flop is at the p×2-th stage of the initial clock signal. j-1 +1 trigger edge causes a signal flip, i is any positive integer less than or equal to M, p is any positive integer; The output signal of the first trigger of the Mth stage is the first counting signal; the output signal of the first trigger of the Nth stage is the second counting signal, M and N are integers greater than or equal to 1, M is greater than or equal to N, Among them, 2 M-1 and 2 N-1 are both greater than or equal to the number of clock cycles required for the command.

3. The clock signal generating circuit according to claim 1 or 2, characterized in that: The counting circuit (23) comprises: The second counting circuit (235) includes M stages of second flip-flops (DFF31-DFF3M), wherein the output signal of the j-th stage second flip-flop is at the p×2-th stage of the initial clock signal. j-1 +1 trigger edge causes a signal flip, the output signal of the second trigger of the Mth level is the first counting signal, j is any positive integer less than or equal to M, and p is any positive integer; The third counting circuit (236) includes N stages of third flip-flops (DFF41-DFF4N), wherein the output signal of the k-th stage third flip-flop is at the p×2-th stage of the initial clock signal. k-1 +1 trigger edge causes a signal flip, the output signal of the third counter of the Nth stage is the second counting signal, k is any positive integer less than or equal to N, M and N are integers greater than or equal to 1, N is less than or equal to M, Among them, 2 M-1 and 2 N-1 are both greater than or equal to the number of clock cycles required for the command.

4. The clock signal generating circuit according to claim 2 or 3, characterized in that: The clock signal interception circuit (24) comprises a first clock signal interception circuit (241) and a second clock signal interception circuit (242), wherein: The first clock signal interception circuit is connected to the command pre-decoding circuit and the counting circuit, and is used to intercept at least part of the initial clock signal according to the pre-decoding command signal and the first counting signal to generate a first intercepted clock signal (C2); The second clock signal interception circuit (242) is connected to the first clock signal interception circuit, the command decoding circuit and the counting circuit, and is used to intercept at least part of the first intercepted clock signal according to the internal command signal and the second counting signal to generate the target clock signal.

5. The clock signal generating circuit according to claim 4, characterized in that: The first clock signal interception circuit and / or the second clock signal interception circuit comprises an interception pulse signal generation circuit (2411) and an interception clock signal generation circuit (2412), wherein: The intercepted pulse signal generating circuit comprises a command signal input terminal, a count signal input terminal and an intercepted pulse output terminal, wherein the command signal input terminal is used to obtain the pre-decoding command signal or the internal command signal, and the count signal input terminal is used to obtain the first count signal or the second count signal. The intercepted pulse signal generating circuit is used to generate an intercepted pulse signal (P1) according to the signal obtained by the command signal input terminal and the signal obtained by the count signal input terminal. The intercepted clock signal generating circuit comprises an intercepted pulse signal input terminal, a clock signal to be intercepted input terminal and an intercepted clock output terminal, wherein the intercepted pulse signal input terminal is connected to the intercepted pulse output terminal, the clock signal to be intercepted input terminal is used to obtain the initial clock signal or the first intercepted clock signal, and the intercepted clock signal generating circuit is used to intercept at least part of the signal obtained by the clock signal to be intercepted input terminal according to the intercepted pulse signal, generate the first intercepted clock signal or the target clock signal, and output the first intercepted clock signal or the target clock signal through the intercepted clock output terminal.

6. The clock signal generating circuit according to claim 5, characterized in that: The intercept pulse signal generating circuit comprises: A pulse generating circuit (2411A) for generating a target pulse signal (net1) according to a signal obtained at a command signal input terminal of the intercepted pulse signal generating circuit and a signal obtained at a count signal input terminal of the intercepted pulse signal generating circuit, wherein the effective level start time of the target pulse signal is generated based on a transition edge of the signal obtained at the command signal input terminal of the intercepted pulse signal generating circuit, and the effective level end time of the target pulse signal is generated based on a transition edge of the signal obtained at the count signal input terminal of the intercepted pulse signal generating circuit; A pulse signal adjustment circuit (2411B) is connected to the pulse generation circuit and is used to adjust the pulse width of the target pulse signal according to the signal obtained from the input end of the clock signal to be intercepted, and use the target pulse signal after the width adjustment as the intercepted pulse signal.

7. The clock signal generating circuit according to claim 6, characterized in that: The pulse signal adjustment circuit (2411B) comprises: The pulse extension subcircuit (2411B_1) is used to use the pulse extension signal (CS_MASK_E / O) to adjust the effective level start time of the target pulse signal to generate the target pulse signal after the time is adjusted; The pulse adjustment subcircuit (2411B_2) is connected to the pulse expansion subcircuit and is used to adjust the pulse width of the target pulse signal after the moment is adjusted forward according to the signal obtained from the input end of the clock signal to be intercepted, so as to obtain the intercepted pulse signal with a complete period.

8. The clock signal generating circuit according to any one of claims 5 to 7, characterized in that: For any one of the first clock signal interception circuit and the second clock signal interception circuit, the any one of the clock signal interception circuits includes: A signal shielding circuit (2413), wherein the input end of the signal shielding circuit is connected to the output end of the intercepted pulse signal generating circuit, and is used to receive a mode signal (CONTI_MODE) and the intercepted pulse signal; the output end of the signal shielding circuit is used to connect to the input end of the clock signal interception circuit, and is used to shield or output the intercepted pulse signal based on the mode signal.

9. The clock signal generating circuit according to any one of claims 1 to 8, characterized in that: The command pre-decoding circuit comprises: A plurality of command pre-decoding sub-circuits (211), different command pre-decoding sub-circuits decode command bits of different numbers / positions, and each command pre-decoding sub-circuit is used to pre-decode the command to obtain a pre-decoded command sub-signal; The pre-decoding command sub-signal processing circuit (212) is connected to the plurality of command pre-decoding sub-circuits and is used to combine the plurality of pre-decoding command sub-signals to generate the pre-decoding command signal.

10. The clock signal generating circuit according to any one of claims 2 to 9, characterized in that: The counting circuit also includes: A first counting control circuit (232) is connected to the first counting circuit and is used to receive the initial clock signal and the output signal of the first trigger of the Mth stage, and is used to start the first counting circuit to count based on the initial clock signal when the output signal of the first trigger of the Mth stage is at a first level; and to control the first counting circuit to stop counting when the output signal of the first trigger of the Mth stage is at a second level.

11. The clock signal generating circuit according to claim 10, characterized in that: The first counting control circuit (232) comprises: a second NOT gate (NOT2), a fifth NAND gate (NAND5) and a third NOT gate (NOT3); wherein, The second NOT gate is used to invert the initial clock signal to obtain the inverted signal of the initial clock signal; one end of the fifth NAND gate receives the inverted signal of the initial clock signal, and the other end receives the output signal of the first trigger of the Mth level, and is used to input the inverted signal of the initial clock signal to the clock input end of the first trigger of the first level when the output signal of the first trigger of the Mth level is at a high level.

12. The clock signal generating circuit according to any one of claims 3 to 11, characterized in that: The counting circuit further comprises: a second counting control circuit (237) and / or a third counting control circuit (238), wherein: The second counting control circuit is connected to the second counting circuit, and is used to receive the initial clock signal and the output signal of the second flip-flop of the Mth stage, and is used to start the second counting circuit to count based on the initial clock signal when the output signal of the second flip-flop of the Mth stage is at a first level; and control the second counting circuit to stop counting when the output signal of the second flip-flop of the Mth stage is at a second level; The third counting control circuit is connected to the third counting circuit, and is used to receive the first intercepted clock signal and the output signal of the N-th level third trigger, and is used to start counting the output signal of the N-th level third trigger based on the first intercepted clock signal when the output signal of the N-th level third trigger is at a first level; and to control the second counting circuit to stop counting when the output signal of the N-th level third trigger is at a second level.

13. A memory, characterized in that: Comprising a clock signal generating circuit as described in any one of claims 1-12.

14. A clock signal generation method, characterized in that: include: (S2110) the command decoding circuit decodes the input command to obtain an internal command signal; (S2120) the counting circuit counts the clock cycles based on the initial clock signal to generate a counting signal; (S2130) The clock signal interception circuit intercepts the initial clock signal according to the internal command signal and the counting signal to obtain a target clock signal.

15. A clock signal generation method, characterized in that: include: (S2210) decoding part of the command bits in the command to obtain a pre-decoded command signal; (S2220) counting clock cycles based on the initial clock signal to generate a first counting signal; (S2230) intercepting the initial clock signal according to the pre-decoding command signal and the first counting signal to obtain a first intercepted clock signal; (S2240) decoding the command to obtain an internal command signal; (S2250) counting clock cycles based on the initial clock signal to generate a second counting signal; (S2260) The first intercepted clock signal is intercepted according to the internal command signal and the second counting signal to obtain a target clock signal.

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