Efficient residual number system multiplication for selected prime moduli

Abstract

A multiplication circuit which multiplies two selected numbers, modulo n (wherein a necessary but not sufficient condition is that n is prime) in a fast and efficient manner. Multiplication is achieved by one-dimensional source table lookups in parallel, a rotate operation, and a set of one-dimensional reverse table lookups. Two dimensional table lookups (which do not scale well with n) and slow non-{2k, 2k-1} multipliers are both bypassed by this method.

Description

EFFICIENT RESIDUAL NUMBER SYSTEM MULTIPLICATION FOR SELECTED PRIME MODULIInventor:Michael DibrinoFIELD

[0001] The following is related generally to the field of electronic circuits and, more specifically, to electronic circuits for performing arithmetic functions such as multiplication.BACKGROUND

[0002] Computer systems frequently include one or more circuits for performing arithmetic functions such as addition, subtraction, multiplication, and division. In general-purpose computer architectures, one or more circuits for performing arithmetic operations such as multiplication may be integrated as execution units within a central processing unit (CPU). For example, computer systems frequently include combinatorial logic circuits (e.g., in a microprocessor) such as a Vector Unit, or VU, an arithmetic logic unit, or ALU, and / or a floating-point unit, or FPU, often referred to as a math coprocessor. One or more such units may include multiplication circuits (multiplication units) to perform multiplication operations. In general-purpose computer architectures, one or more VUs, ALUs and / or FPUs may be integrated as execution units within the central processing unit. One way to improve the efficiency of multiplication operations is through use of a Residual, or Residue, Number System (RNS) multiplication operations in which the operands are represented by a set of remainders for a set of moduli. Although this approach can provide advantages, as usually implemented it can require m x m lookup tables for a modulus value of m, and need to use division for performing modular reduction. The need for division can significantly slow the process and the need for 2-dimensional lookup tables can result in large area and power requirements for larger moduli. Circuits that perform RNS based multiplication operations in an efficient manner may mitigate such delays.SUMMARY

[0003] According to one aspect of the present disclosure, a multiplication circuit includes: a one dimensional vector lookup table configured to receive a first modulo p input number, where p is a prime number, and provide a corresponding first binary valued vector output, at most one of the values of the vector being one and other values of the vector being zero; a one dimensional rotate lookup table configured to receive a second modulo p input number and provide a corresponding first rotate amount; a rotate circuit configured to receive the first binary valued vector and the first rotate amount and to rotate the first binary valued vector by the first rotate amount; and a first one dimensional product vector lookup table configured to receive the first binary valued vector rotated by the first rotate amount and provide a corresponding first modulo p product of the first modulo p input number and the second modulo p input number.

[0004] Optionally, in the preceding aspect, the multiplication circuit further comprises: a zero detect circuit configured to receive the second modulo p input number and determine an output indicating whether the second modulo p input number has a value of zero; and a logic circuit connected to receive the output of the zero detect circuit and the first modulo p product and to set the modulo p product to zero in response to the output of the zero detect circuit indicating that the second modulo p input number has a value of zero.

[0005] Optionally, in any of the preceding aspects, the binary valued vector output is of (p-1 ) values and first rotate amount is between 0 and (p-1 ).

[0006] Optionally, in of the first two preceding aspects, the binary valued vector output is of (p-1 ) / 2 values and first rotate amount is between 0 and (p-1 ) / 2.

[0007] Optionally, in the preceding aspect, the multiplication circuit further comprises: a first one dimensional sign value lookup table configured to receive the first modulo p input number and provide a corresponding first sign value; a second one dimensional sign value lookup table configured to receive the second modulo p input number and provide a corresponding second sign value; a second one dimensional product vector lookup table configured to receive the first binary valued vector rotatedby the first rotate amount and provide a corresponding second modulo p product of the first modulo p input number and the second modulo p input number; a logic circuit configured to receive the first sign value and the second sign value and to provide a logical combination of the first sign value and the second sign value; and a multiplexer configured provide as output either the first modulo p product or the second modulo p product based on the logical combination of the first sign value and the second sign value.

[0008] Optionally, in the preceding aspect, p has a primitive root of two and the logic circuit is an XNOR circuit.

[0009] Optionally, in the preceding aspect p does not have a primitive root of two and the logic circuit is an XOR circuit.

[0010] According to an additional aspect of the present disclosure, there is provided a method of performing modulo p multiplication, where p is a prime number, comprising: receiving a first modulo p input number; determining from a one dimensional vector lookup table a corresponding first binary valued vector for the first modulo p number, at most one of the values of the vector being one and other values of the vector being zero; receiving a second modulo p input number; determining from a one dimensional rotate lookup table a corresponding first rotate amount corresponding to the second modulo p number; rotating the first binary valued vector by the first rotate amount; and determining from a first one dimensional product vector lookup table a first modulo p product of the first modulo p input number and the second modulo p input number from the first binary valued vector rotated by the first rotate amount.

[0011] Optionally, the preceding aspect, of the method further includes: determining whether the second modulo p input number has a value of zero; and setting the modulo p product to zero in response to determining that the second modulo p input number has a value of zero.

[0012] Optionally, in any of the preceding two aspects the binary valued vector output is of (p-1 ) values and first rotate amount is between 0 and (p-1 ).

[0013] Optionally, in any of the two aspects preceding the immediately preceding aspect the binary valued vector output is of (p-1 ) / 2 values and first rotate amount is between 0 and (p-1 ) / 2.

[0014] Optionally, in the preceding aspect, the method further comprises: determining a corresponding first sign value for the first modulo p input number from a first one dimensional sign value lookup table; determining a corresponding second sign value for the second modulo p input number from a second one dimensional sign value lookup table; determining from a second one dimensional product vector lookup table a second modulo p product of the first modulo p input number and the second modulo p input number from the first binary valued vector rotated by the first rotate amount; forming a logical combination of the first sign value and the second sign value; and selecting either the first modulo p product or the second modulo p product as a result of the multiplication based on the logical combination of the first sign value and the second sign value.

[0015] Optionally, in the preceding aspect, p has a primitive root of two and the logical combination is an XNOR.

[0016] Optionally, in the preceding aspect before the last, p does not have a primitive root of two and the logical combination is an XOR.

[0017] According to a further aspect, an arithmetical logic circuit includes a plurality of mod-p arithmetic units, each for a different value of a prime number p and each configured to receive mod-p components of input values in a residual number format system, each mod-p arithmetic unit including a multiplication circuit comprising: a one dimensional vector lookup table configured to receive a first modulo p input number, where p is a prime number, and provide a corresponding first binary valued vector output, at most one of the values of the vector being one and other values of the vector being zero; a one dimensional rotate lookup table configured to receive a second modulo p input number and provide a corresponding first rotate amount; a rotate circuit configured to receive the first binary valued vector and the first rotate amount and to rotate the first binary valued vector by the first rotate amount; and a first one dimensional product vector lookup table configured to receive the first binary valuedvector rotated by the first rotate amount and provide a corresponding first modulo p product of the first modulo p input number and the second modulo p input number.

[0018] Optionally, in the preceding aspect, the arithmetical logic circuit further includes: a first input register configured to receive the first modulo p input numbers for each of the plurality of the mod-p arithmetic units and provide each of the first modulo p input numbers to the corresponding one of the mod-p arithmetic units; a second input register configured to receive the second modulo p input numbers for each of the plurality of the mod-p arithmetic units and provide each of the second modulo p input numbers to the corresponding one of the mod-p arithmetic units; and a result register configured to receive the first modulo p product of each of the plurality of mod-p arithmetic units.

[0019] Optionally, in either of the preceding two aspects, the multiplication circuit of each mod-p arithmetic unit further comprises: a zero detect circuit configured to receive the second modulo p input number and determine an output indicating whether the second modulo p input number has a value of zero; and a logic circuit connected to receive the output of the zero detect circuit and the modulo p product and to set the modulo p product to zero in response to the output of the zero detect circuit indicating that the second modulo p input number has a value of zero.

[0020] Optionally, in any of the three preceding aspects, the binary valued vector output is of (p-1 ) values and first rotate amount is between 0 and (p-1 ).

[0021] Optionally, in any of the three aspects preceding the immediately preceding aspect, the binary valued vector output is of (p-1 ) / 2 values and first rotate amount is between 0 and (p-1 ) / 2.

[0022] Optionally, the preceding aspect, the multiplication circuit of each mod-p arithmetic unit further comprises: a first one dimensional sign value lookup table configured to receive the first modulo p input number and provide a corresponding first sign value; a second one dimensional sign value lookup table configured to receive the second modulo p input number and provide a corresponding second sign value; a second one dimensional product vector lookup table configured to receive the first binary valued vector rotated by the first rotate amount and provide a second modulo pproduct of the first modulo p input number and the second modulo p input number; a logic circuit configured to receive the first sign value and the second sign value and to provide a logical combination of the first sign value and the second sign value; and a multiplexer configured provide as output either the first modulo p product or the second modulo p product based on the logical combination of the first sign value and the second sign value.

[0023] Optionally, in the preceding aspect, p has a primitive root of two and the logic circuit is an XNOR circuit.

[0024] Optionally, in the preceding aspect before last, p does not have a primitive root of two and the logic circuit is an XOR circuit..

[0025] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background.BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying Figures for which like references indicate elements.

[0027] Figures 1A and 1 B are respectively block diagrams of a computer system and a microprocessor that can be incorporated into such a computer system.

[0028] Figure 2A illustrates a Residual, or Residue, Number System (RNS) number RNS(8|7|5|3) represented in a binary-coded number format.

[0029] Figure 2B illustrates an embodiment for the structure of an adder, subtractor, or multiplier for numbers in the RNS format using the RNS(8|7|5|3) example.

[0030] Figure 3 illustrates components for implementing modular multiplication for moduli not of the form 2kor 2k-1 .

[0031] Figure 4 is a table to illustrate the determination of the primitive roots of a prime number of the example of p=7.

[0032] Figure 5 is a table illustrating the modulo 11 value of 2kfor the k values 0 to 9.

[0033] Figure 6 lists the primitive roots of the prime numbers up to 100 with the prime numbers having a primitive root of 2 highlighted.

[0034] Figure 7 is a table illustrating the modulo 11 value of 2kfor the k values 0 to 9 for both positive and negative remainder values.

[0035] Figures 8 and 9 are tables respectively illustrating the modulo 7 and 23 value of 2kfor both positive and negative remainder values.

[0036] Figure 10 lists the primitive roots of the prime numbers up to 100 with the additional available primes without a primitive root of 2 for which the methods presented here can be applied.

[0037] Figures 11 A and 11 B provide the value of 2kfor both positive and negative remainder values for selected small primes which have primitive roots of 2 that can be used in the process, specifically for modulus values of 5, 11 , 13, 19, and 29.

[0038] Figure 12 illustrates an embodiment for a multiplication circuit that can implement modular multiplication based on a simple rotation and 1 dimensional lookup tables.

[0039] Figure 13A illustrates an embodiment for the circuit of Figure 12 for a modulus 29 example.

[0040] Figures 13B-13E are enlarged version of the lookup tables of the embodiment of Figure 13A.

[0041] Figure 14 is a flowchart for an embodiment of a flowchart for implementing multiplication for a prime modulus based on the rotation of a 1-hot vector.

[0042] Figure 15 illustrates an example of a computing system configured to implement embodiments of the present technology.DETAILED DESCRIPTION

[0043] One technique to improve the efficiency of a multiplication circuit is through use of the Residual, or Residue, Number System (RNS) in which the multiplication operands are represented as a set of remainder values for a set of moduli. This allows for the multiplication to be broken down into a set of channels, one for each of the moduli, that can perform modular arithmetic within each of the channels. Although this approach has advantages, as traditionally implemented, it has a number of inefficiencies. One is that it uses two dimensional lookup tables for modular multiplication, where such tables scale as the square of the size of the modulus. Another inefficiency is that for moduli not of the form 2kor 2k-1 , modular multiplication can be slow as it uses division in the modular reduction of the product. Another inefficiency is that for moduli of the form 2k-1 for which somewhat efficient modular multiplications are possible, only a limited number of ‘small’ moduli exist (e.g., 3, 7, 15, 31 for k<6). A limited number of moduli will limit the range of the number which can be represented by the plurality of moduli channels. Additionally, since the moduli must be pairwise co-prime, only a single moduli of the form 2kcan be used. Larger moduli of the form 2k-1 are not desirable due to the inherent delay of carry propagation.

[0044] The following presents embodiments for a multiplication circuit that can multiply two selected numbers, modulo n (wherein a necessary but not sufficient condition is that n is prime) in a fast and efficient manner. Multiplication is achieved by one dimensional source table lookups in parallel, a rotate operation, and a set of one dimensional reverse table lookups. Two dimensional table lookups (which do not scale well with n) and slow, non-{2k, 2k-1 } multipliers are both bypassed by this method. More specifically, to avoid 2k-1 multipliers and two dimensional lookup tables modular multiplication is performed by converting a first operand into a 1-hot vector (i.e., a vector in which, at most, a single component has a value of 1 , with the other components 0) and the second operand is converted to a rotation amount. Both the 1 -hot vector and rotation amount can be determined from one dimensional lookuptables. The multiplication is effected by rotating the 1-hot vector by the rotate amount, which is then converted into the result through use of another one dimensional lookup table. The size of the 1 hot vector, and resultant register sized, can be halved if both positive and negative remainder values are used for the moduli.

[0045] The present embodiments of the disclosure may be implemented in many different forms and the claim scope should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to convey the inventive embodiment concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details.

[0046] Figures 1 A and 1 B, respectively, are block diagrams of a computer system and a microprocessor that can be incorporated into such a computer system that implements one or more embodiments of the disclosure. In the simplified representation of Figure 1A, the computer system 100 includes a computer 105, one or more input devices 101 and one or more output devices 103. Common examples of input devices 101 include a keyboard or mouse or even a voice recognition system to support voice commands. Common examples of output devices 103 include monitors, speakers or printers. The computer 105 includes a memory 107 and a microprocessor 120, where in this simplified representation the memory 107 is represented as a single block. The memory 107 can include ROM memory, RAM memory and / or non-volatile memory and, depending on the embodiment, can include separate memory for data and instructions.

[0047] Figure 1 B illustrates one embodiment for the microprocessor 120 of Figure 1A and also includes the memory 107. In the representation of Figure 1 B, the microprocessor 120 includes control logic 125, a processing block 140, an input interface 121 , and an output interface 123. The dashed lines represent control signals exchanged between the control logic 125 and the other elements of themicroprocessor 120 and the memory 107. The solid lines represent the flow of data and instructions within the microprocessor 120 and between the microprocessor 120 and the memory 107.

[0048] The processing block 140 includes combinatorial logic 143 that is configured to execute instructions and registers 141 in which the combinatorial logic stores instructions and data while executing these instructions. In the simplified representation of Figure 1 B, certain elements or units, such as a vector unit (VII) 146, an arithmetic logic unit (ALU) 147, and a floating-point unit (FPU) processor 149, are shown, while other elements are not explicitly shown in the combinatorial logic 143. The combinatorial logic 143 is connected to the memory 107 to receive and execute instruction and supply back the results. The combinatorial logic 143 is also connected to the input interface 121 to receive input from input device(s) 101 and / or other sources. The combinatorial logic 143 is also connected to the output interface 123 to provide output to output device(s) 103 and / or other destinations.

[0049] A microprocessor, such as the microprocessor 120, may perform a range of different functions including arithmetic operations. For example, a microprocessor may perform addition, subtraction, multiplication, multiply-accumulate, and / or division. Aspects of the present technology may enable efficient multiplication operations to be performed by a microprocessor. More generally, aspects of the present technology can more generally be applied to embodiments for one or more central processing units (CPUs), graphic processing units (GPUs), artificial intelligence (Al) accelerators, Tensor Processing Units (TPUs), and / or any other digital logic that performs multiplication or multiplication as part of a multiply-accumulate operation.

[0050] Multiplication operations may be performed by one or more multiplication circuits in the microprocessor 120. For example, one or more of the VU 146, the ALU 147 and the FPU 149 may include one or more multiplication circuits. Other elements of combinatorial logic 143 may alternatively or additionally include one or more multiplication circuits. The present technology is not limited to multiplication circuits or multiply-accumulate units in any particular location (in a microprocessor or elsewhere) or used for any particular purpose and can be applied wherever efficient multiplication or multiply-accumulate operations are desired.

[0051] A number of different approaches may be used to perform multiplication. The embodiments presented in the following discussion are based on the use of the Residual, or Residue, Number System (RNS). Before discussing these embodiments, some discussion is given of the Residual Number System.

[0052] The residual number system is based on the use of modular arithmetic and a property known as the Chinese Remainder Theorem. If mi, ...,are integers greater than 1 (often called moduli or divisors), then the Chinese remainder theorem asserts that if the mzare pairwise coprime, and if ai, ..., a / < are integers such that 0 < az< m, for every / , then there is one and only one integer x, such that 0 < x < N and the remainder of the Euclidean division of x by mzis azfor every / . The consequence is that, if M denotes the product of k pairwise relatively prime moduli,M = mk-i X • • • X mi x mo , then M is the number of different representable values in the RNS and is known as its dynamic range. This allows any number within this dynamic range to be expressed as a vector of its values for each of the moduli.

[0053] To take the example of the moduli 8, 7, 5, and 3, The dynamic range in this example is M = 8 x 7 x 5 x 3 = 840, which is the total number of distinct values that are representable in this example 4-modulus RNS. A number in this format is made up of four components, one for each modulus, and referred to an RNS(8|7|5|3) number. The following are some example numbers in RNS(8|7|5| 3) format: Represents 0 or 840 or ■ ■ ■ Represents 1 or 841 or ■ ■ ■ Represents 2 or 842 or ■ ■ ■ Represents 8 or 848 or ■ ■ ■ Represents 21 or 861 or ■ ■ ■ Represents 64 or 904 or - - Represents -70 or 770 or - -Represents -1 or 839 or ■ ■ ■Other numbers, modulo 840, can be similarly expressed in the RNS(8|7|5|3) format. When performing arithmetic for integers in the RNS format, the operations can be ona component by component basis, using the corresponding modulus. Performing arithmetic for integers in this can have a number of advantages.

[0054] Continuing with the example of the moduli 8, 7, 5, and 3, an integer (within the corresponding dynamic range) in a binary-coded number format for RNS(8|7|5|3) is illustrated in Figure 2A. This includes three 3-bit slots for the mod 8, mod 7, and mod 5 components and a 2-bit slot for the mod 3 component. When performing an arithmetic operation between two numbers in this format, operations can individually be performed pair-wise on each component. This allows arithmetic operations for numbers in such an RNS format to be separated out into independent RNS channels, as illustrated in Figure 2B.

[0055] Figure 2B illustrates an embodiment for the structure of an adder, subtractor, or multiplier for numbers in the RNS format using the RNS(8|7|5|3) example that may be implemented by a processor. At top are shown two operands, Operand 1 and Operand 2, in the RNS(8|7|5|3) format that can be stored in corresponding registers 2111 and 2112, where these operands will be converted to the RNS format previously in an operation that typically takes a few steps that can be hidden behind other operations. The modulus 8, 7, 5, and 3 components of each operand go to the corresponding mod-8 unit 201 , mod-7 unit 203, mod-5 unit 205, and mod-3 unit 207 to undergo pair-wise operations in each RNS channel using the corresponding modular arithmetic. The components of the results can then be stored in the result register 221 , which can be used in subsequent RNS computations or converted out of the RNS format when needed.

[0056] The RNS approach illustrated with respect to Figure 2B has a number of advantages. It solves the carry-propagation problem, as carry-propagation is limited to a few bits. It is faster, as 4x4 multipliers are considerably more than 4 times simpler than a 16x16 multiplier. It is also smaller as a 4x4 multiplier is ~1 / 16 the size of a 16x16 multiplier (power and area scaled quadratically). Additionally, small residue arithmetic operations can be implemented with direct table lookup. This approach does require conversion between the RNS format and binary, and some arithmetic operations (e.g., division, sign detection, overflow detection) are more difficult, but the following is concerned with multiplication, where it can have a number of advantages.

[0057] Considering the details of implementing efficient RNS multiplication, one detail is the selection of the RNS moduli, where two of the considerations are channel width and the number of channels. If the objective is to reduce the addition / multiplication execution time, then a large number of small moduli is desirable, as the execution time is determined by the largest modulus and Power / Area of multipliers proportional to n2.

[0058] One approach to selecting moduli is to use moduli of the form 2kor 2k-1 for ease of implementation. In this approach the total number of bits can be minimized by using an efficient binary representation — i.e., maximize the dynamic range by selecting a modulus, mi, that equals 2kor is very close to it (2k-1 ), for example. Only a single mi of the form 2kbecause the moduli must be relatively prime. Moduli mi of the form (2k-1 ) work well, since end-around-carry adders may be used for this form; however, not all terms of the form (2k-1 ) may be selected, since for example 2k-1 = (2^2 - 1 )(2k / 2+1 ) for even values of k.

[0059] Considering the case of representing a 32-bit integer in the RNS system, this has a range = 232= 4,294,967,296 and using moduli of the form 2kor 2k-1 for ease of implementation. One set of possible moduli are then rrij = 31 , 63, 127, 255, 256. The dynamic range M is adequate as M / 232= 3.7799 and this set of moduli are relatively prime. These five moduli are of 5, 6, 7, 8, and 8 bits respectively for a total of 34 bits. For moduli of the form 2k, an ordinary binary adder can be used, with the residue read directly from the LSBs. For moduli of the form 2k-1 , an ‘end-around carry’ adder can be used.

[0060] Another approach is to use the smallest prime moduli for which a symmetric complete residue system exists. One example for a 32 bit integer are the nine moduli rrij = 3, 5, 7, 11 , 13, 19, 23, 29, 37. The dynamic range M is adequate as M / 232= 1 .6393 and this set of 9 moduli are of 2, 3, 3, 4, 4, 5, 5, 5, and 6 bits respectively, for a total of 37 bits. Although this has more moduli (and a higher total number of bits), its largest moduli are significantly smaller. This has the advantages of smaller moduli2 begin faster and that area / power are reduced as this is proportional to log^m,) . However, implementing multiplication for moduli not of the form 2kor 2k-1 has some complications, as can illustrated with respect to Figure 3.

[0061] Figure 3 illustrates components for implementing modular multiplication for moduli not of the form 2kor 2k-1 . Multiplier block 301 receives two n-bit operands A and B and multiplies these together to generate the 2n-bit result of AB. To turn this into the n-bit mod-m product of these numbers, |AB|m, the product AB needs to undergo modular reduction in block 303. However, implementing modular reduction requires division, which is a time consuming multistep operation that slows down the process. To avoid this problem, the embodiments below present a simple and efficient method to multiply moduli not of the form 2kor 2k-1 .

[0062] The embodiments presented below involve the use of the primitive roots of a number in modular arithmetic: Given gx(mod p) and where p is a prime number, the question is whether there a value of g that makes ensures a unique output from 1 to p-1 , for every value of x from 0 to p-1. If so, this generator (g) is known as a primitive root under modulo p: Y = gx(mod p). This can be determined though use the Euler Totient Function (p(p) that counts the positive integers up to a given integer p that are relatively prime to p (i.e., has no greatest common divisors except 1 ). For prime numbers, cp(p) = p-1. The factors, f, of cp(p) are then determined and, for each generator g, gf(mod p) is tested for all powers from i =1 to p-2. If any gf(mod p) = 1 , then g is not a primitive root of p. The table of Figure 4 illustrates an example.

[0063] Figure 4 is a table to illustrate the determination of the primitive roots of a prime number of the example of p=7. If p=7, cp(7) = p-1 = 6, which has factors f = 2, 3. In the table for p=7, the first row are the generators and the first column the powers x. The table values are then the corresponding generator raised the power x. As shown in the table both of g2and g4to the third are 1 and g6to the second is also one. Consequently, 2, 3, and 6 are not primitive roots of p=7 and we find that by testing g{2 3}(mod 7) that the primitive roots are Y = 3, 5.

[0064] In the following, primes with a primitive root of 2 will be or particular interest, since, for primes with primitive roots of 2 as moduli, modular multiplication can be performed by rotating of 1 -hot vectors, i.e., a binary valued vector all 0s with a single 1 entry. This can be illustrated by the table of Figure 5 for the example of p=11 .

[0065] Figure 5 is a table illustrating the modulo 11 value of 2kfor the k values 0 to 9. The top row is the values of k, with the corresponding value of 2kbelow. The mod11 reductions of 2kare in the bottom row. (The labelling of “Positive” will be explained below.) As the prime number 11 has a primitive root of 2, each of the mod 11 reductions of 2kare different. (Note that k=0 corresponds to 2°=1 and that 0 would be represented as a vector of all zeros.)

[0066] An example calculation can be the multiplication of 3 (mod 11 ) x 6 (mod 11 ). The first operand is represented as a 1-hot vector of (p-1 ) elements in which the location of the 1 is based on the location of the operand in the bottom row, so that for the example of 3, this is represented by 1-hot vector 0000000010. The second operand is represented by a rotate amount, where the amount of rotate is, for an operand value of k, the modular reduction of 2k, so that for the example of 6, the amount of rotate is amount of 9. To compute the product of the operands, the 1-hot vector of the first operand is right rotated by the rotate amount of the second operand, so that to compute 3 (mod 11 ) x 6 (mod 11 ), 0000000010 is rotated right by 9 bits. The result is 0000000100 which corresponds to 7, which is the correct result. As in this example, this approach allows for modular multiplication with respect to prime numbers that have a primitive root of 2 to be multiplied using a simple rotation.

[0067] Figure 6 lists the primitive roots of the prime numbers up to 100. The primes with a primitive root of 2 and boxed in a darker line. As can be seen, the primes (up to 100) which have a primitive root of 2 are: 3,5,11 ,13,19,29,37,53,59,51 ,67,83. Using a set of these primes as the moduli for RNS numbers, embodiments given below use modular multiplication to efficiently performed using only the (positive) remainder values, such as given on the bottom line of the table of Figure 5 for the p=11 . In other embodiments, both positive and negative remainders can be used, as can be illustrated with respect to Figure 7.

[0068] Figure 7 is a table illustrating the modulo 11 value of 2kfor the k values 0 to 9 for both positive and negative remainder values. Figure 5 repeats the elements of Figure 5, but also adds a bottom line for negative remainder values. For each positive remainder x, there exists a negative remainder, y, such that y = x - p, where p is the moduli. So, for the p=11 example, instead of using the number set {1 , 2, 4, 8, 5, 10, 9, 7, 3, 6}, alternatively the combined positive number set {1 , 2, 4, 8, 5} and negative number set {-10, -9, -7, -3, -6} can be used.

[0069] Considering again the example of multiplying 3 (mod 11 ) x 6 (mod 11 ) and just looking at the 1 to 4 columns, 3 is represented by 1 -hot vector 00010 for a negative remainder. 6 is in the negative remainder row as corresponding to k=4, or a rotate amount of 4. The product is then computed by rotating 00010 right by 4 bits, or 00100. This corresponds to k=2, so that result corresponds to either +4 (in the positive row) or -7 (in the negative row). The determination of which of these values to select is based on whether the operands were selected from the positive or negative row: Assigning “0” for a positive row selection and “1” for a negative row selection, the operand signs can then be XNOR-ed for result selection. In this example, both operands have a sign value of 1 , so 1 XNOR 1 = 1 , so the negative value 7 is selected, which is the correct result. An XNOR operation is used since the process has taken a right hand side rotate (positive moduli of powers of 25to 29) and replaced them with negative complements of the moduli.

[0070] The use of negative remainders along with positive remainders can provide additional advantages. One of these is that the rotate register size has been cut in half. Another is that this can remove the need for the primitive root to generate all values, but only half of them. As discussed above, when only using the positive remainders, the usable primes needed to have a primitive root of 2, but being able to use both positive and negative remainders expands the number of usable primes. Examples of this can be illustrated with respect to the tables of Figures 8 and 9 for the primes 7 and 23.

[0071] Figures 8 and 9 are tables respectively illustrating the modulo 7 and 23 value of 2kfor both positive and negative remainder values. These figures are laid out similarly to Figure 7, but also include lower row “Check” listing the sum of the positive and negative remainder values directly above to check that they add up to 7 or 23, respectively. As can be seen from Figure 6, modulo 7 has primitive roots 3, 5 and modulo 23 has primitive roots 5, 7, 10, 11 , 14, 15, 18, 19, 21 , 26, 27. Neither has a primitive root of 2 and, as seen on the remainder lines of Figures 8 and 9, the remainders repeat after three k values for modulo 7 and after 11 k values for modulo 23. So only half the roots are available if only positive remainders are used, but if + / - remainder values are used, this is enough.

[0072] The multiplication process using positive and negative remainders for such roots can be illustrated by the example of multiplying 3 (mod 23) x 6 (mod 23). Referring to the remainder lines, the operand 3 is represented by the 1 -hot vector 00000000100 from the positive line. Again referring to the remainder lines, the second operand 6 is in the positive remainder line and is represented by a rotate amount of k=9. The product is then computed by rotating 00000000100 right by 9 bits, with the result of 00000010000, which corresponds to +18 or -5. Again using the sign encoding of “0” positive, “1” negative, the choice can be made by XOR-ing the sign values: 0 XOR 0 = 0, so 18 is selected, which is the correct result. In the non-2 primitive root case, XOR (rather than XNOR) is used because the negative complements of the moduli on the left side of the table of Figure 9 represent the “true” positive moduli values on the right side.

[0073] This technique allows for some, but not all, primes without a primitive root of 2 to be also used, complementing the primes with a primitive root of two and allowing the use of more smaller primes. However, this cannot be done for all primes without a primitive root of 2. The table of Figure 10 repeats the table of Figure 6, but now highlight the added primes.

[0074] Figure 10 lists the primitive roots of the prime numbers up to 100 with the additional available primes without a primitive root of 2 highlighted. As highlighted, the added primes are 7, 23, 47, 79, 97. Not all of the primes have this property, however, such as 17. Using available primes that are 6 bits or less, this gives a dynamic range 0f M = 2 x 3 x 5 x 7 x 11 x 13 = 30,030 = 1.83 x 2A14. Using up to 7 bits gives a dynamic range 0f M = 2 x 3 x 5 x 7 x 11 x 13 x 19 x 23 x 29 = 380,570,190 = 1 .42 x 228. Extending up to an 8-B it range, M = 2 x 3 x 5 x 7 x 11 x 13 x 19 x 23 x 29 x 37 x 47 x 53 x 59 x 61 = 1.26 x 1017= 1.75 x 256. Consequently, use of an RNS implementation can allow for multiplication of quite large number with relatively small circuitry.

[0075] Figures 11 A and 11 B provide the value of 2kfor both positive and negative remainder values for additional smaller primes that can be used in the process, specifically for modulus values of 5, 11 , 13, 19, and 29.

[0076] Considering now hardware implementations, the modular multiplication circuits of each of the RNS channels Figure 2B can implement the modular multiplication technique described above based on a 1 -hot vector and rotation. To minimize the register sizes, the smallest set of moduli that provide sufficient range and that either have a primitive root of 2 or are one of the added primes that cover all of the values if both positive and negative remainders can be used.

[0077] In a hardware friendly implementation, for a modulo-y multiplication circuit, defining q = (y-3) / 2, then a first operand ao be represented as a 1 -hot binary vector of length q+1 and sign from a forward lookup table. (If 0, the first operand would have all q+1 components as 0.) The second operand bo can be represented as a rotate count and sign from another forward lookup table. The product aobo product is the 1- hot binary vector rotated by the rotate count. Note that this allows the multiplication to be accomplished by a single rotate. The final result | AB |yis then achieved through a set of two reverse lookup tables, selected by either the XOR or the XNOR of source signs for the operands as described in the examples above, where the XNOR logic is used if the modulus has a primitive root of 2 and XOR logic used in the case of the added, non-primitive root 2 primes. An important advantage of this approach is that all of the lookup tables are 1 dimensional. Figure 12 is a block diagram of such an embodiment.

[0078] Figure 12 illustrates an embodiment for a multiplication circuit that can implement modular multiplication based on a simple rotation and 1 dimensional lookup tables. Referring back to Figure 2B, this can implement one of the RNS channels for a number in the RNS format of Figure 2A, where the specific modulus can be one of the moduli selected as the set of the smallest moduli that provide sufficient dynamic range. The first and second operands of modulo-y are here denoted as SrcO and Src1 .

[0079] The two operands are respectively inputs into the Dq,o* Src Vector Lookup table 1201 that provides the corresponding 1 -hot vector for SrcO and the Dq,i* Src Count Lookup table 1205 that provides the rotation amount. If only positive remainders are used, these are both 1 -dimensional lookup tables of y entries and the 1 -hot vectors will be of (y -1 ) components and the rotation values will similarly have y values. As discussed above, if both positive and negative remainder values are used, the 1 -hot vectors will be of q+1 components and each of the 1 -hot vector and rotation count willalso receive a sign value, where the Dq,o* Src Sign Lookup table 1203 that provides the sign for the 1 -hot vector corresponding to SrcO and the Dq,i* Src Sign Lookup table 1207 provides the sign for the rotation value corresponding to Src1. In either case, the 1 -hot vector corresponding to SrcO from Dq,o* Src Vector Lookup table 1201 and the rotation amount from Dq,i* Src Count Lookup table 1205 are provided to the right rotate circuit 1211 to perform the rotation of the 1 -hot vector. If both positive and negative remainders are used, the sign values from Dq,o* Src Sign Lookup table 1203 and Dq,i* Src Sign Lookup table 1207 are provided to the XNOR / XOR logic block 1213, where, as discussed above, XNOR logic is used if the modulus has a primitive root of 2 and XOR logic if not.

[0080] The output of the right rotate logic 1211 then becomes the input of a product vector lookup table or tables. If only positive remainders are used, this will be a single 1 -dimensional lookup table. If both positive and negative remainders are used, the product vector lookup table is split into product vector positive lookup table 1221 and product vector negative lookup table 1223, each 1 -dimensional tables of q+1 entries. In this case, a multiplex circuit Mux 1215 selects between these two based on the output of the XNOR / XOR logic circuit 1213.

[0081] Considering 0 values for either operand, if the first operand is 0, the corresponding vector value is all zeros and the resultant product will also be 0. However, the case of the second operand being 0 needs to be accounted for since a rotation of 0 would correspond to multiplication by unity. To account for the second operand being zero, a zero detect circuit 1209 and AND logic 1217 can be included. The zero detect circuit 1209 receives the second operand Src1 and, if Src1 is 0, outputs a 0 and, if Src1 is not 0, outputs a 1 . The AND circuit 1217 receives the output of the output of the zero detect circuit 1209 and the output of the product vector lookup table 1221 or 1223 as selected by Mux 1215. Consequently, if Src1 is 0, the AND circuit 1217 sets the product to 0, but otherwise outputs the selected output from the Mux 1215 for the product.

[0082] Figure 13A illustrates an embodiment for the circuit of Figure 12 for a modulus 29 example. Figure 13A repeats the elements of Figure 12 and elements are similarly numbered (e.g., zero detect 1209 is now 1309, right rotate 1211 is now 1311 ,and so on), but the lookup tables for modulus y =29, q = (y-3) / 2 =13, using both positive and negative remainders are explicitly shown.

[0083] In Figure 13A, the 1 dimensional Dq,o* Src Vector Lookup table 1301 and the 1 dimensional Dq,o* Src Sign Lookup table 1303 are written together and for each input value in the range 0-28 provide a 14 component vector and a sign value. Each non-0 14 component vector value occurs twice, once with a + sign and once with a - sign. For reference, a larger version of the tables 1301 / 1303 are given in Figure 13B. The 1 dimensional Dq,i* Src Count Lookup table 1305 that provides the rotation amount and the 1 dimensional Dq,i* Src Sign Lookup table 1307 provides the corresponding sign are similarly written together and for each input value in the range 1 -28 provide a rotation value of 0-13 and a sign value. For reference, a larger version of the tables 1305 / 1307 are given in Figure 13C. The product vector positive lookup table 1321 and product vector negative lookup table 1323 each take as input the right rotate value from 1311 and provide a corresponding residue value, with (as the modulus 29 has 2 as a primitive root) the result from the XNOR logic 1313 selecting which value is final result. For reference, a larger versions of the tables 1321 and 1323 are given in Figures 13d and 13E.

[0084] Figure 14 is a flowchart for an embodiment of a flowchart for implementing multiplication for a prime modulus based on the rotation of a 1 -hot vector. The modulus can be one of the moduli selected for an RNS channel of the multiplication circuit of Figure 2B, where these can be selected as the set of smallest prime number that either have a primitive root of 2 and also the add primes, such as those indicated in Figure 10, that can provide all of the needed values between the positive and negative remainders. At 1401 a first modulo p number, corresponding to the operand SrcO of Figure 12 is received, where this can be in a binary format and from the corresponding portion of the register 211 i of Figure 2B. Using the 1 dimensional lookup table 1201 , a corresponding 1 -hot vector (i.e., a binary valued vector with at most one of the values of the vector being one and other values of the vector being zero) is determined at 1403. If positive and negative remainders are used, allowing smaller registers, a corresponding sign from lookup table 1203 is also determined at 1403.

[0085] At 1405 a second modulo p number, corresponding to the operand Src1 of Figure 12 is received, where this can be in a binary format and from the corresponding portion of the register 2112 of Figure 2B. Using the 1 dimensional lookup table 1205, a corresponding first rotate amount is determined at 1407. If positive and negative remainders are used, allowing smaller registers, a corresponding sign from lookup table 1203 is also determined at 1407. (Although following 1401 and 1403 in Figure 14, 1405 and 1407 will typically performed concurrently.)

[0086] The right rotate of the 1 -hot vector representation of the first operand by the rotate amount corresponding to the second operand then occurs at 1409, where this can be performed in the registers of the right rotate block 1211. At 1411 , the modulo p result of the multiplication is then determined from a one dimensional lookup table of tables 1221 and 1223, where the two tables are used if positive and negative remainders were used. Which table is selected by the MUX 1215 is based on the XNOR / XOR logic 1213 result of the sign values from the tables 1203 and 1207. Although not included in the flow of Figure 14, the final result for the product can also account for a zero value of the second operation by the zero detect logic 1209 and the AND logic 1217.

[0087] Consequently, the embodiments presented above can provide a unique representation of multiplier and multiplicand as residuals for modulo n using 1 dimensional lookup tables. The residuals can then be represented in hardware as 1- hot bit vector and rotate amount, where the size of the vector and corresponding registers can be cut in half by using both positive and negative remainders. Multiplication can then be implemented by a simple rotate operation, with no adders and no division. The product residuals can then calculated by reverse 1 dimensional lookup tables based on rotate result and the XOR / XNOR of forward residual signs. This can be important for any RNS applications involving multiplications or multiply- accumulate operations. Additionally, it expands the choice of RNS moduli from 2kor 2k-1to a large number of primes, both all primes with a primitive root of 2 and also a number of primes without a primitive root of 2. Since power and area of each RNS channel is determined by RNS width, being able to use such smaller primes lowers power and area requirements. Consequently, among the applications where these techniques can be applied are: digital speech processing, including FIR filters andfault-tolerant digital speech processing chips; neural networks, such as large language models (e.g., ChatGPT), “transformers”, vision recognition, and speech recognition; graphics (GPU); general purpose computing (CPU); SIMD computing (vector processing); and fault tolerant systems (using redundant “channels” for error detection and correction), among others.

[0088] Figure 15 is a high-level block diagram of a computing system 1500 that can be used to implement various embodiments of the microprocessors described above. In one example, the computing system 1500 is a network system 1500. Specific devices may utilize all of the components shown, or only a subset of the components, and levels of integration may vary from device to device. Furthermore, a device may contain multiple instances of a component, such as multiple processing units, processors, memories, transmitters, receivers, etc.

[0089] The network system may comprise a computing system 1501 equipped with one or more input / output devices, such as network interfaces, storage interfaces, and the like. The computing system 1501 may include a central processing unit (CPU) 1510, a memory 1520, a mass storage device 1530, and an I / O interface 1560 connected to a bus 1570, where the CPU can include a microprocessor such as described above with respect to Figures 1A-B. The computing system 1501 is configured to connect to various input and output devices (keyboards, displays, etc.) through the I / O interface 1560. The bus 1570 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus or the like.

[0090] The CPU 1510 may comprise any type of electronic data processor, including the microprocessor 120 of Figure 1 B, which includes divide circuits (e.g., any of the divide circuits described above). The CPU 1510 may be configured to implement any of the schemes described herein with respect to division, using any one or combination of steps described in the embodiments. The memory 1520 may comprise any type of system memory such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), a combination thereof, or the like. In an embodiment, the memory 1520 may include ROM for use at boot-up, and DRAM for program and data storage for use while executing programs.

[0091] The mass storage device 1530 may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 1570. The mass storage device 1530 may comprise, for example, one or more of a solid-state drive, hard disk drive, a magnetic disk drive, an optical disk drive, or the like.

[0092] The computing system 1501 also includes one or more network interfaces 1550, which may comprise wired links, such as an Ethernet cable or the like, and / or wireless links to access nodes or one or more networks 1580. The network interface 1550 allows the computing system 1501 to communicate with remote units via the network 1580. For example, the network interface 1550 may provide wireless communication via one or more transmitters / transmit antennas and one or more receivers / receive antennas. In an embodiment, the computing system 1501 is coupled to a local-area network or a wide-area network for data processing and communications with remote devices, such as other processing units, the Internet, remote storage facilities, or the like. In one embodiment, the network interface 1550 may be used to receive and / or transmit interest packets and / or data packets in an ICN. Herein, the term “network interface” will be understood to include a port.

[0093] The components depicted in the computing system of Figure 10 are those typically found in computing systems suitable for use with the technology described herein, and are intended to represent a broad category of such computer components that are well known in the art. Many different bus configurations, network platforms, and operating systems can be used.

[0094] The technology described herein can be implemented using hardware, firmware, software, or a combination of these. Depending on the embodiment, these elements of the embodiments described above can include hardware only or a combination of hardware and software (including firmware). For example, logic elements programmed by firmware to perform the functions described herein is one example of elements of the described multiplication circuit. A multiplication circuit can include a processor, FGA, ASIC, integrated circuit or other type of circuit. The software used is stored on one or more of the processor readable storage devices described above to program one or more of the processors to perform the functions described herein. The processor readable storage devices can include computer readablemedia such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information, and which can be accessed by a computer. A computer readable medium or media does (do) not include propagated, modulated or transitory signals.

[0095] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

[0096] In alternative embodiments, some or all of the software can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Applicationspecific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media / storage devices, peripherals and / or communication interfaces.

[0097] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

[0098] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0099] The description of the present disclosure has been presented for purposes of illustration and description but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated.

[0100] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices.Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.

[0101] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

CLAIMSWhat is claimed is:

1. A multiplication circuit, comprising: a one dimensional vector lookup table configured to receive a first modulo p input number, where p is a prime number, and to provide a corresponding first binary valued vector output, wherein, at most, one of the values of the vector being one and other values of the vector being zero; a one dimensional rotate lookup table configured to receive a second modulo p input number and to provide a corresponding first rotate amount; a rotate circuit configured to receive the first binary valued vector and the first rotate amount and to rotate the first binary valued vector by the first rotate amount; and a first one dimensional product vector lookup table configured to receive the first binary valued vector rotated by the first rotate amount and to provide a corresponding first modulo p product of the first modulo p input number and the second modulo p input number.

2. The multiplication circuit of claim 1 , further comprising: a zero detect circuit configured to receive the second modulo p input number and determine an output indicating whether the second modulo p input number has a value of zero; and a logic circuit connected to receive the output of the zero detect circuit and the first modulo p product and to set the modulo p product to zero in response to the output of the zero detect circuit indicating that the second modulo p input number has a value of zero.

3. The multiplication circuit of either of claims 1 and 2, wherein the binary valued vector output is of (p-1 ) values and first rotate amount is between 0 and (p-1 ).

4. The multiplication circuit of either of claims 1 and 2, wherein the binary valued vector output is of (p-1 ) / 2 values and first rotate amount is between 0 and (p-5. The multiplication circuit of claim 4, further comprising: a first one dimensional sign value lookup table configured to receive the first modulo p input number and provide a corresponding first sign value; a second one dimensional sign value lookup table configured to receive the second modulo p input number and provide a corresponding second sign value; a second one dimensional product vector lookup table configured to receive the first binary valued vector rotated by the first rotate amount and provide a corresponding second modulo p product of the first modulo p input number and the second modulo p input number; a logic circuit configured to receive the first sign value and the second sign value and to provide a logical combination of the first sign value and the second sign value; and a multiplexer configured provide as output either the first modulo p product or the second modulo p product based on the logical combination of the first sign value and the second sign value.

6. The multiplication circuit of claim 5, wherein p has a primitive root of two and the logic circuit is an XNOR circuit.

7. The multiplication circuit of claim 5, wherein p does not have a primitive root of two and the logic circuit is an XOR circuit.

8. A method of performing modulo p multiplication, where p is a prime number, comprising: receiving a first modulo p input number; determining from a one dimensional vector lookup table a corresponding first binary valued vector for the first modulo p number, at most one of the values of the vector being one and other values of the vector being zero; receiving a second modulo p input number; determining from a one dimensional rotate lookup table a corresponding first rotate amount corresponding to the second modulo p number; rotating the first binary valued vector by the first rotate amount; anddetermining from a first one dimensional product vector lookup table a first modulo p product of the first modulo p input number and the second modulo p input number from the first binary valued vector rotated by the first rotate amount.

9. The method of claim 8, further comprising: determining whether the second modulo p input number has a value of zero; and setting the modulo p product to zero in response to determining that the second modulo p input number has a value of zero.

10. The method of either of claims 8 and 9, wherein the binary valued vector output is of (p-1 ) values and first rotate amount is between 0 and (p-1 ).11 . The method of either of claims 8 and 9, wherein the binary valued vector output is of (p-1 ) / 2 values and first rotate amount is between 0 and (p-1 ) / 2.

12. The method of claim 11 , further comprising: determining a corresponding first sign value for the first modulo p input number from a first one dimensional sign value lookup table; determining a corresponding second sign value for the second modulo p input number from a second one dimensional sign value lookup table; determining from a second one dimensional product vector lookup table a second modulo p product of the first modulo p input number and the second modulo p input number from the first binary valued vector rotated by the first rotate amount; forming a logical combination of the first sign value and the second sign value; and selecting either the first modulo p product or the second modulo p product as a result of the multiplication based on the logical combination of the first sign value and the second sign value.

13. The method of claim 12, wherein p has a primitive root of two and the logical combination is an XNOR.

14. The method of claim 12, wherein p does not have a primitive root of two and the logical combination is an n XOR.

15. An arithmetical logic circuit, comprising: a plurality of mod-p arithmetic units, each for a different value of a prime number p and each configured to receive mod-p components of input values in a residual number format system, each mod-p arithmetic unit including a multiplication circuit comprising: a one dimensional vector lookup table configured to receive a first modulo p input number, where p is a prime number, and provide a corresponding first binary valued vector output, at most one of the values of the vector being one and other values of the vector being zero; a one dimensional rotate lookup table configured to receive a second modulo p input number and provide a corresponding first rotate amount; a rotate circuit configured to receive the first binary valued vector and the first rotate amount and to rotate the first binary valued vector by the first rotate amount; and a first one dimensional product vector lookup table configured to receive the first binary valued vector rotated by the first rotate amount and provide a corresponding first modulo p product of the first modulo p input number and the second modulo p input number.

16. The arithmetical logic circuit of claim 15, further comprising: a first input register configured to receive the first modulo p input numbers for each of the plurality of the mod-p arithmetic units and provide each of the first modulo p input numbers to the corresponding one of the mod-p arithmetic units; a second input register configured to receive the second modulo p input numbers for each of the plurality of the mod-p arithmetic units and provide each of the second modulo p input numbers to the corresponding one of the mod-p arithmetic units; and a result register configured to receive the first modulo p product of each of the plurality of mod-p arithmetic units.

17. The arithmetical logic circuit of either of claims 15 and 16, the multiplication circuit of each mod-p arithmetic unit further comprising: a zero detect circuit configured to receive the second modulo p input number and determine an output indicating whether the second modulo p input number has a value of zero; and a logic circuit connected to receive the output of the zero detect circuit and the modulo p product and to set the modulo p product to zero in response to the output of the zero detect circuit indicating that the second modulo p input number has a value of zero.

18. The arithmetical logic circuit of any of claims 15-17, wherein the binary valued vector output is of (p-1 ) values and first rotate amount is between 0 and (p-1 ).

19. The arithmetical logic circuit of any of claims 15-17, wherein the binary valued vector output is of (p-1 ) / 2 values and first rotate amount is between 0 and (p- 1 ) / 2.

20. The arithmetical logic circuit of claim 19, the multiplication circuit of each mod-p arithmetic unit further comprising: a first one dimensional sign value lookup table configured to receive the first modulo p input number and provide a corresponding first sign value; a second one dimensional sign value lookup table configured to receive the second modulo p input number and provide a corresponding second sign value; a second one dimensional product vector lookup table configured to receive the first binary valued vector rotated by the first rotate amount and provide a second modulo p product of the first modulo p input number and the second modulo p input number; a logic circuit configured to receive the first sign value and the second sign value and to provide a logical combination of the first sign value and the second sign value; anda multiplexer configured provide as output either the first modulo p product or the second modulo p product based on the logical combination of the first sign value and the second sign value.21 . The arithmetical logic circuit of claim 20, wherein p has a primitive root of two and the logic circuit is an XNOR circuit.

22. The arithmetical logic circuit of claim 20, wherein p does not have a primitive root of two and the logic circuit is an XOR circuit.

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