Runtime reconfigurable artificial intelligence chip, processing unit, calculation task execution method and electronic equipment

Abstract

The invention relates to the technical field of artificial intelligence chips, in particular to a runtime reconfigurable artificial intelligence chip, processing units, a calculation task execution method and electronic equipment, the chip comprises a controller and a plurality of processing units, the controller obtains a calculation task, analyzes the calculation task, and sends the calculation task to the processing units; obtaining a plurality of sub-calculation tasks and quantization bits corresponding to the sub-calculation tasks; the processing unit comprises an interception register, a first multiplier, a second multiplier, a shifter, an adder, a splicing register and a multiplexer and is used for processing a specified sub-calculation task, a quantization bit corresponding to the specified sub-calculation task is a specified quantization bit, the controller configures the quantization bit of the processing unit according to the specified quantization bit, and the processing unit is used for processing the specified sub-calculation task according to the quantization bit. Therefore, the runtime reconstruction of the artificial intelligence chip is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to a runtime reconfigurable artificial intelligence chip, a processing unit, a computing task execution method, and an electronic device. Background Art

[0002] Neural network models often use high-precision parameters (e.g., 32-bit floating point numbers) to represent weights and activation values. However, this representation may take up a lot of memory and computing resources, limiting the application of neural network models in resource-constrained devices such as mobile devices and embedded systems. Neural network quantization can be used to reduce the computing and storage resource requirements of neural network models. It converts weights and activation values ​​from high-precision representation (e.g., 32 bits, etc.) to low-precision representation (e.g., 16 bits, 8 bits, 4 bits, 2 bits, 1 bit, etc.), which can significantly reduce the model's storage resource requirements and reduce computing costs, thereby speeding up model processing.

[0003] Quantization includes weight quantization and activation quantization. Weight quantization converts the weight parameters in the neural network into low-precision representation, while activation quantization converts the activation value (i.e., the output of the intermediate layer) in the neural network into a low-precision representation. The processing units (PEs) in existing artificial intelligence chips are usually designed for a fixed number of quantization bits and can only calculate weight parameters with a fixed number of quantization bits, such as only 16-bit weight parameters or only 8-bit weight parameters. The chips have poor versatility, which increases the manufacturing and use costs of the chips and is not conducive to the promotion and application of the chips. On the other hand, existing artificial intelligence chips cannot adaptively set the number of quantization bits according to actual computing needs, resulting in inflexible configuration of computing resources and affecting computing efficiency. Summary of the invention

[0004] In order to solve the problems in the related art, the embodiments of the present disclosure provide a runtime reconfigurable artificial intelligence chip, a processing unit, a computing task execution method and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a runtime reconfigurable artificial intelligence chip, including a controller and a plurality of processing units, wherein:

[0006] The controller is used to obtain a computing task, parse the computing task, and obtain a plurality of sub-computing tasks and quantization bits corresponding to the sub-computing tasks, wherein the sub-computing task includes calculating the product of first input data and second input data, and the quantization bits include the quantization bits of the second input data;

[0007] The processing unit is used to process a specified sub-computation task among the multiple sub-computation tasks, and the number of quantization bits corresponding to the specified sub-computation task is the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit is used to process one specified sub-computation task, and when the specified number of quantization bits is within a second number range, the processing unit is used to process two specified sub-computation tasks, and the processing unit includes:

[0008] A truncation register, used for dividing the truncation register input into high-order input sub-data and low-order input sub-data, wherein: when the specified quantization bit number is within a first bit number range, the truncation register input includes the second input data of the one specified sub-computing task; when the specified quantization bit number is within a second bit number range, the truncation register input includes the concatenation result of the second input data of the two specified sub-computing tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computing tasks respectively;

[0009] a first multiplier, the first multiplier being used for multiplying the first input data by the high-order input sub-data to obtain a first multiplier output;

[0010] a second multiplier, the second multiplier being used for multiplying the first input data by the low-order input sub-data to obtain a second multiplier output;

[0011] a shifter, the shifter being used for, when the specified number of quantization bits is within the range of the first number of bits, shifting the output of the first multiplier to obtain a shift result;

[0012] an adder, the adder being used for, when the specified quantization bit number is within the first bit number range, adding the shift result and the output of the second multiplier to obtain a first calculation result;

[0013] a splicing register, the splicing register being used to, when the specified quantization bit number is within the range of the second bit number, splice the first multiplier output with the second multiplier output to obtain a second calculation result;

[0014] A multiplexer is used to selectively output the first calculation result and the second calculation result according to the specified number of quantization bits.

[0015] According to an embodiment of the present disclosure, the designated sub-computing task includes calculating the product of a first input data and a second input data; when the designated quantization bit number is within the second bit number range, the first input data of the two designated sub-computing tasks are the same.

[0016] According to an embodiment of the present disclosure, the minimum value of the first range of digits is greater than the maximum value of the second range of digits.

[0017] According to an embodiment of the present disclosure, the first bit range is greater than 8 bits and less than or equal to 16 bits, and the second bit range is less than or equal to 8 bits; or, the first bit range is 16 bits, and the second bit range is any one of 8 bits, 4 bits, 2 bits, and 1 bit; the number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

[0018] According to an embodiment of the present disclosure, the intercept register divides the intercept register input into high-bit input sub-data and low-bit input sub-data of equal bit number.

[0019] According to an embodiment of the present disclosure, the first multiplier output includes a reserved bit set at the highest bit of the first multiplier output; and / or the second multiplier output includes a reserved bit set at the highest bit of the second multiplier output.

[0020] According to an embodiment of the present disclosure, the reserved bit is used to determine whether a calculation result of the corresponding multiplier has overflow.

[0021] According to an embodiment of the present disclosure, the first bit number range is greater than 8 bits and less than or equal to 16 bits, the second bit number range is less than or equal to 8 bits, and the bit number of the first input data is 16 bits: the first multiplier is a 16-bit * 8-bit multiplier, and the second multiplier is a 16-bit * 8-bit multiplier; the shifter is used to shift the output of the first multiplier left by 8 bits.

[0022] According to an embodiment of the present disclosure, the output of the first multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the high-order input sub-data; the output of the second multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the low-order input sub-data.

[0023] According to an embodiment of the present disclosure, the splicing register is used to splice the first multiplier output with the second multiplier output to obtain a 50-bit second calculation result.

[0024] According to an embodiment of the present disclosure, when the specified number of quantization bits is within a first range of bits, the splicing register is disabled; when the specified number of quantization bits is within a second range of bits, the shifter and the adder are disabled.

[0025] According to an embodiment of the present disclosure, when the specified number of quantization bits is within a first number range, the multiplexer outputs the first calculation result; when the specified number of quantization bits is within a second number range, the multiplexer outputs the second calculation result.

[0026] According to an embodiment of the present disclosure, the processing unit is used to calculate the product of the input of the convolution kernel and the weight parameters of the convolution kernel, wherein the first input data includes the input of the convolution kernel, and the second input data includes the weight parameters of the convolution kernel; and / or the processing unit is used to calculate the product of the input of the neuron and the weight parameters of the neuron, wherein the first input data includes the input of the neuron, and the second input data includes the weight parameters of the neuron.

[0027] According to an embodiment of the present disclosure, when the specified number of quantization bits is within the range of the first number of bits, the processing unit is used to calculate the product of the input of a convolution kernel and the weight parameter of the convolution kernel; when the specified number of quantization bits is within the range of the second number of bits, the processing unit is used to calculate the product of the input of each of two convolution kernels and the weight parameter of each of the two convolution kernels, and the inputs of the two convolution kernels are equal.

[0028] According to an embodiment of the present disclosure, the controller includes a configuration word pin, and the output level of the configuration word pin is determined according to a specified number of quantization bits. When the specified number of quantization bits is within the range of the first number of bits, the output level of the configuration word pin is a first level, and when the specified number of quantization bits is within the range of the second number of bits, the output level of the configuration word pin is a second level, and the first level is different from the second level; the output level of the configuration word pin is used to control the multiplexer to selectively output the first calculation result and the second calculation result, and / or to disable any one or more of the shifter, the adder, and the splicing register.

[0029] A second aspect of the present disclosure provides a processing unit of a runtime reconfigurable artificial intelligence chip, the processing unit being used to process a specified sub-computing task, the specified sub-computing task comprising calculating the product of first input data and second input data, the number of quantization bits corresponding to the specified sub-computing task being the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit is used to process one specified sub-computing task, and when the specified number of quantization bits is within a second number range, the processing unit is used to process two specified sub-computing tasks, the processing unit comprising:

[0030] A truncation register, used for dividing the truncation register input into high-order input sub-data and low-order input sub-data, wherein: when the specified quantization bit number is within a first bit number range, the truncation register input includes the second input data of the one specified sub-computing task; when the specified quantization bit number is within a second bit number range, the truncation register input includes the concatenation result of the second input data of the two specified sub-computing tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computing tasks respectively;

[0031] a first multiplier, the first multiplier being used for multiplying the first input data by the high-order input sub-data to obtain a first multiplier output;

[0032] a second multiplier, the second multiplier being used for multiplying the first input data by the low-order input sub-data to obtain a second multiplier output;

[0033] a shifter, the shifter being used for, when the specified number of quantization bits is within the range of the first number of bits, shifting the output of the first multiplier to obtain a shift result;

[0034] an adder, the adder being used for, when the specified quantization bit number is within the first bit number range, adding the shift result and the output of the second multiplier to obtain a first calculation result;

[0035] a splicing register, the splicing register being used to, when the specified quantization bit number is within the range of the second bit number, splice the first multiplier output with the second multiplier output to obtain a second calculation result;

[0036] A multiplexer is used to selectively output the first calculation result and the second calculation result according to the specified number of quantization bits.

[0037] According to an embodiment of the present disclosure, the designated sub-computing task includes calculating the product of a first input data and a second input data; when the designated quantization bit number is within the second bit number range, the first input data of the two designated sub-computing tasks are the same.

[0038] According to an embodiment of the present disclosure, the minimum value of the first range of digits is greater than the maximum value of the second range of digits.

[0039] According to an embodiment of the present disclosure, the first bit range is greater than 8 bits and less than or equal to 16 bits, and the second bit range is less than or equal to 8 bits; or, the first bit range is 16 bits, and the second bit range is any one of 8 bits, 4 bits, 2 bits, and 1 bit; the number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

[0040] According to an embodiment of the present disclosure, the intercept register divides the intercept register input into high-bit input sub-data and low-bit input sub-data of equal bit number.

[0041] According to an embodiment of the present disclosure, the first multiplier output includes a reserved bit set at the highest bit of the first multiplier output; and / or the second multiplier output includes a reserved bit set at the highest bit of the second multiplier output.

[0042] According to an embodiment of the present disclosure, the reserved bit is used to determine whether a calculation result of the corresponding multiplier has overflow.

[0043] According to an embodiment of the present disclosure, the first bit number range is greater than 8 bits and less than or equal to 16 bits, the second bit number range is less than or equal to 8 bits, and the bit number of the first input data is 16 bits; the first multiplier is a 16-bit * 8-bit multiplier, and the second multiplier is a 16-bit * 8-bit multiplier; the shifter is used to shift the output of the first multiplier left by 8 bits.

[0044] According to an embodiment of the present disclosure, the output of the first multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the high-order input sub-data; the output of the second multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the low-order input sub-data.

[0045] According to an embodiment of the present disclosure, the splicing register is used to splice the first multiplier output with the second multiplier output to obtain a 50-bit second calculation result.

[0046] According to an embodiment of the present disclosure, when the specified number of quantization bits is within a first range of bits, the splicing register is disabled; when the specified number of quantization bits is within a second range of bits, the shifter and the adder are disabled.

[0047] When the designated number of quantization bits is within a first range of bits, the multiplexer outputs the first calculation result; when the designated number of quantization bits is within a second range of bits, the multiplexer outputs the second calculation result.

[0048] According to an embodiment of the present disclosure, the processing unit is used to calculate the product of the input of the convolution kernel and the weight parameters of the convolution kernel, wherein the first input data includes the input of the convolution kernel, and the second input data includes the weight parameters of the convolution kernel; and / or the processing unit is used to calculate the product of the input of the neuron and the weight parameters of the neuron, wherein the first input data includes the input of the neuron, and the second input data includes the weight parameters of the neuron.

[0049] According to an embodiment of the present disclosure, when the specified number of quantization bits is within the range of the first number of bits, the processing unit is used to calculate the product of the input of a convolution kernel and the weight parameter of the convolution kernel; when the specified number of quantization bits is within the range of the second number of bits, the processing unit is used to calculate the product of the input of each of two convolution kernels and the weight parameter of each of the two convolution kernels, and the inputs of the two convolution kernels are equal.

[0050] According to an embodiment of the present disclosure, the processing unit includes a connecting pin, which is used to connect to a configuration word pin of a controller of the processing unit, and the output level of the configuration word pin is determined according to a specified number of quantization bits. When the specified number of quantization bits is within the range of the first number of bits, the output level of the configuration word pin is a first level, and when the specified number of quantization bits is within the range of the second number of bits, the output level of the configuration word pin is a second level, and the first level is different from the second level; the level of the connecting pin is used to control the multiplexer to selectively output the first calculation result and the second calculation result, and / or to disable any one or more of the shifter, the adder, and the splicing register.

[0051] A third aspect of the present disclosure provides a computing task execution method for a runtime reconfigurable artificial intelligence chip, wherein the runtime reconfigurable artificial intelligence chip includes a controller and a plurality of processing units, wherein the processing units include an intercept register, a first multiplier, a second multiplier, a shifter, an adder, a splicing register, and a multiplexer, and the method includes:

[0052] Acquire a computing task through the controller, parse the computing task to obtain a plurality of sub-computation tasks and the number of quantization bits corresponding to the sub-computation tasks, and assign the sub-computation tasks to corresponding processing units for processing, wherein the sub-computation tasks include calculating the product of first input data and second input data, and the number of quantization bits includes the number of quantization bits of the second input data;

[0053] Processing a specified sub-computing task among the multiple sub-computing tasks by the processing unit, the number of quantization bits corresponding to the specified sub-computing task is the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit processes one specified sub-computing task, and when the specified number of quantization bits is within a second number range, the processing unit processes two specified sub-computing tasks, and the processing of the specified sub-computing task among the multiple sub-computing tasks includes:

[0054] The intercept register input is segmented by the intercept register to obtain high-order input sub-data and low-order input sub-data, wherein: when the designated quantization bit number is within a first bit number range, the intercept register input includes the second input data of the one designated sub-computing task; when the designated quantization bit number is within a second bit number range, the intercept register input includes the concatenation result of the second input data of the two designated sub-computing tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two designated sub-computing tasks respectively;

[0055] multiplying the first input data by the high-order input sub-data through a first multiplier to obtain a first multiplier output;

[0056] multiplying the first input data and the low-order input sub-data by a second multiplier to obtain a second multiplier output;

[0057] When the designated quantization bit number is within the first bit number range, the first multiplier output is shifted by a shifter to obtain a shift result, and the shift result is added to the second multiplier output by an adder to obtain a first calculation result;

[0058] When the specified quantization bit number is within the range of the second bit number, splicing the first multiplier output and the second multiplier output through a splicing register to obtain a second calculation result;

[0059] The first calculation result and the second calculation result are selectively outputted through a multiplexer according to the designated number of quantization bits.

[0060] According to an embodiment of the present disclosure, the controller includes a configuration word pin, and the output level of the configuration word pin is determined according to a specified number of quantization bits. When the specified number of quantization bits is within the range of the first number of bits, the output level of the configuration word pin is a first level, and when the specified number of quantization bits is within the range of the second number of bits, the output level of the configuration word pin is a second level, and the first level is different from the second level. The method further includes:

[0061] The output level of the configuration word pin controls the multiplexer to selectively output the first calculation result and the second calculation result, and / or disables any one or more of the shifter, the adder, and the splicing register.

[0062] According to an embodiment of the present disclosure, the designated sub-computing task includes calculating the product of a first input data and a second input data; when the designated quantization bit number is within the second bit number range, the first input data of the two designated sub-computing tasks are the same.

[0063] According to an embodiment of the present disclosure, the minimum value of the first range of digits is greater than the maximum value of the second range of digits, that is, the first range of digits has no intersection with the second range of digits.

[0064] According to an embodiment of the present disclosure, the first digit range is greater than 8 bits and less than or equal to 16 bits, and the second digit range is less than or equal to 8 bits; or, the first digit range is 16 bits, and the second digit range is any one of 8 bits, 4 bits, 2 bits, and 1 bit. The number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

[0065] According to an embodiment of the present disclosure, the intercept register divides the intercept register input into high-bit input sub-data and low-bit input sub-data of equal bit number.

[0066] According to an embodiment of the present disclosure, the first multiplier output includes a reserved bit set in the highest bit of the first multiplier output; and / or the second multiplier output includes a reserved bit set in the highest bit of the second multiplier output, and the reserved bit is used to determine whether the calculation result of the corresponding multiplier has overflow.

[0067] According to an embodiment of the present disclosure, the first bit number range is greater than 8 bits and less than or equal to 16 bits, the second bit number range is less than or equal to 8 bits, and the bit number of the first input data is 16 bits: the first multiplier is a 16-bit * 8-bit multiplier, and the second multiplier is a 16-bit * 8-bit multiplier; the shifter is used to shift the output of the first multiplier left by 8 bits.

[0068] According to an embodiment of the present disclosure, the output of the first multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the high-order input sub-data; the output of the second multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the low-order input sub-data, and the splicing register is used to splice the output of the first multiplier with the output of the second multiplier to obtain a 50-bit second calculation result.

[0069] According to an embodiment of the present disclosure, the method further includes: when the specified number of quantization bits is within a first number range, disabling the splicing register; when the specified number of quantization bits is within a second number range, disabling the shifter and the adder.

[0070] According to an embodiment of the present disclosure, when the specified number of quantization bits is within a first number range, the multiplexer outputs the first calculation result; when the specified number of quantization bits is within a second number range, the multiplexer outputs the second calculation result.

[0071] According to an embodiment of the present disclosure, the processing unit is used to calculate the product of the input of the convolution kernel and the weight parameters of the convolution kernel, wherein the first input data includes the input of the convolution kernel, and the second input data includes the weight parameters of the convolution kernel; and / or the processing unit is used to calculate the product of the input of the neuron and the weight parameters of the neuron, wherein the first input data includes the input of the neuron, and the second input data includes the weight parameters of the neuron.

[0072] According to an embodiment of the present disclosure, when the specified number of quantization bits is within the range of the first number of bits, the processing unit is used to calculate the product of the input of a convolution kernel and the weight parameter of the convolution kernel; when the specified number of quantization bits is within the range of the second number of bits, the processing unit is used to calculate the product of the input of each of the two convolution kernels and the weight parameter of each of the two convolution kernels, and the inputs of the two convolution kernels are equal.

[0073] A fourth aspect of the present disclosure provides an electronic device, comprising a runtime reconfigurable artificial intelligence chip according to any one of the above items, or comprising a processing unit according to any one of the above items.

[0074] According to the embodiments of the present disclosure, when executing artificial intelligence computing tasks, the number of quantization bits of each processing unit in the artificial intelligence chip can be flexibly configured according to the needs of the computing tasks, thereby solving the technical problem in the prior art that the number of quantization bits of the processing unit cannot be adaptively set according to actual computing needs, improving computing resource utilization and computing efficiency, enhancing chip versatility, and facilitating the large-scale promotion and application of the chip.

[0075] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0077] Figure 1A structural block diagram of a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown.

[0078] Figure 2 A structural block diagram of a processing unit in a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown.

[0079] Figure 3 A flowchart of a method for executing computing tasks in a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown.

[0080] Figure 4 A flowchart of processing a specified sub-computing task among the multiple sub-computing tasks according to an embodiment of the present disclosure is shown.

[0081] Figure 5 A specific example of a computing task execution method for a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown.

[0082] Figure 6 Another specific example of a computing task execution method for a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0083] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0084] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0085] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0086] As mentioned above, the processing units in existing artificial intelligence chips are usually designed for a fixed number of quantization bits, and can only calculate weight parameters with a fixed number of quantization bits, such as only 16-bit weight parameters or only 8-bit weight parameters. The chip has poor versatility, which increases the manufacturing and use costs of the chip and is not conducive to the promotion and application of the chip. On the other hand, existing artificial intelligence chips cannot adaptively set the number of quantization bits according to actual computing needs, resulting in inflexible configuration of computing resources and affecting computing efficiency.

[0087] The present disclosure provides a runtime reconfigurable artificial intelligence chip, characterized in that it includes a controller and a plurality of processing units, wherein: the controller is used to obtain a computing task, parse the computing task, obtain a plurality of sub-computing tasks and the number of quantization bits corresponding to the sub-computing tasks, the sub-computing task includes calculating the product of a first input data and a second input data, and the number of quantization bits includes the number of quantization bits of the second input data; the processing unit is used to process a specified sub-computing task among the plurality of sub-computing tasks, and the number of quantization bits corresponding to the specified sub-computing task is the specified number of quantization bits, wherein when the specified number of quantization bits is within the range of a first number of bits, the processing unit is used to process one specified sub-computing task, and when the specified number of quantization bits is within the range of a second number of bits, the processing unit is used to process two specified sub-computing tasks, and the processing unit includes: a capture register, used to split the capture register input to obtain high-order input sub-data and low-order input sub-data, wherein: when the specified number of quantization bits is within the range of a first number of bits, the capture register input includes the second input data of the specified sub-computing task; when the specified number of quantization bits is within the range of a second number of bits, the capture register input The method comprises a concatenation result of the second input data of the two specified sub-computation tasks, wherein the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computation tasks respectively; a first multiplier, wherein the first multiplier is used to multiply the first input data with the high-order input sub-data to obtain a first multiplier output; a second multiplier, wherein the second multiplier is used to multiply the first input data with the low-order input sub-data to obtain a second multiplier output; and a shifter, wherein the shifter is used to shift the first multiplier output when the specified quantization bit number is within the first bit number range. The output of the multiplier is shifted to obtain a shift result; an adder, the adder is used to add the shift result and the second multiplier output to obtain a first calculation result when the specified quantization bit number is within the first bit range; a splicing register, the splicing register is used to splice the first multiplier output and the second multiplier output to obtain a second calculation result when the specified quantization bit number is within the second bit range; a multiplexer, the multiplexer is used to selectively output the first calculation result and the second calculation result according to the specified quantization bit number.

[0088] According to the embodiments of the present disclosure, when executing artificial intelligence computing tasks, the number of quantization bits of each processing unit in the artificial intelligence chip can be flexibly configured according to the requirements of the task, thereby solving the technical problem in the prior art that the number of quantization bits of the processing unit cannot be adaptively set according to actual computing needs, improving computing resource utilization and computing efficiency, enhancing chip versatility, and facilitating the large-scale promotion and application of the chip.

[0089] Figure 1 A structural block diagram of a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown.

[0090] like Figure 1 As shown, the runtime reconfigurable artificial intelligence chip according to the embodiment of the present disclosure includes a controller and a plurality of processing units (PEs). The controller is used to obtain a computing task, parse the computing task, obtain a plurality of sub-computing tasks and the number of quantization bits corresponding to the sub-computing tasks, the sub-computing task includes calculating the product of the first input data and the second input data, and the number of quantization bits includes the number of quantization bits of the second input data.

[0091] According to an embodiment of the present disclosure, the computing task may be an artificial intelligence computing task, such as a computing task involved in training or reasoning of a neural network, such as a convolution operation, a neuron calculation, etc., but not limited thereto. The controller parses the computing task to obtain a plurality of sub-computing tasks and the number of quantization bits corresponding to the sub-computing tasks.

[0092] For example, when the computing task is a convolution operation, the sub-computation task obtained by parsing the computing task may include multiplying the input of the convolution kernel by the weight parameter of the convolution kernel, wherein the first input data of the sub-computation task includes the input of the convolution kernel, the second input data includes the weight parameter of the convolution kernel, and the number of quantization bits corresponding to the sub-computation task is the number of quantization bits of the weight parameter of the convolution kernel. When the computing task is a neuron calculation, the sub-computation task obtained by parsing the computing task may include multiplying the input of the neuron by the weight parameter of the neuron, wherein the first input data of the sub-computation task includes the input of the neuron, the second input data includes the weight parameter of the neuron, and the number of quantization bits corresponding to the sub-computation task is the number of quantization bits of the weight parameter of the neuron. It can be understood that the processing unit in the artificial intelligence chip according to the embodiment of the present disclosure can be used to perform various product operations, not limited to the product operations in the above examples.

[0093] According to an embodiment of the present disclosure, the processing unit is used to process a specified sub-computation task among the multiple sub-computation tasks, and the number of quantization bits corresponding to the specified sub-computation task is the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit is used to process one specified sub-computation task; when the specified number of quantization bits is within a second number range, the processing unit is used to process two specified sub-computation tasks with the same first input data, and the minimum value of the first number range is greater than the maximum value of the second number range.

[0094] According to an embodiment of the present disclosure, the first digit range may be greater than 8 bits and less than or equal to 16 bits, and the second digit range may be less than or equal to 8 bits; or, the first digit range may be 16 bits, and the second digit range may be any one of 8 bits, 4 bits, 2 bits, and 1 bit. According to an embodiment of the present disclosure, the number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

[0095] In a specific example, the number of bits of the first input data is 16 bits, the first number range is greater than 8 bits and less than or equal to 16 bits, and the second number range is less than or equal to 8 bits. In this case, when the specified quantization bit number is 16 bits, the corresponding processing unit processes one specified sub-computing task, and when the specified quantization bit number is any one of 8 bits, 4 bits, 2 bits, and 1 bit, the corresponding processing unit processes two specified sub-computing tasks, and the first input data of the two specified sub-computing tasks are the same.

[0096] exist Figure 1 In the embodiment, the controller includes a plurality of configuration word pins connected to each processing unit respectively. After the controller parses and obtains a plurality of sub-computation tasks, the controller assigns the plurality of sub-computation tasks to the processing units for execution, and configures the quantization bits of the corresponding processing units through the configuration word pins according to the quantization bits corresponding to each sub-computation task, thereby realizing adaptive configuration of the quantization bits of the processing units according to the needs of the computing tasks at runtime. According to an embodiment of the present disclosure, the output level of the configuration word pin is determined according to the quantization bit number of the corresponding processing unit, and when the quantization bit number is within the range of the first bit number, the output level of the configuration word pin is a first level, and when the quantization bit number is within the range of the second bit number, the output level of the configuration word pin is a second level, and the first level is different from the second level.

[0097] Figure 2 A structural block diagram of a processing unit in a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown.

[0098] like Figure 2 As shown, the processing unit according to the embodiment of the present disclosure includes: a truncation register, a first multiplier, a second multiplier, a shifter, an adder, a splicing register, and a multiplexer.

[0099] The truncation register divides the truncation register input into high-order input sub-data and low-order input sub-data, wherein, when the specified number of quantization bits is within the range of a first number of bits, the truncation register input includes the second input data of the one specified sub-computation task; when the specified number of quantization bits is within the range of a second number of bits, the truncation register input includes the concatenation result of the second input data of the two specified sub-computation tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computation tasks respectively.

[0100] The first multiplier is used to multiply the first input data with the high-order input sub-data to obtain a first multiplier output, and the second multiplier is used to multiply the first input data with the low-order input sub-data to obtain a second multiplier output. The number of bits of the first input data and the high-order input sub-data matches the number of bits of the input of the first multiplier, and the number of bits of the first input data and the low-order input sub-data matches the number of bits of the input of the second multiplier.

[0101] The following takes the case where the first input data is 16 bits, the first digit range is greater than 8 bits and less than or equal to 16 bits, the second digit range is less than or equal to 8 bits, the high-order sub-data and the low-order sub-data are both 8 bits, and the first multiplier and the second multiplier are both 16-bit * 8-bit multipliers as an example to illustrate the operation of the interception register and the multiplier.

[0102] When the designated quantization bit number is 16 bits, the designated quantization bit number is within the first bit range, the interception register input is 16-bit second input data, and the interception register divides the second input data into 8-bit high-order input sub-data and 8-bit low-order input sub-data.

[0103] When the specified number of quantization bits is greater than 8 bits and less than 16 bits, the specified number of quantization bits is within the range of the first bit number, the truncation register input is the 16-bit data obtained by filling "0" before the second input data, and the truncation register divides the 16-bit data into 8-bit high-order input sub-data and 8-bit low-order input sub-data.

[0104] When the specified quantization bit number is 8 bits, the specified quantization bit number is within the range of the second bit number, the interception register input is the concatenation result of the two second input data, totaling 16 bits, and the interception register divides the 16-bit concatenation result into 8-bit high-order input sub-data and 8-bit low-order input sub-data.

[0105] When the specified number of quantization bits is less than 8 bits, the specified number of quantization bits is within the range of the second number of bits, and the truncation register input is a 16-bit splicing result obtained by filling "0" to 8 bits in front of the two second input data and then splicing them. The truncation register divides the 16-bit splicing result into 8-bit high-order input sub-data and 8-bit low-order input sub-data.

[0106] The first multiplier multiplies the 16-bit first input data and the 8-bit high-order input sub-data to obtain a first multiplier output, and the second multiplier multiplies the 16-bit first input data and the 8-bit high-order input sub-data to obtain a second multiplier output.

[0107] When the designated quantization bit number is within the first bit range, the shifter shifts the first multiplier output to obtain a shift result, and the adder adds the shift result to the second multiplier output to obtain a first calculation result. The shift number of the shifter is set so that the first calculation result output by the adder is equal to the product of the first input data and the second input data.

[0108] When the first input data is 16 bits, the first digit range is greater than 8 bits and less than or equal to 16 bits, the second digit range is less than or equal to 8 bits, the high-order sub-data and the low-order sub-data are both 8 bits, and the first multiplier and the second multiplier are both 16-bit * 8-bit multipliers, the output of the first multiplier is 24 bits, and the output of the second multiplier is 24 bits. The shifter shifts the output of the first multiplier left by 8 bits and adds it to the output of the second multiplier to obtain a 32-bit first calculation result.

[0109] According to an embodiment of the present disclosure, a reserved bit can be set at the highest bit of the first multiplier output and the second multiplier output respectively, for judging whether the calculation result of the corresponding multiplier has overflow. For example, when the calculation result of the multiplier has overflow, the reserved bit is 1, indicating that the calculation is wrong, otherwise the reserved bit is 0. In this case, the first multiplier output and the second multiplier output are each 25 bits, and the first calculation result is 33 bits.

[0110] When the designated quantization bit number is within the second bit range, the concatenation register concatenates the first product and the second product to obtain a second calculation result. The second calculation result includes the product of the first input data and the second input data of the two designated calculation tasks.

[0111] When the first input data is 16 bits, the first digit range is greater than 8 bits and less than or equal to 16 bits, the second digit range is less than or equal to 8 bits, the high-order sub-data and the low-order sub-data are both 8 bits, and the first multiplier and the second multiplier are both 16-bit * 8-bit multipliers, the output of the first multiplier is 24 bits, the output of the second multiplier is 24 bits, and the splicing result is 48 bits.

[0112] When the highest bits of the first multiplier output and the second multiplier output are each set to a reserved bit, the first multiplier output and the second multiplier output are each 25 bits, and the second calculation result is 50 bits.

[0113] The multiplexer selectively outputs the first calculation result and the second calculation result according to the specified number of quantization bits, and when the specified number of quantization bits is within the range of the first number of bits, the multiplexer outputs the first calculation result, and when the specified number of quantization bits is within the range of the second number of bits, the multiplexer outputs the second calculation result. The output level of the configuration word pin of the controller can be used to control the multiplexer to selectively output the first calculation result and the second calculation result.

[0114] According to the embodiments of the present disclosure, not only can the processing unit be flexibly configured at runtime according to the number of quantization bits of the task, but when the number of quantization bits is within the second bit range, two multiplication operations with the same first input data can also be performed simultaneously, thereby improving the versatility and computing efficiency of the chip.

[0115] According to an embodiment of the present disclosure, in order to reduce chip power consumption, when the specified quantization bit number is within a first bit range, the splicing register is disabled; when the specified quantization bit number is within a second bit range, the shifter and the adder are disabled. The output level of the configuration word pin of the controller can be used to disable any one or more of the shifter, the adder, and the splicing register.

[0116] Figure 3 A flowchart of a method for executing a computing task for a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is shown. The runtime reconfigurable artificial intelligence chip includes a controller and a plurality of processing units, wherein the processing units include a capture register, a first multiplier, a second multiplier, a shifter, an adder, a splicing register, and a multiplexer. According to an embodiment of the present disclosure, the runtime reconfigurable artificial intelligence chip may be, for example, the above reference Figure 1 and Figure 2 Described is a runtime reconfigurable AI chip.

[0117] like Figure 3 As shown, the computing task execution method includes steps S1-S2.

[0118] In step S1, a computing task is acquired through the controller, the computing task is parsed to obtain a plurality of sub-computation tasks and the number of quantization bits corresponding to the sub-computation tasks, and the sub-computation tasks are assigned to corresponding processing units for processing, wherein the sub-computation tasks include calculating the product of first input data and second input data, and the number of quantization bits includes the number of quantization bits of the second input data.

[0119] In step S2, a specified sub-computation task among the multiple sub-computation tasks is processed by the processing unit, and the number of quantization bits corresponding to the specified sub-computation task is the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit processes one specified sub-computation task, and when the specified number of quantization bits is within a second number range, the processing unit processes two specified sub-computation tasks.

[0120] Figure 4 A flowchart of processing a specified sub-computing task among the plurality of sub-computing tasks according to an embodiment of the present disclosure is shown. Figure 4 As shown, the processing of the specified sub-computing task among the multiple sub-computing tasks includes steps S21-S24.

[0121] In step S21, the interception register input is split through the interception register to obtain high-order input sub-data and low-order input sub-data, wherein: when the specified quantization bit number is within the range of a first bit number, the interception register input includes the second input data of the one specified sub-computation task; when the specified quantization bit number is within the range of a second bit number, the interception register input includes the concatenation result of the second input data of the two specified sub-computation tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computation tasks respectively.

[0122] In step S22, the first input data is multiplied by the high-order input sub-data through a first multiplier to obtain a first multiplier output; and the first input data is multiplied by the low-order input sub-data through a second multiplier to obtain a second multiplier output.

[0123] In step S23, when the specified number of quantization bits is within the range of the first number of bits, the output of the first multiplier is shifted by a shifter to obtain a shift result, and the shift result is added to the output of the second multiplier by an adder to obtain a first calculation result; when the specified number of quantization bits is within the range of the second number of bits, the output of the first multiplier is spliced ​​with the output of the second multiplier by a splicing register to obtain a second calculation result.

[0124] In step S24, the first calculation result and the second calculation result are selectively outputted through a multiplexer according to the designated number of quantization bits.

[0125] According to an embodiment of the present disclosure, the controller includes a configuration word pin, and the output level of the configuration word pin is determined according to a specified number of quantization bits. When the specified number of quantization bits is within the range of the first number of bits, the output level of the configuration word pin is a first level, and when the specified number of quantization bits is within the range of the second number of bits, the output level of the configuration word pin is a second level, and the first level is different from the second level. The method also includes: controlling the multiplexer to selectively output the first calculation result and the second calculation result through the output level of the configuration word pin, and / or disabling any one or more of the shifter, the adder, and the splicing register, thereby reducing the chip operating power consumption.

[0126] According to an embodiment of the present disclosure, the designated sub-computing task includes calculating the product of a first input data and a second input data; when the designated quantization bit number is within the second bit number range, the first input data of the two designated sub-computing tasks are the same.

[0127] According to an embodiment of the present disclosure, the minimum value of the first range of digits is greater than the maximum value of the second range of digits, that is, the first range of digits has no intersection with the second range of digits.

[0128] According to an embodiment of the present disclosure, the first digit range is greater than 8 bits and less than or equal to 16 bits, and the second digit range is less than or equal to 8 bits; or, the first digit range is 16 bits, and the second digit range is any one of 8 bits, 4 bits, 2 bits, and 1 bit. The number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

[0129] According to an embodiment of the present disclosure, the intercept register divides the intercept register input into high-bit input sub-data and low-bit input sub-data of equal bit number.

[0130] According to an embodiment of the present disclosure, the first multiplier output includes a reserved bit set in the highest bit of the first multiplier output; and / or the second multiplier output includes a reserved bit set in the highest bit of the second multiplier output, and the reserved bit is used to determine whether the calculation result of the corresponding multiplier has overflow. For example, when the calculation result of the multiplier has overflow, the reserved bit is 1, indicating that the calculation is wrong, otherwise the reserved bit is 0.

[0131] According to an embodiment of the present disclosure, the first bit number range is greater than 8 bits and less than or equal to 16 bits, the second bit number range is less than or equal to 8 bits, and the bit number of the first input data is 16 bits: the first multiplier is a 16-bit * 8-bit multiplier, and the second multiplier is a 16-bit * 8-bit multiplier; the shifter is used to shift the output of the first multiplier left by 8 bits.

[0132] According to an embodiment of the present disclosure, the output of the first multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the high-order input sub-data; the output of the second multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the low-order input sub-data, and the splicing register is used to splice the output of the first multiplier with the output of the second multiplier to obtain a 50-bit second calculation result.

[0133] According to an embodiment of the present disclosure, the method further includes: when the specified number of quantization bits is within a first number range, disabling the splicing register; when the specified number of quantization bits is within a second number range, disabling the shifter and the adder.

[0134] According to an embodiment of the present disclosure, when the specified number of quantization bits is within a first number range, the multiplexer outputs the first calculation result; when the specified number of quantization bits is within a second number range, the multiplexer outputs the second calculation result.

[0135] According to an embodiment of the present disclosure, the processing unit is used to calculate the product of the input of the convolution kernel and the weight parameters of the convolution kernel, wherein the first input data includes the input of the convolution kernel, and the second input data includes the weight parameters of the convolution kernel; and / or the processing unit is used to calculate the product of the input of the neuron and the weight parameters of the neuron, wherein the first input data includes the input of the neuron, and the second input data includes the weight parameters of the neuron.

[0136] According to an embodiment of the present disclosure, when the specified number of quantization bits is within the range of the first number of bits, the processing unit is used to calculate the product of the input of a convolution kernel and the weight parameter of the convolution kernel; when the specified number of quantization bits is within the range of the second number of bits, the processing unit is used to calculate the product of the input of each of the two convolution kernels and the weight parameter of each of the two convolution kernels, and the inputs of the two convolution kernels are equal.

[0137] Reference below Figure 5 and Figure 6 A specific example of a method for executing computing tasks in a runtime reconfigurable artificial intelligence chip according to an embodiment of the present disclosure is described.

[0138] In this specific example, the first input data is 16 bits, the first digit range is greater than 8 bits and less than or equal to 16 bits, the second digit range is less than or equal to 8 bits, the high-order sub-data and the low-order sub-data are both 8 bits, and the first multiplier and the second multiplier are both 16-bit * 8-bit multipliers.

[0139] exist Figure 5In the example, it is assumed that the first input data of the designated sub-computing task assigned to the processing unit is 16 bits, the second input data is 16 bits, and the designated quantization bit number is 16 bits. Since the designated quantization bit number is within the range of the first bit number, the processing unit processes a designated sub-computing task and calculates the product of the first input data and the second input data of the designated sub-computing task.

[0140] like Figure 5 As shown, the 16-bit second input data is divided into 8-bit high-order input sub-data and 8-bit low-order input sub-data, which are input into the first multiplier and the second multiplier respectively.

[0141] The first multiplier calculates the product of the 16-bit first input data and the 8-bit high-order input sub-data to obtain a 25-bit first multiplier output, wherein the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0142] The second multiplier calculates the product of the 16-bit first input data and the 8-bit low-order input sub-data to obtain a 25-bit second multiplier output, of which the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0143] The 25-bit first multiplier output is left-shifted by 8 bits by the shifter to obtain a 33-bit shift result, which is added to the 25-bit second multiplier output at the adder to obtain a 33-bit first calculation result.

[0144] The selector selects and outputs according to the value of the configuration word. When the value of the configuration word is 1, the first calculation result is output as the output result of the designated sub-computation task.

[0145] exist Figure 6 In the example, it is assumed that the first input data of the designated sub-computing task assigned to the processing unit is 16 bits, the second input data is 8 bits, and the designated quantization bit number is 8 bits. Since the designated quantization bit number is within the range of the second bit number, the processing unit processes two designated sub-computing tasks and calculates the product of the first input data and the second input data of the two designated computing tasks.

[0146] like Figure 6 As shown, after the two 8-bit second input data are spliced, they are divided into 8-bit high-order input sub-data and 8-bit low-order input sub-data by the intercept register, corresponding to the two 8-bit second input data respectively. The 8-bit high-order input sub-data and the 8-bit low-order input sub-data are input into the first multiplier and the second multiplier respectively.

[0147] The first multiplier calculates the product of the 16-bit first input data and the 8-bit high-order input sub-data to obtain a 25-bit first multiplier output, wherein the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0148] The second multiplier calculates the product of the 16-bit first input data and the 8-bit low-order input sub-data to obtain a 25-bit second multiplier output, of which the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0149] The splicer splices the 25-bit first multiplier output and the 25-bit second multiplier output to obtain a 50-bit second calculation result.

[0150] The selector selects and outputs according to the value of the configuration word. When the value of the configuration word is 0, the second calculation result is output as the output result of the designated sub-computation task.

[0151] Reference below Figure 5 Indicates the situation where the specified quantization bit number is within the first digit range but is less than 16 bits.

[0152] exist Figure 5 In the example, it is assumed that the first input data of the designated sub-computing task assigned to the processing unit is 16 bits, the second input data is 10 bits, and the designated quantization bit number is 10 bits. Since the designated quantization bit number is within the range of the first bit number, the processing unit processes a designated sub-computing task and calculates the product of the first input data and the second input data of the designated sub-computing task.

[0153] like Figure 5 As shown, first fill 0 in the high order of the 10-bit second input data to obtain 16-bit filled second input data, and then divide the 16-bit filled second input data into 8-bit high-order input sub-data and 8-bit low-order input sub-data, which are input into the first multiplier and the second multiplier respectively.

[0154] The first multiplier calculates the product of the 16-bit first input data and the 8-bit high-order input sub-data to obtain a 25-bit first multiplier output, wherein the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0155] The second multiplier calculates the product of the 16-bit first input data and the 8-bit low-order input sub-data to obtain a 25-bit second multiplier output, of which the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0156] The 25-bit first multiplier output is left-shifted by 8 bits by the shifter to obtain a 33-bit shift result, which is added to the 25-bit second multiplier output at the adder to obtain a 33-bit first calculation result.

[0157] The selector selects and outputs according to the value of the configuration word. When the value of the configuration word is 1, the first calculation result is output as the output result of the designated sub-computation task.

[0158] Reference below Figure 6 Indicates that the specified quantization bit number is within the range of the second bit number, but is less than 8 bits.

[0159] exist Figure 6 In the example, it is assumed that the first input data of the designated sub-computing task assigned to the processing unit is 16 bits, the second input data is 4 bits, and the designated quantization bit number is 4 bits. Since the designated quantization bit number is within the range of the second bit number, the processing unit processes two designated sub-computing tasks and calculates the product of the first input data and the second input data of the two designated sub-computing tasks.

[0160] like Figure 6 As shown, two 4-bit second input data are first filled with 0 in the high bit to obtain two 8-bit filled second input data, and the two 8-bit filled second input data are spliced ​​and then divided into 8-bit high-bit input sub-data and 8-bit low-bit input sub-data by the interception register, respectively corresponding to the two 8-bit filled second input data. The 8-bit high-bit input sub-data and the 8-bit low-bit input sub-data are respectively input into the first multiplier and the second multiplier.

[0161] The first multiplier calculates the product of the 16-bit first input data and the 8-bit high-order input sub-data to obtain a 25-bit first multiplier output, wherein the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0162] The second multiplier calculates the product of the 16-bit first input data and the 8-bit low-order input sub-data to obtain a 25-bit second multiplier output, of which the highest bit is a reserved bit for detecting overflow, and the remaining 24 bits are the product result. When overflow occurs in the multiplication calculation, the reserved bit is 1, otherwise the reserved bit is 0.

[0163] The splicer splices the 25-bit first multiplier output and the 25-bit second multiplier output to obtain a 50-bit second calculation result.

[0164] The selector selects and outputs according to the value of the configuration word. When the value of the configuration word is 0, the second calculation result is output as the output result of the designated sub-computation task.

[0165] According to an embodiment of the present disclosure, the maximum value W1 of the first digit range and the maximum value W2 of the second digit range satisfy the following relationship: W1≤2W2. The number of bits of the high-order input sub-data and the number of bits of the low-order input sub-data are both equal to the maximum value W2 of the second digit range. The number of bits of the first input of the first multiplier and the second multiplier are both equal to the maximum value of the digit range of the first input data, and the number of bits of the second input of the first multiplier and the second multiplier are both equal to W2.

[0166] When the number of bits of the second input data is within the range of the first number of bits but less than 2W2, the number of bits of the second input data is first supplemented to 2W2 by filling the high bits with 0, and then input into the intercept register for subsequent calculation.

[0167] When the number of bits of the second input data is within the second bit range but less than W2, the number of bits of the second input data is first filled with 0s at high bits to make up for W2, and then the two second input data are concatenated and input into the intercept register for subsequent calculation.

[0168] According to the embodiments of the present disclosure, the processing units in the chip can be flexibly configured to a variety of different quantization bit numbers during runtime, for example, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit, and the processing power of each processing unit can be fully utilized according to different computing task requirements, thereby avoiding the situation in the prior art where some processing units are idle due to the fixed quantization bit number of the processing units, thereby significantly improving computing efficiency.

[0169] An embodiment of the present disclosure also provides an electronic device, which includes the above-mentioned runtime reconfigurable artificial intelligence chip, or includes the above-mentioned processing unit.

[0170] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A runtime reconfigurable artificial intelligence chip, characterized in that: The invention comprises a controller and a plurality of processing units, wherein: The controller is used to obtain a computing task, parse the computing task, and obtain a plurality of sub-computing tasks and quantization bits corresponding to the sub-computing tasks, wherein the sub-computing task includes calculating the product of first input data and second input data, and the quantization bits include the quantization bits of the second input data; The processing unit is used to process a specified sub-computation task among the multiple sub-computation tasks, and the number of quantization bits corresponding to the specified sub-computation task is the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit is used to process one specified sub-computation task, and when the specified number of quantization bits is within a second number range, the processing unit is used to process two specified sub-computation tasks, and the processing unit includes: A truncation register, used for dividing the truncation register input into high-order input sub-data and low-order input sub-data, wherein: when the specified quantization bit number is within a first bit number range, the truncation register input includes the second input data of the one specified sub-computing task; when the specified quantization bit number is within a second bit number range, the truncation register input includes the concatenation result of the second input data of the two specified sub-computing tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computing tasks respectively; a first multiplier, the first multiplier being used for multiplying the first input data by the high-order input sub-data to obtain a first multiplier output; a second multiplier, the second multiplier being used for multiplying the first input data by the low-order input sub-data to obtain a second multiplier output; a shifter, the shifter being used for, when the specified number of quantization bits is within the range of the first number of bits, shifting the output of the first multiplier to obtain a shift result; an adder, the adder being used for, when the specified quantization bit number is within the first bit number range, adding the shift result and the output of the second multiplier to obtain a first calculation result; a splicing register, the splicing register being used to, when the specified quantization bit number is within the range of the second bit number, splice the first multiplier output with the second multiplier output to obtain a second calculation result; A multiplexer is used to selectively output the first calculation result and the second calculation result according to the specified number of quantization bits.

2. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The specified sub-computation task includes calculating the product of a first input data and a second input data; When the designated quantization bit number is within a second bit number range, the first input data of the two designated sub-computing tasks are the same.

3. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The minimum value of the first range of digital numbers is greater than the maximum value of the second range of digital numbers.

4. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The first number range is greater than 8 digits and less than or equal to 16 digits, and the second number range is less than or equal to 8 digits; or, the first number range is 16 digits, and the second number range is any one of 8 digits, 4 digits, 2 digits, and 1 digit; The number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

5. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The intercept register divides the intercept register input into high-bit input sub-data and low-bit input sub-data of equal bit size.

6. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The first multiplier output includes a reserved bit set in the most significant bit of the first multiplier output; and / or The second multiplier output includes a reserved bit set at a most significant bit of the second multiplier output.

7. The runtime reconfigurable artificial intelligence chip according to claim 6, characterized in that: The reserved bit is used to determine whether the calculation result of the corresponding multiplier has overflow.

8. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The first digit range is greater than 8 digits and less than or equal to 16 digits, the second digit range is less than or equal to 8 digits, and the digit of the first input data is 16 digits: The first multiplier is a 16-bit*8-bit multiplier, and the second multiplier is a 16-bit*8-bit multiplier; The shifter is used to shift the output of the first multiplier left by 8 bits.

9. The runtime reconfigurable artificial intelligence chip according to claim 8, characterized in that: The output of the first multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the high-order input sub-data; The output of the second multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the low-order input sub-data.

10. The runtime reconfigurable artificial intelligence chip according to claim 9, characterized in that: The splicing register is used to splice the first multiplier output and the second multiplier output to obtain a 50-bit second calculation result.

11. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: When the designated quantization bit number is within a first bit number range, disabling the splicing register; When the designated number of quantization bits is within a second range of bit numbers, the shifter and the adder are disabled.

12. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: When the specified quantization bit number is within a first bit number range, the multiplexer outputs the first calculation result; When the designated quantization bit number is within a second bit number range, the multiplexer outputs the second calculation result.

13. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The processing unit is used to calculate the product of the input of the convolution kernel and the weight parameter of the convolution kernel, wherein the first input data includes the input of the convolution kernel, and the second input data includes the weight parameter of the convolution kernel; and / or The processing unit is used to calculate the product of the input of the neuron and the weight parameter of the neuron, wherein the first input data includes the input of the neuron and the second input data includes the weight parameter of the neuron.

14. The runtime reconfigurable artificial intelligence chip according to claim 13, characterized in that: When the specified number of quantization bits is within the first range of bits, the processing unit is used to calculate the product of an input of a convolution kernel and a weight parameter of the convolution kernel; When the designated number of quantization bits is within the range of the second number of bits, the processing unit is used to calculate the product of the inputs of the two convolution kernels and the weight parameters of the two convolution kernels, and the inputs of the two convolution kernels are equal.

15. The runtime reconfigurable artificial intelligence chip according to claim 1, characterized in that: The controller includes a configuration word pin, the output level of the configuration word pin is determined according to a specified quantization bit number, when the specified quantization bit number is within the first bit number range, the output level of the configuration word pin is a first level, when the specified quantization bit number is within the second bit number range, the output level of the configuration word pin is a second level, and the first level is different from the second level; The output level of the configuration word pin is used to control the multiplexer to selectively output the first calculation result and the second calculation result, and / or to disable any one or more of the shifter, the adder, and the splicing register.

16. A processing unit of a runtime reconfigurable artificial intelligence chip, characterized in that: The processing unit is used to process a specified sub-computation task, the specified sub-computation task includes calculating the product of first input data and second input data, and the number of quantization bits corresponding to the specified sub-computation task is the specified number of quantization bits, wherein when the specified number of quantization bits is within the range of a first number of bits, the processing unit is used to process one specified sub-computation task, and when the specified number of quantization bits is within the range of a second number of bits, the processing unit is used to process two specified sub-computation tasks, and the processing unit includes: A truncation register, used for dividing the truncation register input into high-order input sub-data and low-order input sub-data, wherein: when the specified quantization bit number is within a first bit number range, the truncation register input includes the second input data of the one specified sub-computing task; when the specified quantization bit number is within a second bit number range, the truncation register input includes the concatenation result of the second input data of the two specified sub-computing tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two specified sub-computing tasks respectively; a first multiplier, the first multiplier being used for multiplying the first input data by the high-order input sub-data to obtain a first multiplier output; a second multiplier, the second multiplier being used for multiplying the first input data by the low-order input sub-data to obtain a second multiplier output; a shifter, the shifter being used for, when the specified number of quantization bits is within the range of the first number of bits, shifting the output of the first multiplier to obtain a shift result; an adder, the adder being used for, when the specified quantization bit number is within the first bit number range, adding the shift result and the output of the second multiplier to obtain a first calculation result; a splicing register, the splicing register being used to, when the specified quantization bit number is within the range of the second bit number, splice the first multiplier output with the second multiplier output to obtain a second calculation result; A multiplexer is used to selectively output the first calculation result and the second calculation result according to the specified number of quantization bits.

17. The processing unit according to claim 16, characterized in that: The specified sub-computation task includes calculating the product of a first input data and a second input data; When the designated quantization bit number is within a second bit number range, the first input data of the two designated sub-computing tasks are the same.

18. The processing unit according to claim 16, characterized in that: The minimum value of the first range of digital numbers is greater than the maximum value of the second range of digital numbers.

19. The processing unit according to claim 16, characterized in that: The first number range is greater than 8 digits and less than or equal to 16 digits, and the second number range is less than or equal to 8 digits; or, the first number range is 16 digits, and the second number range is any one of 8 digits, 4 digits, 2 digits, and 1 digit; The number of bits of the first input data is any one of 32 bits, 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit.

20. The processing unit according to claim 16, characterized in that: The intercept register divides the intercept register input into high-bit input sub-data and low-bit input sub-data of equal bit size.

21. The processing unit according to claim 16, characterized in that: The first multiplier output includes a reserved bit set in the most significant bit of the first multiplier output; and / or The second multiplier output includes a reserved bit set at a most significant bit of the second multiplier output.

22. The processing unit according to claim 21, characterized in that: The reserved bit is used to determine whether the calculation result of the corresponding multiplier has overflow.

23. The processing unit according to claim 16, characterized in that: The first digit range is greater than 8 digits and less than or equal to 16 digits, the second digit range is less than or equal to 8 digits, and the digit of the first input data is 16 digits: The first multiplier is a 16-bit*8-bit multiplier, and the second multiplier is a 16-bit*8-bit multiplier; The shifter is used to shift the output of the first multiplier left by 8 bits.

24. The processing unit according to claim 23, characterized in that: The output of the first multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the high-order input sub-data; The output of the second multiplier is 25 bits, of which the highest bit is a reserved bit, and the remaining 24 bits are the product of the first input data and the low-order input sub-data.

25. The processing unit according to claim 24, characterized in that: The splicing register is used to splice the first multiplier output and the second multiplier output to obtain a 50-bit second calculation result.

26. The processing unit according to claim 16, characterized in that: When the designated quantization bit number is within a first bit number range, disabling the splicing register; When the designated number of quantization bits is within a second range of bit numbers, the shifter and the adder are disabled.

27. The processing unit according to claim 16, characterized in that: When the specified quantization bit number is within a first bit number range, the multiplexer outputs the first calculation result; When the designated quantization bit number is within a second bit number range, the multiplexer outputs the second calculation result.

28. The processing unit according to claim 16, characterized in that: The processing unit is used to calculate the product of the input of the convolution kernel and the weight parameter of the convolution kernel, wherein the first input data includes the input of the convolution kernel, and the second input data includes the weight parameter of the convolution kernel; and / or The processing unit is used to calculate the product of the input of the neuron and the weight parameter of the neuron, wherein the first input data includes the input of the neuron and the second input data includes the weight parameter of the neuron.

29. The processing unit according to claim 28, characterized in that: When the specified number of quantization bits is within the first range of bits, the processing unit is used to calculate the product of an input of a convolution kernel and a weight parameter of the convolution kernel; When the designated number of quantization bits is within the range of the second number of bits, the processing unit is used to calculate the product of the inputs of the two convolution kernels and the weight parameters of the two convolution kernels, and the inputs of the two convolution kernels are equal.

30. The processing unit according to claim 1, characterized in that: The processing unit comprises a connection pin, the connection pin is used to connect to a configuration word pin of a controller of the processing unit, the output level of the configuration word pin is determined according to a specified number of quantization bits, when the specified number of quantization bits is within the range of the first number of bits, the output level of the configuration word pin is a first level, when the specified number of quantization bits is within the range of the second number of bits, the output level of the configuration word pin is a second level, and the first level is different from the second level; The level of the connection pin is used to control the multiplexer to selectively output the first calculation result and the second calculation result, and / or to disable any one or more of the shifter, the adder, and the splicing register.

31. A method for executing computing tasks on a runtime reconfigurable artificial intelligence chip, characterized in that: The runtime reconfigurable artificial intelligence chip includes a controller and a plurality of processing units, wherein the processing unit includes an intercept register, a first multiplier, a second multiplier, a shifter, an adder, a splicing register, and a multiplexer. The method includes: Acquire a computing task through the controller, parse the computing task to obtain a plurality of sub-computation tasks and the number of quantization bits corresponding to the sub-computation tasks, and assign the sub-computation tasks to corresponding processing units for processing, wherein the sub-computation tasks include calculating the product of first input data and second input data, and the number of quantization bits includes the number of quantization bits of the second input data; Processing a specified sub-computing task among the multiple sub-computing tasks by the processing unit, the number of quantization bits corresponding to the specified sub-computing task is the specified number of quantization bits, wherein when the specified number of quantization bits is within a first number range, the processing unit processes one specified sub-computing task, and when the specified number of quantization bits is within a second number range, the processing unit processes two specified sub-computing tasks, and the processing of the specified sub-computing task among the multiple sub-computing tasks includes: The intercept register input is segmented by the intercept register to obtain high-order input sub-data and low-order input sub-data, wherein: when the designated quantization bit number is within a first bit number range, the intercept register input includes the second input data of the one designated sub-computing task; when the designated quantization bit number is within a second bit number range, the intercept register input includes the concatenation result of the second input data of the two designated sub-computing tasks, and the high-order input sub-data and the low-order input sub-data correspond to the second input data of the two designated sub-computing tasks respectively; multiplying the first input data by the high-order input sub-data through a first multiplier to obtain a first multiplier output; multiplying the first input data and the low-order input sub-data by a second multiplier to obtain a second multiplier output; When the designated quantization bit number is within the first bit number range, the first multiplier output is shifted by a shifter to obtain a shift result, and the shift result is added to the second multiplier output by an adder to obtain a first calculation result; When the specified quantization bit number is within the range of the second bit number, splicing the first multiplier output and the second multiplier output through a splicing register to obtain a second calculation result; The first calculation result and the second calculation result are selectively outputted through a multiplexer according to the designated number of quantization bits.

32. The method according to claim 31, characterized in that The controller includes a configuration word pin, the output level of the configuration word pin is determined according to a specified quantization bit number, when the specified quantization bit number is within the first bit number range, the output level of the configuration word pin is a first level, when the specified quantization bit number is within the second bit number range, the output level of the configuration word pin is a second level, the first level is different from the second level, and the method further includes: The output level of the configuration word pin controls the multiplexer to selectively output the first calculation result and the second calculation result, and / or disables any one or more of the shifter, the adder, and the splicing register.

33. An electronic device, characterized in that: A runtime reconfigurable artificial intelligence chip comprising any one of claims 1-15, or a processing unit comprising any one of claims 16-30.

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