Display panel and driving method therefor, and display apparatus

Abstract

A display panel, comprising a plurality of pixel units (1) arranged in an array, wherein each pixel unit (1) at least comprises one first light-emitting element (11), two second light-emitting elements (12) and one third light-emitting element (13) that have different colors; in each pixel unit (1), the second light-emitting elements (12) are located in the same odd-numbered row and different even-numbered columns, and the first light-emitting element (11) and the third light-emitting element (13) are located in the same even-numbered row and different odd-numbered columns; the positions of the first light-emitting elements (11) and the third light-emitting elements (13) in any two adjacent even-numbered rows are staggered with each other, and the positions of the first light-emitting elements (11) and the third light-emitting elements (13) in any two adjacent odd-numbered columns are staggered with each other; a plurality of pixel circuits (100) respectively correspond to the first light-emitting elements (11), the second light-emitting elements (12) and the third light-emitting elements (13) in the pixel units (1); and among the first light-emitting elements (11) and the third light-emitting elements (13) in any two adjacent odd-numbered columns, the pixel circuit (100) corresponding to an n-th light-emitting element in one column is electrically connected to an (n+1)-th light-emitting element, and the pixel circuit (100) corresponding to the (n+1)-th light-emitting element is electrically connected to the n-th light-emitting element, n being an odd number.

Description

Display panel, driving method thereof, and display device Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display panel, a driving method thereof, and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode), a new display product, boasts rich colors, fast response times, and foldability. It is gradually replacing LCD (Liquid Crystal Display) as the mainstream small and medium-sized display product. With the further development of OLED, the market is demanding higher standards for OLED in terms of lifespan, power consumption, and high-brightness mode.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display panel, wherein:

[0005] comprising a plurality of pixel units arranged in an array;

[0006] The pixel unit includes at least one first light-emitting element, two second light-emitting elements and one third light-emitting element, and the first light-emitting element, the second light-emitting element and the third light-emitting element emit light of different colors;

[0007] In the pixel unit, the second light-emitting element is located in the same odd row and different even columns, and the first light-emitting element and the third light-emitting element are located in the same even row and different odd columns.

[0008] In the array of pixel units, the positions of the first light-emitting elements and the third light-emitting elements in any two adjacent even-numbered rows are staggered, and the positions of the first light-emitting elements and the third light-emitting elements in any two adjacent odd-numbered columns are staggered.

[0009] The first light emitting element and the third light emitting element located in the same column are electrically connected to the same data line; the second light emitting element located in the same column are electrically connected to the same data line;

[0010] The pixel unit further includes a plurality of pixel circuits, and the plurality of pixel circuits correspond to the first light-emitting element, the second light-emitting element, and the third light-emitting element in the pixel unit, respectively.

[0011] Among any two adjacent odd-numbered columns of the first light-emitting elements and the third light-emitting elements, the pixel circuit corresponding to the nth light-emitting element in one column is electrically connected to the n+1th light-emitting element, and the pixel circuit corresponding to the n+1th light-emitting element is electrically connected to the nth light-emitting element, where n is an odd number; the nth light-emitting element is the first light-emitting element or the third light-emitting element, and the n+1th light-emitting element is the third light-emitting element or the first light-emitting element.

[0012] In some embodiments, the plurality of pixel circuits correspond one-to-one to the first light-emitting element, the two second light-emitting elements, and the third light-emitting element in the pixel unit.

[0013] Among the second light-emitting elements in any two adjacent even-numbered columns, the pixel circuit corresponding to the nth second light-emitting element in one column is electrically connected to the n+1th second light-emitting element, and the pixel circuit corresponding to the n+1th second light-emitting element is electrically connected to the nth second light-emitting element, where n is an odd number.

[0014] In some embodiments, the array of pixel units in the display area includes X rows, X ≥ 8,

[0015] The display area is divided into A sub-areas, and the A sub-areas are arranged in sequence along the column direction of the array, and each sub-area includes at least four rows of pixel units.

[0016] A is any integer in the range of 1 to X / 4.

[0017] In some embodiments, the invention further comprises at least one light emitting control driving circuit located in at least one side frame area, and different light emitting control driving circuits are electrically connected to the pixel circuits in different sub-areas.

[0018] The light emitting control driving circuit includes a plurality of first shift registers, wherein the odd-numbered first shift registers are sequentially cascaded, and the even-numbered first shift registers are sequentially cascaded, and the output end of the last odd-numbered first shift register is electrically connected to the input end of the first even-numbered first shift register.

[0019] The output terminals of the odd-numbered first shift registers are electrically connected to the pixel circuits in the pixel units located in odd-numbered rows.

[0020] Output terminals of the even-numbered first shift registers are electrically connected to the pixel circuits in the pixel units located in even-numbered rows;

[0021] The output end of the last first shift register of the upper light emitting control driving circuit among two adjacent light emitting control driving circuits is electrically connected to the input end of the first first shift register of the lower light emitting control driving circuit.

[0022] In some embodiments, in the light emitting control driving circuit, the output end of the Nth first shift register is electrically connected to the pixel circuits in the pixel units in the 2N-1th and 2N+1th rows in the corresponding sub-area, where N is an odd number;

[0023] The output end of the Mth first shift register is electrically connected to the pixel circuits in the pixel units in the 2M-2th and 2Mth rows in the corresponding sub-area, where M is an even number.

[0024] In some embodiments, an input terminal of a first of the first shift registers of the first light emitting control driving circuit is electrically connected to a light emitting control trigger signal output terminal.

[0025] In some embodiments, at least one gate driving circuit is further included, located in at least one side frame area, and different gate driving circuits are electrically connected to the pixel circuits in different sub-areas.

[0026] The gate drive circuit includes a plurality of second shift registers, wherein the odd-numbered second shift registers are sequentially cascaded, and the even-numbered second shift registers are sequentially cascaded, and the output end of the last odd-numbered second shift register is electrically connected to the input end of the first even-numbered second shift register.

[0027] The output terminals of the odd-numbered second shift registers are electrically connected to the pixel circuits in the pixel units located in odd-numbered rows.

[0028] Output terminals of the even-numbered second shift registers are electrically connected to the pixel circuits in the pixel units located in even-numbered rows;

[0029] The output end of the last second shift register of the upper gate driving circuit among two adjacent gate driving circuits is electrically connected to the input end of the first second shift register of the lower gate driving circuit.

[0030] In some embodiments, in the gate driving circuit, the output end of the Nth second shift register is electrically connected to the pixel circuits in the pixel units in the 2N-1th and 2N+1th rows in the corresponding sub-area, where N is an odd number;

[0031] The output end of the Mth second shift register is electrically connected to the pixel circuits in the pixel units in the 2M-2th and 2Mth rows in the corresponding sub-area, where M is an even number.

[0032] In some embodiments, an input terminal of a first of the second shift registers of the first of the gate driving circuits is electrically connected to a gate driving trigger signal output terminal.

[0033] In some embodiments, the gate driving circuit includes a first gate driving circuit, a second gate driving circuit, and a third gate driving circuit;

[0034] An input terminal of a first second shift register of a first first gate driving circuit is electrically connected to a first gate driving trigger signal output terminal;

[0035] An input terminal of a first second shift register of a first second gate driving circuit is electrically connected to a second gate driving trigger signal output terminal;

[0036] An input terminal of a first second shift register of a first third gate driving circuit is electrically connected to a third gate driving trigger signal output terminal.

[0037] In some embodiments, at least one pair of fourth gate driving circuits is further included, located in the border areas on opposite sides, and different fourth gate driving circuits located in the border area on the same side are electrically connected to the pixel circuits in different sub-areas.

[0038] The fourth gate driving circuit includes a plurality of third shift registers, wherein odd-numbered third shift registers among the plurality of third shift registers are sequentially cascaded, and even-numbered third shift registers are sequentially cascaded, and the output end of the last odd-numbered third shift register is electrically connected to the input end of the first even-numbered third shift register.

[0039] The output terminals of the odd-numbered third shift registers are electrically connected to the pixel circuits in the pixel units located in odd-numbered rows.

[0040] Output ends of the even-numbered third shift registers are electrically connected to the pixel circuits in the pixel units located in even-numbered rows;

[0041] The output end of the last third shift register of the upper fourth gate driving circuit in the two adjacent fourth gate driving circuits located in the border area on the same side is electrically connected to the input end of the first third shift register of the lower fourth gate driving circuit.

[0042] In some embodiments, in the fourth gate driving circuit, the output end of the Nth third shift register is electrically connected to the pixel circuit in the Nth row of pixel units in the corresponding sub-area, where N is an odd number;

[0043] An output end of the Mth third shift register is electrically connected to the pixel circuit in the Mth row of pixel units in the corresponding sub-area, where M is an even number.

[0044] In some embodiments, the input end of the first third shift register of the first fourth gate driving circuit located in the border area on the same side is electrically connected to the fourth gate driving trigger signal output end.

[0045] In some embodiments, the first light-emitting element, the second light-emitting element, and the third light-emitting element each include an anode, a light-emitting functional layer, and a cathode stacked in sequence.

[0046] The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a driving transistor, a first capacitor and a second capacitor.

[0047] The first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the sixth transistor, and the first electrode of the driving transistor are connected to a third node.

[0048] The second electrode of the first transistor, the first electrode of the fifth transistor, the first plate of the first capacitor, and the first plate of the second capacitor are connected to a first node.

[0049] The second plate of the second capacitor, the gate of the driving transistor and the first electrode of the fourth transistor are connected to a second node.

[0050] The first electrode of the seventh transistor, the first electrode of the third transistor, and the anode are connected to a fourth node.

[0051] The second electrode of the second transistor and the second plate of the first capacitor are connected to a first power supply,

[0052] The second electrode of the fifth transistor is connected to the data line,

[0053] The second electrode of the sixth transistor is connected to the third reset power supply,

[0054] The second electrode of the fourth transistor is connected to the second reset power supply,

[0055] The second electrode of the driving transistor is connected to the second electrode of the seventh transistor,

[0056] The second electrode of the third transistor is connected to the first reset power supply,

[0057] The cathode is connected to a second power supply;

[0058] The gate of the first transistor and the gate of the fourth transistor are connected to the first gate driving circuit,

[0059] The gate of the third transistor is connected to the second gate driving circuit,

[0060] The gate of the sixth transistor and the gate of the seventh transistor are connected to the third gate driving circuit,

[0061] The gate of the second transistor is connected to the light emitting control driving circuit,

[0062] The gate of the fifth transistor is connected to the fourth gate driving circuit.

[0063] In some embodiments, the first light-emitting element includes a first anode, the third light-emitting element includes a third anode, and the first anode and the third anode are provided in the same layer.

[0064] The fourth node of the pixel circuit corresponding to the nth first light-emitting element is connected to the third anode of the n+1th third light-emitting element through a first lead.

[0065] The fourth node of the pixel circuit corresponding to the (n+1)th third light-emitting element is connected to the first anode of the (n)th first light-emitting element through a second lead.

[0066] In some embodiments, the pixel circuit includes a plurality of conductive layers,

[0067] The first lead and the second lead are arranged in the same layer and are located in any one of the conductive layers.

[0068] In some embodiments, the second light-emitting element includes a second anode, and the second anode is disposed in the same layer as the first anode and the third anode.

[0069] The fourth node of the pixel circuit corresponding to the nth second light-emitting element is connected to the second anode of the (n+1)th second light-emitting element through a third lead.

[0070] The fourth node of the pixel circuit corresponding to the (n+1)th second light emitting element is connected to the second anode of the (n)th second light emitting element through a fourth lead.

[0071] In some embodiments, the third lead and the fourth lead are provided on the same layer as the first lead and the second lead.

[0072] The first lead, the second lead, the third lead, and the fourth lead respectively extend along the column direction of the array and are sequentially arranged along the row direction of the array.

[0073] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel.

[0074] In a third aspect, an embodiment of the present disclosure further provides a method for driving the display panel, comprising: dividing a display area into A sub-areas, where A is any integer in the range of 1 to X / 4, X is the total number of rows of the array of pixel units in the display area, and X ≥ 8;

[0075] The driving method includes sequentially driving the pixel units in each of the sub-areas to perform display.

[0076] When driving the pixel units in each sub-area to display, the first 1 / 2A frame scans the odd-numbered rows of pixel units, the odd-numbered data lines input data signals driving the first light-emitting elements to emit light, and the even-numbered data lines input data signals driving the second light-emitting elements to emit light;

[0077] The next 1 / 2A frame scans even-numbered rows of pixel units, the odd-numbered data lines input data signals driving the third light-emitting element to emit light, and the even-numbered data lines input data signals driving the second light-emitting element to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0079] FIG1 is a top view schematically showing the arrangement of pixel units in a display area of ​​a display panel according to an embodiment of the present disclosure.

[0080] FIG2 a is a schematic top view of a display area of ​​another display panel provided by an embodiment of the present disclosure.

[0081] FIG2 b is a schematic top view of another display panel provided by an embodiment of the present disclosure.

[0082] FIG2 c is a corresponding layout diagram of pixel circuits and light-emitting elements in another display panel provided by an embodiment of the present disclosure.

[0083] FIG3 is a schematic top view of another display panel provided by an embodiment of the present disclosure.

[0084] FIG4 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0085] FIG. 5 a is a partial structural diagram of a conductive layer in a display panel according to an embodiment of the present disclosure.

[0086] FIG5 b is a partial structural layout of a conductive layer and an anode in a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display panel, a driving method thereof, and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation plans.

[0088] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0089] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0090] An embodiment of the present disclosure provides a display panel. Referring to FIG1 , which is a top view schematic diagram of the arrangement of pixel units in a display area of ​​a display panel according to an embodiment of the present disclosure, the display panel includes a plurality of pixel units 1 located in a display area 101 and arranged in an array; a plurality of data lines 2; and the pixel unit 1 includes a first light-emitting element 11, two second light-emitting elements 12, and a third light-emitting element 13 of different colors.

[0091] The multiple pixel units 1 include multiple first pixel units 1a and multiple second pixel units 1b. The multiple first pixel units 1a are located in odd rows and arranged along the row direction L of the array. The multiple second pixel units 1b are located in even rows and arranged along the row direction L of the array. In the first pixel unit 1a, the first light-emitting element 11, one second light-emitting element 12, the third light-emitting element 13 and another second light-emitting element 12 are arranged in sequence along the row direction L. In the second pixel unit 1b, the third light-emitting element 13, one second light-emitting element 12, the first light-emitting element 11 and another second light-emitting element 12 are arranged in sequence along the row direction L.

[0092] The first light-emitting elements 11 and the third light-emitting elements 13 are alternately arranged in sequence along the column direction H of the array, and the first light-emitting elements 11 and the third light-emitting elements 13 in the same column are electrically connected to the same data line 2; the second light-emitting elements 12 are arranged in sequence along the column direction H of the array, and the second light-emitting elements 12 in the same column are electrically connected to the same data line 2.

[0093] The first pixel unit 1a also includes multiple first pixel circuits, which correspond one-to-one to and are electrically connected to the first light-emitting element 11, the second light-emitting element 12, and the third light-emitting element 13 in the first pixel unit 1a; the second pixel unit 1b also includes multiple second pixel circuits, which correspond one-to-one to and are electrically connected to the first light-emitting element 11, the second light-emitting element 12, and the third light-emitting element 13 in the second pixel unit 1b.

[0094] In some embodiments, the first light-emitting element 11 is a blue light-emitting element B, the second light-emitting element 12 is a green light-emitting element G, and the third light-emitting element 13 is a red light-emitting element R. The blue light-emitting elements B and red light-emitting elements R in the same column are electrically connected to the same data line Data_BR / Data_RB, and the green light-emitting elements G in the same column are electrically connected to the same data line Data_G. The first pixel circuit P_B, the first pixel circuit P_G, and the first pixel circuit P_R correspond to and are electrically connected to the blue light-emitting element B, the green light-emitting element G, and the red light-emitting element R in the first pixel unit 1a, respectively. The second pixel circuit P_B', the second pixel circuit P_G', and the second pixel circuit P_R' correspond to and are electrically connected to the first light-emitting element 11, the second light-emitting element 12, and the third light-emitting element 13 in the second pixel unit 1b, respectively.

[0095] Referring to the pixel unit arrangement in Figure 1, the data lines Data_BR / Data_RB connected to the odd-numbered columns of light-emitting elements write data signals to the blue light-emitting elements B and the red light-emitting elements R, and the data lines Data_G connected to the even-numbered columns of light-emitting elements write data signals to the green light-emitting elements G. Since the odd-numbered columns are formed by alternating blue light-emitting elements B and red light-emitting elements R, the data signals of the light-emitting elements in the odd-numbered columns will jump when writing row by row, that is, the data signals of the light-emitting elements in the odd-numbered columns will repeatedly jump the data signals of the blue light-emitting elements B and the red light-emitting elements R as the gate drive circuit scans row by row. Since the data signal ranges of the blue light-emitting elements B and the red light-emitting elements R are different, the data driver chip needs to continuously charge and discharge the light-emitting elements in the odd-numbered columns, resulting in increased power consumption of the display panel.

[0096] In order to solve the problem of increased power consumption of the display panel in the above-mentioned embodiments, on the first aspect, the embodiments of the present disclosure further provide a display panel, referring to Figures 2a and 2b, Figure 2a is a schematic top view of a display area of ​​another display panel provided by the embodiment of the present disclosure; Figure 2b is a schematic top view of another display panel provided by the embodiment of the present disclosure; wherein, the display panel includes a plurality of pixel units 1 arranged in an array; a plurality of data lines 2; the pixel unit 1 includes at least one first light-emitting element 11, two second light-emitting elements 12 and one third light-emitting element 13, the first light-emitting element 11, the second light-emitting element 12 and the third light-emitting element 13 have different luminous colors, the second light-emitting element 12 in the pixel unit 1 is located in the same odd row and different even columns, the first light-emitting element 11 and the third light-emitting element 13 are located in the same even row and different odd columns, and in the array of the pixel unit 1, the first light-emitting element 11 and the third light-emitting element 13 in any two adjacent even rows are located at the same position. The first light-emitting elements 11 and the third light-emitting elements 13 of any two adjacent odd-numbered columns are staggered with each other, and the first light-emitting elements 11 and the third light-emitting elements 13 in the same column are electrically connected to the same data line 2; the second light-emitting elements 12 in the same column are electrically connected to the same data line 2; the pixel unit 1 further includes a plurality of pixel circuits 100, and the plurality of pixel circuits 100 correspond to the first light-emitting elements 11, the second light-emitting elements 12, and the third light-emitting elements 13 in the pixel unit 1, respectively. Among the first light-emitting elements 11 and the third light-emitting elements 13 of any two adjacent odd-numbered columns, the pixel circuit 100 corresponding to the nth light-emitting element in one column is electrically connected to the n+1th light-emitting element, and the pixel circuit 100 corresponding to the n+1th light-emitting element is electrically connected to the nth light-emitting element, where n is an odd number; the nth light-emitting element is the first light-emitting element 11 or the third light-emitting element 13, and the n+1th light-emitting element is the third light-emitting element 13 or the first light-emitting element 11.

[0097] The row direction of the array is L, and the column direction is H. Referring to FIG2c , there is shown a corresponding layout of pixel circuits and light-emitting elements in another display panel provided by an embodiment of the present disclosure; wherein, a plurality of pixel circuits 100 correspond to the first light-emitting element 11, the second light-emitting element 12, and the third light-emitting element 13 in the pixel unit 1, respectively. This refers to the correspondence between the pixel circuits 100 and the light-emitting elements of different colors in the pixel unit 1 in terms of their placement positions. The correspondence in placement positions actually means that the orthographic projections of the pixel circuits 100 and the light-emitting elements corresponding thereto in their placement positions on the substrate at least partially overlap, i.e., the orthographic projections of one pixel circuit 100 on the substrate at least partially overlap with a light-emitting element or a light-emitting element of one color in the pixel unit 1.

[0098] By making the pixel circuit 100 corresponding to the nth light-emitting element in one column of any two adjacent odd-numbered columns of the first light-emitting elements 11 and the third light-emitting elements 13 electrically connected to the n+1th light-emitting element, and the pixel circuit 100 corresponding to the n+1th light-emitting element electrically connected to the nth light-emitting element, the display panel drives the first light-emitting element 11 or the third light-emitting element 13 to emit light when the odd-numbered row pixel units 1 are driven, and drives the third light-emitting element 13 or the first light-emitting element 11 to emit light when the even-numbered row pixel units 1 are driven. Therefore, when the display panel first drives at least part of the odd rows and then drives at least part of the even rows, the data signal on the data line 2 that drives the odd-numbered column light-emitting elements formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 only needs to jump once, that is, avoiding repeated jumping of the data signal on the data line 2 when the display panel drives the pixel units 1 row by row, thereby reducing the power consumption of the display panel.

[0099] In some embodiments, referring to Figure 2a, multiple pixel circuits 100 correspond one-to-one to the first light-emitting element 11, two second light-emitting elements 12 and the third light-emitting element 13 in the pixel unit 1. Among the second light-emitting elements 12 in any two adjacent even-numbered columns, the pixel circuit 100 corresponding to the nth second light-emitting element 12 in one column is electrically connected to the n+1th second light-emitting element 12, and the pixel circuit 100 corresponding to the n+1th second light-emitting element 12 is electrically connected to the nth second light-emitting element 12, where n is an odd number.

[0100] In particular, one pixel circuit 100 is provided corresponding to one light-emitting element in the pixel unit 1, and one pixel circuit 100 is electrically connected to one light-emitting element in the pixel unit 1. The first light-emitting element 11 and one adjacent second light-emitting element 12 in the pixel unit 1 are calculated as a sub-pixel unit during display, and an image is displayed according to the display brightness. The third light-emitting element 13 and another adjacent second light-emitting element 12 in the pixel unit 1 are calculated as a sub-pixel unit during display, and an image is displayed according to the display brightness. By electrically connecting the pixel circuit 100 corresponding to the nth second light-emitting element 12 in one column of any two adjacent even-numbered columns to the n+1th second light-emitting element 12, and electrically connecting the pixel circuit 100 corresponding to the n+1th second light-emitting element 12 to the nth second light-emitting element 12, the display effect of the above-mentioned sub-pixel units in the pixel unit 1 is improved, thereby improving the display effect of the display panel.

[0101] In some embodiments, referring to FIG. 2 a , the first light-emitting element 11 is a blue light-emitting element B, the second light-emitting element 12 is a green light-emitting element G, and the third light-emitting element 13 is a red light-emitting element R. The blue light-emitting elements B and the red light-emitting elements R in the same column are electrically connected to the same data line Data_BR / Data_RB, and the green light-emitting elements G in the same column are electrically connected to the same data line Data_G. In two adjacent odd-numbered columns formed by the blue light-emitting elements B and the red light-emitting elements R, the pixel circuit P_B corresponding to the nth blue light-emitting element B in one column is electrically connected to the nth blue light-emitting element B, and the pixel circuit P_B corresponding to the nth red light-emitting element R in the other column is electrically connected to the n+1th blue light-emitting element B. In two adjacent even-numbered columns formed by the green light-emitting elements G and the green light-emitting elements G, the pixel circuit P_G corresponding to the nth green light-emitting element G in one column is electrically connected to the nth green light-emitting element G, and the pixel circuit P_G corresponding to the nth green light-emitting element G in the other column is electrically connected to the n+1th green light-emitting element G.

[0102] In some embodiments, referring to FIG3 , which is a top view schematic diagram of another display panel provided in an embodiment of the present disclosure, the array of pixel units 1 in the display area 101 includes X rows, where X ≥ 8, and the display area 101 is divided into A sub-areas 101 a , which are arranged in sequence along the column direction H of the array, and each sub-area 101 a includes at least four rows of pixel units 1, where A is any integer in the range of 1 to X / 4.

[0103] Among them, when A=1, referring to Figure 2b, the display area 101 is divided into a sub-area, that is, the display area 101 is taken as a whole. According to the arrangement and setting of the pixel units 1 in the display area 101 of the display panel in Figure 2b, when the odd-numbered row pixel units 1 are driven, the display panel drives the first light-emitting element 11 or the third light-emitting element 13 to emit light, and when the even-numbered row pixel units 1 are driven, the third light-emitting element 13 or the first light-emitting element 11 to emit light, so that when the display panel first drives each odd row and then drives each even row, the data signal on the data line 2 that drives the odd-numbered column light-emitting elements formed by the alternating arrangement of the first light-emitting element 11 and the third light-emitting element 13 only needs to jump once. For example, during the driving process of each odd row, the data signal on the data line 2 that drives the odd-numbered column light-emitting elements formed by the alternating arrangement of the first light-emitting element 11 and the third light-emitting element 13 drives the first light-emitting element 11 Regarding the data signal for luminescence, during the driving process of each even-numbered row, the data signal on the data line 2 that drives the light-emitting elements in the odd-numbered columns formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 is the data signal that drives the third light-emitting element 13 to emit light; that is, during the display process of one frame of the entire display area 101, the data signal on the data line 2 that drives the light-emitting elements in the odd-numbered columns formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 only needs to jump once, thereby greatly reducing the power consumption of the display panel.

[0104] When A=2 or an integer greater than 2, referring to FIG3 , the display area 101 is divided into two or more sub-areas. According to the arrangement and setting of the pixel units 1 in the display area 101 of the display panel in FIG2 , when the display panel displays in each sub-area, the first light-emitting element 11 or the third light-emitting element 13 is driven to emit light when the pixel units 1 in the odd rows are driven, and the third light-emitting element 13 or the first light-emitting element 11 is driven to emit light when the pixel units 1 in the even rows are driven. Therefore, when the display panel first drives the odd rows in the sub-area and then drives the even rows, the data signal on the data line 2 that drives the odd-numbered column light-emitting elements formed by the alternating arrangement of the first light-emitting element 11 and the third light-emitting element 13 only needs to jump once, as shown in FIG3 . During the driving process of each odd-numbered row in the sub-area, the data signal on the data line 2 driving the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 is all a data signal for driving the first light-emitting elements 11 to emit light. During the driving process of each even-numbered row in the sub-area, the data signal on the data line 2 driving the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 is all a data signal for driving the third light-emitting elements 13 to emit light. That is, during the display process of the image in each sub-area, the data signal on the data line 2 driving the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 only needs to jump once, thereby reducing the power consumption of the display panel.

[0105] In some embodiments, referring to Figures 2b and 3, the display panel further includes at least one light-emitting control driving circuit 3, which is located in at least one side frame area 102. Different light-emitting control driving circuits 3 are electrically connected to pixel circuits in different sub-areas 101a. The light-emitting control driving circuit 3 includes multiple first shift registers EM, and the odd-numbered first shift registers EM in the multiple first shift registers EM are cascaded in sequence, and the even-numbered first shift registers EM are cascaded in sequence. The output end of the last odd-numbered first shift register EM is electrically connected to the input end of the first even-numbered first shift register EM, the output ends of the odd-numbered first shift registers EM are electrically connected to the pixel circuits in the pixel units 1 located in odd rows, and the output ends of the even-numbered first shift registers EM are electrically connected to the pixel circuits in the pixel units 1 located in even rows; the output end of the last first shift register EM of the upper light-emitting control driving circuit 3 of two adjacent light-emitting control driving circuits 3 is electrically connected to the input end of the first first shift register EM of the next light-emitting control driving circuit 3.

[0106] In some embodiments, in the light-emitting control driving circuit 3, the output end of the Nth first shift register EMN is electrically connected to the pixel circuits in the 2N-1th and 2N+1th row pixel units 1 in the corresponding sub-area 101a, where N is an odd number; the output end of the Mth first shift register EMM is electrically connected to the pixel circuits in the 2M-2th and 2Mth row pixel units 1 in the corresponding sub-area 101a, where M is an even number.

[0107] In some embodiments, an input terminal of the first first shift register EM1 of the first light emitting control driving circuit 3 is electrically connected to the light emitting control trigger signal output terminal EM_STV.

[0108] In some embodiments, referring to Figures 2b and 3, the display panel also includes at least one gate driving circuit 4, which is located in at least one side frame area 102, and different gate driving circuits 4 are electrically connected to pixel circuits in different sub-areas 101a. The gate driving circuit 4 includes multiple second shift registers, and the odd-numbered second shift registers in the multiple second shift registers are cascaded in sequence, and the even-numbered second shift registers are cascaded in sequence. The output end of the last odd-numbered second shift register is electrically connected to the input end of the first even-numbered second shift register, and the output end of the odd-numbered second shift register is electrically connected to the pixel circuit in the pixel unit 1 located in the odd row, and the output end of the even-numbered second shift register is electrically connected to the pixel circuit in the pixel unit 1 located in the even row; the output end of the last second shift register of the upper gate driving circuit 4 in two adjacent gate driving circuits 4 is electrically connected to the input end of the first second shift register of the next gate driving circuit 4.

[0109] In some embodiments, in the gate drive circuit 4, the output end of the Nth second shift register S_N is electrically connected to the pixel circuits in the 2N-1th and 2N+1th rows of pixel units 1 in the corresponding sub-area 101a, where N is an odd number; the output end of the Mth second shift register S_M is electrically connected to the pixel circuits in the 2M-2th and 2Mth rows of pixel units 1 in the corresponding sub-area 101a, where M is an even number.

[0110] In some embodiments, the input terminal of the first second shift register of the first gate driving circuit 4 is electrically connected to the gate driving trigger signal output terminal.

[0111] In some embodiments, the gate drive circuit 4 includes a first gate drive circuit S1, a second gate drive circuit S2 and a third gate drive circuit S3; the input end of the first second shift register S1_1 of the first first gate drive circuit S1 is electrically connected to the first gate drive trigger signal output end S1_STV; the input end of the first second shift register S2_1 of the first second gate drive circuit S2 is electrically connected to the second gate drive trigger signal output end S2_STV; the input end of the first second shift register S3_1 of the first third gate drive circuit S3 is electrically connected to the third gate drive trigger signal output end S3_STV.

[0112] In some embodiments, referring to Figures 2b and 3, the display panel also includes at least one pair of fourth gate driving circuits 5, which are located in the two opposite side frame areas 102, and different fourth gate driving circuits 5 located in the same side frame area 102 are electrically connected to the pixel circuits in different sub-areas 101a, and the fourth gate driving circuit 5 includes multiple third shift registers GN, the odd-numbered third shift registers GN in the multiple third shift registers GN are cascaded in sequence, and the even-numbered third shift registers GN are cascaded in sequence, and the output end of the last odd-numbered third shift register GN is electrically connected to the input end of the first even-numbered third shift register GN, the output end of the odd-numbered third shift register GN is electrically connected to the pixel circuit in the pixel unit 1 located in the odd row, and the output end of the even-numbered third shift register GN is electrically connected to the pixel circuit in the pixel unit 1 located in the even row; the output end of the last third shift register GN of the upper fourth gate driving circuit 5 in the two adjacent fourth gate driving circuits 5 located in the same side frame area 102 is electrically connected to the input end of the first third shift register GN of the next fourth gate driving circuit 5.

[0113] In some embodiments, in the fourth gate driving circuit 5, the output end of the Nth third shift register GNN is electrically connected to the pixel circuit in the Nth row of pixel units 1 in the corresponding sub-area 101a, where N is an odd number; the output end of the Mth third shift register GNM is electrically connected to the pixel circuit in the Mth row of pixel units 1 in the corresponding sub-area 101a, where M is an even number.

[0114] In some embodiments, the input terminal of the first third shift register GN1 of the first fourth gate driving circuit 5 located in the same side frame area 102 is electrically connected to the fourth gate driving trigger signal output terminal GN_STV.

[0115] In some embodiments, referring to FIG4 , which is a circuit diagram of a pixel circuit in an embodiment of the present disclosure, wherein the first light-emitting element 11, the second light-emitting element 12, and the third light-emitting element 13 each include an anode, a light-emitting functional layer, and a cathode stacked in sequence, and the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a driving transistor DTFT, a first capacitor C1, and a second capacitor C2. The first electrode of the first transistor T1, the first electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the first electrode of the driving transistor DTFT are connected to the third node N3. The second electrode of the first transistor T1, the first electrode of the fifth transistor T5, the first plate of the first capacitor C1, and the first plate of the second capacitor C2 are connected to the first node N1. The second plate of the second capacitor C2, the gate of the driving transistor DTFT, and the first electrode of the fourth transistor T4 are connected to the second node N2. The first electrode of the seventh transistor T7, The first electrode and anode of the third transistor T3 are connected to the fourth node N4, the second electrode of the second transistor T2 and the second electrode plate of the first capacitor C1 are connected to the first power supply VDD, the second electrode of the fifth transistor T5 is connected to the data line Vdata, the second electrode of the sixth transistor T6 is connected to the third reset power supply Vinit3, the second electrode of the fourth transistor T4 is connected to the second reset power supply Vinit2, the second electrode of the driving transistor DTFT is connected to the second electrode of the seventh transistor T7, the second electrode of the third transistor T3 is connected to the first reset power supply Vinit1, and the cathode is connected to the second power supply VSS; the gate of the first transistor T1 and the gate of the fourth transistor T4 are connected to the first gate driving circuit S1, the gate of the third transistor T3 is connected to the second gate driving circuit S2, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are connected to the third gate driving circuit S3, the gate of the second transistor T2 is connected to the light emitting control driving circuit EM(3), and the gate of the fifth transistor T5 is connected to the fourth gate driving circuit G(n)(5).

[0116] In some embodiments, in addition to the 8T2C (i.e., eight transistors and two capacitors) structure shown in Figure 4, the pixel circuit can also be a circuit structure including other numbers of transistors and capacitors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, etc., which is not limited to the embodiments of the present disclosure.

[0117] Among them, the above circuit structures of the pixel circuit are relatively mature traditional circuits, and their specific working processes are not described here in detail.

[0118] In some embodiments, referring to FIG4 , under the drive of the first gate drive circuit S1, the second gate drive circuit S2, the third gate drive circuit S3, the light emitting control drive circuit EM(3) and the fourth gate drive circuit G(n)(5), the pixel circuits in each sub-area 101a are driven in sequence; when driving the pixel circuits in any sub-area 101a, the pixel circuits in the odd-numbered rows in the sub-area 101a are driven in sequence first, and then the pixel circuits in the even-numbered rows in the sub-area 101a are driven in sequence; the pixel circuits in the odd-numbered rows in any sub-area 101a are driven in sequence. The circuit can drive two or more rows at the same time, or drive row by row; the pixel circuits of the even-numbered rows in any sub-area 101a can drive two or more rows at the same time, or drive row by row; thus, during the display process of the image in each sub-area 101a, the data signal on the data line 2 that drives the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 only needs to jump once, thereby reducing the number of jumps of the data signal on the data line 2, thereby reducing the power consumption of each sub-area 101a during display, and ultimately reducing the power consumption of the entire display panel during display.

[0119] In some embodiments, referring to Figure 5a, which is a local structural layout of a conductive layer in a display panel of an embodiment of the present disclosure, Figure 5b is a local structural layout of a conductive layer and an anode in a display panel of an embodiment of the present disclosure, wherein the first light-emitting element 11 includes a first anode 110, and the third light-emitting element 13 includes a third anode 130. The first anode 110 and the third anode 130 are arranged in the same layer, and the fourth node N4 of the pixel circuit corresponding to the nth first light-emitting element 11 is connected to the third anode 130 of the n+1th third light-emitting element 13 through the first lead 6, and the fourth node N4 of the pixel circuit corresponding to the n+1th third light-emitting element 13 is connected to the first anode 110 of the nth first light-emitting element 11 through the second lead 7.

[0120] In some embodiments, referring to Figures 2a, 2b and 3, the downward arrow between the first light-emitting element 11 and the third light-emitting element 13 in an odd column schematically indicates that the pixel circuit 100 corresponding to the third light-emitting element 13 in the upper row is electrically connected to the first light-emitting element 11 in the next row through the first lead 6; the upward arrow between the first light-emitting element 11 and the third light-emitting element 13 in an odd column schematically indicates that the pixel circuit 100 corresponding to the first light-emitting element 11 in the next row is electrically connected to the third light-emitting element 13 in the upper row through the second lead 7.

[0121] In some embodiments, the pixel circuits each include multiple conductive layers, and the first lead 6 and the second lead 7 are provided in the same layer and located in any one of the conductive layers. Specifically, the connection between the fourth node N4 of the pixel circuit corresponding to the nth first light-emitting element 11 and the third anode 130 of the n+1th third light-emitting element 13 can be achieved through the first lead 6 and a via hole provided in the insulating layer between the anode layer and the conductive layer where the first lead 6 is provided, and the connection between the fourth node N4 of the pixel circuit corresponding to the n+1th third light-emitting element 13 and the first anode 110 of the nth first light-emitting element 11 can be achieved through the second lead 7 and a via hole provided in the insulating layer between the anode layer and the conductive layer where the second lead 7 is provided.

[0122] In some embodiments, referring to Figures 5a and 5b, the second light-emitting element 12 includes a second anode 120, and the second anode 120 is arranged in the same layer as the first anode 110 and the third anode 130. The fourth node N4 of the pixel circuit corresponding to the nth second light-emitting element 12 is connected to the second anode 120 of the n+1th second light-emitting element 12 through the third lead 8, and the fourth node N4 of the pixel circuit corresponding to the n+1th second light-emitting element 12 is connected to the second anode 120 of the nth second light-emitting element 12 through the fourth lead 9.

[0123] In some embodiments, referring to Figures 2a, 2b and 3, the downward arrow between the second light-emitting element 12 and the second light-emitting element 12 in an even column schematically indicates that the pixel circuit 100 corresponding to the second light-emitting element 12 in the upper row is electrically connected to the second light-emitting element 12 in the next row through the third lead 8; the upward arrow between the second light-emitting element 12 and the second light-emitting element 12 in an even column schematically indicates that the pixel circuit 100 corresponding to the second light-emitting element 12 in the next row is electrically connected to the second light-emitting element 12 in the upper row through the fourth lead 9.

[0124] In some embodiments, the third lead 8 and the fourth lead 9 are arranged in the same layer as the first lead 6 and the second lead 7, and the first lead 6, the second lead 7, the third lead 8 and the fourth lead 9 extend respectively along the column direction H of the array and are arranged in sequence along the row direction L of the array.

[0125] In some embodiments, the first lead 6 and the second lead 7 are mirror-symmetrical to the third lead 8 and the fourth lead 9 .

[0126] The display panel provided in the embodiment of the present disclosure electrically connects the pixel circuit corresponding to the nth first light-emitting element 11 in one column of any two adjacent odd-numbered columns of first light-emitting elements 11 and third light-emitting elements 13 to the n+1th third light-emitting element 13, and electrically connects the pixel circuit corresponding to the n+1th third light-emitting element 13 to the nth first light-emitting element 11. This allows the display panel to drive either the first light-emitting element 11 or the third light-emitting element 13 to emit light when the odd-numbered pixel units 1 are driven, and to drive either the third light-emitting element 13 or the first light-emitting element 11 to emit light when the even-numbered pixel units 1 are driven. This allows the display panel to first drive at least a portion of the odd rows and then drive at least a portion of the even rows. The data signal on the data line 2 that drives the light-emitting elements in the odd columns formed by the alternating arrangement of the first light-emitting elements 11 and the third light-emitting elements 13 only needs to jump once, thereby avoiding repeated jumping of the data signal on the data line 2 when the display panel drives the pixel units 1 row by row, thereby reducing the power consumption of the display panel.

[0127] Based on the above structure of the display panel, an embodiment of the present disclosure further provides a driving method for the display panel, which includes: dividing the display area into A sub-areas, where A is any integer in the range of 1 to X / 4, and X is the total number of rows of the array of pixel units in the display area, and X≥8. The driving method includes sequentially driving the pixel units in each sub-area for display. When driving the pixel units in each sub-area for display, the first 1 / 2A frame scans the odd-numbered rows of pixel units, and the odd-numbered data lines input data signals for driving the first light-emitting element to emit light, and the even-numbered data lines input data signals for driving the second light-emitting element to emit light; the second 1 / 2A frame scans the even-numbered rows of pixel units, and the odd-numbered data lines input data signals for driving the third light-emitting element to emit light, and the even-numbered data lines input data signals for driving the second light-emitting element to emit light.

[0128] In some embodiments, when A=1, the first half of the display area scans odd-numbered rows of pixels, with odd-numbered data lines receiving data signals driving the first light-emitting element to emit light, and even-numbered data lines receiving data signals driving the second light-emitting element to emit light. The second half of the display area scans even-numbered rows of pixels, with odd-numbered data lines receiving data signals driving the third light-emitting element to emit light, and even-numbered data lines receiving data signals driving the second light-emitting element to emit light. This drive significantly reduces the number of data signal transitions on the data lines. Compared to the method in FIG. 1 where the data signals of the odd-numbered columns of the display panel repeatedly switch between the first and third light-emitting elements as the gate drive circuit scans row by row, this method effectively reduces parasitic data signal transitions between adjacent data lines in the fanout region (i.e., the fanout region) of the display panel, improves flickering in the bright and dark display of the fanout region, and enhances the display quality of the display panel.

[0129] The display panel driving method realizes sequential driving of odd-numbered rows and even-numbered rows of pixel units in each sub-area. In the driving process of the odd-numbered rows in each sub-area, the data signals on the data lines driving the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements and the third light-emitting elements are all data signals for driving the first light-emitting elements or the third light-emitting elements to emit light. In the driving process of the even-numbered rows in each sub-area, the data signals on the data lines driving the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements and the third light-emitting elements are all data signals for driving the third light-emitting elements or the first light-emitting elements to emit light. That is, in the display process of each sub-area, the data signals on the data lines driving the odd-numbered columns of light-emitting elements formed by the alternating arrangement of the first light-emitting elements and the third light-emitting elements only need to jump once, thereby reducing the number of jumps of the data signals on the data lines, reducing the power consumption of each sub-area during display, and further reducing the power consumption of the display panel.

[0130] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel in the above embodiment.

[0131] By adopting the display panel in the above embodiment, the power consumption of the display device is reduced.

[0132] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, or a navigation system.

[0133] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, wherein: comprising a plurality of pixel units arranged in an array; The pixel unit comprises at least one first light emitting element, two second light emitting elements and one third light emitting element, and the first light emitting element, the second light emitting element and the third light emitting element have different light emitting colors; In the pixel unit, the second light emitting element is located in the same odd row and different even columns, and the first light emitting element and the third light emitting element are located in the same even row and different odd columns, In the array of the pixel units, the positions of the first light emitting elements and the third light emitting elements in any two adjacent even-numbered rows are staggered, and the positions of the first light emitting elements and the third light emitting elements in any two adjacent odd-numbered columns are staggered. The first light emitting element and the third light emitting element located in the same column are electrically connected to the same data line; the second light emitting element located in the same column is electrically connected to the same data line; The pixel unit further includes a plurality of pixel circuits, and the plurality of pixel circuits correspond to the first light-emitting element, the second light-emitting element, and the third light-emitting element in the pixel unit, respectively. Among the first light-emitting elements and the third light-emitting elements in any two adjacent odd-numbered columns, the pixel circuit corresponding to the nth light-emitting element in one column is electrically connected to the n+1th light-emitting element, and the pixel circuit corresponding to the n+1th light-emitting element is electrically connected to the nth light-emitting element, where n is an odd number; the nth light-emitting element is the first light-emitting element or the third light-emitting element, and the n+1th light-emitting element is the third light-emitting element or the first light-emitting element.

2. The display panel according to claim 1, wherein: The plurality of pixel circuits correspond one-to-one to the first light emitting element, the two second light emitting elements and the third light emitting element in the pixel unit, Among the second light emitting elements in any two adjacent even-numbered columns, the nth light emitting element in one column The pixel circuit corresponding to the second light-emitting element is electrically connected to the n+1th second light-emitting element, and the pixel circuit corresponding to the n+1th second light-emitting element is electrically connected to the nth second light-emitting element, where n is an odd number.

3. The display panel according to claim 1 or 2, wherein: The array of pixel units in the display area includes X rows, X ≥ 8, The display area is divided into A sub-areas, and the A sub-areas are arranged in sequence along the column direction of the array, and each of the sub-areas includes at least four rows of pixel units, The A is any integer in the range of 1 to X / 4.

4. The display panel according to claim 3, wherein: It also includes at least one light emitting control driving circuit, which is located in at least one side frame area, and different light emitting control driving circuits are electrically connected to the pixel circuits in different sub-areas. The light emitting control driving circuit comprises a plurality of first shift registers, wherein the odd-numbered first shift registers are sequentially cascaded, the even-numbered first shift registers are sequentially cascaded, and the output end of the last odd-numbered first shift register is electrically connected to the input end of the first even-numbered first shift register. The output ends of the odd-numbered first shift registers are electrically connected to the pixel circuits in the pixel units located in the odd-numbered rows. The output ends of the even-numbered first shift registers are electrically connected to the pixel circuits in the pixel units located in the even-numbered rows; The output end of the last first shift register of the upper light emitting control driving circuit among two adjacent light emitting control driving circuits is electrically connected to the input end of the first first shift register of the lower light emitting control driving circuit.

5. The display panel according to claim 4, wherein: In the light emitting control driving circuit, the output end of the Nth first shift register is electrically connected to the pixel circuits in the pixel units in the 2N-1th and 2N+1th rows in the corresponding sub-area, where N is an odd number; The output end of the Mth first shift register is electrically connected to the pixel circuit in the pixel units in the 2M-2th and 2Mth rows in the corresponding sub-area, where M is an even number.

6. The display panel according to claim 5, wherein: An input end of the first shift register of the first light emitting control driving circuit is electrically connected to the light emitting control trigger signal output end.

7. The display panel according to claim 6, wherein: It also includes at least one gate driving circuit located in at least one side frame area, and different gate driving circuits are electrically connected to the pixel circuits in different sub-areas. The gate driving circuit includes a plurality of second shift registers, wherein the odd-numbered second shift registers among the plurality of second shift registers are cascaded in sequence, the even-numbered second shift registers are cascaded in sequence, and the output end of the last odd-numbered second shift register is electrically connected to the input end of the first even-numbered second shift register. The output ends of the odd-numbered second shift registers are electrically connected to the pixel circuits in the pixel units located in the odd-numbered rows. The output ends of the even-numbered second shift registers are electrically connected to the pixel circuits in the pixel units located in the even-numbered rows; The output end of the last second shift register of the upper gate driving circuit of two adjacent gate driving circuits is electrically connected to the input end of the first second shift register of the lower gate driving circuit.

8. The display panel according to claim 7, wherein: In the gate driving circuit, the output end of the Nth second shift register is electrically connected to the pixel circuits in the pixel units in the 2N-1th row and the 2N+1th row in the corresponding sub-area, where N is an odd number; The output end of the Mth second shift register is electrically connected to the pixel circuits in the pixel units in the 2M-2th and 2Mth rows in the corresponding sub-area, where M is an even number.

9. The display panel according to claim 8, wherein: An input end of a first of the second shift registers of the first of the gate driving circuits is electrically connected to a gate driving trigger signal output end.

10. The display panel according to claim 9, wherein: The gate driving circuit includes a first gate driving circuit, a second gate driving circuit and a third gate driving circuit; An input terminal of a first of the second shift registers of the first gate driving circuit is electrically connected to a first gate driving trigger signal output terminal; An input terminal of a first of the second shift registers of the first of the second gate driving circuits is electrically connected to a second gate driving trigger signal output terminal; An input terminal of a first of the second shift registers of the first of the third gate driving circuits is electrically connected to a third gate driving trigger signal output terminal.

11. The display panel according to claim 10, wherein: It also includes at least one pair of fourth gate driving circuits located in the frame areas on opposite sides, and different fourth gate driving circuits located in the frame area on the same side are electrically connected to the pixel circuits in different sub-areas. The fourth gate driving circuit includes a plurality of third shift registers, wherein the odd-numbered third shift registers among the plurality of third shift registers are cascaded in sequence, the even-numbered third shift registers are cascaded in sequence, and the output end of the last odd-numbered third shift register is electrically connected to the input end of the first even-numbered third shift register. The output ends of the odd-numbered third shift registers are electrically connected to the pixel circuits in the pixel units located in the odd-numbered rows. The output terminals of the even-numbered third shift registers are electrically connected to the pixel cells located in the even-numbered rows. The pixel circuit in the element; The output end of the last third shift register of the previous fourth gate driving circuit in two adjacent fourth gate driving circuits located in the border area on the same side is electrically connected to the input end of the first third shift register of the next fourth gate driving circuit.

12. The display panel according to claim 11, wherein: In the fourth gate driving circuit, an output terminal of the Nth third shift register is electrically connected to the pixel circuit in the Nth row of pixel units in the corresponding sub-area, where N is an odd number; An output terminal of the Mth third shift register is electrically connected to the pixel circuit in the Mth row of pixel units in the corresponding sub-area, where M is an even number.

13. The display panel according to claim 12, wherein: An input end of the first third shift register of the first fourth gate driving circuit located in the frame area on the same side is electrically connected to the fourth gate driving trigger signal output end.

14. The display panel according to any one of claims 2 to 13, wherein: The first light-emitting element, the second light-emitting element and the third light-emitting element each include an anode, a light-emitting functional layer and a cathode stacked in sequence, The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a driving transistor, a first capacitor and a second capacitor. The first electrode of the first transistor, the first electrode of the second transistor, the first electrode of the sixth transistor and the first electrode of the driving transistor are connected to a third node. The second electrode of the first transistor, the first electrode of the fifth transistor, the first plate of the first capacitor, and the first plate of the second capacitor are connected to a first node. The second plate of the second capacitor, the gate of the driving transistor and the fourth transistor The first electrode is connected to the second node, The first electrode of the seventh transistor, the first electrode of the third transistor and the anode are connected to a fourth node, The second electrode of the second transistor and the second electrode plate of the first capacitor are connected to a first power source, The second electrode of the fifth transistor is connected to the data line, The second electrode of the sixth transistor is connected to a third reset power supply, The second electrode of the fourth transistor is connected to a second reset power supply, The second electrode of the driving transistor is connected to the second electrode of the seventh transistor, The second electrode of the third transistor is connected to the first reset power supply, The cathode is connected to a second power source; The gate of the first transistor and the gate of the fourth transistor are connected to the first gate driving circuit, The gate of the third transistor is connected to the second gate driving circuit, The gate of the sixth transistor and the gate of the seventh transistor are connected to the third gate driving circuit, The gate of the second transistor is connected to the light emitting control driving circuit. The gate of the fifth transistor is connected to the fourth gate driving circuit.

15. The display panel according to claim 14, wherein: The first light emitting element includes a first anode, the third light emitting element includes a third anode, the first anode and the third anode are arranged in the same layer, The fourth node of the pixel circuit corresponding to the nth first light emitting element is connected to the third anode of the n+1th third light emitting element through a first lead wire, The fourth node of the pixel circuit corresponding to the (n+1)th third light emitting element is connected to the first anode of the (n)th first light emitting element through a second lead.

16. The display panel according to claim 15, wherein: The pixel circuit includes a plurality of conductive layers. The first lead and the second lead are arranged in the same layer and are located in any one of the conductive layers.

17. The display panel according to claim 16, wherein: The second light emitting element includes a second anode, and the second anode is arranged in the same layer as the first anode and the third anode. The fourth node of the pixel circuit corresponding to the nth second light emitting element is connected to the second anode of the n+1th second light emitting element through a third lead wire, The fourth node of the pixel circuit corresponding to the (n+1)th second light emitting element is connected to the second anode of the (n)th second light emitting element through a fourth lead.

18. The display panel according to claim 17, wherein: The third lead and the fourth lead are arranged in the same layer as the first lead and the second lead, The first lead, the second lead, the third lead and the fourth lead extend along the column direction of the array respectively, and are arranged in sequence along the row direction of the array.

19. A display device, wherein: A display panel comprising any one of claims 1-18.

20. A method for driving a display panel according to any one of claims 1 to 18, wherein: include: The display area is divided into A sub-areas, where A is any integer in the range of 1 to X / 4, X is the total number of rows of the array of pixel units in the display area, and X≥8, The driving method comprises driving the pixel units in each of the sub-areas in sequence to display, When the pixel units in each sub-area are driven to display, the first 1 / 2A frame scans the odd-numbered rows of pixel units, and the odd-numbered data lines input the data signal driving the first light-emitting element to emit light, and the even-numbered data lines input the data signal driving the first light-emitting element to emit light. A data signal driving the second light emitting element to emit light is inputted into the data line; The next 1 / 2A frame scans the even-numbered rows of pixel units, the odd-numbered data lines are input with data signals driving the third light-emitting element to emit light, and the even-numbered data lines are input with data signals driving the second light-emitting element to emit light.

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