Silicon carbide semiconductor device, and method for producing same

Abstract

Provided is a method for manufacturing a silicon carbide semiconductor device, the method being capable of bringing an electrode into ohmic contact with a semiconductor layer made of silicon carbide without forming a silicide layer. The method for manufacturing a silicon carbide semiconductor device includes: a step for ion-implanting impurities into, on the upper surface thereof, a first semiconductor layer made of 4H-SiC silicon carbide at an angle of 30° or more but less than 90° with respect to a line normal to the upper surface of the first semiconductor layer, to form on the upper surface of the first semiconductor layer, a second semiconductor layer made of silicon carbide containing 3C-SiC at least on the upper surface side thereof; and a step for forming a main electrode on the upper surface side of the second semiconductor layer.

Description

Silicon carbide semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a silicon carbide semiconductor device that is a semiconductor device using silicon carbide (SiC), and a method for manufacturing the same.

[0002] Patent Document 1 discloses a method for forming a semiconductor structure, including the steps of providing a silicon carbide layer having a crystal axis, heating the silicon carbide layer to a temperature of about 300°C or higher, implanting dopant ions into the heated silicon carbide layer at an implantation angle of less than about 2° between the direction of implantation and the crystal axis, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000°C-hour to activate the implanted ions.

[0003] Patent Document 2 discloses a silicon carbide layer having a first surface having an off angle of 0 to 8 degrees with respect to the {0001} plane, and a second surface opposite to the first surface, and having a 4H—SiC crystal structure, the silicon carbide layer including a p-type first silicon carbide region, an n-type second silicon carbide region located between the first silicon carbide region and the first surface, a third silicon carbide region located between the first silicon carbide region and the first surface, the second silicon carbide region being located between the first silicon carbide region and the first surface, and containing oxygen, a gate electrode, a silicon oxide layer between the silicon carbide layer and the gate electrode, and a silicon carbide layer located between the silicon carbide layer and the silicon oxide layer, the third silicon carbide region having a nitrogen concentration of 1×10 ２１ cm －３ A semiconductor device including the above-mentioned regions is disclosed.

[0004] Patent Document 3 discloses an electronic device comprising: a silicon carbide drift region having a first conductivity type and a first doping concentration; a well region in the drift region, the well region having a second conductivity type opposite to the first conductivity type and having a second doping concentration; and a region of the second conductivity type deeply implanted below the well region, the deeply implanted region having a third doping concentration higher than the first doping concentration and lower than the second doping concentration; the drift region comprising a drift layer having a first doping concentration and a current spreading layer on the drift layer having a fourth doping concentration, the fourth doping concentration being higher than the first doping concentration of the drift layer and lower than the third doping concentration of the deeply implanted region, the deeply implanted region extending to a depth shallower than a thickness of the current spreading layer.

[0005] Patent Document 4 discloses a method for implanting dopant ions into a silicon carbide layer having a crystal axis, the method including the steps of: preparing a silicon carbide layer having a crystal axis; heating the silicon carbide layer to a temperature of about 300° C. or higher; implanting dopant ions into the heated silicon carbide layer at an implantation angle of less than about 2° between the direction of implantation and the crystal axis; and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hour to activate the implanted ions, the step of implanting dopant ions being performed at a rate of 1E13 cm at an implantation energy of about 100 keV or less. －２ A method of forming a semiconductor structure is disclosed that includes implanting dopant ions at a dose of less than 1000 .mu.m.

[0006] Patent Documents 5 and 6 disclose a substrate having a low off-angle of less than 4 degrees and a SiC epitaxial growth layer provided on the substrate, in which the SiC epitaxial growth layer uses a Si compound as a Si supply source and a C compound as a C supply source, and has a carrier density uniformity of less than 10% and a defect density of 1 / cm ２ and the C / Si ratio of the Si compound to the C compound is in the range of 0.7 to 0.95.

[0007] Patent Documents 7 and 8 disclose a method for producing a SiC epitaxial growth layer, which includes the steps of preparing a SiC ingot, cutting it at an off-angle, and polishing it to form a SiC bare wafer having a (0001) plane as its surface; removing the cut surface of the SiC bare wafer to form a SiC substrate; and growing a SiC epitaxial growth layer on the SiC substrate; the source gas supplied during the epitaxial growth contains a Si compound serving as a Si supply source and a C compound serving as a C supply source, and the Si compound contains both the Si compound and the C compound, or a compound containing fluorine; and the surface irregularity defect density including particles on the surface of the SiC epitaxial growth layer is 0.07 / cm. ２ A method for manufacturing a SiC epitaxial wafer is disclosed in which the crystal growth temperature is controlled so that the temperature is less than

[0008] Patent Document 9 discloses a semiconductor device having an element region having an insulated gate switching element and a peripheral region adjacent to the element region, in which a first trench and a second trench are formed in the peripheral region, a surface region of a second conductivity type is formed between the first trench and the second trench, a first bottom region of the second conductivity type is formed on a bottom surface of the first trench, a second bottom region of the second conductivity type is formed on a bottom surface of the second trench, a first side region of the second conductivity type connecting the surface region and the first bottom region is formed along a side surface of the first trench, a second side region of the second conductivity type connecting the surface region and the second bottom region is formed along a side surface of the second trench, and a low surface density region is formed in at least a part of the first side region and the second side region.

[0009] Japanese Patent Publication No. 2022-31923 Japanese Patent Publication No. 2022-144217 Japanese Patent No. 7015750 Japanese Patent No. 6391689 Japanese Patent No. 6584253 International Publication No. 2017 / 047350 Japanese Patent No. 6479347 International Publication No. 2015 / 186791 Japanese Patent No. 6169966

[0010] In silicon carbide semiconductor devices, the formation of a silicide layer such as nickel silicide (NiSi) has been considered for the purpose of achieving ohmic contact between a silicon carbide semiconductor layer and an electrode. However, the surface of the silicide layer is prone to becoming uneven, which may adversely affect reliability.

[0011] An object of the present disclosure is to provide a silicon carbide semiconductor device that can achieve ohmic contact between a semiconductor layer made of silicon carbide and an electrode without forming a silicide layer, and a method for manufacturing the same.

[0012] In order to achieve the above object, one aspect of the present disclosure provides a semiconductor device comprising: a first semiconductor layer made of silicon carbide of 4H—SiC; a second semiconductor layer provided on an upper surface of the first semiconductor layer and made of silicon carbide containing 3C—SiC at least on an upper surface thereof; and a main electrode provided on the upper surface of the second semiconductor layer, wherein an impurity concentration at a depth of 0.3 μm from the upper surface of the second semiconductor layer is 1×10 １８ / cm ３ or more, and the impurity concentration at a depth of 0.5 μm or more from the top surface of the second semiconductor layer is 1×10 １７ / cm ３ The present invention provides a silicon carbide semiconductor device as follows.

[0013] Another aspect of the present disclosure is summarized as a method for manufacturing a silicon carbide semiconductor device, including: forming a second semiconductor layer made of silicon carbide containing 3C—SiC on at least an upper surface side of the first semiconductor layer by ion-implanting impurities into an upper surface of a first semiconductor layer made of 4H—SiC silicon carbide at an angle of 30° or more and less than 90° with respect to a normal to the upper surface of the first semiconductor layer; and forming a main electrode on the upper surface side of the second semiconductor layer.

[0014] According to the present disclosure, it is possible to provide a silicon carbide semiconductor device that can bring an electrode into ohmic contact with a semiconductor layer made of silicon carbide without forming a silicide layer, and a method for manufacturing the same.

[0015] 1 is a plan view of a silicon carbide semiconductor device according to a first embodiment. FIG. 1 is a cross-sectional view taken along the A-A direction of FIG. 1 . FIG. 1 is a cross-sectional view taken along the B-B direction of FIG. FIG. 1 is a cross-sectional view taken along the B-B direction of FIG. FIG. 1 is a cross-sectional view taken along the B-B direction of FIG. FIG. 1 is a cross-sectional view taken along the B-B direction of FIG. FIG. 1 is a cross-sectional view taken along the B-B direction of FIG. FIG. 1 is a cross-sectional view taken along the B-B direction of FIG. FIG. 17 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the third embodiment. FIG. 18 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 19 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 20 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 21 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 22 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 23 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 24 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. FIG. 25 is a cross-sectional view illustrating a process of the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment.Fig. 27 is a cross-sectional view illustrating a process following Fig. 28 in the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. Fig. 29 is a cross-sectional view illustrating a process following Fig. 30 in the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. Fig. 31 is a cross-sectional view illustrating a process following Fig. 32 in the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. Fig. 32 is a cross-sectional view illustrating a process following Fig. 33 in the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. Fig. 33 is a cross-sectional view illustrating a process following Fig. 34 in the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment. Fig. 34 is a cross-sectional view illustrating a process following Fig. 35 in the method for manufacturing a silicon carbide semiconductor device according to the fifth embodiment. Fig. 35 is a cross-sectional view illustrating a silicon carbide semiconductor device according to a sixth embodiment.

[0016] Hereinafter, first to sixth embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to sixth embodiments shown below are examples of devices and methods for embodying the technical concept of the present disclosure, and the technical concept of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components described below.

[0017] In this disclosure, the source region of a metal-oxide semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as an emitter region in an insulated gate bipolar transistor (IGBT) or as a cathode region in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor) or a diode. The drain region of a MOSFET is "the other main region (second main region)" that can be selected as a collector region in an IGBT or as an anode region in a thyristor or a diode. In this disclosure, the term "main region" simply refers to either "one main region (first main region)" or "the other main region (second main region)" that is appropriate based on the common technical knowledge of a person skilled in the art.

[0018] Furthermore, the definitions of directions such as up and down in this disclosure are merely for the convenience of explanation and do not limit the technical concept of this disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Furthermore, "top surface" may be read as "front surface" and "bottom surface" may be read as "rear surface."

[0019] Furthermore, in this disclosure, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, a "+" or "-" attached to "n" or "p" indicates a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without a "+" or "-" attached. However, even if the same "n" and "n" are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0020] In addition, in the notation of Miller indices in the present disclosure, "-" means a bar attached to the index immediately following it, and placing "-" before an index represents a negative index.

[0021] Furthermore, SiC crystals exist in various crystal polymorphs, the main ones being the cubic 3C structure (3C-SiC), and the hexagonal 4H structure (4H-SiC) and 6H structure (6H-SiC). The band gaps at room temperature have been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In this disclosure, we will exemplify the case where 4H-SiC and 3C-SiC are primarily used.

[0022] First Embodiment <Structure of Silicon Carbide Semiconductor Device> A diode with a merged PN Schottky (MPS) structure is exemplified as a silicon carbide semiconductor device according to the first embodiment. The MPS structure is a structure in which a Schottky junction and a pn junction are mixed on the upper surface side of a semiconductor substrate.

[0023] 1 is a plan view of a silicon carbide semiconductor device according to the first embodiment. The silicon carbide semiconductor device according to the first embodiment includes an active region 101 provided in a semiconductor substrate (semiconductor base) 100, and a termination region 102 provided in the semiconductor substrate 100 so as to surround the periphery of the active region 101. The active region 101 is a region through which current flows when the diode is in an on-state. The termination region 102 is a region that relieves an electric field applied to an end of the active region 101 and maintains a breakdown voltage.

[0024] In the active region 101, a plurality of second conductivity type (p ＋ The anode regions 3 are semiconductor layers of a type (striped type). In a planar pattern, the anode regions 3 have linear (striped) portions extending parallel to each other in one direction (the vertical direction in FIG. 1 ). The anode regions 3 are arranged spaced apart from each other in a direction (the horizontal direction in FIG. 1 ) perpendicular to the direction in which the anode regions 3 extend. The number of anode regions 3 arranged is not particularly limited.

[0025] 2 shows a cross-sectional view taken along a direction perpendicular to the direction in which the anode region 3 extends, as viewed from the direction AA in FIG. 1. As shown in FIG. 2, a first conductivity type (n ＋ The cathode region 1 is formed of a substrate (SiC substrate) made of SiC such as 4H—SiC.

[0026] A first conductivity type (n-type) drift layer 2 having a lower impurity concentration than the cathode region 1 is provided on the upper surface side of the cathode region 1. The drift layer 2 is composed of an epitaxially grown layer made of SiC, such as 4H—SiC. An n-type buffer layer may be provided between the cathode region 1 and the drift layer 2. The impurity concentration of the n-type buffer layer may be lower than the impurity concentration of the cathode region 1 and higher than the impurity concentration of the drift layer 2.

[0027] The upper surface of the drift layer 2 is provided with a plurality of p ＋ Anode regions 3 of the same type are provided spaced apart from each other. ＋Each of the n-type anode regions 3 and the n-type drift layer 2 forms a pn junction. The anode regions 3 are formed by ion implantation of p-type impurities such as aluminum (Al) or boron (B) into the drift layer 2. When viewed from the A-A direction in FIG. 1 , the anode regions 3 have a substantially rectangular cross-sectional shape in a cross-sectional view taken along a direction perpendicular to the extension direction of the planar pattern of the anode regions 3.

[0028] FIG. 3 shows a cross-sectional view of the anode region 3 along the extension direction, as viewed from the B-B direction in FIG. 1 . As shown in FIG. 3 , in a cross-sectional view along the extension direction of the planar pattern of the anode region 3, the anode region 3 has a substantially parallelogram cross-sectional shape. The upper and lower surfaces of the anode region 3 are substantially parallel, and both inclined side surfaces of the anode region 3 are substantially parallel. The angle θ0 formed between the normal L1 to the upper surface of the semiconductor substrate 100 and the inclined side surface of the anode region 3 is, for example, approximately 30° or more and less than 90°. The anode region 3 is formed to have a substantially parallelogram cross-sectional shape by ion-implanting p-type impurities from an oblique direction inclined with respect to the normal L1 to the upper surface of the semiconductor substrate 100. The side surface of the anode region 3 is substantially parallel to the injection direction of the ions.

[0029] 3, in the termination region 102, a p-type electric field relaxation layer is provided on the upper surface side of the drift layer 2. When this electric field relaxation layer is in contact with or overlaps the end of the anode region 3, the anode region 3 does not need to have a substantially parallelogram cross-sectional shape.

[0030] The depth d1 of the anode region 3 is, for example, about 0.1 μm or more and 0.5 μm or less, and may be about 0.1 μm or more and 0.3 μm or less. The depth d1 of the anode region 3 may be about 0.5 μm or more. The greater the inclination angle of the ion implantation for forming the anode region 3 with respect to the normal L1 to the upper surface of the semiconductor substrate 100, the shallower the depth d1 of the anode region 3.

[0031] The impurity concentration in the range from the top surface of the anode region 3 to a depth of 0.3 μm is, for example, 1×10 １８ / cm ３ That's it, 1 x 10 ２２ / cm ３It is about 1 × 10 １９ / cm ３ That's it, 1 x 10 ２２ / cm ３ The impurity concentration in the upper surface of the anode region 3 is preferably about 1×10 ２０ / cm ３ That's it, 1 x 10 ２２ / cm ３ In the depth direction, which is perpendicular to the upper surface of the anode region 3, the impurity concentration may be uniform within a range from the upper surface of the anode region 3 to a depth of about 0.3 μm, and the impurity concentration may be uniform within a range from the upper surface of the anode region 3 to a depth of about 0.4 μm. The term "uniform impurity concentration" refers not only to the case where the impurity concentration is strictly the same, but also to a range in which the impurity concentration varies within ±10%.

[0032] In the depth direction, which is perpendicular to the upper surface of the anode region 3, the impurity concentration in a range of 0.5 μm or more from the upper surface of the anode region 3 is lower than the impurity concentration in a range of 0.3 μm from the upper surface of the anode region 3. The impurity concentration in a range of 0.5 μm or more from the upper surface of the anode region 3 is, for example, 1×10 １７ / cm ３ It is about the following.

[0033] 2 and 3, damage 4 occurs in the upper surface portion (also referred to as the "upper portion" or "surface layer") of the anode region 3, including at least the upper surface, during ion implantation to form the anode region 3, destroying the 4H—SiC crystal structure and forming an amorphous structure. Subsequent heat treatment (activation annealing) recrystallizes the amorphous structure, forming 3C—SiC. Therefore, the surface layer of the anode region 3 contains 3C—SiC.

[0034] The proportion of 3C-SiC contained in the surface layer of the anode region 3 is, for example, approximately 10% or more and 100% or less. The surface layer of the anode region 3 may be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the surface layer of the anode region 3 may also contain an amorphous structure, 4H-SiC, etc. Because 3C-SiC has a narrower bandgap than 4H-SiC, the surface layer of the anode region 3 containing 3C-SiC can form an ohmic contact with the anode electrode 5 on the upper surface of the anode region 3 with low resistance. The lower portion (lower part) of the surface layer of the anode region 3 may be composed of 4H-SiC.

[0035] As a method for measuring (observing) the crystal structure of 3C—SiC or 4H—SiC, for example, the area ratio of the crystal structure on the surface can be measured using a field emission scanning electron microscope (FE-SEM) and electron backscatter diffraction (EBSD).

[0036] 2 and 3, an anode electrode (top electrode) 5 is provided on the top surface of the drift layer 2 and the anode region 3. The anode electrode 5 is not shown in FIG. 1. The anode electrode 5 is in contact with the top surfaces of the drift layer 2 and the anode region 3. The anode electrode 5 is made of a metal such as aluminum (Al), an Al alloy, or molybdenum (Mo). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu), and Al-Si-Cu.

[0037] The anode electrode 5 may have a barrier metal layer in a portion in contact with the anode region 3. The barrier metal layer may be made of a metal such as titanium nitride (TiN), titanium (Ti), or a TiN / Ti laminate structure with a Ti underlayer. The metal material of the portion of the anode electrode 5 in contact with the anode region 3 is, for example, aluminum (Al), an Al alloy, molybdenum (Mo), titanium (Ti), or titanium nitride (TiN).

[0038] Because the surface layer of the anode region 3 contains 3C—SiC, the anode region 3 is in ohmic contact with the anode electrode 5 with low resistance. For this reason, no silicide layer made of nickel silicide (NiSi) or the like is provided between the anode electrode 5 and the anode region 3. On the other hand, the drift layer 2 sandwiched between adjacent anode regions 3 forms a Schottky junction with the anode electrode 5.

[0039] The silicon carbide semiconductor device according to the first embodiment has an MPS structure that combines pn junctions between a plurality of anode regions 3 and the drift layer 2, and Schottky junctions between the drift layers 2 between the anode regions 3 and the anode electrodes 5. This reduces the electric field strength at the junction surface between the semiconductor substrate 100 and the anode electrodes 5, thereby suppressing reverse leakage current.

[0040] 2 and 3, a cathode electrode (rear electrode) 6 is provided on the lower surface side of the cathode region 1. The cathode electrode 6 is configured, for example, as a single layer film made of a metal such as gold (Au), or a laminated film in which titanium (Ti), nickel (Ni), and gold (Au) are laminated in this order. A silicide layer may also be provided between the cathode region 1 and the cathode electrode 6.

[0041] <Method for Manufacturing Silicon Carbide Semiconductor Device> Next, an example of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described, focusing mainly on the cross section corresponding to FIG.

[0042] First, a first conductivity type (n) made of SiC such as 4H—SiC and doped with n-type impurities such as nitrogen (N) is used. ＋ A starting substrate, which is a SiC substrate of a first conductivity type (n-type), is prepared as cathode region 1 (see FIG. 4 ). The upper surface of cathode region 1 may have an off-angle of, for example, about 0° to 8° (for example, about 4°). Next, as shown in FIG. 4 , a drift layer 2 of a first conductivity type (n-type) made of SiC such as 4H—SiC and doped with n-type impurities such as N is epitaxially grown on cathode region 1. If the upper surface of cathode region 1 has an off-angle, the upper surface of drift layer 2 also has a similar off-angle. Cathode region 1 and drift layer 2 constitute a semiconductor substrate 100.

[0043] Next, a photoresist film 7 (see FIG. 5) is applied to the upper surface of the drift layer 2, and the photoresist film 7 is patterned using photolithography. Using the patterned photoresist film 7 as an ion implantation mask, p-type impurities such as aluminum (Al) are ion-implanted into the upper surface of the drift layer 2, as shown in FIG. ＋ The anode region 3 of the mold is formed.

[0044] FIG. 6 shows a cross section corresponding to FIG. 3 during the ion implantation shown in FIG. 5 . As shown in FIG. 6 , p-type impurities are ion-implanted obliquely at a predetermined angle θ1 with respect to a normal L1 to the upper surface of the semiconductor substrate 100. The predetermined angle θ1 is, for example, approximately 30° or more and less than 90°, or may be approximately 45° or more and less than 90°, or may be approximately 60° or more and less than 90°. The larger the predetermined angle θ1, the shallower the anode region 3 formed. As shown in FIG. 6 , by tilting the implantation direction of ion implantation in the longitudinal direction (extension direction) of the planar pattern of the anode region 3, shadowing (misalignment between the mask and the ion implantation) can be prevented.

[0045] The acceleration energy of the ion implantation is about 300 keV or more and 700 keV or less, and may be about 400 keV or more and 700 keV or less. By setting the acceleration energy of the ion implantation to a high acceleration of 300 keV or more, damage 4 can be introduced into the surface layer of the anode region 3, as schematically shown by "x" in Figures 5 and 6, and the crystal structure of 4H-SiC can be destroyed to form an amorphous structure. The higher the acceleration energy of the ion implantation, the more easily damage 4 can be introduced.

[0046] 7, consider a case where the semiconductor substrate 100 has an off angle θ2 in the <11-20> direction with respect to the <0001> (c-axis) direction. The off angle θ2 is the angle between the top surface of the semiconductor substrate 100 (shown by the dashed line) and a plane (basal plane) perpendicular to the c-axis, which is the (0001) plane (silicon (Si) plane) or the (000-1) plane (carbon (C) plane).

[0047] 7 , when the implantation direction of ions is tilted at a predetermined angle θ1 toward the off-angle θ2 (off-angle direction) with respect to the normal L1 to the top surface of the semiconductor substrate 100, the predetermined angle θ1 is set to approximately less than (90°-θ2), which is less than the angle parallel to the off-angle direction. This makes it possible to prevent the implantation direction from becoming parallel to the off-angle θ2, thereby enabling uniform ion implantation. For example, when the off-angle θ2 of the semiconductor substrate 100 is 4°, the implantation angle θ1 may be set to approximately less than 86°.

[0048] On the other hand, as shown in Figure 8, when the implantation direction of ions is tilted in a direction different from the off-angle θ2, the predetermined angle θ1 with respect to the normal L1 to the top surface of the semiconductor substrate 100 is set to less than 90°, thereby enabling uniform ion implantation. Figure 8 illustrates an example in which the implantation direction of ions is tilted in a direction opposite to the off-angle direction. In this case, the implantation angle θ1 can be set to less than 90°.

[0049] Next, the implanted p-type impurity ions are activated by heat treatment (activation annealing) at a temperature of, for example, about 1600° C. or higher and 1900° C. or lower. At this time, the amorphous structure of the surface layer of the anode region 3 is recrystallized to become 3C—SiC.

[0050] Next, an anode electrode 5 made of aluminum (Al) or the like is formed on the upper surfaces of the drift layer 2 and the anode region 3 by sputtering, vapor deposition, or the like (see FIGS. 2 and 3). The drift layer 2 and the anode electrode 5 form a Schottky junction, and the anode region 3 and the anode electrode 5 form an ohmic contact with low resistance.

[0051] Next, semiconductor substrate 100 is ground from the underside to adjust the thickness of semiconductor substrate 100 to the product thickness. Next, a cathode electrode 6 made of gold (Au) or the like is formed on the entire underside of semiconductor substrate 100 by sputtering, vapor deposition, or the like (see FIGS. 2 and 3 ). Thereafter, semiconductor substrate 100 is cut (diced) into individual pieces, thereby completing the silicon carbide semiconductor device according to the first embodiment.

[0052] <First Comparative Example> Here, a silicon carbide semiconductor device according to a first comparative example will be described. As shown in FIG. 9, the silicon carbide semiconductor device according to the first comparative example has a p ＋ 2 in that a silicide layer 8 made of nickel silicide (NiSi) is provided between the anode region 3 and the anode electrode 5. The depth d2 of the anode region 3 is the same as the depth d1 of the anode region 3 of the silicon carbide semiconductor device according to the first embodiment shown in Fig. 2. The anode region 3 is made of 4H—SiC, and the silicide layer 8 is provided between the anode region 3 and the anode electrode 5 to form an ohmic contact between the anode region 3 and the anode electrode 5.

[0053] In the method for manufacturing a silicon carbide semiconductor device according to the first comparative example, in the ion implantation step for forming anode region 3, p-type impurities are ion-implanted from the direction normal to the upper surface of semiconductor substrate 100, without tilting the substrate relative to the normal to the upper surface of semiconductor substrate 100. The acceleration energy during ion implantation is less than 300 keV, which is lower than the acceleration energy during ion implantation in the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Therefore, no damage occurs to the surface layer of anode region 3, and anode region 3 remains 4H—SiC. Thereafter, a metal film such as nickel (Ni) is formed on the upper surface side of anode region 3, and heat treatment is performed to form silicide layer 8.

[0054] In the silicon carbide semiconductor device and its manufacturing method according to the first comparative example, unevenness is likely to occur on the surface of silicide layer 8, which may adversely affect reliability due to, for example, deterioration of coverage of the barrier metal layer formed on the upper surface side of silicide layer 8. Furthermore, since anode region 3 and anode electrode 5 are in ohmic contact, a step of forming silicide layer 8 is required, which increases the number of steps and costs.

[0055] In contrast, in the silicon carbide semiconductor device and its manufacturing method according to the first embodiment, in the ion implantation step for forming the anode region 3, p-type impurities are ion-implanted into the upper surface of the drift layer 2 from an oblique direction inclined at a predetermined angle θ1 with respect to the normal L1 to the upper surface of the semiconductor substrate 100. This allows the anode region 3 to be formed shallowly despite high acceleration energy, and damage 4 is introduced into the surface layer of the anode region 3, allowing 3C-SiC to be formed, thereby enabling ohmic contact between the anode region 3 and the anode electrode 5 with low resistance. Therefore, since it is not necessary to form a silicide layer between the anode region 3 and the anode electrode 5, there is no concern about unevenness on the surface of the silicide layer, improving reliability and reducing the number of steps and costs involved in the process of forming the silicide layer.

[0056] Second Comparative Example Next, a silicon carbide semiconductor device according to a second comparative example will be described. As shown in FIG. 10 , the silicon carbide semiconductor device according to the second comparative example has a p ＋ The present embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the depth d3 of the anode region 3 is deeper than the depth d1 of the anode region 3 shown in Figure 2. The surface layer of the anode region 3 contains 3C-SiC due to damage 4 caused by ion implantation for forming the anode region 3. Therefore, the anode region 3 and the anode electrode 5 are in ohmic contact with low resistance, and no silicide layer is provided between the anode region 3 and the anode electrode 5.

[0057] In the method for manufacturing a silicon carbide semiconductor device according to the second comparative example, in the ion implantation step for forming anode region 3, p-type impurity ions are implanted from the normal direction to the upper surface of semiconductor substrate 100, without tilting the ion implantation with respect to the normal to the upper surface of semiconductor substrate 100. The acceleration energy during ion implantation is 300 keV or more, which is similar to the acceleration energy during ion implantation in the method for manufacturing a silicon carbide semiconductor device according to the first embodiment, and therefore damage 4 occurs in the surface layer of anode region 3, and 3C-SiC is formed in the surface layer of anode region 3 after heat treatment.

[0058] However, in the silicon carbide semiconductor device according to the second comparative example, ions are implanted at high acceleration from the normal direction of the upper surface of the semiconductor substrate 100, so that the p-type impurity is implanted deep, resulting in a low impurity concentration in the surface layer of the anode region 3. For example, the impurity concentration in the range from the upper surface of the anode region 3 to a depth of 0.3 μm is 1×10 １８ / cm ３ Therefore, in order to increase the impurity concentration in the surface layer of the anode region 3, it is necessary to perform ion implantation such as multi-stage ion implantation on the surface layer of the anode region 3, which increases the process load and requires a long implantation time for a high dose.

[0059] In contrast, in the silicon carbide semiconductor device and its manufacturing method according to the first embodiment, in the ion implantation step for forming anode region 3, p-type impurities are ion-implanted into the upper surface of drift layer 2 from an oblique direction inclined at a predetermined angle θ1 with respect to normal L1 to the upper surface of semiconductor substrate 100. This makes it possible to increase the impurity concentration in the surface layer of anode region 3 while causing damage 4 on the upper surface side of anode region 3. This reduces the process load.

[0060] <Simulation Results> Figure 11 shows the results of a Monte Carlo simulation of the impurity profile when phosphorus (P) or aluminum (Al) ions are implanted from the normal direction of the top surface of the wafer, and the acceleration energy of the ion implantation is changed to 30 keV, 100 keV, 200 keV, 500 keV, 1000 keV, 1500 keV, and 2000 keV. The horizontal axis of Figure 11 represents the depth from the top surface of the wafer, and the vertical axis of Figure 11 represents the impurity concentration (damage). As shown in Figure 11, it can be seen that the higher the acceleration energy, the deeper the damage.

[0061] FIG. 12 shows the results when the ion species is Al, the wafer off-angle is 4°, and the dose is 1×10 １３ cm －２12 shows the results of Monte Carlo simulation of impurity profiles when the implantation angle with respect to the normal direction to the upper surface of the wafer is fixed at 86° and the implantation energy is changed to 100 keV, 200 keV, 300 keV, 400 keV, 500 keV, 600 keV, and 700 keV. The horizontal axis of FIG. 12 represents the depth from the upper surface of the wafer, and the vertical axis of FIG. 12 represents the impurity concentration (damage).

[0062] As shown in FIG. 12, the impurity concentration is 1×10 ２０ cm －３ The high-concentration damage layer described above must be at least 0.1 μm deep from the top surface of the wafer. This is because the portion of the wafer at a depth of about 0.1 μm from the top surface may be lost due to the subsequent oxidation process. Therefore, the acceleration energy is 1×10 ２０ cm －３ It is preferable to set the energy to 400 keV or more, which is about the same as the energy of the laser.

[0063] FIG. 13 shows the results when the ion species is Al, the wafer off-angle is 4°, and the dose is 1×10 １３ cm －２ 13 shows the results of a Monte Carlo simulation of the impurity profile when the implantation energy is fixed at 300 keV and the implantation angle with respect to the normal direction of the upper surface of the wafer is changed to 0°, 15°, 30°, 45°, 60°, 75°, and 86°. The horizontal axis of FIG. 13 represents the depth from the upper surface of the wafer, and the vertical axis of FIG. 13 represents the impurity concentration (damage).

[0064] As shown in Figure 13, the peak damage amount is similar when the implantation angle is 0° and 15°. On the other hand, when the implantation angle is 30° or more, the damage amount increases and 3C-SiC increases. Therefore, the implantation angle with respect to the normal direction to the top surface of the wafer is preferably 30° or more.

[0065] Second Embodiment Fig. 14 shows a cross section of a silicon carbide semiconductor device according to a second embodiment when viewed from the A-A direction in Fig. 1. The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that, as shown in Fig. 14, the anode region 3 has a substantially parallelogram cross-sectional shape when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1. The other configuration of the silicon carbide semiconductor device according to the second embodiment is the same as that of the silicon carbide semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0066] 15 , in a method for manufacturing a silicon carbide semiconductor device according to the second embodiment, in a cross-sectional view taken along a direction orthogonal to the extension direction of the planar pattern of anode region 3, a photoresist film 9 is patterned, and the patterned photoresist film 9 is used as an ion implantation mask to implant ions of p-type impurities from an oblique direction inclined at an angle θ3 with respect to a normal L1 to the top surface of semiconductor substrate 100, thereby forming anode region 3. Other steps in the method for manufacturing a silicon carbide semiconductor device according to the second embodiment are the same as those in the method for manufacturing a silicon carbide semiconductor device according to the first embodiment.

[0067] According to the silicon carbide semiconductor device and manufacturing method thereof in accordance with the second embodiment, as in the first embodiment, p-type impurities are ion-implanted into the upper surface of the drift layer 2 from an oblique direction inclined at a predetermined angle θ3 with respect to the normal L1 to the upper surface of the semiconductor substrate 100. This causes damage 4 in the surface layer of the anode region 3, forming 3C-SiC, thereby enabling ohmic contact between the anode region 3 and the anode electrode 5 and eliminating the need for a silicide layer. Furthermore, since the impurity concentration in the surface layer of the anode region 3 can be increased, the process load can be reduced.

[0068] Third Embodiment Fig. 16 shows a cross section of a silicon carbide semiconductor device according to a third embodiment when viewed from the A-A direction in Fig. 1. The silicon carbide semiconductor device according to the third embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that, as shown in Fig. 16, the anode region 3 has a substantially trapezoidal cross-sectional shape when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1 when viewed from the B-B direction in Fig. 1

[0069] In the method for manufacturing a silicon carbide semiconductor device according to the third embodiment, ion implantation to form anode region 3 is performed twice. First, in the first ion implantation step, similar to the procedure in the method for manufacturing a silicon carbide semiconductor device according to the second embodiment shown in FIG. 15 , photoresist film 9 is patterned in a cross-sectional view taken along a direction perpendicular to the extension direction of the planar pattern of anode region 3, and p-type impurity ions are implanted from an oblique direction inclined at angle θ3 with respect to normal L1 to the top surface of semiconductor substrate 100, using the patterned photoresist film 9 as an ion implantation mask. Then, photoresist film 9 is removed.

[0070] Next, in the second ion implantation step, as shown in FIG. 17 , photoresist film 10 is patterned in a cross-sectional view taken along a direction perpendicular to the extension direction of the planar pattern of anode region 3. Using the patterned photoresist film 10 as an ion implantation mask, p-type impurity ions are implanted from an oblique direction tilted at an angle θ4, which is the same angle as angle θ3 shown in FIG. 15 , in the opposite direction to angle θ3 with respect to normal L1 to the top surface of semiconductor substrate 100. Thereafter, photoresist film 10 is removed. Since ion implantation to form anode region 3 is performed twice, the dose amount for each implantation is reduced compared to when ion implantation to form anode region 3 is performed once. Other steps in the method for manufacturing a silicon carbide semiconductor device according to the third embodiment are similar to those in the method for manufacturing a silicon carbide semiconductor device according to the first embodiment.

[0071] According to the silicon carbide semiconductor device and manufacturing method thereof of the third embodiment, as in the first embodiment, p-type impurities are ion-implanted into the upper surface of the drift layer 2 from an oblique direction inclined by a predetermined angle θ3 or θ4 with respect to the normal L1 to the upper surface of the semiconductor substrate 100. This causes damage 4 in the surface layer of the anode region 3, forming 3C-SiC, which allows ohmic contact between the anode region 3 and the anode electrode 5 and eliminates the need for a silicide layer. Furthermore, the impurity concentration in the surface layer of the anode region 3 can be increased, thereby reducing the process load.

[0072] Furthermore, in the silicon carbide semiconductor device and the manufacturing method thereof according to the third embodiment, by performing ion implantation twice to form anode region 3, anode region 3 can be formed with a substantially trapezoidal cross-sectional shape, thereby improving left-right symmetry.

[0073] Fourth Embodiment <Structure of Silicon Carbide Semiconductor Device> A MOSFET will be exemplified as a silicon carbide semiconductor device according to a fourth embodiment. As shown in FIG. 18 , the silicon carbide semiconductor device according to the fourth embodiment has a first conductivity type (n － The drift layer 12 is an epitaxially grown layer made of SiC such as 4H—SiC.

[0074] The upper surface side of the drift layer 12 is provided with n-type impurity layers having a higher impurity density than the drift layer 12. ＋ The drift layer 2 has a current spreading layer (CSL) 13, which is a semiconductor layer of a n-type. The current spreading layer 13 is formed of an epitaxially grown layer made of SiC such as 4H-SiC. The current spreading layer 13 may be a region in which n-type impurities are ion-implanted in the upper part of the drift layer 12. The current spreading layer 13 is not necessarily required, and if the current spreading layer 13 is not provided, the drift layer 2 may be provided up to the region of the current spreading layer 13.

[0075] Base regions 17a to 17c, which are semiconductor layers of the second conductivity type (p-type), are provided on the upper surface side of the current spreading layer 13. The base regions 17a to 17c are formed of epitaxially grown layers made of SiC, such as 4H—SiC. The base regions 17a to 17c may be regions formed by ion-implanting p-type impurities into the current spreading layer 13.

[0076] The upper surface of the base regions 17a to 17c is provided with n-type impurity layers having a higher impurity density than the drift layer 12. ＋ First main electrode regions (source regions) 18a to 18d, which are n-type semiconductor layers, are provided on the base regions 17a to 17c. The source regions 18a to 18d are formed by ion implantation of n-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As) from a direction oblique to the normal to the top surfaces of the base regions 17a to 17c.

[0077] The depth of the source regions 18a to 18d is, for example, about 0.1 μm or more and 0.5 μm or less, and may be about 0.1 μm or more and 0.3 μm or less. The depth of the source regions 18a to 18d may be about 0.5 μm or more. The impurity concentration in the range from the top surface of the source regions 18a to 18d to a depth of 0.3 μm is, for example, 1×10 １８ / cm ３ That's it, 1 x 10 ２２ / cm ３ It is about 1 × 10 １９ / cm ３ That's it, 1 x 10 ２２ / cm ３ The impurity concentration in the upper surface of the source regions 18a to 18d is preferably about 1×10 ２０ / cm ３ That's it, 1 x 10 ２２ / cm ３ In the depth direction, which is the direction perpendicular to the upper surfaces of the source regions 18a to 18d, the impurity concentration may be uniform within the range from the upper surfaces of the source regions 18a to 18d to a depth of 0.3 μm.

[0078] In the depth direction, which is perpendicular to the upper surfaces of the source regions 18a to 18d, the impurity concentration in a range of 0.5 μm or more from the upper surfaces of the source regions 18a to 18d is lower than the impurity concentration in a range of 0.3 μm from the upper surfaces of the source regions 18a to 18d. The impurity concentration in a range of 0.5 μm or more from the upper surfaces of the source regions 18a to 18d is, for example, 1×10 １７ / cm ３ It is about the following.

[0079] The source regions 18a to 18d are primarily composed of 4H-SiC. During ion implantation to form the source regions 18a to 18d, damage occurs to at least the upper surface portions (surface layers) of the source regions 18a to 18d, including their upper surfaces, destroying the crystalline structure of the 4H-SiC and forming an amorphous structure. Subsequent heat treatment (activation annealing) recrystallizes the amorphous structure, forming 3C-SiC. As a result, the surface layers of the source regions 18a to 18d contain 3C-SiC.

[0080] The proportion of 3C-SiC contained in the surface layers of the source regions 18a to 18d is, for example, approximately 10% or more and 100% or less. The surface layers of the source regions 18a to 18d may be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the surface layers of the source regions 18a to 18d may also contain an amorphous structure, 4H-SiC, etc. By including 3C-SiC in the surface layers of the source regions 18a to 18d, low resistance ohmic contact can be made with the source electrodes (24, 25, 26) on the upper surfaces of the source regions 18a to 18d.

[0081] On the upper surface side of the base regions 17a to 17c, p-type impurity layers having a higher impurity concentration than the base regions 17a to 17c are formed so as to contact the source regions 18a to 18d. ＋ The base contact regions 19a to 19c are p-type semiconductor layers. The base contact regions 19a to 19c have a substantially trapezoidal cross section. The base contact regions 19a to 19c are formed by ion implantation of p-type impurities such as aluminum (Al) or boron (B) from an oblique direction relative to the normal to the top surfaces of the base regions 17a to 17c.

[0082] The depth of the base contact regions 19a to 19c is, for example, about 0.1 μm or more and 0.5 μm or less, and may be about 0.1 μm or more and 0.3 μm or less. The depth of the base contact regions 19a to 19c may be about 0.5 μm or more. The impurity concentration in the range from the top surface of the base contact regions 19a to 19c to a depth of 0.3 μm is, for example, 1×10 １８ / cm ３ That's it, 1 x 10 ２２ / cm ３ It is about 1 × 10 １９ / cm ３ That's it, 1 x 10 ２２ / cm ３ The impurity concentration in the upper surface of the base contact regions 19a to 19c is preferably 1×10 ２０ / cm ３ That's it, 1 x 10 ２２ / cm ３ In the depth direction, which is the direction perpendicular to the upper surfaces of the base contact regions 19a to 19c, the impurity concentration may be uniform within a range from the upper surfaces of the base contact regions 19a to 19c to a depth of 0.3 μm.

[0083] In the depth direction, which is perpendicular to the upper surfaces of the base contact regions 19a to 19c, the impurity concentration in a range of 0.5 μm or more from the upper surfaces of the base contact regions 19a to 19c is lower than the impurity concentration in a range of 0.3 μm from the upper surfaces of the base contact regions 19a to 19c. The impurity concentration in a range of 0.5 μm or more from the upper surfaces of the base contact regions 19a to 19c is, for example, 1×10 １７ / cm ３ It is about the following.

[0084] The base contact regions 19a to 19c are primarily composed of 4H-SiC. During ion implantation to form the base contact regions 19a to 19c, damage occurs to at least the upper surface (surface layer) of the base contact regions 19a to 19c, destroying the crystalline structure of the 4H-SiC and forming an amorphous structure. Subsequent heat treatment (activation annealing) recrystallizes the amorphous structure, forming 3C-SiC. As a result, the surface layers of the base contact regions 19a to 19c contain 3C-SiC.

[0085] The proportion of 3C-SiC contained in the surface layers of the base contact regions 19a-19c is, for example, approximately 10% or more and 100% or less. The surface layers of the base contact regions 19a-19c may be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the surface layers of the base contact regions 19a-19c may also contain an amorphous structure, 4H-SiC, or the like. By including 3C-SiC in the surface layers of the base contact regions 19a-19c, low resistance ohmic contact can be made with the source electrodes (24, 25, 26) on the upper surfaces of the base contact regions 19a-19c.

[0086] Trenches 31a and 31b are provided by digging in the depth direction from the upper surface side of the source regions 18a to 18d. The trenches 31a and 31b penetrate the source regions 18a to 18d and the base regions 17a to 17c and reach the current spreading layer 13. The trenches 31a and 31b may have a planar pattern extending in a stripe shape in the depth and front directions of the paper in FIG. 18, or may have a dotted planar pattern.

[0087] Gate insulating films 20a and 20b are provided on the bottom and side surfaces of the trenches 31a and 31b, respectively. Gate electrodes 21a and 21b are buried inside the trenches 31a and 31b with the gate insulating films 20a and 20b interposed therebetween.

[0088] The gate insulating films 20a and 20b are made of silicon oxide (SiO ２ film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si ３ N ４) film, aluminum oxide (Al ２ O ３ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ２ O ３ ) film, hafnium oxide (HfO ２ ) film, zirconium oxide (ZrO ２ ) film, tantalum oxide (Ta ２ O ５ ) film, bismuth oxide (Bi ２ O ３ The gate electrodes 21 a and 21 b may be made of a single layer of any one of the above films, or a composite film formed by stacking a plurality of these films. The gate electrodes 21 a and 21 b may be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type or n-type impurities, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni).

[0089] In order to protect the gate insulating films 20a and 20b at the bottoms of the trenches 31a and 31b from a high voltage at the time of reverse bias, p ＋ Mold gate bottom protection regions 14a, 14b are provided.

[0090] The base regions 17a to 17c below the base contact regions 19a to 19c have p ＋ The base bottom buried regions (15a, 16a), (15b, 16b), and (15c, 16c) are respectively arranged. The base bottom buried regions (15a, 16a) include a first buried region 15a and a second buried region 16a provided on the upper surface of the first buried region 15a. The base bottom buried regions (15b, 16b) include a first buried region 15b and a second buried region 16b provided on the upper surface of the first buried region 15b. The base bottom buried regions (15c, 16c) include a first buried region 15c and a second buried region 16c provided on the upper surface of the first buried region 15c.

[0091] On the upper surface side of the gate electrodes 21a and 21b, first main electrodes (source electrodes) (24, 25, 26) are provided via interlayer insulating films 22a and 22b. The interlayer insulating films 22a and 22b are made of silicon oxide films (SiO ２A silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), etc. can be used as the interlayer insulating films 22a and 22b. Furthermore, a silicon oxide film doped with phosphorus and boron (BPSG film) or a silicon nitride film (Si ３ N ４ A single layer membrane of the above-mentioned membrane or a composite membrane in which two or more of these membranes are selected and combined can also be used.

[0092] The source electrodes (24, 25, 26) are in ohmic contact with the source regions 18a to 18d and the base contact regions 19a to 19c with low resistance. The source electrodes (24, 25, 26) include a first barrier metal layer 24, a second barrier metal layer 25, and a wiring layer 26. The first barrier metal layer 24 is in contact with the base contact regions 19a to 19c and the source regions 18a to 18d. The second barrier metal layer 25 is provided to cover the first barrier metal layer 24. The wiring layer 26 is provided to cover the second barrier metal layer 25. For example, the first barrier metal layer 24 is made of titanium nitride (TiN), the second barrier metal layer 25 is made of titanium (Ti) / TiN / Ti, and the wiring layer 26 is made of aluminum (Al). The metal material of the portions of the source electrodes (24, 25, 26) in contact with the base contact regions 19a to 19c and the source regions 18a to 18d is, for example, aluminum (Al), an Al alloy, molybdenum (Mo), titanium (Ti), or titanium nitride (TiN).

[0093] The lower surface side of the drift layer 12 is provided with an n-type impurity layer having a higher impurity concentration than the drift layer 12. ＋ A second main electrode region (drain region) 11 is provided on the semiconductor substrate 1. The drain region 11 is made of a substrate (SiC substrate) made of SiC such as 4H—SiC.

[0094] A second main electrode (drain electrode) 27 is disposed on the lower surface side of the drift layer 12 so as to be in contact with the drift layer 12. As the drain electrode 27, for example, a single layer film made of gold (Au) or a metal film laminated in this order of Al, nickel (Ni), and Au can be used, and a metal plate such as molybdenum (Mo) or tungsten (W) may be further laminated on the bottom layer thereof.

[0095] During operation of the silicon carbide semiconductor device according to the fourth embodiment, when a positive voltage is applied to drain electrode 27 and a positive voltage equal to or greater than a threshold value is applied to gate electrodes 21a and 21b, an inversion layer (channel) is formed in base regions 17a to 17c on the gate electrodes 21a and 21b sides, resulting in an ON state. In the ON state, current flows from drain electrode 27 to source electrodes (24, 25, 26) via drain region 11, drift layer 12, inversion layers in base regions 17a to 17c, and source regions 18a to 18d. On the other hand, when the voltage applied to gate electrodes 21a and 21b is less than the threshold value, no inversion layer is formed in base regions 17a to 17c, resulting in an OFF state, and no current flows from drain electrode 27 to source electrodes (24, 25, 26).

[0096] <Method for Manufacturing Silicon Carbide Semiconductor Device> Next, an example of a method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment will be described.

[0097] First, n-type impurities such as nitrogen (N) are added to SiC such as 4H-SiC. ＋ A type semiconductor substrate (SiC substrate) is prepared. The top surface of the SiC substrate may have an off-axis angle of about 4°. The SiC substrate is used as a drain region 11, and an n-type semiconductor substrate made of SiC such as 4H—SiC is formed on the top surface of the drain region 11, as shown in FIG. － A mold drift layer 12 is epitaxially grown.

[0098] Next, n-type impurity ions such as nitrogen (N) are implanted into the entire surface of the drift layer 12 from the upper surface side of the drift layer 12, thereby forming n-type impurity ions made of SiC such as 4H—SiC as shown in FIG. ＋ A mold current diffusion layer 13 is formed on the drift layer 12. The current diffusion layer 13 may be epitaxially grown on the upper surface of the drift layer 12. The current diffusion layer 13 does not necessarily have to be formed, and the following steps may be performed on the drift layer 12.

[0099] 21, first buried regions 15a to 15c and gate bottom protection regions 14a and 14b are formed inside the current diffusion layer 13 by photolithography and ion implantation. Furthermore, second buried regions 16a to 16c are formed on the upper surface sides of the first buried regions 15a to 15c above the current diffusion layer 13 by photolithography and ion implantation.

[0100] Next, as shown in FIG. 22, a p-type base region 17 made of SiC such as 4H—SiC is epitaxially grown on the upper surface of the current spreading layer 13 .

[0101] Next, n ＋ The ion implantation process for forming the source region 18 is performed in two stages. First, in the first ion implantation process, a photoresist film 41 (see FIG. 23) is applied to the base region 17, and the photoresist film 41 is patterned using photolithography. Using the patterned photoresist film 41 as an ion implantation mask, n-type impurities such as N are ion-implanted from an oblique direction inclined at a predetermined angle θ11 with respect to the normal L11 to the top surface of the base region 17, as shown in FIG. 23. As a result, n ＋ The source region 18 of the mold is formed to have a substantially parallelogram cross section. Thereafter, the photoresist film 41 is removed. Note that an oxide film may be used as a mask instead of the photoresist film 41.

[0102] In the first ion implantation, the predetermined angle θ11 is, for example, approximately 30° or more and less than 90°, or may be approximately 45° or more and less than 90°, or may be approximately 60° or more and less than 90°. The acceleration energy of the ion implantation is approximately 300 keV or more and 700 keV or less, or may be approximately 400 keV or more and 700 keV or less. By setting the acceleration energy of the ion implantation to a high acceleration of 300 keV or more, damage can be introduced into the surface layer of the source region 18, destroying the crystalline structure of 4H—SiC and forming an amorphous structure.

[0103] Next, in the second ion implantation step, a photoresist film 42 (see FIG. 24) is applied to the base region 17, and the photoresist film 42 is patterned using photolithography. Using the patterned photoresist film 42 as an ion implantation mask, n-type impurities such as N are ion-implanted from an oblique direction inclined at an angle θ12, which is the same as the predetermined angle θ11, with respect to the normal L11 to the upper surface of the base region 17, on the opposite side from the first ion implantation step, as shown in FIG. 24. As a result, the regions ion-implanted in the first and second times overlap, and n ＋ The source region 18 of the mold is formed to have a substantially trapezoidal cross section. Thereafter, the photoresist film 42 is removed. Note that an oxide film may be used as a mask instead of the photoresist film 42.

[0104] In the second ion implantation, the predetermined angle θ12 is, for example, approximately 30° or more and less than 90°, or may be approximately 45° or more and less than 90°, or may be approximately 60° or more and less than 90°. The acceleration energy of the ion implantation is approximately 300 keV or more and 700 keV or less, or may be approximately 400 keV or more and 700 keV or less. By setting the acceleration energy of the ion implantation to a high acceleration of 300 keV or more, damage can be introduced into the surface layer of the source region 18, destroying the crystalline structure of 4H—SiC and forming an amorphous structure.

[0105] Next, p ＋ Ion implantation to form the base contact regions 19a to 19c is performed in two stages. First, in the first ion implantation step, a photoresist film 43 (see FIG. 25) is applied to the base region 17, and the photoresist film 43 is patterned using photolithography. Using the patterned photoresist film 43 as an ion implantation mask, p-type impurity ions such as Al are implanted from an oblique direction inclined at a predetermined angle θ13 with respect to the normal L11 to the upper surface of the base region 17. As a result, p-type impurity ions such as Al are implanted into the upper surface side of the base region 17. ＋The mold base contact regions 19a to 19c are formed to have a substantially parallelogram cross section. Thereafter, the photoresist film 43 is removed. Note that an oxide film may be used as a mask instead of the photoresist film 43.

[0106] In the first ion implantation, the predetermined angle θ13 is, for example, approximately 30° or more and less than 90°, or may be approximately 45° or more and less than 90°, or may be approximately 60° or more and less than 90°. The acceleration energy of the ion implantation is approximately 300 keV or more and 700 keV or less, or may be approximately 400 keV or more and 700 keV or less. By setting the acceleration energy of the ion implantation to a high acceleration of 300 keV or more, damage can be introduced into the surface layers of the base contact regions 19 a-19 c, destroying the crystalline structure of 4H—SiC and forming an amorphous structure.

[0107] Next, in the second ion implantation step, a photoresist film 44 (see FIG. 26) is applied to the base region 17, and the photoresist film 44 is patterned using photolithography. Using the patterned photoresist film 44 as an ion implantation mask, p-type impurity ions such as Al are implanted from an oblique direction tilted at an angle θ14, which is the same as the predetermined angle θ13, on the opposite side from the first ion implantation step with respect to the normal L11 to the upper surface of the base region 17, as shown in FIG. 26. As a result, the regions implanted in the first and second ions overlap, and p-type impurity ions are implanted on the upper surface side of the base region 17. ＋ The mold base contact regions 19a to 19c are formed to have a substantially trapezoidal cross section. Thereafter, the photoresist film 44 is removed. Note that an oxide film may be used as a mask instead of the photoresist film 44.

[0108] In the second ion implantation, the predetermined angle θ14 is, for example, approximately 30° or more and less than 90°, or may be approximately 45° or more and less than 90°, or may be approximately 60° or more and less than 90°. The acceleration energy of the ion implantation is approximately 300 keV or more and 700 keV or less, or may be approximately 400 keV or more and 700 keV or less. By setting the acceleration energy of the ion implantation to a high acceleration of 300 keV or more, damage can be introduced into the surface layers of the base contact regions 19 a-19 c, destroying the crystalline structure of 4H—SiC and forming an amorphous structure.

[0109] Next, the n-type impurity ions and p-type impurity ions implanted by each ion implantation are activated by heat treatment (activation annealing) at a temperature of, for example, about 1600° C. or higher and 1900° C. or lower. At this time, the amorphous structure of the surface layers of the source region 18 and base contact regions 19 a to 19 c is recrystallized to become 3C—SiC.

[0110] Next, a photoresist film 45 (see FIG. 27) is applied to the source region 18 and the base contact regions 19a-19c, and the photoresist film 45 is patterned using photolithography. Using the patterned photoresist film 45 as an etching mask, trenches 31a, 31b are selectively formed by dry etching such as reactive ion etching (RIE), which penetrates the source regions 18a-18d and the base regions 17a-17c and reaches the current spreading layer 13, as shown in FIG. 27. The photoresist film 45 is then removed. Note that an oxide film may be used as a mask instead of the photoresist film 45.

[0111] Next, as shown in FIG. 28, the bottom and side surfaces of the trenches 31a and 31b, the source region 18, and the p ＋A gate insulating film 20 is formed on the upper surfaces of the mold base contact regions 19a to 19c. Next, a polysilicon layer (doped polysilicon layer) doped with a high concentration of impurities such as N is deposited on the gate insulating film 20 by a method such as CVD. The polysilicon layer is then etched back to fill the trenches 31a and 31b with the gate insulating film 20 interposed therebetween, as shown in FIG. 29, thereby forming gate electrodes 21a and 21b.

[0112] Next, an interlayer insulating film is deposited on the gate electrodes 21a, 21b and the gate insulating film 20 by CVD or the like. A photoresist film 46 (see FIG. 30) is then applied to the interlayer insulating film, and the photoresist film 46 is patterned using photolithography. Using the patterned photoresist film 46 as an etching mask, portions of the interlayer insulating films 22a, 22b and the gate insulating film 20 are selectively removed by dry etching to open contact holes, as shown in FIG. 30. Thereafter, the photoresist film 46 is removed.

[0113] Next, as shown in Fig. 31 , first barrier metal layer 24 and second barrier metal layer 25 are formed by sputtering, vapor deposition, or the like. Next, wiring layer 26 shown in Fig. 18 is formed by sputtering, vapor deposition, or the like. Source electrodes (24, 25, 26) are formed by first barrier metal layer 24, second barrier metal layer 25, and wiring layer 26. Next, drain electrode 27 shown in Fig. 18 is formed on the entire lower surface of drain region 11 by sputtering, vapor deposition, or the like. In this manner, the silicon carbide semiconductor device according to the fourth embodiment is completed.

[0114] In the silicon carbide semiconductor device and its manufacturing method according to the fourth embodiment, ion implantation may be performed in only one of the ion implantation steps for forming base contact regions 19a-19c and for forming source region 18, with an implantation direction at an angle of 30° or more and less than 90° with respect to normal L11 to the upper surface of base region 17, and with an acceleration energy of 300 keV or more. As a result, only one of base contact regions 19a-19c and source regions 18a-18d shown in FIG. 18 may contain 3C-SiC and be in ohmic contact with source electrodes (24, 25, 26) with low resistance.

[0115] Also, n ＋ The ion implantation step for forming the p-type source region 18 may not be performed twice, but only one of the first and second ion implantation steps may be performed. Furthermore, when only one of the first and second ion implantation steps is performed, n-type impurities such as N may be ion-implanted into the entire upper surface of the base region 17 from an oblique direction without using the photoresist films 41 and 42. In this case, the source region 18 is formed over the entire upper part of the base region 17. In addition, the p-type impurity in the surface layer of the source region 18 may be ion-implanted into the entire upper surface of the base region 17 from an oblique direction. ＋ Since damage also occurs in the region where the base contact regions 19a to 19c are formed, in the ion implantation process for forming the base contact regions 19a to 19c, ions may be implanted with an acceleration energy of less than 300 keV from the direction of the normal L11 of the top surface of the base region 17.

[0116] Alternatively, the ion implantation process for forming the base contact regions 19 a to 19 c may be performed only once, rather than twice. In this case, the base contact regions 19 a to 19 c have a substantially parallelogram cross section.

[0117] According to the silicon carbide semiconductor device and its manufacturing method according to the fourth embodiment, as shown in FIGS. 23 and 24 , in the ion implantation step for forming source region 18, n-type impurities are ion-implanted into the upper surface of base region 17 from an oblique direction inclined by a predetermined angle θ11 or θ12 with respect to the normal L11 to the upper surface of base region 17. This allows shallow formation of source region 18 despite high acceleration energy, and damage is introduced into the surface layer of source region 18, forming 3C-SiC, thereby achieving low-resistance ohmic contact between source region 18 and source electrode (24, 25, 26). Therefore, since a silicide layer need not be formed between source region 18 and source electrode (24, 25, 26), there is no concern about surface irregularities of the silicide layer, improving reliability and reducing the man-hours and costs involved in the silicide layer formation process. Furthermore, since the impurity concentration in the surface layer of source region 18 can be increased while damaging the upper surface of source region 18, the process load can be reduced.

[0118] 25 and 26, in the ion implantation process for forming the base contact regions 19a-19c, p-type impurities are ion-implanted into the upper surface of the base region 17 from an oblique direction inclined by predetermined angles θ13 and θ14 with respect to the normal L11 to the upper surface of the base region 17. This allows the base contact regions 19a-19c to be formed shallowly despite high acceleration energy, and damage is introduced into the surface layers of the base contact regions 19a-19c to form 3C-SiC, thereby achieving low-resistance ohmic contact between the base contact regions 19a-19c and the source electrodes (24, 25, 26). Therefore, since a silicide layer need not be formed between the base contact regions 19a-19c and the source electrodes (24, 25, 26), there is no need to worry about unevenness on the surface of the silicide layer, improving reliability and reducing the number of steps and costs required for the process of forming the silicide layer. Furthermore, since the impurity concentration in the surface layer of the base contact regions 19a to 19c can be increased while damaging the upper surface side of the base contact regions 19a to 19c, the process load can be reduced.

[0119] Fifth Embodiment As shown in Fig. 32, a silicon carbide semiconductor device according to a fifth embodiment differs from the silicon carbide semiconductor device according to the fourth embodiment shown in Fig. 18 in that base contact regions 19a to 19c have a substantially parallelogram cross-sectional shape. Other configurations of the silicon carbide semiconductor device according to the fifth embodiment are similar to those of the silicon carbide semiconductor device according to the fourth embodiment, and therefore redundant description will be omitted.

[0120] The method for manufacturing a silicon carbide semiconductor device according to the fifth embodiment differs from the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment in that the ion implantation for forming base contact regions 19a to 19c is not divided into two steps, but only the first ion implantation step shown in FIG. 25 is performed, and the second ion implantation step shown in FIG. 26 is not performed.

[0121] The silicon carbide semiconductor device and method of manufacturing the same in accordance with the fifth embodiment have the same effects as the silicon carbide semiconductor device and method of manufacturing the same in accordance with the fourth embodiment.

[0122] Sixth Embodiment As shown in Fig. 33, a silicon carbide semiconductor device according to a sixth embodiment differs from the silicon carbide semiconductor device according to the fourth embodiment shown in Fig. 18 in that base contact regions 19a-19c have a substantially rectangular cross-sectional shape. Other configurations of the silicon carbide semiconductor device according to the sixth embodiment are similar to those of the silicon carbide semiconductor device according to the fourth embodiment, and therefore redundant description will be omitted.

[0123] The method for manufacturing a silicon carbide semiconductor device according to the sixth embodiment differs from the method for manufacturing a silicon carbide semiconductor device according to the fourth embodiment in that in the two ion implantation steps for forming base contact regions 19a to 19c, the implantation direction is tilted toward the front and back of Figure 33.

[0124] The silicon carbide semiconductor device and method of manufacturing the same in accordance with the sixth embodiment have the same effects as the silicon carbide semiconductor device and method of manufacturing the same in accordance with the fourth embodiment.

[0125] Although the first to sixth embodiments have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0126] For example, although the fourth to sixth embodiments have been described with reference to MOSFETs, they can also be applied to IGBTs. ＋ The n-type source regions 18a to 18d are used as emitter regions, ＋ Instead of the p type drain region 11 ＋ A structure in which a collector region of the type is provided is sufficient. In addition to the IGBT itself, the present invention can also be applied to a reverse conducting IGBT (RC-IGBT) and a reverse blocking insulated gate bipolar transistor (RB-IGBT). Furthermore, although a MOSFET with a trench gate structure has been exemplified, the present invention can also be applied to a MOSFET or IGBT with a planar gate structure.

[0127] Furthermore, the configurations disclosed in the first to sixth embodiments can be combined as appropriate within the scope of not causing any contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description.

[0128] REFERENCE SIGNS LIST 1... cathode region 2... drift layer 3... anode region 4... damage 5... anode electrode (upper electrode) 6... cathode electrode (rear electrode) 7... photoresist film 8... silicide layer 9, 10... photoresist film 11... drain region 12... drift layer 13... current diffusion layer 14a, 14b... gate bottom protection region 17, 17a to 17c... base region 18, 18a to 18d... source region 19a to 19c... base contact region 20a, 20b... gate insulating film 21a, 21b... gate electrode 22a, 22b... interlayer insulating film 24... first barrier metal layer 25... second barrier metal layer 26... wiring layer 27... drain electrode 31a, 31b... trench 41 to 46... photoresist film 100... semiconductor substrate (semiconductor base) 101... active region 102...Terminal area

Claims

1. A semiconductor device comprising: a first semiconductor layer made of silicon carbide of 4H-SiC; a second semiconductor layer provided on an upper surface side of the first semiconductor layer and made of silicon carbide containing 3C-SiC at least on an upper surface thereof; and a main electrode provided on an upper surface side of the second semiconductor layer; １８ / cm ３ or more, and the impurity concentration at a depth of 0.5 μm or more from the top surface of the second semiconductor layer is 1×10 １７ / cm ３ The following is a silicon carbide semiconductor device.

2. The impurity concentration of the upper surface of the second semiconductor layer is 1×10 ２０ / cm ３ The silicon carbide semiconductor device according to claim 1 .

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the second semiconductor layer has a cross-sectional shape of a parallelogram.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein the second semiconductor layer has a trapezoidal cross-sectional shape.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein the first semiconductor layer is n-type and forms a Schottky junction together with the main electrode, and the second semiconductor layer is p-type and forms a pn junction together with the first semiconductor layer.

6. The silicon carbide semiconductor device according to claim 1 or 2, wherein the second semiconductor layer constitutes a p-type base contact region of a MOSFET.

7. The silicon carbide semiconductor device according to claim 1 or 2, wherein the second semiconductor layer constitutes an n-type main electrode region of a MOSFET.

8. The silicon carbide semiconductor device according to claim 1 or 2, wherein a portion of said main electrode in contact with said second semiconductor layer is made of any one of titanium, titanium nitride, aluminum, an aluminum alloy, and molybdenum.

9. A method for manufacturing a silicon carbide semiconductor device, comprising: forming a second semiconductor layer made of silicon carbide containing 3C-SiC on at least an upper surface side of the first semiconductor layer by ion-implanting impurities into an upper surface of a first semiconductor layer made of 4H-SiC silicon carbide at an angle of 30° or more and less than 90° with respect to a normal to the upper surface of the first semiconductor layer; and forming a main electrode on the upper surface side of the second semiconductor layer.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the acceleration energy of the ion implantation is 300 keV or more.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the ion implantation includes: a first ion implantation that performs ion implantation tilted at a first angle of 30° or more and less than 90° with respect to a normal to the top surface of the first semiconductor layer; and a second ion implantation that performs ion implantation that is tilted at a second angle the same as the first angle on a side opposite to the first angle with respect to the normal to the top surface of the first semiconductor layer.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein, when the angle of the ion implantation is inclined toward an off-angle direction of the first semiconductor layer, the angle of the ion implantation is set to be less than an angle parallel to the off-angle direction.

13. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the angle of the ion implantation is inclined in a direction different from the off-angle direction of the first semiconductor layer.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the second semiconductor layer has a planar shape extending in a stripe shape, and an angle of the ion implantation is inclined in the extending direction.

15. A method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the first semiconductor layer is n-type and forms a Schottky junction together with the main electrode, and the second semiconductor layer is p-type and forms a pn junction together with the first semiconductor layer.

16. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the second semiconductor layer constitutes a p-type base contact region of a MOSFET.

17. The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the second semiconductor layer constitutes an n-type main electrode region of a MOSFET.

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