Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device is provided with a silicon carbide substrate having a first main surface and a second main surface. The silicon carbide substrate has a drift region of a first conductivity type, a body region of a second conductivity type on the drift region, a source region of the first conductivity type on the body region, a connection region of the second conductivity type provided in contact with the lower part of the body region, and an electric field relaxation region of the second conductivity type provided in contact with the lower part of the connection region. The substrate is provided with a gate trench provided with a side surface reaching from the first main surface to the drift region, and a bottom surface continuous with the side surface. The substrate has a gate insulating film in contact with the gate trench, and a gate electrode on the gate insulating film. The gate trench extends along a first axis; the connection region is farther from the gate trench than from the body region along a second axis perpendicular to the first axis; the electric field relaxation region is farther from the gate trench than from the connection region along the second axis; and the first thickness of the electric field relaxation region is greater than the second thickness of the connection region.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2023-119164, filed on July 21, 2023, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] As one silicon carbide semiconductor device, a trench MOSFET (metal oxide semiconductor field effect transistor) has been disclosed, in which an electric field relaxation region is provided below a gate trench formed in a main surface.

[0004] Japanese Patent Publication No. 2021-182639 Japanese Patent Publication No. 2019-161200 Japanese Patent Publication No. 2011-253837

[0005] A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region provided on the body region so as to be spaced from the drift region and having the first conductivity type; a connection region provided below the body region and in contact with the body region, the connection region having the second conductivity type; and an electric field relaxation region provided below the connection region and in contact with the connection region, the electric field relaxation region having the second conductivity type. a gate trench having a side surface reaching a lift region and a bottom surface continuous with the side surface, a gate insulating film in contact with the side surface and the bottom surface of the gate trench, and a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate trench and the silicon carbide substrate, the gate trench extending along a first axis parallel to the first main surface, the connection region being farther from the gate trench than the body region along a second axis parallel to the first main surface and perpendicular to the first axis, the electric field relaxation region being farther from the gate trench than the connection region along the second axis, and a first thickness of the electric field relaxation region being greater than a second thickness of the connection region.

[0006] Fig. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Fig. 3 is a schematic view showing the range of a connection region and an electric field relaxation region. Fig. 4 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a second embodiment.

[0007] [Problem to be Solved by the Present Disclosure] In conventional silicon carbide semiconductor devices, it is difficult to ensure the reliability of the gate insulating film while reducing the on-resistance at the same time.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can ensure the reliability of a gate insulating film while reducing on-resistance.

[0009] [Effects of the Present Disclosure] According to the present disclosure, it is possible to ensure the reliability of the gate insulating film and reduce the on-resistance at the same time.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are denoted by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually expressed by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of a silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region provided on the body region to be separated from the drift region and having the first conductivity type; a connection region provided below the body region and in contact with the body region, the connection region having the second conductivity type; and an electric field relaxation region provided below the connection region and in contact with the connection region, the electric field relaxation region having the second conductivity type. a gate trench having a side surface reaching the drift region and a bottom surface continuous with the side surface, a gate insulating film in contact with the side surface and the bottom surface of the gate trench, and a gate electrode provided on the gate insulating film to sandwich the gate insulating film between the gate trench and the silicon carbide substrate, the gate trench extending along a first axis parallel to the first main surface, the connection region being farther from the gate trench than the body region along a second axis parallel to the first main surface and perpendicular to the first axis, the electric field relaxation region being farther from the gate trench than the connection region along the second axis, and a first thickness of the electric field relaxation region being greater than a second thickness of the connection region.

[0013] The connection region is farther from the gate trench than the body region along the second axis, the electric field relaxation region is farther from the gate trench than the connection region along the second axis, and the first thickness of the electric field relaxation region is greater than the second thickness of the connection region. This makes it possible to reduce the on-resistance while mitigating the voltage applied to the gate insulating film. In other words, it is possible to ensure the reliability of the gate insulating film and reduce the on-resistance at the same time.

[0014] [2] In [1], the second thickness may be greater than the third thickness of the body region, which makes it easier to alleviate the voltage applied to the gate insulating film.

[0015] [3] In [1] or [2], the drift region may have a first semiconductor region in contact with the side surface and the body region, and a second semiconductor region provided between the first semiconductor region and the second main surface and in contact with the first semiconductor region, wherein a first effective concentration of the first conductivity type impurity in the first semiconductor region is higher than a second effective concentration of the first conductivity type impurity in the second semiconductor region. In this case, an on-current is likely to flow over a wide range of the drift region, and on-resistance is likely to be reduced.

[0016] [4] In any one of [1] to [3], the lower end surface of the connection region may be closer to the second main surface than the bottom surface. In this case, the voltage applied to the gate insulating film is more easily alleviated.

[0017] [5] In any one of [1] to [4], a plurality of the gate trenches may be provided in the first main surface at a constant first pitch, and in a cross section perpendicular to the first axis, the silicon carbide substrate may have the connection region on both sides of the gate trench, and a distance between the connection regions may be 0.5 times the first pitch or less. In this case, noise during switching operation may be easily reduced.

[0018] [6] In any one of [1] to [5], a third effective concentration of the second conductivity type impurity in the body region may be higher than a fourth effective concentration of the second conductivity type impurity in the connection region, and the fourth effective concentration may be higher than a fifth effective concentration of the second conductivity type impurity in the electric field relaxation region. In this case, the voltage applied to the gate insulating film may be more easily relaxed.

[0019] [7] In any one of [1] to [6], a first depth of the bottom surface relative to the first main surface may be smaller than a second depth of the lower end surface of the electric field relaxation region relative to the bottom surface. In this case, it is easier to relax the voltage applied to the gate insulating film.

[0020] [8] In any of [1] to [7], the silicon carbide substrate may have the electric field relaxation region on both sides of the gate trench in a cross section perpendicular to the first axis, and when a second depth of a lower end surface of the electric field relaxation region relative to the bottom surface is D2, a first width of the electric field relaxation region may be larger than a second width of the drift region between adjacent electric field relaxation regions in an imaginary plane that is deeper than the bottom surface by D2 / 2 in a cross section perpendicular to the first axis. In this case, it is easier to relax the voltage applied to the gate insulating film and to reduce noise during switching operation.

[0021] [9] In any one of [1] to [8], the second depth of the lower end surface of the electric field relaxation region from the bottom surface may be 2 μm or more. In this case, the voltage applied to the gate insulating film is more easily relaxed.

[0022]

[10] In any one of [1] to [9], the conductivity type of the semiconductor between the bottom surface and the second main surface may be the first conductivity type. In this case, the on-resistance is more likely to be reduced.

[0023]

[11] In any one of [1] to

[10] , the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0024] [Embodiments of the Present Disclosure] (First Embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOS field effect transistor (FET) using silicon carbide, and this MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0025] As shown in Figures 1 and 2, the silicon carbide semiconductor device 100 according to the first embodiment mainly has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0026] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0027] The first main surface 1 is a {0001} plane or a {0001} plane tilted at an off angle of 8 degrees or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a (000-1) plane tilted at an off angle of 8 degrees or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 degree or more, or 2 degrees or more. The off angle may be 6 degrees or less, or 4 degrees or less.

[0028] The silicon carbide epitaxial layer 40 mainly includes a drift region 11 , a body region 12 , a source region 13 , a connection region 14 , an electric field reduction region 15 , and a contact region 18 .

[0029] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. Drift region 11 mainly has a first region 11A and a second region 11B.

[0030] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is provided on the drift region 11. For example, the third thickness T3 of the body region 12 is not less than 100 nm and not more than 1000 nm.

[0031] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0032] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first major surface 1. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and a portion of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first major surface 1 and the second major surface 2. In a cross-sectional view perpendicular to the Y axis, an angle θ1 of the side surfaces 3 with respect to an imaginary plane 31 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The Y axis is an example of the first axis, and the X axis is an example of the second axis.

[0033] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.

[0034] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0035] The connection region 14 contains p-type impurities such as aluminum and has p-type conductivity. In a plan view perpendicular to the first main surface 1, the connection region 14 is located between adjacent gate trenches 5 along the X-axis. The connection region 14 is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The connection region 14 is spaced apart from the gate trench 5 along the X-axis relative to the body region 12. The connection region 14 is located below the body region 12 and in contact with the body region 12. In a plan view perpendicular to the first main surface 1, the connection region 14 overlaps the contact region 18. The connection region 14 may be in contact with the body region 12 and the contact region 18. The connection region 14 may extend along the Y-axis. Multiple connection regions 14 are arranged at regular intervals along the X-axis. Multiple connection regions 14 may be arranged in a stripe pattern. For example, the second thickness T2 of the connection region 14 is 100 nm or more and 1000 nm or less. The second thickness T2 of the connection region 14 may be greater than the third thickness T3 of the body region 12 .

[0036] The electric field relaxation region 15 contains p-type impurities such as aluminum and has p-type conductivity. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 15 is located between adjacent gate trenches 5 along the X-axis. The electric field relaxation region 15 is farther from the gate trench 5. The electric field relaxation region 15 is farther from the gate trench 5 along the X-axis than the connection region 14 is. The electric field relaxation region 15 is located below the connection region 14 and is in contact with the connection region 14. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 15 overlaps the contact region 18 and the connection region 14. The electric field relaxation region 15 may extend along the Y-axis. Multiple electric field relaxation regions 15 are arranged at regular intervals along the X-axis. Multiple electric field relaxation regions 15 may be arranged in a striped pattern. For example, the first thickness T1 of the electric field relaxation region 15 may be 1000 nm or more and 5000 nm or less, or may be 1200 nm or more and 2500 nm or less. The first thickness T1 of the electric field relaxation region 15 is greater than the second thickness T2 of the connection region 14. The electric field relaxation region 15 can be formed by, for example, channeling implantation.

[0037] The connection region 14 is located between the field relief region 15 and the body region 12. The contact region 18, the body region 12, the connection region 14 and the field relief region 15 are electrically connected to one another.

[0038] The first region 11A of the drift region 11 is exposed at the side surface 3 and is in contact with the body region 12 and the connection region 14. The thickness of the first region 11A is, for example, 0.1 μm or more and 0.6 μm or less. The second region 11B of the drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The first region 11A is located between the second region 11B and the body region 12. The lower end surface of the first region 11A is in contact with the upper end surface of the second region 11B. The second region 11B may be exposed at the side surface 3. The second region 11B may be exposed at the bottom surface 4. The lower end surface of the first region 11A may be on an imaginary plane 31 including the bottom surface 4, or may be closer to the first main surface 1 than the imaginary plane 31. The first region 11A is an example of a first semiconductor region, and the second region 11B is an example of a second semiconductor region.

[0039] The second effective concentration of the n-type impurity in the second region 11B is lower than the first effective concentration of the n-type impurity in the first region 11A. For example, the second effective concentration is 1×10１６ cm －３ 1x10 or more １７ cm －３ and the first effective concentration is 1×10 １７ cm －３ 1x10 or more １８ cm －３ The first region 11A is sometimes called a current spreading region.

[0040] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type. Along the Z axis, no semiconductor with p-type conductivity exists between bottom surface 4 and second main surface 2. The Z axis is an example of a third axis.

[0041] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the second region 11B at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 contacts the first region 11A and the second region 11B at the side surface 3. As long as the gate insulating film 81 contacts the first region 11A at the side surface 3, it does not have to contact the second region 11B. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0042] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0043] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0044] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged so that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0045] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0046] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0047] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0048] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a part of source electrode 60 may be provided.

[0049] The effective concentration of the p-type impurity in the contact region 18 may be higher than the effective concentration of the p-type impurity in the body region 12. For example, the effective concentration of the p-type impurity in the contact region 18 may be, for example, 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The effective concentration of p-type impurities in the body region 12 is 5×10 １７ cm －３ 1x10 or more １８ cm－３ The following is the result.

[0050] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 １９ cm －３ The effective concentration of the p-type impurity in the connection region 14 and the effective concentration of the p-type impurity in the electric field relaxation region 15 are, for example, 5×10 １７ cm －３ 5x10 or more １８ cm －３ The following is the result.

[0051] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0052] Here, the ranges of the connection region 14 and the electric field relaxation region 15 in the present disclosure will be described. FIG.

[0053] Drift region 11 has n-type conductivity, and body region 12, connection region 14, and electric field relaxation region 15 have p-type conductivity. Therefore, the boundaries between drift region 11 and body region 12, between drift region 11 and connection region 14, and between drift region 11 and electric field relaxation region 15 are clear.

[0054] The top surface 21 of the drift region 11 is in contact with the bottom surface 22 of the body region 12. In the present disclosure, the top surface 23 of the connection region 14 is assumed to be in the same plane as the top surface 21 of the drift region 11. Furthermore, in a region closer to the second main surface 2 than the top surface 23, when the center of an osculating circle 33 tangent to the curves representing the p-type region (connection region 14 or electric field relaxation region 15) and the drift region 11 is moved toward the second main surface in a cross-sectional view perpendicular to the Y axis, the center of the osculating circle 33 moves from the p-type region to the drift region 11 on a plane a certain distance away from the first main surface 1. In the present disclosure, the bottom surface 24 of the connection region 14 and the top surface 25 of the electric field relaxation region 15 are assumed to be located on this plane. The bottom surface 24 of the connection region 14 may be closer to the second main surface 2 than the bottom surface 4. The bottom surface 26 of the electric field relaxation region 15 is the surface facing the silicon carbide single crystal substrate 50.

[0055] In the silicon carbide semiconductor device 100 according to the first embodiment, the connection region 14 is farther from the gate trench 5 than the body region 12 along the X-axis, and the electric field relaxation region 15 is farther from the gate trench 5 than the connection region 14 along the X-axis. Furthermore, the first thickness T1 of the electric field relaxation region 15 is greater than the second thickness T2 of the connection region 14. This reduces the on-resistance while mitigating the voltage applied to the gate insulating film 81. That is, it is possible to ensure the reliability of the gate insulating film 81 and reduce the on-resistance at the same time. Furthermore, excessively widening the current diffusion region to reduce the on-resistance can increase noise during switching operations. However, in this embodiment, the on-resistance can be reduced without widening the first region 11A to the extent that noise during switching operations increases. Therefore, an increase in noise during switching operations can be avoided. Furthermore, forming a source trench between the gate trenches, providing a source electrode in the source trench, and providing a deep well region around the source trench can reduce the drain breakdown voltage. However, in this embodiment, the reduction in drain breakdown voltage associated with the deep well region can be avoided.

[0056] Along the Z axis, if the conductivity type of the semiconductor (silicon carbide substrate 10) between the bottom surface 4 and the second main surface 2 is n-type and there is no semiconductor with p-type conductivity between the bottom surface 4 and the second main surface 2, the on-resistance is more likely to be reduced.

[0057] When the second thickness T2 of the connection region 14 is greater than the third thickness T3 of the body region 12, the voltage applied to the gate insulating film 81 is more easily alleviated.

[0058] When the first effective concentration in the first region 11A of the drift region 11 is higher than the second effective concentration in the second region 11B, the on-current tends to flow over a wide range of the drift region 11, and the on-resistance tends to be reduced.

[0059] When the lower end surface 24 of the connection region 14 is closer to the second main surface 2 than the bottom surface 4 , the voltage applied to the gate insulating film 81 is more easily alleviated.

[0060] The distance L1 between the two connection regions 14 sandwiching the gate trench 5 in a plan view perpendicular to the first main surface 1 may be, for example, 0.5 times or less the first pitch P1. When the distance L1 is 0.5 times or less the first pitch P1, noise during switching operations is easily reduced.

[0061] The third effective concentration of the p-type impurity in the body region 12 may be higher than the fourth effective concentration of the p-type impurity in the connection region 14, and the fourth effective concentration may be higher than the fifth effective concentration of the p-type impurity in the electric field relaxation region 15. When the third effective concentration is higher than the fourth effective concentration and the fourth effective concentration is higher than the fifth effective concentration, the voltage applied to the gate insulating film 81 is more easily relaxed.

[0062] The first depth D1 of the bottom surface 4 relative to the first main surface 1 may be smaller than the second depth D2 of the lower end surface 26 of the electric field relaxation region 15 relative to the bottom surface 4. When the first depth D1 is smaller than the second depth D2, the voltage applied to the gate insulating film 81 is more easily relaxed.

[0063] When the second depth D2 is 2 μm or more, it is easier to reduce the voltage applied to the gate insulating film 81. The second depth D2 may be 2.5 μm or more, or may be 3 μm or more.

[0064] Second Embodiment A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the width of electric field relaxation region 15. Fig. 4 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment.

[0065] 4 , in silicon carbide semiconductor device 200 according to the second embodiment, electric field relaxation region 15 is formed wider than in the first embodiment. More specifically, on imaginary plane 32 that is deeper than bottom surface 4 by half (D2 / 2) of second depth D2, first width W1 of electric field relaxation region 15 is larger than second width W2 of drift region 11 between adjacent electric field relaxation regions 15 in a cross section perpendicular to the Y axis.

[0066] Other configurations of the second embodiment are the same as those of the first embodiment.

[0067] The second embodiment also provides the same effects as the first embodiment. Furthermore, since the first width W1 is larger than the second width W2 in the imaginary plane 32, the voltage applied to the gate insulating film 81 can be more easily alleviated, and noise during switching operations can be more easily reduced.

[0068] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0069] REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 11A First region 11B Second region 12 Body region 13 Source region 14 Connection region 15 Electric field relaxation region 18 Contact region 21, 23, 25 Upper end surface 22, 24, 26 Lower end surface 31, 32 Virtual plane 33 Oscillating circle 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 90 Contact hole 100, 200 Silicon carbide semiconductor device D1 First depth D2 Second depth L1 Distance P1 First pitch T1 First thickness T2 Second thickness T3 Third thickness W1 First width W2 Second width θ1 Angle

Claims

a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; a connection region having the second conductivity type and provided below the body region; and an electric field relief region having the second conductivity type and provided below the connection region; a gate trench having a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface; a gate insulating film in contact with the side surface and the bottom surface of the gate trench; and a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate trench and the silicon carbide substrate, the gate trench extending along a first axis parallel to the first main surface, a first thickness of the electric field relaxation region that is greater than a second thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the first thickness being greater than a second thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the second thickness being greater than a first thickness of the connection region, the third thickness being greater than a second thickness of the connection region, the third thickness being greater than a first thickness of the connection region, the second thickness being greater than a first ...

2. The silicon carbide semiconductor device according to claim 1, wherein said second thickness is greater than a third thickness of said body region.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the drift region has: a first semiconductor region in contact with the side surface and the body region; and a second semiconductor region provided between the first semiconductor region and the second main surface and in contact with the first semiconductor region, and a first effective concentration of the first conductivity type impurity in the first semiconductor region is higher than a second effective concentration of the first conductivity type impurity in the second semiconductor region.

4. The silicon carbide semiconductor device according to claim 1, wherein a lower end surface of said connection region is closer to said second main surface than said bottom surface.

5. A silicon carbide semiconductor device according to any one of claims 1 to 4, wherein a plurality of the gate trenches are provided on the first main surface at a constant first pitch, and in a cross-sectional view perpendicular to the first axis, the silicon carbide substrate has the connection regions on both sides of the gate trenches, and the distance between the connection regions is 0.5 times the first pitch or less.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein a third effective concentration of the second conductivity type impurity in the body region is higher than a fourth effective concentration of the second conductivity type impurity in the connection region, and the fourth effective concentration is higher than a fifth effective concentration of the second conductivity type impurity in the electric field relaxation region.

7. A silicon carbide semiconductor device according to any one of claims 1 to 6, wherein a first depth of the bottom surface relative to the first main surface is smaller than a second depth of the lower end surface of the electric field relaxation region relative to the bottom surface.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein, in a cross-sectional view perpendicular to the first axis, the silicon carbide substrate has the electric field relaxation region on both sides of the gate trench, and when a second depth of a lower end surface of the electric field relaxation region with respect to the bottom surface is D2, in an imaginary plane deeper by D2 / 2 from the bottom surface, in a cross-sectional view perpendicular to the first axis, a first width of the electric field relaxation region is larger than a second width of the drift region between adjacent ones of the electric field relaxation regions.

9. The silicon carbide semiconductor device according to claim 1, wherein a second depth of the lower end surface of the electric field relaxation region with respect to the bottom surface is equal to or greater than 2 μm.

10. The silicon carbide semiconductor device according to claim 1, wherein the conductivity type of a semiconductor between said bottom surface and said second main surface is said first conductivity type.

11. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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