Pll circuit, integrated circuit, and electronic apparatus

Abstract

The present invention is provided with: a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on an output clock signal; a conversion circuit that outputs a current corresponding to the phase difference; a smoothing circuit that smooths the output of the conversion circuit and outputs the smoothed output as a control voltage; a correction signal generation circuit that generates a correction signal corresponding to the fluctuation of the control voltage on the basis of the control voltage; and a voltage control oscillation circuit that outputs, as the output clock signal, a clock signal of a frequency corresponding to the control voltage and the correction signal. The correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in a direction opposite to the fluctuation of the control voltage with respect to the factor of the fluctuation of the control voltage.

Description

PLL circuit, integrated circuit and electronic device

[0001] The present disclosure relates to a PLL circuit, an integrated circuit, and an electronic device.

[0002] In recent years, data traffic has increased dramatically due to the increasing volume of image data and faster communication speeds, and this has created a demand for faster interface circuits that control data transfer. For example, circuits that make up high-speed interfaces require high-speed signal processing technology that enables data processing at several tens of Gbps (Giga bit-per-second).

[0003] On the other hand, in recent years, design rules for semiconductor integrated circuits have become finer, and as a result, variations in the threshold voltage of transistors and other parameters caused by the semiconductor manufacturing process have tended to increase. Generally, interface circuits generate reference clock signals using a PLL (Phase Locked Loop) circuit, and as variations in the threshold voltage of these transistors increase, variations in the jitter value of the output clock signal from the PLL circuit also increase.

[0004] Japanese Patent Application Laid-Open No. 2008-124687

[0005] Jitter in a PLL circuit directly affects data transfer via the interface circuit. In particular, in the above-mentioned high-speed data transfer of several tens of Gbps, the variation in jitter value for each PLL circuit accounts for a large proportion of the jitter tolerance of the circuit. Therefore, in high-speed data transfer, for example, there is a risk that the jitter value will vary depending on whether it satisfies the jitter tolerance for each integrated circuit including an interface circuit using the PLL circuit.

[0006] Therefore, an object of the present disclosure is to provide a PLL circuit, an integrated circuit, and an electronic device that are capable of suppressing jitter for each PLL circuit.

[0007] The PLL circuit according to the present disclosure comprises a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on an output clock signal, a conversion circuit that outputs a current corresponding to the phase difference, a smoothing circuit that smooths the output of the conversion circuit and outputs it as a control voltage, a correction signal generation circuit that generates a correction signal based on the control voltage in accordance with fluctuations in the control voltage, and a voltage-controlled oscillation circuit that outputs a clock signal having a frequency corresponding to the control voltage and the correction signal as the output clock signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in the opposite direction to fluctuations in the control voltage in response to factors that cause fluctuations in the control voltage.

[0008] FIG. 1 is a block diagram showing a schematic configuration example of a PLL circuit according to existing technology. FIG. 2 is a block diagram showing the configuration of an example of a PLL circuit according to an embodiment. FIG. 3 is a block diagram showing the configuration of an example of a frequency slope trimming circuit according to an embodiment. FIG. 4 is a schematic diagram for explaining a frequency slope correction signal generated by the frequency slope trimming circuit according to an embodiment. FIG. 5 is a schematic diagram for explaining characteristic variations in a VCO depending on fluctuation factors. FIG. 6 is a circuit diagram of an example of a frequency trimming circuit and a VCO according to a first embodiment. FIG. 7 is a schematic diagram for explaining suppression of variations depending on fluctuation factors by a frequency slope correction signal according to the first embodiment. FIG. 8 is a schematic diagram for explaining a resistive element applicable to the first embodiment. FIG. 9 is a schematic diagram for explaining the temperature variation rate of a ring oscillator applied to the first embodiment. FIG. 10 is a schematic diagram showing a more specific configuration example of the frequency slope correction circuit according to the first embodiment. FIG. 11 is a block diagram showing the configuration of an example of a trimming control circuit applicable to the first embodiment. FIG. 12 is a graph showing an example of variations due to fluctuation factors when the frequency slope trimming circuit according to the first embodiment is not used. FIG. 13 is a graph showing an example of variations due to fluctuation factors when the frequency slope trimming circuit according to the first embodiment is used. FIG. 1 is a schematic diagram showing an example of a layout on a substrate of a PLL circuit according to a first embodiment. FIG. 2 is a circuit diagram of an example of a frequency gradient trimming circuit and a VCO according to a modified example of the first embodiment. FIG. 3 is a circuit diagram of an example of a frequency gradient trimming circuit and a VCO according to a second embodiment. FIG. 4 is a block diagram showing a configuration of an example of an electronic device applicable to each embodiment and modified examples thereof of the present disclosure. FIG. 5 is a block diagram showing a configuration of an example of an image sensor applicable to the embodiments.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and redundant description will be omitted.

[0010] Hereinafter, embodiments of the present disclosure will be described in the following order: 1. Regarding existing technology 2. Overview of embodiments according to the present disclosure 3. First embodiment of the present disclosure 3-1. Configuration according to the first embodiment 3-1-1. Specific example of frequency gradient correction circuit according to the first embodiment 3-1-2. Effects according to the first embodiment 3-1-3. Layout example of PLL circuit according to the first embodiment 3-2. Modification of the first embodiment 4. Second embodiment of the present disclosure 4-1. Configuration according to the second embodiment 4-2. Modification of the second embodiment 5. Third embodiment of the present disclosure

[0011] The present disclosure relates to a technique for suppressing jitter in a PLL (Phase Locked Loop) circuit. In particular, the present disclosure relates to suppressing jitter in an output clock signal associated with fluctuations in oscillation frequency due to temperature and other fluctuation factors in a VCO (Voltage-Controlled Oscillator) used in the PLL circuit. The PLL circuit according to the present disclosure is not particularly limited in its application, but is suitable for use in, for example, an interface circuit for transferring high-frame-rate and high-resolution image data.

[0012] (1. Regarding Existing Technology) Prior to describing the embodiments of the present disclosure, a PLL circuit based on existing technology will be briefly described to facilitate understanding. Fig. 1 is a block diagram showing a schematic configuration example of a PLL circuit based on existing technology.

[0013] In FIG. 1, the PLL circuit 1000 includes a frequency / phase comparison circuit 10 , a charge pump 11 , an LPF (low-pass filter) 12 , a VCO 13 , a buffer 14 , and a frequency divider circuit 15 .

[0014] The frequency phase comparator circuit 10 receives the reference clock signal REFCLK and the feedback clock signal FBCLK output from the frequency divider circuit 15. The frequency phase comparator circuit 10 compares the input reference clock signal REFCLK with the feedback clock signal FBCLK to detect the phase difference between them. The charge pump 11 outputs a current corresponding to the phase difference detected by the frequency phase comparator circuit 10. The LPF 12 smoothes the current output from the charge pump 11 and generates a control voltage V C Generate.

[0015] The VCO 13 controls the control voltage V generated by the LPF 12. C The clock signal generated by the VCO 13 is output to the outside of the PLL circuit 1000 as an output clock signal CKOUT via a buffer 14. The output clock signal CKOUT is also input to a frequency divider circuit 15. The frequency divider circuit 15 divides the input output clock signal CKOUT by a predetermined division ratio to generate a feedback clock signal FBCLK.

[0016] The PLL circuit 1000 described above is often configured within a single semiconductor integrated circuit or is incorporated into a single semiconductor integrated circuit. In recent years, as design rules for semiconductor integrated circuits have become finer, there has been a tendency for variations in the threshold voltage of transistors due to manufacturing processes to increase, which has resulted in an increase in variations in the jitter value of the output clock signal CKOUT of the PLL circuit 1000.

[0017] The jitter of the output clock signal CKOUT of the PLL circuit 1000 directly affects the connectivity of the interface for data transfer. In particular, in the communication standards for high-speed communication of, for example, several tens of Gbps (Giga bit-per-second) for transferring image data with a high frame rate and high resolution, as described above, the ratio of the variation in jitter value to the jitter specification increases, and whether the jitter value satisfies the jitter specification may differ for each semiconductor integrated circuit, such as an LSI (Large Scale Integration).

[0018] Therefore, suppressing variations in jitter in the output clock signal CKOUT of the PLL circuit is important in order to ensure stable connectivity of the high-speed interface.

[0019] In Patent Document 1, a feedback loop for controlling the gain of VCO 13 and buffer 14, and a feedback loop for controlling the offset of VCO 13 are provided to suppress variations in jitter in the output clock signal CKOUT of the PLL circuit. However, the configuration of Patent Document 1 uses two loops in addition to the loop that feeds back the output clock signal CKOUT to frequency phase comparison circuit 10, which may make it difficult to ensure stability.

[0020] Furthermore, in the configuration of Patent Document 1, in each feedback loop, a circuit for controlling gain and a circuit for controlling offset are operated by a clock signal. In this way, if a large number of circuits that operate by a clock signal are included, power consumption increases, which may make it difficult to reduce power consumption.

[0021] 2. Overview of an embodiment of the present disclosure Next, an overview of an embodiment of the present disclosure will be described. Fig. 2 is a block diagram showing an example of a configuration of a PLL circuit according to an embodiment.

[0022] 2, the PLL circuit 1 according to the embodiment is configured by adding a frequency gradient trimming circuit 20 to the PLL circuit 1000 according to the existing technology shown in FIG. C is supplied to the VCO 13 and also to the frequency slope trimming circuit 20. The frequency slope trimming circuit 20 controls the control voltage V C The frequency slope trimming circuit 20 generates a frequency slope correction signal for correcting fluctuations in the oscillation frequency of the VCO 13 due to fluctuation factors based on the above. The frequency slope correction signal generated by the frequency slope trimming circuit 20 is supplied to the VCO 13.

[0023] The VCO 13 receives the control voltage V Cand the frequency gradient correction signal supplied from the frequency gradient trimming circuit 20. The clock signal generated by the VCO 13 is output to the outside of the PLL circuit 1 as an output clock signal CKOUT via a buffer 14, and is also supplied to a frequency divider circuit 15 and supplied to the frequency phase comparator circuit 10 as a feedback clock signal FBCLK.

[0024] 3 is a block diagram showing an example of the configuration of the frequency gradient trimming circuit 20 according to the embodiment. The frequency gradient trimming circuit 20 includes a current conversion unit 200 and a frequency gradient correction unit 201.

[0025] Control voltage V C is supplied to the frequency gradient trimming circuit 20 and input to the current conversion unit 200. The current conversion unit 200 converts the input control voltage V C is converted into a current and output as a frequency gradient correction signal.

[0026] 3, the frequency slope correction unit 201 includes a plurality of resistance elements 202, 202, 202, ... connected in parallel, and switch circuits 203, 203, 203, ... connected in series to the resistance elements 202, 202, 202, .... With this configuration, the frequency slope correction unit 201 can use one of the resistance elements 201, 201, 201, ... alone, or can use a plurality of arbitrarily selected resistance elements connected in parallel.

[0027] The current conversion unit 200 is connected to a low potential, for example, a ground potential, via the frequency slope correction unit 201. A specific example of the current conversion unit 200 will be described later, but the current conversion unit 200 controls the frequency slope correction signal in accordance with a voltage drop due to the resistance of the frequency slope correction unit 201. In other words, the frequency slope correction signal may be controlled in accordance with a combination of resistance elements 202, 202, 202, ... in the frequency slope correction unit 201.

[0028] In the following description, when there is no need to distinguish between the resistance elements 202 1 , 202 2 , 202 3 , . . . , they may be collectively referred to as the resistance element 202.

[0029] FIG. 4 is a schematic diagram for explaining the frequency slope correction signal generated by the frequency slope trimming circuit 20 according to the embodiment.

[0030] The oscillation frequency F of VCO 13 has a positive characteristic in response to a fluctuation factor, as shown by characteristic line 81. That is, the oscillation frequency F of VCO 13 fluctuates in a positive direction in response to a positive fluctuation in the fluctuation factor. On the other hand, the frequency slope correction signal generated by frequency slope trimming circuit 20 has a negative characteristic in response to a fluctuation factor, fluctuating in the opposite direction to the fluctuation in the fluctuation factor, as shown by characteristic line 80. That is, the frequency slope correction signal generated by frequency slope trimming circuit 20 has a negative current fluctuation in response to a positive fluctuation in the fluctuation factor.

[0031] More specifically, when the fluctuation factor is temperature, the higher the temperature (positive characteristic fluctuation) of the VCO 13, the higher the oscillation frequency F (positive fluctuation). In contrast, the higher the temperature of the frequency gradient trimming circuit 20 (positive characteristic fluctuation), the smaller the current (I) of the frequency gradient correction signal (negative fluctuation).

[0032] In this way, the frequency slope trimming circuit 20 adjusts the control voltage V C The control voltage V C The compensation signal generating circuit generates a compensation signal using a plurality of resistance elements whose characteristics fluctuate in the opposite direction to the fluctuation of the resistance.

[0033] In the VCO 13, the control voltage V C is converted into a current and combined with the frequency gradient correction signal. C The fluctuations caused by the fluctuation factors of the control voltage V can be offset by the characteristics of the frequency gradient correction signal. C By controlling the oscillation frequency of the VCO 13 based on a signal obtained by combining the current obtained by converting the above and the frequency gradient correction signal, it is possible to suppress fluctuations in the oscillation frequency F in the VCO 13 due to fluctuation factors.

[0034] 5 is a schematic diagram for explaining the characteristic variations in the VCO 13 depending on the fluctuation factors. In FIG. 5, the horizontal axis represents the control voltage VC The vertical axis represents the frequency of the output clock signal CKOUT. A characteristic line 82 shows an example of the characteristics of the VCO 13 in an ideal state without fluctuations. In the example shown in the figure, the VCO 13 operates in response to a control voltage V C and the output clock signal CKOUT are shown as being linear.

[0035] In contrast, characteristic lines 83a and 83b show an example of the temperature-dependent variation in the characteristics of the VCO 13. The VCO 13 varies the control voltage V C The slope of the line showing the relationship between the control voltage V C The ratio of the change in frequency of the output clock signal CKOUT to the change in the control voltage V ... C You will need to enter:

[0036] 5, characteristic lines 84a and 84b show an example of the variation in characteristics due to the manufacturing process of the VCO 13. The VCO 13 varies in control voltage V according to differences in the structure of each element, such as wiring width, due to the manufacturing process. C The slope of the line showing the relationship between the control voltage V C The ratio of the change in frequency of the output clock signal CKOUT to the change in VCO frequency will differ from that shown by the characteristic line 82 in an ideal state. This difference in ratio will appear as variations due to fluctuations in the manufacturing process. In this case, in order for the VCO 13 to output an output clock signal CKOUT of a certain frequency, an appropriate control voltage V C You will need to enter:

[0037] In the embodiment, the control voltage V C The frequency gradient correction signal is synthesized with the converted current, and the control voltage VC The slope of the line showing the relationship between the control voltage V C The ratio of the change in frequency of the output clock signal CKOUT to the change in frequency of the output clock signal CKOUT is controlled to a target value, that is, the ratio according to the characteristics shown by the characteristic line 82, thereby suppressing jitter in the output clock signal CKOUT.

[0038] As described above, the PLL circuit 1 according to the embodiment of the present disclosure makes it possible to suppress jitter caused by fluctuations without using multiple loops. Therefore, by applying the PLL circuit 1 according to the embodiment of the present disclosure, it becomes possible to supply a higher quality and more stable clock signal with a simple configuration. Furthermore, since a control circuit that operates in accordance with the clock signal is not required within the PLL circuit 1, low power consumption is possible, making the PLL circuit suitable for application to mobile devices, for example.

[0039] 3. First Embodiment of the Present Disclosure Next, a first embodiment of the present disclosure will be described. The first embodiment is an example in which diffused resistors are used as the above-described resistor elements 202 1 , 202 2 , 202 3 , . . .

[0040] (3-1. Configuration According to First Embodiment) The configuration according to the first embodiment will be described below. Fig. 6 is a circuit diagram of an example of the frequency gradient trimming circuit 20 and the VCO 13 according to the first embodiment.

[0041] 6, frequency gradient trimming circuit 20a includes operational amplifier 210, P-type transistors 211 and 212, frequency gradient correction unit 201a, and trimming control circuit 220. VCO 13a includes P-type transistors 130 and 131, P-type or N-type transistor 132, and ring oscillator circuit 133 consisting of three inverter circuits. Note that the power supply path of operational amplifier 210 is omitted in FIG. 6.

[0042] In the frequency gradient trimming circuit 20a, a control voltage V CThe output terminal of the operational amplifier 210 is connected to the gates of the transistors 211 and 212. The sources of the transistors 211 and 212 are connected to the power supply lines V cc The drain of the transistor 211 is connected to the non-inverting input of the operational amplifier 210 and to one end of the frequency slope correction unit 201a. The other end of the frequency slope correction unit 201a is connected to, for example, ground potential. The drain of the transistor 212 is connected to the gate of the transistor 132 in the VCO 13a.

[0043] In the frequency slope trimming circuit 20a, an operational amplifier 210 and a transistor 211 are connected to a control voltage V C , the current I output from the drain of the transistor 211 DR In addition, a current mirror circuit is formed by the operational amplifier 210, the transistor 211, and the transistor 212. As a result, the current I output from the drain of the transistor 211 is DR is replicated and output from the drain of transistor 212 as a frequency slope correction signal.

[0044] The frequency slope correction unit 201a is obtained by replacing the resistance elements 202, 202, 202, ... in the frequency slope correction unit 201 shown in Fig. 3 with diffused resistors 202DR, 202DR, 202DR, .... Specific examples will be described later, but diffused resistors generally have the property that their resistance value increases as the temperature rises.

[0045] 6, the frequency slope correction unit 201a includes a plurality of diffused resistors 202DR, 202DR, 202DR, ... connected in parallel, and switch circuits 203, 203, 203, ... connected in series to the diffused resistors 202DR, 202DR, 202DR, .... With this configuration, the frequency slope correction unit 201a can use one of the diffused resistors 202DR, 202DR, 202DR, ... alone, or can use a plurality of arbitrarily selected resistance elements connected in parallel.

[0046] The trimming control circuit 220 controls the on / off state of each of the switch circuits 203, 203, 203, .... The trimming control circuit 220 may control the on / off state of each of the switch circuits 203, 203, 203, ... in response to an external instruction, or may control the on / off state in accordance with information stored in advance in a register or a ROM (Read Only Memory). Furthermore, the on / off state of each of the switch circuits 203, 203, 203, ... may be set in advance by hardware in the trimming control circuit 220.

[0047] In the frequency gradient correction unit 201a, the diffused resistors 202DR1, 202DR2, 202DR3, ... may have different characteristics from one another. A more specific configuration of the frequency gradient correction unit 201a will be described later.

[0048] In the VCO 13a, the source of the transistor 130 is connected to the power supply line V cc and its drain is connected to a ground potential via one and the other of the source and drain of the transistor 132. The transistor 132 functions as a current converter that controls the current flowing from one of the source and drain to the other in accordance with the voltage input to the gate.

[0049] The gate of the transistor 130 is connected to the drain of the transistor 130 and also to the gate of the transistor 131. In this way, the transistors 130 and 131 form a current mirror circuit. As a result, the current output from the drain of the transistor 130 is replicated and output from the drain of the transistor 131. Therefore, the current value of the current output from the drain of the transistor 131 is equal to the control voltage V C The value depends on the

[0050] The source of the transistor 131 is connected to the power supply line V cc 6, the drain of the transistor 212 in the frequency gradient trimming circuit 20a is connected to the connection point where the drain of the transistor 131 and the ring oscillator circuit 133 are connected.DR is replicated and output from the drain of the transistor 212, and the frequency slope correction signal is combined with the current output from the drain of the transistor 131, resulting in a control current I C The ring oscillator circuit 133 receives the control current I C The oscillator will oscillate at a frequency that corresponds to the current value.

[0051] The oscillation signal generated by the ring oscillator circuit 133 is output from the VCO 13a as the output clock signal CKOUT.

[0052] FIG. 7 is a schematic diagram for explaining suppression of variations according to fluctuation factors by a frequency gradient correction signal according to the first embodiment.

[0053] In FIG. 7, a chart 91 corresponds to the characteristics of the frequency slope trimming circuit 20 in FIG. 4, and shows the current I DR The graph shows the characteristics of the current I in the frequency slope trimming circuit 20a with respect to the fluctuation factors. DR The characteristic of the frequency gradient correction signal generated by the frequency gradient trimming circuit 20a with respect to the fluctuation factors is a negative characteristic, as shown by the characteristic line 85. Therefore, the characteristic of the frequency gradient correction signal generated by the frequency gradient trimming circuit 20a with respect to the fluctuation factors is also a negative characteristic.

[0054] 7, chart 92 corresponds to the characteristics of VCO 13 in FIG. 4 and schematically shows the characteristics of the oscillation frequency (referred to as VCO frequency) of VCO 13a in ring oscillator circuit 133 with respect to fluctuation factors. The characteristics of the oscillation frequency of ring oscillator circuit 133 with respect to fluctuation factors are positive, as shown by characteristic line 86.

[0055] In FIG. 7, a chart 93 shows the control current I C9A and 9B show a schematic diagram illustrating the characteristics of output clock signal CKOUT with respect to fluctuation factors in response to the fluctuation factors. As shown by characteristic line 87 in chart 93, the fluctuation of output clock signal CKOUT with respect to fluctuation factors is suppressed compared to the oscillation frequency of ring oscillator circuit 133 shown by characteristic line 86 in chart 92. That is, the fluctuation of output clock signal CKOUT with respect to fluctuation factors is suppressed relative to the fluctuation of the oscillation frequency of ring oscillator circuit 133 with respect to fluctuation factors.

[0056] As mentioned above, the control current I C is a signal obtained by combining the frequency slope correction signal with the current output from the drain of the transistor 131 in the VCO 13 a. The positive characteristic of the ring oscillator circuit 133 with respect to the fluctuation factors, shown by the characteristic line 86 in chart 92, is canceled out by the negative characteristic of the frequency slope correction signal with respect to the fluctuation factors, shown by the characteristic line 85 in chart 91, thereby suppressing the variation of the output clock signal CKOUT with respect to the fluctuation factors.

[0057] (3-1-1. Specific Example of Frequency Gradient Correction Circuit According to First Embodiment) A more specific example of the configuration of the frequency gradient correction unit 201a according to the first embodiment will be described.

[0058] FIG. 8 is a schematic diagram for explaining a resistive element 202 applicable to the first embodiment. As described above, in the first embodiment, a diffused resistor is used as the resistive element 202. Several types of diffused resistors are known, each with different characteristics depending on parameters such as impurity concentration. In the example of FIG. 8, three types of diffused resistors, called NOD diffused resistors, POD diffused resistors, and NW diffused resistors, are shown. These NOD diffused resistors, POD diffused resistors, and NW diffused resistors have different temperature coefficients of resistance, for example.

[0059] In the example of Fig. 8, the ratio of the resistance values ​​(temperature variation rate) at temperatures of -30°C and 95°C is 21.3% for the NOD diffused resistor, 14.0% for the POD diffused resistor, and 28.1% for the NW diffused resistor. That is, the higher the temperature, the higher the resistance value of the NOD diffused resistor, the POD diffused resistor, and the NW diffused resistor. This is because the higher the temperature, the lower the current I DR This means that the current value of

[0060] In FIG. 8, the POLY resistor is a resistive element made of polysilicon, and the temperature variation rate of the resistance value at temperatures of −30° C. and 95° C. is 2.6%, which is smaller than that of the diffused resistor.

[0061] 9 is a schematic diagram illustrating the temperature variation rate of the ring oscillator circuit 133 applied to the first embodiment. In FIG. 9 , section (a) shows an example of the temperature characteristic of the current consumption of the ring oscillator circuit 133. In this example, when the ring oscillator circuit 133 outputs a signal with a frequency of 4.8 GHz, the current consumption is 3.615 mA at −30° C. and 2.822 mA at 95° C. In other words, in this example, as shown in section (b) of FIG. 9 , the temperature variation rate of the ring oscillator circuit 133 at −30° C. and 95° C. is −21.9%, which is a variation in the opposite direction to the temperature variation rate of each diffused resistor shown in FIG. 8 .

[0062] Here, the ring oscillator circuit 133 receives a control current I C The oscillation frequency is controlled by the control current I C When there is no frequency gradient correction signal, the control voltage V output from the LPF 12 is C Therefore, for example, the control current I C If is a constant value, the oscillation frequency of the ring oscillator circuit 133 will vary in accordance with temperature fluctuations, and for example, the lower the temperature, the lower the oscillation frequency will be.

[0063] In the PLL circuit 1 according to the first embodiment, the frequency gradient trimming circuit 20a uses a resistor element whose characteristics fluctuate in the opposite direction to the direction of fluctuation caused by a fluctuation factor of the oscillation frequency in the ring oscillator circuit 133 to generate a correction signal (frequency gradient correction signal) capable of offsetting fluctuation caused by the fluctuation factor of the oscillation frequency. This correction signal controls the control current I C In this way, the PLL circuit 1 according to the first embodiment suppresses jitter in the output clock signal CKOUT from the ring oscillator circuit 133, that is, the VCO 13a.

[0064] 10 is a schematic diagram showing a more specific example of the configuration of the frequency slope correction unit 201a according to the first embodiment. In the example of FIG. 8, the frequency slope correction circuit 201a includes 16 resistor elements connected in parallel. More specifically, the frequency slope correction circuit 201a includes four resistor elements connected in parallel, and resistor element groups 204a, 204b, 204c, and 204d connected in parallel. The resistor element group 204a includes four POLY resistors 202PL connected in parallel. Furthermore, the resistor element group 204b includes four diffused resistors 202DRb connected in parallel, the resistor element group 204c includes four diffused resistors 202DRc connected in parallel, and the resistor element group 204d includes four diffused resistors 202DRd connected in parallel.

[0065] Each POLY resistor 202PL and each diffusion resistor 202DRb, 202DRc, and 202DRd are connected in series with switch circuits 203a, 203b, 203c, and 203d, respectively.

[0066] Each of the resistor element groups 204b, 204c, and 204d may have a different type of diffused resistor. For example, the four diffused resistors 202DRb included in the resistor element group 204b may each be a NOD diffused resistor, the four diffused resistors 202DRc included in the resistor element group 204c may each be a POD diffused resistor, and the four diffused resistors 202DRd included in the resistor element group 204d may each be a NW diffused resistor.

[0067] Furthermore, the four resistors 202PL included in the resistor group 204a, the four diffused resistors 202DRb included in the resistor group 204b, the four diffused resistors 202DRc included in the resistor group 204c, and the four diffused resistors 202DRd included in the resistor group 204d may have different resistance values ​​or may all have the same resistance value. That is, the combination of resistance values ​​of the resistors included in each of the resistor groups 204a, 204b, 204c, and 204d is not particularly limited. Furthermore, the number of resistors included in the frequency slope correction unit 201a is not limited to 16 as shown in FIG. 10, but may be 17 or more, or may be less than 16.

[0068] Hereinafter, when there is no need to particularly distinguish between the resistance elements 202PL, 202DRb, 202DRc, and 202DRd, they may be collectively referred to as resistance element 202. Similarly, when there is no need to particularly distinguish between the switch circuits 203a to 203d, they may be collectively referred to as switch circuit 203.

[0069] The frequency slope trimming circuit 20a generates a frequency slope correction signal by using one of the multiple resistor elements 202 included in the frequency slope correction unit 201a alone or by combining two or more resistor elements 202 under the control of the trimming control circuit 220. At this time, it is preferable that the frequency slope trimming circuit 20a generates the frequency slope correction signal so as to cancel out fluctuations due to fluctuation factors of the VCO 13a (ring oscillator circuit 133).

[0070] 9, the temperature coefficient of variation of the current consumption of the ring oscillator circuit 133 is −21.9%. In contrast to this, in the example of FIG. 8, the temperature coefficient of variation of the resistance value of the NOD diffused resistor is 21.3%, so one or more diffused resistors 202DRb may be selected from the resistor element group 204b that includes four NOD diffused resistors. In this case, the number of diffused resistors 202DRb to be selected is determined so that the combined resistance value of the selected diffused resistors 202DRb becomes a desired value.

[0071] 11 is a block diagram showing an example of the configuration of a trimming control circuit 220 applicable to the first embodiment. In FIG. 11, the trimming control circuit 220 includes an ON / OFF control circuit 221, a look-up table (LUT) 222, and a memory 223.

[0072] The LUT 222 is, for example, a ROM, and stores each of the resistance elements 202 included in the frequency slope correction unit 201a, a fluctuation rate due to a fluctuation factor (for example, temperature) when the resistance elements 202 are combined, and a combined resistance value, in association with information indicating the on / off state of each switch circuit 203. The on / off control circuit 221 refers to the LUT 222 in response to, for example, a combination control signal input from the outside, acquires information indicating the on / off state of each switch circuit 203 from the LUT 222, and writes the acquired information to, for example, a non-volatile memory, the memory 223. The on / off control circuit 221 controls the on / off state of each switch circuit 203 in accordance with the information indicating the on / off state of each switch circuit 203 read from the memory 223.

[0073] The combination control signal may be information indicating a fluctuation rate due to a fluctuation factor (e.g., temperature) of the ring oscillator circuit 133 that has been measured in advance, and may be input from outside. The combination control signal may be input to the trimming control circuit 220 in advance, such as when the PLL circuit 1 incorporating the trimming control circuit 220 is shipped, or may be input after the PLL circuit 1 is put into operation. The combination control signal may also be input dynamically in accordance with the operation of the PLL circuit 1.

[0074] Alternatively, information indicating the on / off state of each switch circuit 203 may be written in advance to the memory 223. In this case, input of the combination control signal and the LUT 222 can be omitted. The combination control signal may also include information indicating the on / off state of each switch circuit 203. In this case, the LUT 222 can also be omitted.

[0075] (3-1-2. Effects of the First Embodiment) The effects of the first embodiment will be described using the graphs of FIGS. 12A and 12B. FIGS. 12A and 12B show graphs based on values ​​obtained by simulation. In addition, in FIGS. 12A and 12B, a box 300 indicates the characteristic range that is allowable for the PLL circuit 1.

[0076] 12A is a graph showing an example of variations due to fluctuation factors when the frequency gradient trimming circuit 20a according to the first embodiment is not used. In FIG. 12A, the horizontal axis represents the output voltage (VLPF) of the LPF 12, and the vertical axis represents the frequency (Freq) of the output clock signal CKOUT. VLPF on the horizontal axis represents the control voltage V for the ring oscillator circuit 133. C is equivalent to

[0077] In FIG. 12A, characteristic lines 310 and 311 represent the frequency of output clock signal CKOUT and control voltage V at temperatures of 95° C. and −30° C. at one end of the manufacturing process variation. C In this case, the control voltage V to obtain an output clock signal CKOUT with a constant frequency (for example, 4.5 GHz) is C It can be seen that the VLPF has a variation indicated by range 320a.

[0078] Similarly, characteristic lines 312 and 313 represent the frequency of output clock signal CKOUT and control voltage V at temperatures of 95° C. and −30° C. at the other end of the manufacturing process variation. C In this case, too, the control voltage V C It can be seen that the VLPF has a variation shown in range 320b.

[0079] 12B is a graph showing an example of variations due to fluctuation factors when the frequency slope trimming circuit 20a according to the first embodiment is used. That is, FIG. 12B shows the variation of the control current I C When corrected, the control voltage V C1 shows an example of the relationship between the VLPF and the frequency (Freq) of the output clock signal CKOUT.

[0080] In Fig. 12B, characteristic lines 310', 311', 312', and 313' correspond to characteristic lines 310, 311, 312, and 313 in Fig. 12A, respectively. The characteristic lines 310', 311', 312', and 313' are approximately the same, and it can be seen that the variations shown by the characteristic lines 310, 311, 312, and 313 in Fig. 12A are suppressed. In this way, the frequency gradient correction signal is used to control the control current I C By correcting the above, it is possible to suppress variations caused by the manufacturing process and variations caused by temperature.

[0081] (3-1-3. Layout Example of the PLL Circuit According to the First Embodiment) Some or all of the circuits of the PLL circuit 1 according to the first embodiment can be formed on the same substrate. FIG. 13 is a schematic diagram showing an example of the layout on a substrate of the PLL circuit 1 according to the first embodiment. In the example of FIG. 13, of the circuits that make up the PLL circuit 1, the LPF 12, the frequency gradient trimming circuit 20, and the VCO 13 are formed on the same substrate 60 made of, for example, silicon, and configured as a single chip.

[0082] 13, the LPF 12 is disposed on the left side of the substrate 60, and the VCO 13a is disposed on the right side. The frequency slope trimming circuit 20a is disposed between the LPF 12 and the VCO 13a. Note that the order in which the LPF 12, frequency slope trimming circuit 20a, and VCO 13a are disposed is not limited to the order shown in the example of FIG.

[0083] 13, the LPF 12 has a passive configuration with a capacitor 120 and a resistor 121 that form a filter. The LPF 12 generates a control voltage V Cis output to wiring 50. Wiring 50 is connected to current converter 200 of frequency gradient trimming circuit 20, and further connected to current converter 132a of VCO 13. As described with reference to FIG. 6 , current converter 200 includes operational amplifier 210 and transistors 211 and 212. Furthermore, current converter 132a includes transistor 132, and transistors 130 and 131, which were described with reference to FIG. 6 .

[0084] The current conversion unit 200 is connected to one end of the frequency gradient correction unit 201a by a wiring 51. The other end of the frequency gradient correction unit 201a is connected to, for example, a wiring GND of a ground potential.

[0085] The current converter 132a is connected to one end of a ring oscillator circuit 133 via a wiring 53. The other end of the ring oscillator circuit 133 is connected to, for example, a wiring GND of a ground potential. The output clock signal CKOUT generated by the ring oscillator circuit 133 is output to the outside of the PLL circuit 1 via a wiring 54.

[0086] The frequency gradient trimming circuit 20 is further connected to the VCO 13 by a wiring 52. More specifically, the wiring 52 is connected to a wiring 53 in the VCO 13. The frequency gradient correction signal output from the frequency gradient trimming circuit 20 is supplied to the wiring 53 via the wiring 52 and is combined with the current output from the current conversion unit 132a to generate a control current I C is generated. The control current I C is supplied to the ring oscillator circuit 133 via the wiring 53.

[0087] 13, the trimming control circuit 220 is omitted. The trimming control circuit 220 may be disposed between the frequency gradient trimming circuit 20 and the VCO 13, for example.

[0088] In this way, in the PLL circuit 1 according to the first embodiment, the LPF 12, frequency gradient trimming circuit 20, and VCO 13 can be arranged on a single chip and packaged. Furthermore, it is possible to configure all of the circuits included in the PLL circuit 1 on a single chip and package it, without being limited to the configuration shown in FIG.

[0089] (3-2. Modification of the First Embodiment) Next, a modification of the first embodiment will be described. In the first embodiment described above, the control voltage V C The current conversion circuit that converts the voltage Vin into a current is configured using a transistor 132. In contrast, in the modification of the first embodiment, the current conversion circuit is configured using an operational amplifier and a resistor.

[0090] Fig. 14 is a circuit diagram of an example of a frequency gradient trimming circuit 20a and a VCO 13b according to a modification of the first embodiment. Note that the configuration of the frequency gradient trimming circuit 20a in Fig. 14 is the same as that of the frequency gradient trimming circuit 20a according to the first embodiment described with reference to Fig. 6, and therefore a description thereof will be omitted here.

[0091] 14, the VCO 13 b includes P-type transistors 130 and 131 , an operational amplifier 134 , a resistor 135 , and a ring oscillator circuit 133 .

[0092] In the VCO 13b, a control voltage V C The output terminal of the operational amplifier 134 is connected to the gates of the transistors 130 and 131. The sources of the transistors 130 and 131 are connected to the power supply line V cc The drain of the transistor 130 is connected to the ground potential via a resistor 135 and also to the non-inverting input of an operational amplifier 134.

[0093] In the VCO 13b, the operational amplifier 134, the resistor 135, and the transistor 130 generate a control voltage V C into a current output from the drain of transistor 130. A current mirror circuit is formed by operational amplifier 134, transistor 130, and transistor 131. As a result, the current output from the drain of transistor 130 is duplicated, and the duplicated current is output from the drain of transistor 131.

[0094] The source of the transistor 131 is connected to the power supply line V ccand its drain is connected to the ring oscillator circuit 133. The drain of the transistor 212 in the frequency slope trimming circuit 20a is connected to the connection point between the drain of the transistor 131 and the ring oscillator circuit 133. The ring oscillator circuit 133 flows a current I DR The control current I is a combination of the frequency slope correction signal that is copied and output from the drain of the transistor 212 and the current that is output from the drain of the transistor 131. C The oscillator will oscillate at a frequency that corresponds to the current value.

[0095] The oscillation signal generated by the ring oscillator circuit 133 is output from the VCO 13a as the output clock signal CKOUT.

[0096] In this way, the control voltage V C Even when the current conversion circuit that converts the voltage Vin into a current is configured using an operational amplifier 134 and a resistor 135, it is possible to suppress variations due to the manufacturing process and temperature, as in the first embodiment described above.

[0097] (4. Second Embodiment of the Present Disclosure) Next, a second embodiment of the present disclosure will be described. In the first embodiment described above, a diffused resistor is used as the resistive element for generating the frequency slope correction signal in the frequency slope trimming circuit 20. In contrast, in the second embodiment of the present disclosure, a PN junction diode is used as the resistive element for generating the frequency slope correction signal in the frequency slope trimming circuit 20.

[0098] That is, the PN junction diode has a temperature coefficient of resistance similar to the diffused resistor described in the first embodiment. That is, the PN junction diode generally has a characteristic that the resistance increases as the temperature increases. Therefore, it is possible to use a PN junction diode instead of the diffused resistor in the first embodiment.

[0099] (4-1. Configuration According to the Second Embodiment) Fig. 15 is a circuit diagram of an example of a frequency gradient trimming circuit 20b and a VCO 13a according to the second embodiment. Note that the configuration of the VCO 13a in Fig. 15 is the same as that of the VCO 13a according to the first embodiment described using Fig. 6, and therefore will not be described here.

[0100] 15, frequency slope trimming circuit 20b includes operational amplifier 210, P-type transistors 211 and 212, and frequency slope correction unit 201b. Of these, the configurations related to operational amplifier 210 and transistors 211 and 212 are the same as the configurations of frequency slope trimming circuit 20a described using FIG. 6, and therefore description thereof will be omitted here.

[0101] The frequency gradient correction unit 201b is obtained by replacing the diffused resistors 202DR1, 202DR2, 202DR3, . . . of the frequency gradient correction unit 201a described with reference to FIG. 6 with diodes 202PND1, 202PND2, 202PND3, .

[0102] By controlling the on / off state of each switch circuit 2031, 2032, 2033, ... using the trimming control circuit 220, it is possible to use one of the diodes 202PND1, 202PND2, 202PND3, ... alone, or to use a plurality of arbitrarily selected resistance elements connected in parallel.

[0103] In this way, even when the frequency slope correction unit 201b is configured using diodes 202PND1, 202PND2, 202PND3, ..., which are PN junction diodes, instead of the diffused resistors 202DR1, 202DR2, 202DR3, ... as the resistive elements 2021, 2022, 2023, ... in the frequency slope trimming circuit 20b, it is possible to suppress variations due to fluctuations in the manufacturing process and variations due to fluctuations in temperature, as in the first embodiment described above.

[0104] (4-2. Modification of the Second Embodiment) Next, a modification of the second embodiment will be described. In the modification of the second embodiment, similar to the modification of the first embodiment described above, the control voltage V C This is an example of a current conversion circuit that uses an operational amplifier and a resistor to convert a voltage into a current.

[0105] Fig. 16 is a circuit diagram of an example of a frequency gradient trimming circuit 20b and a VCO 13b according to a modification of the second embodiment. Note that the configuration of the frequency gradient trimming circuit 20b in Fig. 16 is the same as that of the frequency gradient trimming circuit 20b according to the second embodiment described with reference to Fig. 15, and therefore a description thereof will be omitted. Also, the configuration of the VCO 13b in Fig. 16 is the same as that of the VCO 13b in the modification of the first embodiment described with reference to Fig. 14, and therefore a description thereof will be omitted.

[0106] In this way, even when the diodes 202PND1, 202PND2, 202PND3, ..., which are PN junction diodes, are used as the resistance elements 2021, 2022, 2023 in the frequency gradient correction unit 201b, it is possible to suppress variations caused by the manufacturing process and variations caused by temperature, as in the first embodiment described above.

[0107] (5. Third Embodiment of the Present Disclosure) Next, a third embodiment of the present disclosure will be described. The third embodiment of the present disclosure is an example in which the PLL circuit 1 according to the first and second embodiments and their modifications described above is applied to an electronic device.

[0108] 17 is a block diagram showing an example of the configuration of an electronic device applicable to each embodiment of the present disclosure and its modified examples. In Fig. 17, an electronic device 2000 includes an optical system 2002, a control unit 2003, an image sensor 2004, an image processing unit 2005, a memory 2006, a storage unit 2007, a display unit 2008, an interface (I / F) unit 2009, and an input device 2012.

[0109] Here, a digital still camera, a digital video camera, a mobile phone or a smartphone with an imaging function, etc. can be applied as the electronic device 2000. Furthermore, a surveillance camera, an in-vehicle camera, a medical camera, etc. can also be applied as the electronic device 2000.

[0110] The image sensor 2004 includes a plurality of photoelectric conversion elements arranged, for example, in a matrix array. The photoelectric conversion elements convert received light into electric charges through photoelectric conversion. The image sensor 2004 includes a drive circuit that drives the plurality of photoelectric conversion elements, a signal processing circuit that reads electric charges from each of the plurality of photoelectric conversion elements and generates image data based on the read electric charges, and a power supply circuit that supplies power to the drive circuit.

[0111] The optical system 2002 includes a main lens formed by a combination of one or more lenses and a mechanism for driving the main lens, and forms an image of image light (incident light) from a subject on the light receiving surface of the image sensor 2004 via the main lens. The optical system 2002 also includes an autofocus mechanism that adjusts the focus in accordance with a control signal and a zoom mechanism that changes the zoom ratio in accordance with a control signal. The electronic device 2000 may also have a detachable optical system 2002 that can be replaced with another optical system 2002.

[0112] The image processing unit 2005 performs predetermined image processing on the pixel data output from the image sensor 2004. For example, the image processing unit 2005 is connected to a memory 2006 such as a frame memory, and writes the image data output from the image sensor 2004 into the memory 2006. The image processing unit 2005 performs predetermined image processing on the pixel data written into the memory 2006, and writes the processed pixel data back into the memory 2006. The memory 2006 can store one frame's worth of pixel data as image data.

[0113] The storage unit 2007 is a nonvolatile memory such as a flash memory or a hard disk drive, and stores image data output from the image processing unit 2005 in a nonvolatile manner. The display unit 2008 includes a display device such as an LCD (Liquid Crystal Display) and a drive circuit for driving the display device, and can display an image based on the image data output from the image processing unit 2005. The I / F unit 2009 is an interface for transmitting the image data output from the image processing unit 2005 to an external device. For example, a USB (Universal Serial Bus) can be used as the I / F unit 2009. However, the I / F unit 2009 is not limited to this, and may also be an interface that can be connected to a network via wired or wireless communication.

[0114] The input device 2012 includes an operator for accepting user input, etc. If the electronic device 2000 is, for example, a digital still camera, a digital video camera, a mobile phone with an image capturing function, or a smartphone, the input device 2012 may include a shutter button for instructing the image sensor 2004 to capture an image, or an operator for realizing the function of the shutter button.

[0115] The control unit 2003 includes a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory), and controls the overall operation of the electronic device 2000 in accordance with a program pre-stored in the ROM, using the RAM as a work memory. For example, the control unit 2003 can control the operation of the electronic device 2000 in response to a user input received by the input device 2012. The control unit 2003 can also control the autofocus mechanism in the optical system 2002 based on the image processing results of the image processing unit 2005.

[0116] FIG. 18 is a block diagram showing an example of the configuration of an image sensor 2004 applicable to the embodiment.

[0117] In FIG. 18, the image sensor 2004 includes an image acquisition unit 2100, a parallel-to-serial conversion circuit (P / S) 2110, a transmission circuit 2111, a reference clock generation unit 2120, a synchronization signal generation unit 2121, a PLL circuit 2122, and a timing generator (TG) 2123.

[0118] The reference clock generation unit 2120 generates a reference clock signal that serves as a reference for the operation of the image sensor 2004. The reference clock signal is supplied to a synchronization signal generation unit 2121 and a PLL circuit 2122. The synchronization signal generation unit 2121 generates a horizontal synchronization signal and a vertical synchronization signal for driving the pixel array in the pixel unit 2101 based on the reference clock. The synchronization signal generation unit 2121 supplies the generated horizontal synchronization signal and vertical synchronization signal to the TG 2123.

[0119] The TG 2123 generates drive signals for driving each pixel in the pixel unit 2101 (described later) based on the horizontal synchronizing signal and vertical synchronizing signal received from the synchronizing signal generating unit 2121. The TG 2123 may generate drive signals by further using a transfer control signal supplied from the logic circuit 2103 (described later). The TG 2123 supplies the generated drive signals to the image acquiring unit 2100.

[0120] The image acquisition unit 2100 includes a pixel unit 2101, an A / D conversion unit 2102, and a logic circuit 2103. The pixel unit 2101 includes a pixel array in which pixels that output electrical signals in response to incident light through photoelectric conversion are arranged in a grid pattern, and a vertical scanning circuit and a horizontal scanning circuit that drive each pixel of the pixel array. Each pixel of the pixel unit 2101 is driven in response to a drive signal supplied from the TG 2123, and outputs an analog image signal based on the electrical signal output from each pixel in response to the incident light.

[0121] A pixel signal output from the pixel unit 2101 is converted into a digital pixel signal by an A / D conversion unit 2102. The digital pixel signal obtained by converting the pixel signal in the A / D conversion unit 2102 is supplied to a logic circuit 2103.

[0122] The logic circuit 2103 performs a predetermined code conversion on the supplied digital pixel signal to generate pixel data. The logic circuit 2103 also adds predetermined information to the pixel data in units of frames to generate image data in units of frames. Note that a frame is composed of, for example, pixel data of pixels in an effective pixel area in the pixel array of the pixel unit 2101. The logic circuit 2103 supplies the generated image data in units of frames to a parallel-serial conversion circuit 2110.

[0123] The logic circuit 2103 is further supplied with a control signal from a higher-level configuration, for example, the control unit 2003. The logic circuit 2103 generates a transfer control signal related to the transfer of image data based on this control signal, a clock signal based on the reference clock signal generated by the reference clock generation unit 2120, and the digital pixel signal supplied from the A / D conversion unit 2102. The logic circuit 2103 supplies the generated transfer control signal to the TG 2123.

[0124] The PLL circuit 2122 performs phase synchronization processing based on the reference clock signal supplied from the reference clock generating unit 2120, and generates a PLL clock signal. The PLL circuit 2122 supplies the generated PLL clock signal to the parallel-serial conversion circuit 2110.

[0125] The parallel-serial conversion circuit 2110 converts the image data supplied as parallel data from the logic circuit 2103 into serial data in accordance with a PLL clock signal supplied from a PLL circuit 2122, and passes the serial data to a transmission circuit 2111. The transmission circuit 2111 outputs the image data, which has been passed from the parallel-serial conversion circuit 2110, as serial data synchronized with the PLL signal from the image sensor 2004. The image data output from the image sensor 2004 is received by an image processing unit 2005.

[0126] The PLL circuit 1 according to each embodiment and each modification of the present disclosure may be applied to the PLL circuit 2122. By supplying the output clock signal CKOUT generated by the PLL circuit 1 according to each embodiment and each modification of the present disclosure to the parallel-serial conversion circuit 2110 as an operating clock signal, it is possible to suppress jitter in the operating clock signal due to fluctuation factors, and to perform faster and more stable data transfer. This makes it possible to achieve stable transfer of image data with a higher frame rate and higher resolution.

[0127] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0128] The present technology may also be configured as follows: (1) A PLL (Phase Locked Loop) circuit including: a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on an output clock signal; a conversion circuit that outputs a current corresponding to the phase difference; a smoothing circuit that smooths the output of the conversion circuit and outputs the result as a control voltage; a correction signal generation circuit that generates, based on the control voltage, a correction signal corresponding to fluctuations in the control voltage; and a voltage controlled oscillation circuit that outputs, as the output clock signal, a clock signal having a frequency corresponding to the control voltage and the correction signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in a direction opposite to that of fluctuations in the control voltage in response to a cause of fluctuations in the control voltage. (2) The PLL circuit according to (1), wherein each of the plurality of resistance elements is a diffused resistor. (3) The PLL circuit according to (1), wherein each of the plurality of resistance elements is a PN junction diode. (4) The PLL circuit according to any one of (1) to (3), wherein the plurality of resistive elements include resistive elements with different characteristics, and the correction signal generation circuit generates the correction signal by a single resistive element or a combination of two or more resistive elements from the plurality of resistive elements. (5) The PLL circuit according to (4), wherein the plurality of resistive elements include a plurality of resistive element groups each having one or more resistive elements with the same characteristics with respect to causes of fluctuations in the control voltage, and the characteristics of the one or more resistive elements in the plurality of resistive element groups are different from one another. (6) The PLL circuit according to (4) or (5), wherein the correction signal generation circuit includes a combination setting circuit that sets a combination of the plurality of resistive elements in response to an external instruction. (7) The PLL circuit according to any one of (1) to (6), further comprising a voltage-current converter that converts the control voltage into a current, wherein the voltage-controlled oscillation circuit controls an oscillation frequency based on a combined current obtained by combining the correction signal and a replicated current obtained by replicating the current obtained by converting the control voltage in the voltage-current converter. (8) The PLL circuit according to (7), wherein the voltage-current converter is configured using a transistor.(9) The PLL circuit according to (7), wherein the voltage-current conversion circuit is configured using an operational amplifier and a resistor element. (10) An integrated circuit including: a PLL (Phase Locked Loop) circuit; and a signal processing circuit that operates based on an output clock signal output from the PLL circuit and is configured on the same chip as the PLL circuit, wherein the PLL circuit includes: a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on the output clock signal; a conversion circuit that outputs a current corresponding to the phase difference; a smoothing circuit that smoothes the output of the conversion circuit and outputs the result as a control voltage; a correction signal generation circuit that generates, based on the control voltage, a correction signal corresponding to fluctuations in the control voltage; and a voltage controlled oscillation circuit that outputs a clock signal having a frequency corresponding to the control voltage and the correction signal as the output clock signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistor elements whose characteristics fluctuate in a direction opposite to that of fluctuations in the control voltage in response to a cause of fluctuations in the control voltage. (11) An electronic device including: a PLL (Phase Locked Loop) circuit, a signal output unit that outputs a signal, and a signal processing unit that performs signal processing on the signal output from the signal output unit based on an output clock signal output from the PLL circuit, wherein the PLL circuit includes: a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on the output clock signal, a conversion circuit that outputs a current corresponding to the phase difference, a smoothing circuit that smooths the output of the conversion circuit and outputs the result as a control voltage, a correction signal generation circuit that generates, based on the control voltage, a correction signal corresponding to fluctuations in the control voltage, and a voltage controlled oscillation circuit that outputs a clock signal having a frequency corresponding to the control voltage and the correction signal as the output clock signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in a direction opposite to that of fluctuations in the control voltage in response to a cause of fluctuation in the control voltage. (12) The electronic device according to (11), wherein at least the PLL circuit and the signal processing unit are configured on the same chip.(13) The electronic device according to (11) or (12), further including an image processing unit that performs image processing on an image signal, wherein the signal output unit has an imaging element that outputs the image signal, and the signal processing unit is an interface circuit that transfers the image signal output from the imaging element to the image processing unit.

[0129] 1, 1000, 2122 PLL circuit 10 Frequency phase comparison circuit 11 Charge pump 12 LPF 13, 13a, 13b VCO 14 Buffer 15 Frequency divider circuit 20, 20a, 20b Frequency gradient trimming circuit 130, 131, 132, 211, 212 Transistor 132a, 200 Current conversion unit 134, 210 Operational amplifier 133 Ring oscillator circuit 201, 201a, 201b Frequency gradient correction unit 2021, 2022, 2023 Resistive element 202DR1, 202DR2, 202DR3, 202DRb, 202DRc, 202DRd Diffused resistor 202PND1, 202PND2, 202PND3 Diode 2031, 2032, 2033, 203a, 203b, 203c, 203d Switch circuit 220 Trimming control circuit 2000 Electronic device 2004 Image sensor 2005 Image processing unit 2110 Parallel-serial conversion circuit 2111 Transmission circuit

Claims

1. A PLL (Phase Locked Loop) circuit comprising: a phase comparison circuit that detects the phase difference between a reference clock signal and a feedback clock signal based on an output clock signal; a conversion circuit that outputs a current corresponding to the phase difference; a smoothing circuit that smoothes the output of the conversion circuit and outputs it as a control voltage; a correction signal generation circuit that generates a correction signal based on the control voltage and corresponding to fluctuations in the control voltage; and a voltage controlled oscillation circuit that outputs a clock signal having a frequency corresponding to the control voltage and the correction signal as the output clock signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in the opposite direction to the fluctuations in the control voltage in response to factors causing the fluctuations in the control voltage.

2. The PLL circuit according to claim 1, wherein each of the plurality of resistive elements is a diffused resistor.

3. The PLL circuit according to claim 1, wherein each of the plurality of resistive elements is a PN junction diode.

4. The PLL circuit according to claim 1, wherein the plurality of resistive elements include resistive elements having different characteristics, and the correction signal generating circuit generates the correction signal using a single resistive element among the plurality of resistive elements or a combination of two or more resistive elements.

5. The PLL circuit according to claim 4, wherein the plurality of resistive elements include a plurality of resistive element groups each having one or more resistive elements with the same characteristics with respect to factors causing fluctuations in the control voltage, and the characteristics of the one or more resistive elements in the plurality of resistive element groups are different from one another.

6. The PLL circuit according to claim 4, wherein said correction signal generating circuit includes a combination setting circuit which sets a combination of said plurality of resistance elements in response to an external instruction.

7. The PLL circuit according to claim 1, further comprising a voltage-to-current conversion circuit that converts the control voltage into a current, wherein the voltage-controlled oscillation circuit controls an oscillation frequency based on a composite current obtained by combining the correction signal and a replicated current obtained by replicating the current into which the control voltage is converted by the voltage-to-current conversion circuit.

8. The PLL circuit according to claim 7, wherein the voltage-to-current conversion circuit is configured using a transistor.

9. The PLL circuit according to claim 7, wherein the voltage-to-current conversion circuit is configured using an operational amplifier and a resistive element.

10. An integrated circuit comprising: a PLL (Phase Locked Loop) circuit; and a signal processing circuit configured on the same chip as the PLL circuit and operating based on an output clock signal output from the PLL circuit, wherein the PLL circuit comprises: a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on the output clock signal; a conversion circuit that outputs a current corresponding to the phase difference; a smoothing circuit that smoothes the output of the conversion circuit and outputs it as a control voltage; a correction signal generation circuit that generates a correction signal based on the control voltage and corresponding to fluctuations in the control voltage; and a voltage controlled oscillation circuit that outputs a clock signal having a frequency corresponding to the control voltage and the correction signal as the output clock signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in the opposite direction to the fluctuations in the control voltage in response to a cause of the fluctuation in the control voltage.

11. An electronic device comprising: a PLL (Phase Locked Loop) circuit; a signal output unit that outputs a signal; and a signal processing unit that performs signal processing on the signal output from the signal output unit based on the output clock signal output from the PLL circuit, wherein the PLL circuit comprises: a phase comparison circuit that detects a phase difference between a reference clock signal and a feedback clock signal based on the output clock signal; a conversion circuit that outputs a current corresponding to the phase difference; a smoothing circuit that smoothes the output of the conversion circuit and outputs it as a control voltage; a correction signal generation circuit that generates a correction signal based on the control voltage and corresponding to fluctuations in the control voltage; and a voltage controlled oscillation circuit that outputs a clock signal having a frequency corresponding to the control voltage and the correction signal as the output clock signal, wherein the correction signal generation circuit generates the correction signal using a plurality of resistance elements whose characteristics fluctuate in the opposite direction to the fluctuations in the control voltage in response to a cause of the fluctuation in the control voltage.

12. The electronic device according to claim 11, wherein at least the PLL circuit and the signal processing section are configured on the same chip.

13. The electronic device according to claim 11, further comprising: an image processing unit that performs image processing on an image signal; the signal output unit has an imaging element that outputs the image signal; and the signal processing unit is an interface circuit for transferring the image signal output from the imaging element to the image processing unit.

Images