Power converter

Abstract

A power converter (1) comprises: a switching element; an integration circuit (106) that outputs an integrated value of a voltage generated in an inductance component and a parasitic resistance connected in series to a main electrode of the switching element; and a first current detection circuit (21) that obtains a current flowing through the main electrode of the switching element on the basis of the integral value output from the integration circuit. The first current detection circuit calculates a first current value representing a magnitude of a current flowing through the main electrode on the basis of a first integral value output from the integration circuit in an interval before and after the switching element is turned off and a second integral value output from the integration circuit in an interval before and after the switching element is turned on.

Description

Power Conversion Device

[0001] The present invention relates to a power conversion device.

[0002] With growing social awareness of protecting the global environment and the efficient use of resources, as well as the need for economic rationality in household finances, new services such as car sharing, autonomous driving, and MaaS (Mobility as a Service) are expected to become more widespread in the future, leading to a significant increase in automobile utilization rates. To accommodate this increase in operating hours, various on-board automotive devices must either extend the lifespan of their components or maintain their functionality through appropriate maintenance. Extending the lifespan of components is subject to many constraints, including cost and performance, and significant improvements are expected to take time. Therefore, it is considered effective to perform maintenance in conjunction with predictive diagnostic technology that detects abnormalities in components before they break down, allowing for timely part replacement.

[0003] For example, Patent Documents 1 and 2 disclose techniques for detecting abnormalities in components in on-board devices. Patent Document 1 discloses a technique for determining whether a current sensor provided in each phase of a three-phase AC motor mounted on an electric vehicle is faulty by estimating the current value of each phase based on measurements by current sensors for the other two phases and comparing the estimated result with the measured value for each phase. Patent Document 2 discloses a technique for detecting a potential difference in wiring connected to each terminal of a switching element constituting an upper arm or a lower arm of a power module in a power conversion device mounted on an electric vehicle, and estimating the current value of each wiring based on the detected potential difference, thereby independently detecting a short circuit and an overcurrent in the switching element.

[0004] Japanese Patent Publication No. 2000-116176 Japanese Patent Publication No. 2017-92789

[0005] The technology of Patent Document 1 can detect a failure in a current sensor of one of the three phases, but cannot detect a failure in a current sensor if a current sensor of two or more phases fails because it cannot estimate the current value of each phase. On the other hand, the technology of Patent Document 2 can detect a short circuit and an overcurrent in each arm of each phase, but does not take into account temperature changes of parasitic resistance components, and therefore the accuracy of current estimation is low.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to accurately estimate the current flowing through a switching element provided in a power conversion device.

[0007] A power conversion device according to the present invention comprises a switching element, an integrating circuit that outputs an integral value of a voltage generated across an inductance component and a parasitic resistance connected in series to a main electrode of the switching element, and a first current detection circuit that determines a current flowing through the main electrode of the switching element based on the integral value output from the integrating circuit, wherein the first current detection circuit calculates a first current value that indicates the magnitude of the current flowing through the main electrode based on a first integral value output from the integrating circuit in a period before and after the switching element is turned off and a second integral value output from the integrating circuit in a period before and after the switching element is turned on.

[0008] According to the present invention, it is possible to accurately estimate the current flowing through a switching element provided in a power conversion device.

[0009] 5 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(I) in the waveform example of FIG. 5; FIG. 6 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(II) in the waveform example of FIG. 5; FIG. 7 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(III) in the waveform example of FIG. 5; FIG. 8 is an enlarged view of a portion of a section including a period corresponding to pulse condition U-(IV) in the waveform example of FIG. 5; FIG. 9 is an explanatory view of the effect of application of the present invention; FIG. 10 is a view showing how the magnitude of the relative error of the estimated current with respect to the true output current changes when the resistance value of the parasitic resistance is changed; FIG. 11 is a view showing an example of a configuration of a power conversion device according to a second embodiment of the present invention; FIG. 12 is an example of a flowchart showing the processing flow when the abnormality detection circuit according to the second embodiment of the present invention performs abnormality determination. 1 is a diagram showing an example of a flowchart illustrating a processing flow when an abnormality detection circuit according to a second embodiment of the present invention performs abnormality determination. FIG. 2 is a diagram showing a configuration example of a power conversion device according to a third embodiment of the present invention. FIG. 3 is a diagram showing a configuration example of a power conversion device according to a fourth embodiment of the present invention.

[0010] (First embodiment) In the first embodiment of the present invention described below, an example of a power conversion device will be described in which, instead of using a conventional current sensor, an output current is calculated based on the integral value of the voltage of the inductance component and parasitic resistance at the main terminal of each switching element, and the calculation result is used to control a motor.

[0011] Fig. 1 is a diagram showing an example of the configuration of a power conversion device according to a first embodiment of the present invention. The power conversion device 1 shown in Fig. 1 is connected between a storage battery 2 and a motor 3, converts DC power supplied from the storage battery 2 into AC power, and supplies it to the stator windings (U-phase winding L) of the motor 3. u , V phase winding L V , W phase winding L W), which rotates and drives a motor 3. The power conversion device 1, the storage battery 2, and the motor 3 are mounted on an electric vehicle such as an electric car, and the electric vehicle is driven by the driving force generated by the motor 3. The power conversion device 1 is configured to include an inverter circuit 10, a smoothing capacitor 11, and a control device 20.

[0012] The inverter circuit 10 has a plurality of power modules 100 (U-phase upper arm power module 100UU, U-phase lower arm power module 100UL, V-phase upper arm power module 100VU, V-phase lower arm power module 100VL, W-phase upper arm power module 100WU, and W-phase lower arm power module 100WL) respectively provided for the upper and lower arms of each phase of three-phase AC current output from the power conversion device 1 to the motor 3. Each power module 100 has a switching element 101, a freewheeling diode 102, an inductance component 103, and a parasitic resistance 104, and is connected to a gate driver 105 and an integrating circuit 106.

[0013] The DC power supplied from the storage battery 2 is input to the inverter circuit 10 via a smoothing capacitor 11. The inverter circuit 10 receives a gate command V output from the control device 20 to each arm of each phase. G (U-phase upper arm gate command V G_UU , U-phase lower arm gate command V G_UL , V-phase upper arm gate command V G_VU , V-phase lower arm gate command V G_VL , W-phase upper arm gate command V G_WU , W-phase lower arm gate command V G_WL The DC power is converted into three-phase AC power by switching the switching elements 101 of the power modules 100 in accordance with the voltages. The smoothing capacitors 11 suppress fluctuations in the DC voltage caused by the switching of the switching elements 101.

[0014] The switching element 101 is a power semiconductor element that has a pair of main electrodes and a gate electrode, and performs switching drive to establish or interrupt conduction between the pair of main electrodes in response to a gate signal input from a gate driver 105 to the gate electrode. The switching element 101 is configured using, for example, a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). If the switching element 101 is a MOSFET, the main electrodes are a source electrode and a drain electrode, and if the switching element 101 is an IGBT, the main electrodes are an emitter electrode and a collector electrode. While an example in which the switching element 101 is a MOSFET will be described below, the same applies to an IGBT.

[0015] The freewheel diode 102 is connected in antiparallel to the switching element 101 and protects the switching element 101 from a current flowing in the reverse direction in the power module 100. When the switching element 101 is a MOSFET, the body diode of the MOSFET may be used as the freewheel diode 102.

[0016] An inductance component 103 and a parasitic resistance 104 connected in series with the source electrode of the switching element 101 represent, for example, an inductance component and a resistance component inside the switching element 101 and in the wiring of the power module 100 and the inverter circuit 10 .

[0017] The gate driver 105 receives a gate command V G Based on this, a pulsed gate signal is output to the gate electrode of the switching element 101. The switching element 101 is alternately turned on and off in response to this gate signal, whereby the switching element 101 is switched and driven, and DC power is converted into AC power.

[0018] The integrating circuit 106 detects the voltage across the series connection of the inductance component 103 and the parasitic resistance 104, and outputs an output voltage V outThe integration circuit 106 detects the voltage generated across the series connection of the inductance component 103 and the parasitic resistance 104 in the period before and after the switching element 101 is turned off and in the period before and after the switching element 101 is turned on, and outputs an output voltage V out The integrating circuit 106 is configured by an integrating circuit with a reset switch that uses an operational amplifier, for example.

[0019] The control device 20 has a plurality of first current detection circuits 21 provided for each power module 100 of the inverter circuit 10, an output current estimation circuit 22, a control signal generation circuit 23, and a communication connector 24.

[0020] Each first current detection circuit 21 receives the output voltage V from each integration circuit 106 of the inverter circuit 10. out Each first current detection circuit 21 detects the input output voltage V out Based on this, a calculation method called the di / dt integration method, which will be described later, is used to calculate the magnitude of the current flowing through the main electrode (source electrode) of the switching element 101 in each arm of each phase, and the calculation result is used as the first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) to the output current estimation circuit 22. Details of how the first current detection circuit 21 calculates the first current value will be described later.

[0021] The output current estimation circuit 22 estimates the first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ), the output current of each phase (U-phase output current I outU , V-phase output current I outV, W-phase output current I outW ) and outputs the estimated results of the output current of each phase to the control signal generating circuit 23. Details of the method for estimating the output current of each phase by the output current estimating circuit 22 will be described later.

[0022] The control signal generating circuit 23 performs well-known vector control based on the estimation result of the output current of each phase by the output current estimating circuit 22, and generates gate commands V for each arm of each phase in response to a torque command input from a higher-level control device (not shown) via a communication connector 24. G (U-phase upper arm gate command V G_UU , U-phase lower arm gate command V G_UL , V-phase upper arm gate command V G_VU , V-phase lower arm gate command V G_VL , W-phase upper arm gate command V G_WU , W-phase lower arm gate command V G_WL ) and outputs it to the inverter circuit 10.

[0023] Specifically, for example, the control signal generation circuit 23 determines a d-axis current command value Id* and a q-axis current command value Iq* based on the voltage and torque command of the storage battery 2, and also determines a U-phase output current I outU , V-phase output current I outV and W-phase output current I outW are converted into output currents on the d- and q-axes (d-axis current value Id and q-axis current value Iq). Then, a d-axis voltage command value Vd* and a q-axis voltage command value Vq* are calculated from the difference between the d-axis current command value Id* and the d-axis current value Id, and the difference between the q-axis current command value Iq* and the q-axis current value Iq. These voltage command values ​​are then converted from two-phase to three-phase to calculate voltage commands for each phase (U-phase voltage command value Vu*, V-phase voltage command value Vv*, and W-phase voltage command value Vw*). By performing PWM control based on the voltage commands for each phase calculated in this way, gate commands V for each arm of each phase are calculated. GThe above-described method for generating gate commands is merely an example, and the control signal generating circuit 23 can generate gate commands by any method as long as it can generate gate commands for each arm of each phase based on the estimation result of the output current of each phase by the output current estimating circuit 22.

[0024] Next, the details of the method (di / dt integration method) for calculating the first current value by the first current detection circuit 21 will be described below. Note that, in the following, the output voltage V output from the integration circuit 106 connected to the W-phase upper arm power module 100WU is out An example will be described in which the magnitude of the current flowing through the source electrode of the switching element 101 in the W-phase upper arm power module 100WU is calculated as a first current value by the corresponding first current detection circuit 21 based on the above, but the same applies to the other first current detection circuits 21.

[0025] The inductance value of the inductance component 103 in the W-phase upper arm power module 100WU is set to L Ss , the resistance value of the parasitic resistor 104 is R Ss Then, the voltage V between both ends of these input to the integrating circuit 106 is Ss is expressed by the following (Equation 1). In (Equation 1), di S / dt represents the rate of change of the source current flowing through the switching element 101 over time.

[0026] Output voltage V from the integrator circuit 106 out is the voltage V between both ends of equation (1) Ss Using the formula (2), it is expressed as the following formula (2). i , C i represent the values ​​of the resistance component and capacitance component of the integrating circuit 106, respectively.

[0027] In (Equation 2), t st , t read represent the start time of the integration operation and the reading time in the integration circuit 106. That is, in the integration circuit 106, at time t st From t read During the period up to Ssis integrated and the integral value is the output voltage V out and is read by the first current detection circuit 21.

[0028] From (Equation 2), the output voltage V out The source current estimate I is estimated from S_est is expressed by the following (Equation 3).

[0029] According to (Equation 3), the error component due to the voltage drop of the parasitic resistance 104 (second term on the right side) is subtracted from the output of the integrator circuit 106 (first term on the right side) to obtain the time rate of change of the source current, di S The source current estimate I is calculated by extracting only the integral value of / dt. S_est Here, the apparent source current estimate before subtracting the error due to the parasitic resistance 104 is I S_est ', this is expressed by the following (Equation 4).

[0030] The apparent source current estimate I obtained by (Equation 4) S_est 2, (a) shows an example of the circuit configuration of the integrating circuit 106, and (b) shows examples of waveforms when the switching element 101 is turned off. In FIG. 2(b), the gate voltage V gs and the reset signal of the integrating circuit 106, and the actual source current I S and the apparent source current estimate I S_est ' and ' are calculated.

[0031] For example, when the integrator circuit 106 having the circuit configuration shown in FIG. 2A is used, the apparent source current estimated value I S_est ' is the source current I before the actual turn-off. S On the other hand, the resistance value R of the parasitic resistor 104 Ss In the example of the current waveform in FIG. 2B, the resistance value R of the parasitic resistor 104 is Ss The apparent source current estimate I S_est ' is shown.

[0032] Resistance value R of parasitic resistor 104 Ss When Ω is 0, the apparent source current estimate I calculated by (Equation 4) S_est ' is the source current before turn-off I S0 Therefore, in this case, the apparent source current estimate I S_est ' is the source current I S0 By calculating the resistance R of the parasitic resistor 104 as Ss is not 0Ω, the apparent source current estimate I calculated by (Equation 4) S_est ' is the resistance value R of the parasitic resistor 104 Ss The error corresponding to the source current I before turn-off is included. S0 As shown in FIG. 2(b), this error is due to the resistance value R Ss It can be seen that the resistance increases as the resistance increases, and even a small resistance value of about 50 to 200 μΩ cannot be ignored.

[0033] Here, the resistance value R of the parasitic resistor 104 Ss changes according to the temperature of the switching element 101. That is, when the switching element 101 is energized and the terminal temperature of the main electrode rises, the resistance value R Ss For example, when copper is used for the main electrode of the switching element 101, if the temperature of the main electrode increases from 20° C. to 150° C., the resistance value R Ss increases by about 1.5 times.

[0034] In the present invention, the resistance value R of the parasitic resistor 104 due to the temperature change of the switching element 101 is Ss Regardless of the change in S In order to accurately determine the first current value, the first current detection circuit 21 estimates the current of each phase and each arm. This makes it possible to accurately calculate the first current value for each power module 100. A specific method for this will be described below.

[0035] 3A and 3B are diagrams showing examples of waveforms when the switching element 101 is turned off and turned on. In FIG. 3A, (a) shows an example of a waveform when the switching element 101 is turned off, and (b) shows an example of a waveform when the switching element 101 is turned on. In FIGS. 3A and 3B, as in the above-mentioned FIG. 2B, the gate voltage V gs 3A shows an example of the voltage waveform of the reset signal of the integrating circuit 106, and the lower part shows an example of the current waveform of the actual source current and the apparent source current estimated value. S(off) , the apparent source current estimate is I S(off)est In FIG. 3(b), the source current after turn-on is expressed as I S(on) , the apparent source current estimate is I S(on)est 3(a) and 3(b), the current estimation error due to the parasitic resistance 104 is expressed as I RSs(off) , I RSs(on) and respectively.

[0036] As shown in FIG. 3, the source current I S(off) , I S(on) is the apparent source current estimate I calculated from (Equation 4). S(off)est ', I S(on)est ' and the current estimation error I due to the parasitic resistance 104 RSs(off) , I RSs(on) Using these, the following expressions (5) and (6) can be expressed, respectively.

[0037] Here, if a specific pulse condition is selected in which the load current of the phase does not increase or decrease during the off period from after the switching element 101 of each phase is turned off until it is turned on, the source current I S(off) and the source current after turn-on I S(on) In this case, when the difference between the above (Equation 5) and (Equation 6) is taken, the following (Equation 7) is established.

[0038] From (Equation 7), the apparent source current estimated value I before turn-off and after turn-on, which is calculated without taking into account the voltage drop of the parasitic resistance 104, is S(off)est ', I S(on)estFrom the difference between RSs(off) , I RSs(on) 3, the integration range of the integrating circuit 106 is divided into a period before and after turn-off and a period before and after turn-on. The output voltages V output from the integrating circuit 106 are calculated in accordance with the integral values ​​in these integration ranges. out The apparent source current estimate I is calculated before turn-off and after turn-on based on S(off)est ', I S(on)est By finding the difference between V and V′, the calculation of (Equation 7) can be performed. However, the polarity of the integral obtained in the period before and after turn-off is opposite to that of the integral obtained in the period before and after turn-on. Therefore, integration is continued from before turn-off to after turn-on, and the output voltage V output from the integrating circuit 106 in this integration range is out Using Equation 4, the apparent source current estimate I S_est Even if ' is calculated, the same result as that of the calculation of (Equation 7) is obtained.

[0039] Normally, in order to correct the current error due to the voltage integration of the parasitic resistance 104, the current value I flowing through the parasitic resistance 104 is calculated as shown in the second term on the right side of (Equation 3). S However, the source current we ultimately want to find is the same current value I S Therefore, the current value I S Therefore, in the power conversion device 1 of this embodiment, the first current value calculated by the first current detection circuit 21 of each phase and each arm under the specific pulse conditions as described above is selected, and the accurate source current value I of each phase and each arm can be obtained regardless of the current error due to the voltage integral of the parasitic resistance 104. S This is a main feature of the power conversion device 1 of this embodiment.

[0040] Specifically, the current waveforms at turn-off and turn-on are approximated by square waves, and the current conduction period Δt cond(off) , Δt cond(on) The magnitude of the source current at a constant current value I SIf we put (i s =I S ), the current estimation error I at turn-off on the left side of the above (Equation 7) RSs(off) and the turn-on current estimation error I RSs(on) are calculated by the following (Equation 8) and (Equation 9), respectively.

[0041] From (Equation 7) to (Equation 9), the following (Equation 10) and (Equation 11) can be obtained.

[0042] From (Equation 8), (Equation 9), and (Equation 11), the following (Equation 12) and (Equation 13) can be obtained.

[0043] By substituting (Equation 12) and (Equation 13) into the above-mentioned (Equation 5) and (Equation 6), respectively, the following (Equation 14) and (Equation 15) are obtained.

[0044] The prerequisite for formula 7 to hold is, as mentioned above, S(off) ≒I S(on) ≒I S Therefore, whether (Equation 14) or (Equation 15) is used, the output voltage V output from the integrating circuit 106 in the period before and after the turn-off is out The apparent source current estimate I is calculated using Equation 4. S(off)est ', and the output voltage V output from the integrating circuit 106 in the period before and after the turn-on. out The apparent source current estimate I is calculated using Equation 4. S(on)est ' and the actual source current value I S Here, the source current value I S That is, in the power conversion device 1 of this embodiment, the above-described calculation process is performed in each first current detection circuit 21, and the output voltage V output from the integrator circuit 106 of each phase and each arm in the period before and after the turn-off is calculated. out and the output voltage V output from the integrator circuit 106 of each phase and each arm in the period before and after the turn-on. outand a first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) can be calculated.

[0045] 4 is a diagram showing an example of the configuration of the first current detection circuit 21. As shown in FIG. 4, the first current detection circuit 21 has functional blocks, for example, a source current estimation unit 211, a turn-off / turn-on determination unit 212, a current conduction period estimation unit 213, and a parasitic resistance error correction unit 214. The first current detection circuit 21 can realize these functional blocks by combining logic circuits and programs executed by a microcomputer, for example. The logic circuits may be, for example, a field programmable gate array (FPGA).

[0046] The source current estimation unit 211 receives the output voltage V out The source current estimation unit 211 receives the input output voltage V out Based on this, the apparent source current estimate I is calculated using (Equation 4). S_est ' is calculated.

[0047] The turn-off / turn-on discrimination unit 212 receives a gate command V output from the control device 20 to each arm of each phase. G and the apparent source current estimation value I calculated by the source current estimation unit 211. S_est The turn-off / turn-on determination unit 212 receives the apparent source current estimates I S_est ' and gate command V for all phases GBased on this, the timing of turning on and off the switching element 101 of the arm in question and the corresponding current detection timing are determined. The method of determining the current detection timing will be described in detail later. Then, the data acquired in the period before and after the turn-off and the data acquired in the period before and after the turn-on are distinguished from each other, and the former is used as the apparent source current estimated value I before the turn-off. S(off)est ', the latter is the apparent source current estimate after turn-on I S(on)est ' respectively.

[0048] The current conduction period estimation unit 213 receives the apparent source current estimation value I obtained by the turn-off / turn-on determination unit 212. S(off)est ', I S(on)est ', a battery voltage representing the DC voltage of the storage battery 2, and an output signal from an on-chip temperature sensor (not shown) attached to the switching element 101 of the arm corresponding to the first current detection circuit 21. Based on these input parameters, the current conduction period estimation unit 213 determines the switching conditions (current, voltage, temperature) of the switching element 101, and calculates the current conduction period Δt cond(off) , Δt cond(on) The current conduction period estimation unit 213 estimates the current conduction period Δt cond(off) , Δt cond(on) By referring to this table data, the current conduction period Δt corresponding to the switching condition represented by the input parameter can be calculated. cond(off) , Δt cond(on) can be estimated.

[0049] The current conduction period estimation unit 213 estimates the current conduction period Δt cond(off) , Δt cond(on) At least one of the above input parameters may be omitted when estimating the current conduction period Δt cond(off) , Δt cond(on) The current conduction period Δt within the integration period of the integrating circuit 106 may be a preset fixed value. cond(off) , Δt cond(on)If these can be appropriately estimated, the current conduction period estimation unit 213 can estimate these by any method.

[0050] The parasitic resistance error correction unit 214 corrects the apparent source current estimated value I obtained by the turn-off / turn-on determination unit 212. S(off)est ', I S(on)est ' and the current conduction period Δt estimated by the current conduction period estimation unit 213 cond(off) , Δt cond(on) Based on this, the source current value I , in which the error due to the parasitic resistance 104 has been corrected, is calculated using (Equation 14) and (Equation 15). S Then, the obtained source current value I S The calculation result of the current flowing through the arm is used as the estimated current (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) and outputs it to the output current estimation circuit 22.

[0051] Next, the current detection timing determination method in the turn-off / turn-on determination unit 212 will be described in detail below.

[0052] As described above, the turn-off / turn-on determination unit 212 in the first current detection circuit 21 of each phase and each arm receives the gate command V G At this time, the timing at which the PWM control state of the arm satisfies the condition of (Equation 7) described above, that is, the timing at which the load current does not increase or decrease during the off period from after the switching element 101 is turned off until before it is turned on, is determined.

[0053] A specific example of the above-mentioned specific pulse conditions will be explained below using examples of gate command and output current waveforms shown in Figure 5. In Figure 5, (a) shows the gate command V for the upper arm of each of the U, V, and W phases. G_UU , V G_VU , V G_WU(b) shows an example of the waveform of the gate command V for the lower arm of each of the U, V, and W phases. G_UL , V G_VL , V G_WL 5(a) and 5(b) show waveform examples in which the waveforms of the gate commands are offset from each other in the vertical direction so that the waveforms of the gate commands can be seen. Also, (c) shows the output current I of each phase output from the power conversion device 1 in response to the gate commands of (a) and (b). outU , I outV , I outW (d) shows an example of the waveform of the current flowing through the U-phase (U-phase upper arm current I UU , U-phase lower arm current I UL ) waveform example is shown.

[0054] For example, in FIG. 5, the U-phase output current I outU In each of the sections 51 to 56 shown in FIG. 5C, the upper arm gate command V of the U phase relative to the gate commands of the other phases is G_UU and lower arm gate command V G_UL The pulse width of and the U-phase output current I outU The turn-off / turn-on determination unit 212 sets U-phase pulse conditions U-(I) to U-(V) according to these combinations, and detects the current at different timings for each pulse condition.

[0055] In addition, in FIG. 5, the U-phase output current I outU The sections 51 to 56 and pulse conditions U-(I) to U-(V) for the V phase are shown in the figure, but similarly for the V phase, the upper arm gate command V for the V phase relative to the gate commands for the other phases is G_VU and lower arm gate command V G_VL The magnitude of the pulse width and the V-phase output current I outV The pulse conditions V-(I) to V-(V) for the V phase can be set according to the combination with the polarity of the W phase. Similarly, for the W phase, the upper arm gate command V for the W phase relative to the gate commands of the other phases can be set. G_WU and lower arm gate command V G_WL The pulse width of the W-phase output current I outWThe pulse conditions W-(I) to W-(V) of the W phase can be set according to the combination with the polarity of the

[0056] Figure 6 is a table summarizing the pulse conditions and current detection timing for each phase. In Figure 6, Table 61 shows the U-phase pulse conditions U-(I) to U-(V) and their respective current detection timings, Table 62 shows the V-phase pulse conditions V-(I) to V-(V) and their respective current detection timings, and Table 63 shows the W-phase pulse conditions W-(I) to W-(V) and their respective current detection timings.

[0057] In the first current detection circuit 21 provided for each of the upper and lower arms of the U-phase, V-phase, and W-phase, a turn-off / turn-on determination unit 212 determines whether or not a gate command V is output from the control device 20. G 6 applies based on the pulse conditions in Fig. 6. Then, the timing for reading the output of the integration circuit 106 is changed to match the timing for detecting the current under the applicable pulse condition, thereby setting the integration period of the integration circuit 106.

[0058] 6, when one of the U, V, and W phases corresponds to pulse condition U-(V), V-(V), or W-(V), the other two phases correspond to either U-(I) to U-(IV), V-(I) to V-(IV), or W-(I) to W-(IV). Therefore, for a phase that corresponds to pulse condition U-(V), V-(V), or W-(V), the output current of that phase can be obtained using the calculation results of the first current detection circuit 21 for the other two phases.

[0059] Next, the details of the U-phase pulse conditions U-(I) to U-(V) shown in Table 61 of Figure 6 will be explained below with reference to the enlarged views of each section of Figure 5 shown in Figures 7A to 7D, respectively.

[0060] [Section 51: Pulse condition U-(I)] The pulse condition U-(I) is the gate command V G_UU , V G_VU , V G_WU Pulse width PW of the off period UU_OFF , P.W. VU_OFF , P.W.WU_OFF Among them, the pulse width PW of the U-phase upper arm (UU arm) UU_OFF is minimum, and the U-phase output current I outU The polarity of the U-phase winding L u 7A is an enlarged view of a portion of section 51 in FIG. 5 that includes the period that corresponds to this pulse condition U-(I).

[0061] 7A, in section 51, the value of the current flowing through the UU arm does not change during the period from when the switching element 101 of the UU arm is turned off until it is turned on again (the off period of the UU arm). The reason for this is as follows.

[0062] In order to prevent the U-phase current from changing during the OFF period of the UU arm, the U-phase winding L of the motor 3, which is the U-phase load, must be turned ON during this period. u There must be no voltage applied across the U-phase output current I outU When the polarity of is positive, the switching element 101 of the UU arm is turned off, and the U-phase winding L u At this time, if either the V-phase upper arm (VU arm) or the W-phase upper arm (WU arm) is on, the V-phase or W-phase output voltage will be at a high potential, and the U-phase winding L u On the other hand, when the VU arm and WU arm are both OFF and the V-phase lower arm (VL arm) and W-phase lower arm (WL arm) are both ON, the output voltages of both the V-phase and W-phase are at low potentials. u No high voltage is applied to the U-phase output current I outU does not change.

[0063] In PWM control, when a certain carrier period is considered, as shown in FIG. 5, the gate command V G_UU , V G_VU , V G_WUOn the other hand, the gate command V for each arm (UL, VL, WL arm) on the low potential side is generated as follows: G_UL , V G_VL , V G_WL In the case of the MOSFET, each pulse on the high potential side is inverted, and a dead time is ensured so that the upper and lower arms of the same phase do not turn on at the same time.

[0064] As shown in FIG. 7A, in section 51, the gate command V G_UU , V G_VU , V G_WU Among them, the gate command V of the UU arm G_UU , and the pulse width PW UU_OFF At this time, the VU arm and WU arm are in the OFF state, the VL arm and WL arm are in the ON state, and the switching element 101 of the UU arm is turned OFF. After that, the pulse width PW UU_OFF That is, when the pulse condition U-(I) is satisfied, the gate command V G_UU During the off period, the U-phase winding L u When no high voltage is applied to the U-phase output current I outU Therefore, the U-phase output current I before turn-off and after turn-on outU can be considered to be the same in magnitude, and the condition for formula 7 is satisfied.

[0065] From the above explanation, when the pulse condition U-(I) is met, the first current detection circuit 21 provided for the UU arm detects the output voltage V out and read this output voltage V out Based on this, the U-phase upper arm current I UU At this time, the output current estimation circuit 22 can obtain the U-phase upper arm current I UU The value of U-phase output current I outU can be output as an estimated result.

[0066] When determining the pulse condition U-(I) in the first current detection circuit 21, the U-phase output current I outU The polarity of the apparent source current estimation value I before correction calculated by the source current estimation unit 211 using (Equation 4), for example, S_est This can be done in the same way when determining other pulse conditions.

[0067] [Section 56: Pulse Condition U-(II)] The pulse condition U-(II) is the same as the pulse condition U-(I) in terms of the pulse width, and the U-phase output current I outU The polarity of the U-phase winding L u This is a condition in which current flows from the power source 1 to the power conversion device 1. Fig. 7B is an enlarged view of a part of the section 56 in Fig. 5 that includes the period that corresponds to this pulse condition U-(II).

[0068] 7B, in section 56, during the off period of the UU arm, the value of the current flowing through the UU arm does not change during the period from when the switching element 101 of the UL arm is turned on until it is turned off again. The reason for this is as follows.

[0069] As shown in FIG. 7B, in section 56, the gate command V G_UL , V G_VL , V G_WL Among them, the gate command V of the UL arm G_UL The pulse width PW during the ON period UL_ON becomes minimum. At this time, even after the switching element 101 of the UU arm is turned off, current flows in the UU arm via the freewheeling diode 102 of the UU arm, and the current in the UU arm is cut off in response to the turning on of the switching element 101 of the UL arm, not the switching element 101 of the UU arm. After that, in response to the turning off of the switching element 101 of the UL arm, the current in the UU arm is conducted again. In other words, when the pulse condition U-(II) is satisfied, the gate command V of the UL arm G_UL During the ON period of the U-phase winding L u When no high voltage is applied to the U-phase output current I outUTherefore, the U-phase output current I before turn-off and after turn-on outU can be considered to be the same in magnitude, and the condition for formula 7 is satisfied.

[0070] From the above explanation, when the pulse condition U-(II) is met, the first current detection circuit 21 provided for the UU arm detects the output voltage V in synchronization with the turn-on period and the turn-off period of the switching element 101 of the UL arm, or in synchronization with the period from turn-on to turn-off of the switching element 101 of the UL arm. out and read this output voltage V out Based on this, the U-phase upper arm current I UU At this time, the output current estimation circuit 22 can obtain the U-phase upper arm current I output from the first current detection circuit 21, as in the case of the pulse condition U-(I). UU The value of U-phase output current I outU can be output as an estimated result.

[0071] [Section 53: Pulse Condition U-(III)] The pulse condition U-(III) is the gate command V G_UL , V G_VL , V G_WL Pulse width PW of the off period UL_OFF , P.W. VL_OFF , P.W. WL_OFF Among them, the pulse width PW of the U-phase lower arm (UL arm) UL_OFF is minimum, and the U-phase output current I outU This is a condition where the polarity of is positive. That is, compared to the above-mentioned pulse conditions U-(I) and U-(II), this differs in that it targets the lower arm. Figure 7C is an enlarged view of a portion of section 53 in Figure 5 that includes the period corresponding to this pulse condition U-(III).

[0072] 7C, in section 53, during the off-period of the UL arm, the value of the current flowing through the UL arm does not change during the period from when the switching element 101 of the UU arm is turned on until it is turned off again. The reason for this is as follows.

[0073] As shown in FIG. 7C, in section 53, the gate command V G_UU , V G_VU , V G_WU Among them, the gate command V of the UU arm G_UU The pulse width PW during the ON period UU_ON becomes minimum. At this time, even after the switching element 101 of the UL arm is turned off, current flows in the UL arm via the freewheeling diode 102 of the UL arm, and the current in the UL arm is cut off in response to the turning on of the switching element 101 of the UU arm, not the switching element 101 of the UL arm. After that, in response to the turning off of the switching element 101 of the UU arm, the current in the UL arm is conducted again. In other words, when the pulse condition U-(III) is satisfied, the gate command V of the UU arm G_UU During the on-period, the gate command V of the UL arm under pulse condition U-(II) G_UL As in the on-period of U-phase winding L u When no high voltage is applied to the U-phase output current I outU Therefore, the U-phase output current I before turn-off and after turn-on outU can be considered to be the same in magnitude, and the condition for formula 7 is satisfied.

[0074] From the above explanation, when the pulse condition U-(III) is met, the first current detection circuit 21 provided for the UL arm detects the output voltage V out and read this output voltage V out Based on this, the U-phase lower arm current I UL At this time, the output current estimation circuit 22 can obtain the U-phase lower arm current I output from the first current detection circuit 21. UL The polarity of -I was reversed. UL The value of U-phase output current I outU can be output as an estimated result.

[0075] [Section 54: Pulse Condition U-(IV)] The pulse condition U-(IV) is the same as the pulse condition U-(III) in terms of the pulse width, and the U-phase output current I outU 7D is an enlarged view of a portion of section 54 in FIG. 5 that includes the period that corresponds to this pulse condition U-(IV).

[0076] As shown in FIG. 7D, in the section 54, the gate command V G_UL In other words, when the pulse condition U-(IV) is satisfied, the gate command V G_UL During the off period, the U-phase winding L u When no high voltage is applied to the U-phase output current I outU Therefore, the U-phase output current I before turn-off and after turn-on outU can be considered to be the same in magnitude, and the condition for formula 7 is satisfied.

[0077] From the above explanation, when the pulse condition U-(IV) is met, the first current detection circuit 21 provided for the UL arm detects the output voltage V out and read this output voltage V out Based on this, the U-phase lower arm current I UL At this time, the output current estimation circuit 22 can obtain the U-phase lower arm current I output from the first current detection circuit 21. UL The polarity of -I was reversed. UL The value of U-phase output current I outU can be output as an estimated result.

[0078] [Sections 52 and 55: Pulse Condition U-(V)] The pulse condition U-(V) is the pulse width PW of the UU arm and the UL arm. UU_OFF , P.W. UL_OFF In this case, both the UU arm and the UL arm have a gate command VG_UU , V G_UL During the off period of the U-phase winding L u A high voltage is applied to the U-phase output current I outU Therefore, the condition of (Equation 7) does not hold for the U-phase current. On the other hand, for the remaining V-phase and W-phase, the pulse width of the on or off period is minimum in either the upper arm or lower arm, and each corresponds to one of the pulse conditions V-(I) to V-(IV) and W-(I) to W-(IV) shown in Tables 62 and 63 in FIG. 6, respectively, so the condition of (Equation 7) is satisfied. Therefore, in this case, the output current estimation circuit 22 estimates the V-phase output current I obtained by the first current detection circuit 21 corresponding to the upper arm or lower arm of the V-phase. outV and the W-phase output current I obtained by the first current detection circuit 21 corresponding to the upper arm or lower arm of the W-phase. outW Based on the value of and the fact that the sum of the output currents of each phase is 0, I outU =-(I outV +I outW ) can be calculated.

[0079] In the above, the U-phase pulse conditions U-(I) to U-(V) and the U-phase output current I outU The method for estimating the V-phase output current I has been explained, but for the other V-phase and W-phase, it is similarly determined which of the pulse conditions V-(I) to V-(V) and W-(I) to W-(V) applies to each, and the V-phase output current I outV and W-phase output current I outW can be estimated.

[0080] 8 is an explanatory diagram of the effect of applying the present invention. Fig. 8 shows an example of a case where, for the output current of each phase output from the power conversion device 1, a current waveform of each phase estimated using the current detection result in which the parasitic resistance error has been corrected by the first current detection circuit 21 of this embodiment, and a current waveform of each phase estimated without correcting the parasitic resistance error are each calculated. From the current waveforms in Fig. 8 , it can be confirmed that by applying the first current detection circuit 21 of this embodiment to estimate the output current of each phase, the deviation from the actual output current of the power conversion device 1 is reduced compared to the case in which the parasitic resistance error is not corrected.

[0081] 9 is a diagram showing how the magnitude of the relative error of the estimated current with respect to the true output current changes when the resistance value of the parasitic resistance 104 is changed. In a conventional method of estimating the output current from the integral value obtained by the integrating circuit 106 without considering the error due to the parasitic resistance 104, the current estimation error increases as the resistance value of the parasitic resistance 104 increases. On the other hand, in a method of estimating the output current by correcting the error due to the parasitic resistance 104, as in the first current detection circuit 21 of this embodiment, the current estimation error can be suppressed without increasing even if the resistance value of the parasitic resistance 104 increases.

[0082] According to the first embodiment of the present invention described above, the following advantageous effects are achieved.

[0083] (1) The power conversion device 1 has a switching element 101, an inductance component 103 connected in series to the source electrode, which is the main electrode of the switching element 101, and a parasitic resistance 104, and an integral value of the voltage generated across the inductance component 103 and the parasitic resistance 104 (output voltage V out ), and the integral value (output voltage V out ), a current I flows through the source electrode of the switching element 101. S The first current detection circuit 21 detects a first integral value (output voltage V out ), and the second integral value (output voltage V out ), and a first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ) is calculated. In this way, the current flowing through the switching element 101 provided in the power conversion device 1 can be estimated with high accuracy.

[0084] (2) The power conversion device 1 includes a plurality of switching elements 101, and a first current detection circuit 21 is provided for each of the plurality of switching elements 101. The power conversion device 1 detects a first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL ), the output current of the power conversion device 1 (U-phase output current I outU , V-phase output current I outV , W-phase output current I outW ) is provided. In this way, the output current of the power conversion device 1 can be estimated with high accuracy from the estimation result of the current flowing through each switching element 101.

[0085] (3) The switching element 101 controls the three-phase AC current (U-phase output current I outU , V-phase output current I outV , W-phase output current I outW The output current estimation circuit 22 is provided for each of the upper and lower arms of each phase (U-phase, V-phase, W-phase). The output current estimation circuit 22 is provided for each of the gate commands (U-phase upper arm gate command V G_UU , U-phase lower arm gate command V G_UL , V-phase upper arm gate command V G_VU , V-phase lower arm gate command V G_VL , W-phase upper arm gate command V G_WU , W-phase lower arm gate command V G_WL ), the upper arm or lower arm of any two phases is selected according to Tables 61 to 63 of FIG. 6 , and the first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current IWU , W-phase lower arm current I WL ), the output current of each phase of the power conversion device 1 (U-phase output current I outU , V-phase output current I outV , W-phase output current I outW ) is estimated. In this way, it is possible to sequentially and appropriately select the arms that satisfy the condition for formula (7), and accurately estimate the current flowing through each phase and each arm, regardless of the current error due to the voltage integral of the parasitic resistance 104. As a result, it is possible to accurately estimate the output current of the power conversion device 1.

[0086] Second Embodiment Fig. 10 is a diagram showing an example of the configuration of a power conversion device according to a second embodiment of the present invention. The power conversion device 1A shown in Fig. 10 further includes a Hall sensor 30 in addition to the power conversion device 1 described in the first embodiment, so that the motor is controlled using the current value detected by the Hall sensor 30 and an abnormality in the Hall sensor 30 can be detected. The following describes the power conversion device 1A of this embodiment, focusing on the differences from the first embodiment.

[0087] The power conversion device 1A of this embodiment includes a Hall sensor 30 as a second current detection circuit that detects the output current of each phase. The Hall sensor 30 is used as a main current sensor that is used by the control signal generation circuit 23 of the control device 20 for motor control, and includes Hall elements 31U, 31V, and 31W provided in the U phase, V phase, and W phase, respectively, and a Hall IC 32 that outputs a second current value corresponding to the current detection result of each phase based on the sensor signals output from these Hall elements 31U to 31W.

[0088] Furthermore, in the power conversion device 1A of the present embodiment, the control device 20 includes the first current detection circuit 21, the output current estimation circuit 22, the control signal generation circuit 23, and the communication connector 24 described in the first embodiment, and further includes an abnormality detection circuit 25. In the example of Fig. 10, only the configuration of the inverter circuit 10 and the control device 20 related to the W phase is shown, and the U phase and the V phase are not shown, but these are similar to the W phase.

[0089] In this embodiment, the first current detection circuit 21, which estimates the current value of each phase and each arm by the di / dt integration method, is used as a sub-current sensor. The output current value of each phase estimated by the output current estimation circuit 22 based on the current value of each phase and each arm calculated by the first current detection circuit 21, and the second current value representing the output current of each phase detected by the second current detection circuit (Hall sensor 30) are input to the abnormality detection circuit 25 in the control device 20. In the following, the output current value of each phase output from the output current estimation circuit 22 (U-phase output current I outU , V-phase output current I outV , W-phase output current I outW ) to the first current value I out1 , the output current value of each phase output from the Hall sensor 30 is set to the second current value I out2 and respectively.

[0090] The abnormality detection circuit 25 detects the first current value I out1 and the second current value I out2 and based on the comparison result, it is determined whether or not there is an abnormality in the Hall sensor 30. If it is determined that there is no abnormality, the second current value I out2 is used as the normal output current detection value, and is output as the control current value to the control signal generation circuit 23. On the other hand, if it is determined that there is an abnormality in the Hall sensor 30, the first current value I out1 is adopted as the detected value of the normal output current and is output as the control current value to the control signal generation circuit 23. At this time, an abnormality signal indicating the occurrence of an abnormality in the Hall sensor 30 may also be sent to a higher-level system via the communication connector 24. Based on this abnormality signal, the higher-level system controls the operation of the power conversion device 1A (continue operation, stop operation, ease conditions, etc.) or issues a warning to the user.

[0091] 11A and 11B are diagrams showing an example of a flowchart illustrating a process flow when the abnormality detection circuit 25 according to the second embodiment of the present invention performs an abnormality determination. In this embodiment, the abnormality detection circuit 25 performs the process shown in FIGS. 11A and 11B at predetermined intervals, for example, to determine an abnormality in the Hall sensor 30.

[0092] 11A, it is determined whether or not there is an abnormality determination command from the host system. If there is an abnormality determination command from the host system, the process proceeds to step S102, and if there is no abnormality determination command, the process proceeds to step S111.

[0093] In step S102, the second current value I output from the Hall sensor 30 is out2 and the first current value I output from the output current estimation circuit 22. out1 The difference between the two is calculated, and the absolute value of the difference is taken as the difference value ΔI 21 Let's say.

[0094] In step S103, the difference value ΔI calculated in step S102 is 21 It is determined whether the difference value ΔI is equal to or smaller than a preset allowable difference. 21 If the difference ΔI is equal to or smaller than the allowable difference, it is determined that there is no abnormality in either the first current detection circuit 21 or the Hall sensor 30, and the process proceeds to step S111. 21 If the difference is greater than the allowable difference, it is determined that there is an abnormality in at least one of the first current detection circuit 21 and the Hall sensor 30, and the process proceeds to step S104. The allowable difference used in the determination in step S103 is set according to the detection accuracy of the Hall sensor 30, and is, for example, twice the error specified in the specifications of the Hall sensor 30.

[0095] In step S104, the first current value I out1 and the second current value I out2 For each of the U-phase, V-phase, and W-phase currents, the sum I sum1 , I sum2 Calculate.

[0096] In step S105, the first current value I calculated in step S104 is out1 Sum of I sum1 It is determined whether the first current value I is equal to or smaller than a predetermined allowable total error. out1 Sum of I sum1 If the sum error is equal to or smaller than the allowable sum error, the process proceeds to step S106, and if the sum error is greater than the allowable sum error, the first current detection circuit 21 is determined to be abnormal, and the process proceeds to step S112 in FIG. 11B.

[0097] In step S106, the second current value I calculated in step S104 is out2 Sum of I sum2 It is determined whether the second current value I is equal to or less than a predetermined allowable total error. out2 Sum of I sum2 If the sum error is equal to or smaller than the allowable sum error, the process proceeds to step S107, and if the sum error is greater than the allowable sum error, the Hall sensor 30 is determined to be abnormal and the process proceeds to step S110.

[0098] If both the first current detection circuit 21 and the Hall sensor 30 are normal, the first current value I out1 and the second current value I out2 Sum of I sum1 , I sum2 Ideally, each of these is 0, but in reality, an error occurs between them due to the displacement current that flows through the wiring of the inverter circuit 10 and the parasitic capacitance of the motor 3. Therefore, in the processes of steps S105 and S106, the sum I sum1 , I sum2 An allowable total error is set for each of these, and if this error is not exceeded, it is determined that there is no abnormality in the first current detection circuit 21 or the Hall sensor 30. This allowable total error is set, for example, according to the error determined in the specifications of the Hall sensor 30, and is, for example, a value obtained by adding a displacement current component to three times the error. The magnitude of the displacement current component is approximately 1 to 2 A, assuming, for example, a parasitic capacitance of 100 pF and a voltage change rate of 10 to 20 kV / μs during switching in the switching element 101.

[0099] However, in steps S105 and S106, the first current value I out1 and the second current value I out2 Sum of I sum1 , I sum2If it is determined that all of the errors are equal to or less than the allowable total error, it is not possible to determine at this point whether the first current detection circuit 21 or the Hall sensor 30 is abnormal. This situation may occur, for example, when the accuracy of the Hall elements 31U, 31V, and 31W provided in the U-phase, V-phase, and W-phase, respectively, in the Hall sensor 30 deteriorates to the same extent. In such a case, the following steps S107 and S108 are executed to determine whether the first current detection circuit 21 or the Hall sensor 30 is abnormal.

[0100] In step S107, the initial values ​​I of the first current value and the second current value at the beginning of operation of the power conversion device 1A are calculated. Ini1 , I Ini2 and using these, the first current value I out1 and the first current initial value I Ini1 Absolute value of the difference between |I out1 -I Ini1 |, and the second current value I out2 and the second current initial value I Ini2 Absolute value of the difference between |I out2 -I Ini2 At this time, the initial value I Ini1 , I Ini2 For example, the current value at which the motor control conditions at the beginning of operation are equivalent to the control conditions at the time of abnormality determination is obtained by referring to a preset lookup table. In the case of vector control, the control conditions include a torque command or a current command, a current detected current value, a motor angular velocity and angle, and a voltage applied from the storage battery 2 to the inverter circuit 10. This lookup table can be realized by storing data on each control condition in advance, for example, before shipping the power conversion device 1A or while the product is in operation, in a memory within the control device 20.

[0101] In step S108, the absolute difference value |I out1 -I Ini1 | and the absolute difference value |I out2 -I Ini2 | and determine which absolute difference value is larger. As a result, the absolute difference value |I out1 -I Ini1If | is larger, it is determined that the first current detection circuit 21 is abnormal, and the process proceeds to step S109. out2 -I Ini2 If | is larger, it is determined that the Hall sensor 30 is abnormal, and the process proceeds to step S110.

[0102] In step S109, it is determined that some abnormality has occurred in the first current detection circuit 21, and as a result, the first current value I output from the output current estimation circuit 22 is out1 In this case, the abnormality detection circuit 25 determines that the second current value I output from the Hall sensor 30 is abnormal. out2 is selected as a normal current detection result and output to the control signal generation circuit 23. The control signal generation circuit 23 selects this second current value I out2 The gate command for each phase and each arm is generated using

[0103] In step S110, it is determined that some abnormality has occurred in the Hall sensor 30, and as a result, the second current value I output from the Hall sensor 30 is out2 In this case, the abnormality detection circuit 25 determines that the first current value I output from the output current estimation circuit 22 is abnormal. out1 is selected as a normal current detection result and output to the control signal generation circuit 23. The control signal generation circuit 23 selects this first current value I out1 The gate command for each phase and each arm is generated using

[0104] In step S111, it is determined that no abnormality has occurred in either the first current detection circuit 21 or the Hall sensor 30, and the first current value I output from the output current estimation circuit 22 is out1 and the second current value I output from the Hall sensor 30. out2 In this case, the abnormality detection circuit 25 determines that both the second current value I out2 is selected as a normal current detection result and output to the control signal generation circuit 23. The control signal generation circuit 23 selects this second current value I out2 The gate command for each phase and each arm is generated using

[0105] Once any one of steps S109 to S111 has been executed, the processing of FIGS. 11A and 11B ends.

[0106] In step S112 of FIG. 11B, similarly to step S106 of FIG. 11A, the second current value I out2 Sum of I sum2 It is determined whether the second current value I is equal to or less than a predetermined allowable total error. out2 Sum of I sum2 If the sum error is equal to or smaller than the allowable sum error, the process proceeds to step S117, and if the sum error is greater than the allowable sum error, the Hall sensor 30 is determined to be abnormal and the process proceeds to step S113.

[0107] When the process proceeds to step S113, that is, when the first current value I out1 Sum of I sum1 and the second current value I out2 Sum of I sum2 If both of the errors are larger than the allowable total error, it is determined that both the first current detection circuit 21 and the Hall sensor 30 are abnormal. Even in such a case, in preparation for the case where the operation of the power conversion device 1A cannot be stopped immediately, it is necessary to output a current value from the abnormality detection circuit 25 to the control signal generation circuit 23. out1 and the second current value I out2 Therefore, in steps S113 and S114, the first current value I is calculated by the same processes as in steps S107 and S108 in FIG. out1 and the second current value I out2 Among these, the initial value I Ini1 , I Ini2 The control circuit 23 selects the control current value with the smallest possible difference from the control current value.

[0108] Specifically, in step S113, the first current value I out1 and the first current initial value I Ini1 Absolute value of the difference between |I out1 -I Ini1 |, and the second current value I out2 and the second current initial value I Ini2 Absolute value of the difference between |I out2 -IIni2 In the following step S114, the absolute difference |I out1 -I Ini1 | and the absolute difference value |I out2 -I Ini2 | and determine which absolute difference value is larger. As a result, the absolute difference value |I out1 -I Ini1 If | is larger, the process proceeds to step S115, and the absolute difference value |I out2 -I Ini2 If | is larger, the process proceeds to step S116.

[0109] In step S115, some abnormality has occurred in both the first current detection circuit 21 and the Hall sensor 30, but the first current value I output from the output current estimation circuit 22 is out1 is the second current value I output from the Hall sensor 30. out2 In this case, the abnormality detection circuit 25 determines that the error is greater than the second current value I out2 and outputs the second current value I to the control signal generating circuit 23. out2 The gate command for each phase and each arm is generated using

[0110] In step S116, some abnormality has occurred in both the first current detection circuit 21 and the Hall sensor 30, but the second current value I output from the Hall sensor 30 is out2 is the first current value I output from the output current estimation circuit 22. out1 In this case, the abnormality detection circuit 25 determines that the error is larger than the first current value I out1 and outputs it to the control signal generating circuit 23. The control signal generating circuit 23 selects the first current value I out1 The gate command for each phase and each arm is generated using

[0111] In step S117, it is determined that some abnormality has occurred in the first current detection circuit 21, and as a result, the first current value I output from the current detection circuit 21 is out1In this case, the abnormality detection circuit 25 determines that the second current value I output from the Hall sensor 30 is abnormal. out2 is selected as a normal current detection result and output to the control signal generation circuit 23. The control signal generation circuit 23 selects this second current value I out2 The gate command for each phase and each arm is generated using

[0112] Once any one of steps S115 to S117 has been executed, the processing of FIGS. 11A and 11B ends.

[0113] In the second embodiment of the present invention described above, the Hall sensor 30, which is the second current detection circuit, is used as a main current sensor, and the first current detection circuit 21 is used as a sub current sensor. However, the main and sub current sensors may be reversed. Furthermore, the second current detection circuit may be something other than the Hall sensor 30.

[0114] According to the second embodiment of the present invention described above, in addition to the effects described in the first embodiment, the following effects are further achieved.

[0115] (4) The power conversion device 1A includes a Hall sensor 30, which is a second current detection circuit for detecting the output current of each phase of the power conversion device 1A, and an output current (first current value I out1 ), and the output current of each phase detected by the Hall sensor 30 (second current value I out2 ) and an abnormality detection circuit 25 that determines whether or not an abnormality has occurred in the Hall sensor 30 based on the comparison result. In this way, while using the Hall sensor 30 as the main current sensor, it is possible to detect any abnormality that has occurred in the Hall sensor 30.

[0116] (5) The second current detection circuit is, for example, the Hall sensor 30 that detects the three-phase AC current output by the power conversion device 1A. This makes it possible to accurately and reliably detect the three-phase AC current output by the power conversion device 1A.

[0117] Third Embodiment Fig. 12 is a diagram showing a configuration example of a power conversion device according to a third embodiment of the present invention. The power conversion device 1B shown in Fig. 12 further includes, in the power conversion device 1 described in the first embodiment, a current sense element 107 and a temperature sensor 108, which are on-chip current sensors formed on the same chip as the switching elements 101 of each phase and each arm, and a second current detection circuit 40 that detects the current flowing through the switching elements 101 based on signals from the on-chip current sensors and outputs a second current value corresponding to the detection result. The second current detection circuit 40 includes a sense current detection circuit 109 that detects a sense current flowing through the current sense element 107, a temperature sensor temperature detection circuit 110 that detects the temperature of the temperature sensor 108, and an on-chip sensor output current estimation circuit 41 that accurately estimates the current of the switching elements 101 from these detected values. In the example of Figure 12, the current sense element 107 and the temperature sensor 108 of the W-phase upper arm power module 100WU, and the sense current detection circuit 109 and the temperature sensor temperature detection circuit 110 connected thereto, respectively, are shown, and the other arms are not shown, but the configuration of each arm is similar to that of the W-phase upper arm.

[0118] In this embodiment, the second current detection circuit 40 estimates the source current value I of the switching element 101 in the on-chip sensor output current estimation circuit 41 based on the detection results of the sense current and the temperature sensor element temperature by the sense current detection circuit 109 of each phase and each arm and the temperature sensor element temperature detection circuit 110. S At this time, the deviation of the sense ratio of the current sense element 107 according to the temperature distribution in the chip caused by the self-heating of the switching element 101 is corrected based on the temperature detection value, and the source current value I is calculated from the sense current value using the corrected sense ratio. S For example, a look-up table showing the sense ratio values ​​obtained in advance for each temperature is stored in the on-chip sensor output current estimation circuit 41, and this look-up table is used to determine the sense ratio corresponding to the temperature detection value. Using the sense ratio thus determined, the source current value I S Calculate.

[0119] In the second current detection circuit 40 of this embodiment, the characteristics (on-resistance, switching loss, thermal resistance, etc.) of the switching element 101 that change depending on the temperature are taken into consideration by the method described above, and the source current value I that flows through the source electrode, which is the main power of the switching element 101, is detected in a manner different from that of the first current detection circuit 21. S can be accurately detected.

[0120] Furthermore, the on-chip sensor output current estimation circuit 41 estimates the source current value I S For example, the source current value I of the upper and lower arms of each phase is calculated based on the S By calculating the difference between these values, the output current value of each phase can be obtained.

[0121] Furthermore, in the power conversion device 1B of this embodiment, the control device 20, like the second embodiment, further includes an abnormality detection circuit 25 in addition to the first current detection circuit 21, the output current estimation circuit 22, the control signal generation circuit 23, and the communication connector 24. In the example of Fig. 12, only the configuration of the inverter circuit 10 and the control device 20 related to the W-phase upper arm is shown, and the W-phase lower arm and the upper and lower arms of the U and V phases are not shown, but these are similar to the W-phase upper arm.

[0122] In this embodiment, as in the second embodiment, the first current detection circuit 21, which estimates the current value of each phase and each arm using the di / dt integration method, is used as a sub-current sensor. The current value of each phase and each arm calculated by the first current detection circuit 21 is output to the control device 20 as the output current value of each phase estimated by the output current estimation circuit 22. In addition, a second current value representing the output current of each phase detected by the second current detection circuit 40 is also output to the control device 20. In the control device 20, the abnormality detection circuit 25 compares these input current values ​​to determine whether or not an abnormality exists in the second current detection circuit 40 or the current sense element 107, as in the second embodiment.

[0123] Furthermore, in this embodiment, an abnormality can be detected even when an abnormality occurs in the characteristics of the switching element 101. For example, when the switching element 101 approaches the end of its power cycle life, the bonding material (e.g., solder or sintered material) between the switching element 101 and the terminals deteriorates, increasing thermal resistance. In such a case, the abnormality detection circuit 25 of this embodiment determines that the second current value is abnormal before the switching element 101 overheats and is destroyed due to the increased thermal resistance. This allows the power cycle life to be detected and prompts the user to take action, such as replacing the part. Furthermore, if there is a change in the turn-on or turn-off threshold of the switching element 101, the sense ratio changes, and the abnormality detection circuit 25 of this embodiment similarly determines that the second current value is abnormal and can detect this. Furthermore, if the switching element 101 is made of SiC or the like, the on-resistance may increase due to bipolar degradation. In this case, the abnormality detection circuit 25 of this embodiment similarly determines that the second current value is abnormal and can detect this.

[0124] According to the third embodiment of the present invention described above, in addition to the effects described in the first embodiment, the following effects are further achieved.

[0125] (6) The power conversion device 1B detects the current I flowing through the source electrode, which is the main electrode of the switching element 101, using a method different from that of the first current detection circuit 21. S and an abnormality detection circuit 25 that compares the first current value calculated by the first current detection circuit 21 with the second current value output from the second current detection circuit 40 and determines whether or not an abnormality has occurred in the second current detection circuit 40 or the switching element 101 based on the comparison result. This makes it possible to detect an abnormality if one has occurred in the second current detection circuit 40 or the switching element 101.

[0126] (7) The switching element 101 includes a current sensing element 107 and a temperature sensing element 108. The second current detection circuit 40 includes a sense current detection circuit 109 that detects a sense current, which is the current of the current sensing element 107, a temperature sensing element temperature detection circuit 110 that detects the temperature of the temperature sensing element 108, and a second current value I out2 ) is provided. In this way, the second current detection circuit 40 can reliably detect the output current of the power conversion device 1B using a method different from that of the first current detection circuit 21.

[0127] (Fourth embodiment) Fig. 13 is a diagram showing an example of the configuration of a power conversion device according to a fourth embodiment of the present invention. The power conversion device 1C shown in Fig. 13 is configured such that, in the power conversion device 1 described in the first embodiment, the terminal temperatures of the source electrodes, which are the main electrodes of the switching elements 101 of each phase and each arm, are estimated and overtemperature is detected based on the estimation results. The power conversion device 1C of this embodiment will be described below, focusing on the differences from the first embodiment.

[0128] In the power conversion device 1C of this embodiment, the control device 20 includes the first current detection circuit 21, the output current estimation circuit 22, the control signal generation circuit 23, and the communication connector 24 described in the first embodiment, as well as a terminal temperature estimation circuit 26 and a terminal over-temperature detection circuit 27. In the example of Fig. 13, only the configuration of the inverter circuit 10 and the control device 20 related to the W phase is shown, and the U phase and the V phase are not shown, but they are similar to those of the W phase.

[0129] In this embodiment, the first current detection circuit 21 detects the first current value (U-phase upper arm current I UU , U-phase lower arm current I UL , V-phase upper arm current I VU , V-phase lower arm current I VL , W-phase upper arm current I WU , W-phase lower arm current I WL), the first current detection circuit 21 further calculates the estimated parasitic resistance value of each phase and each arm based on the first current value. For example, the first current detection circuit 21 calculates the resistance value R of the parasitic resistance 104 by the following (Equation 16) which is a modification of the above-mentioned (Equation 11): Ss can be estimated.

[0130] In (Equation 16), the source current value I S For the resistance R of the parasitic resistor 104, the resistance R of the parasitic resistor 104 can be calculated by the following equation (17) obtained by substituting equation (14) or (15) into equation (16). Ss can be estimated.

[0131] The first current detection circuit 21 provided for each phase and each arm calculates a parasitic resistance estimated value R representing the magnitude of the parasitic resistance 104 of the corresponding switching element 101 by (Equation 17). Ss and outputs it to the terminal temperature estimation circuit 26. The terminal temperature estimation circuit 26 calculates the parasitic resistance estimated value R Ss The terminal temperature estimation circuit 26 estimates the terminal temperature of the source electrode, which is the main electrode of the switching element 101 of each phase and each arm, based on the above, and outputs the estimation result to the terminal over-temperature detection circuit 27. The terminal temperature estimation circuit 26 stores, for example, table data or an approximate expression based on the relationship between the parasitic resistance and the terminal temperature acquired in advance, and by referring to this table data or approximate expression, calculates the parasitic resistance estimated value R Ss The terminal temperature of the source electrode can be estimated from

[0132] The terminal over-temperature detection circuit 27 detects an over-temperature of the source electrode, which is the main electrode of the switching element 101 of each phase and each arm, based on the terminal temperature estimated by the terminal temperature estimation circuit 26. For example, if the estimated value of the terminal temperature exceeds a predetermined allowable temperature, it determines that the source electrode of the switching element 101 is in an over-temperature state and transmits an over-temperature abnormality signal to the upper system via the communication connector 24. If the upper system determines that a control change is necessary in response to this over-temperature abnormality signal, the upper system transmits an abnormality control command to the control signal generation circuit 23, and the control signal generation circuit 23 changes the control to resolve the over-temperature, such as by stopping operation of the power conversion device 1C or easing the operating conditions.

[0133] 13 shows a configuration in which control is changed via a higher-level system, a configuration in which an over-temperature abnormality signal is output directly from the terminal over-temperature detection circuit 27 to the control signal generation circuit 23, and the control signal generation circuit 23 changes the control of the power conversion device 1C in response to this over-temperature abnormality signal may also be used. In this way, by outputting a signal directly from the terminal over-temperature detection circuit 27 to the control signal generation circuit 23 without going through a higher-level system, it is possible to change the control with low delay when quick response is required, such as in an emergency stop.

[0134] According to the fourth embodiment of the present invention described above, in addition to the effects described in the first embodiment, the following effects are further achieved.

[0135] (8) The power conversion device 1C includes a terminal temperature estimation circuit 26 that estimates the terminal temperature of the source electrode, which is the main electrode of the switching element 101. The first current detection circuit 21 calculates the first integral value (output voltage V out ) and the second integral value (output voltage V out ) based on the estimated parasitic resistance R Ss The terminal temperature estimation circuit 26 outputs the estimated parasitic resistance R Ss In this way, the terminal temperature of the main electrode of the switching element 101 provided in the power conversion device 1C can be accurately estimated from the estimation result of the current flowing through the switching element 101.

[0136] (9) The power conversion device 1C includes a terminal overtemperature detection circuit 27 that detects an overtemperature of the source electrode based on the terminal temperature estimated by the terminal temperature estimation circuit 26. This configuration makes it possible to reliably detect an overtemperature abnormality in the switching element 101.

[0137] The present invention is not limited to the various embodiments described above, and includes various modifications. For example, the above-described embodiments have been specifically described to clearly explain the present invention, and are not necessarily limited to those having all of the described configurations. Furthermore, part of the configuration of one embodiment can be replaced with part of the configuration of another embodiment. Furthermore, the configuration of another embodiment can be added to the configuration of one embodiment. Furthermore, part of the configuration of each embodiment can be deleted, and part of another configuration can be added or replaced with part of another configuration.

[0138] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0139] 1, 1A, 1B, 1C: power conversion device, 2: storage battery, 3: motor, 10: inverter circuit, 11: smoothing capacitor, 20: control device, 21: first current detection circuit, 22: output current estimation circuit, 23: control signal generation circuit, 24: communication connector, 25: abnormality detection circuit, 26: terminal temperature estimation circuit, 27: terminal over-temperature detection circuit, 30: hall sensor, 40: second current detection circuit, 41: on-chip sensor output current estimation circuit, 100: power module, 101: switching element, 102: freewheel diode, 103: inductance, 104: parasitic resistance, 105: gate driver, 106: integrator circuit, 107: current sense element, 108: temperature sensor, 109: sense current detection circuit, 110: temperature sensor temperature detection circuit

Claims

1. A power conversion device comprising: a switching element; an integrating circuit that outputs an integral value of a voltage generated across an inductance component and a parasitic resistance connected in series to a main electrode of the switching element; and a first current detection circuit that determines a current flowing through the main electrode of the switching element based on the integral value output from the integrating circuit, wherein the first current detection circuit calculates a first current value indicating the magnitude of the current flowing through the main electrode based on a first integral value output from the integrating circuit in a period before and after the switching element is turned off and a second integral value output from the integrating circuit in a period before and after the switching element is turned on.

2. A power conversion device as described in claim 1, comprising a plurality of the switching elements, the first current detection circuit being provided for each of the plurality of switching elements, and an output current estimation circuit which estimates an output current of the power conversion device based on the first current value for each switching element calculated by the first current detection circuit.

3. A power conversion device according to claim 2, wherein the switching elements are provided for upper and lower arms of each phase of a three-phase AC current output by the power conversion device, and the output current estimation circuit selects either the upper arm or the lower arm of any two phases based on a combination of pulse widths of gate commands input to the switching elements of the upper and lower arms of each phase, and estimates the output current of each phase of the power conversion device based on the first current value output from the first current detection circuit provided for the switching elements of each selected arm.

4. A power conversion device as claimed in claim 2 or 3, comprising: a second current detection circuit which detects an output current of each phase of said power conversion device; and an abnormality detection circuit which compares the output current of each phase estimated by said output current estimation circuit with the output current of each phase detected by said second current detection circuit, and determines whether or not an abnormality has occurred in said second current detection circuit based on the comparison result.

5. A power conversion device according to claim 4, wherein the second current detection circuit is a Hall sensor that detects the three-phase AC current output by the power conversion device.

6. A power conversion device according to any one of claims 1 to 3, comprising: a second current detection circuit that detects the current flowing through the main electrode of the switching element using a method different from that of the first current detection circuit and outputs a second current value corresponding to the detection result; and an abnormality detection circuit that compares the first current value calculated by the first current detection circuit with the second current value output from the second current detection circuit and determines whether or not an abnormality has occurred in the second current detection circuit or the switching element based on the comparison result.

7. A power conversion device according to claim 6, wherein the switching element comprises a current sense element and a temperature sensing element, and the second current detection circuit comprises a sense current detection circuit for detecting a sense current which is the current of the current sense element, a temperature sensing element temperature detection circuit for detecting a temperature sensing element temperature which is the temperature of the temperature sensing element, and an on-chip sensor output current estimation circuit for estimating an output current of the power conversion device based on the sense current and the temperature sensing element temperature.

8. A power conversion device according to any one of claims 1 to 3, comprising a terminal temperature estimation circuit that estimates a terminal temperature of the main electrode, wherein the first current detection circuit outputs a parasitic resistance estimate value representing the magnitude of the parasitic resistance based on the first integral value and the second integral value, and the terminal temperature estimation circuit estimates the terminal temperature of the main electrode based on the parasitic resistance estimate value.

9. A power conversion device according to claim 8, further comprising a terminal over-temperature detection circuit that detects an over-temperature of said main electrodes based on said terminal temperature estimated by said terminal temperature estimation circuit.

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