Semiconductor device and method for producing semiconductor device

Abstract

This semiconductor device comprises: a substrate; a rectangular first semiconductor chip arranged on the substrate; a plurality of spacers arranged around the first semiconductor chip on the substrate; a second semiconductor chip opposing the substrate so as to cover the first semiconductor chip; and an adhesive layer provided on a surface on the first semiconductor chip side of the second semiconductor chip and adhered to the first semiconductor chip and the plurality of spacers. The plurality of spacers include: a first main spacer and a second main spacer respectively disposed on both sides of the first semiconductor chip in a long-side direction of the first semiconductor chip; and a first additional spacer and a second additional spacer respectively disposed on both sides of the first semiconductor chip in a short-side direction of the first semiconductor chip.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device having a dolmen structure and a method for manufacturing the semiconductor device.

[0002] In recent years, there has been a demand for higher integration, smaller size, and faster speeds in the field of semiconductor devices. One type of semiconductor device that has attracted attention is a structure in which a semiconductor chip is stacked on a controller chip disposed on a substrate. For example, Patent Document 1 (JP-A-2005-102626) discloses a semiconductor device having a dolmen structure, including a substrate, a first semiconductor chip disposed on the surface of the substrate, a plurality of spacers disposed on the surface of the substrate around the first semiconductor chip, a second semiconductor chip disposed above the first semiconductor chip, and an adhesive layer sandwiched between the second semiconductor chip, the first semiconductor chip, and the plurality of spacers. In this semiconductor device, the first semiconductor chip and the second semiconductor chip are bonded together by the adhesive layer, and the plurality of spacers are disposed only on both sides of the first semiconductor chip in the direction of the long side of the second semiconductor chip.

[0003] International Publication No. 2020 / 218526

[0004] The inventors conducted a detailed analysis of a semiconductor device manufactured using a rectangular (oblong) first semiconductor chip and found that voids occurred between the first semiconductor chip and the adhesive layer.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress the occurrence of voids between the first semiconductor chip and the adhesive layer.

[0006] The inventors of the present invention conducted further intensive research into the above-mentioned problem and discovered the following: First, a rectangular first semiconductor chip and a pair of spacers arranged on both sides of the first semiconductor chip in the direction of its long side were bonded to a substrate, and an adhesive layer was attached to one surface of a second semiconductor chip. Next, a second semiconductor chip was bonded to the surfaces of the first semiconductor chip and the pair of spacers with an adhesive layer so that the first semiconductor chip was covered by the second semiconductor chip, and the adhesive layer was cured, thereby manufacturing a semiconductor device. After that, the semiconductor device was analyzed using an ultrasonic microscope and a void extending in the direction of the long side of the first semiconductor chip was found between the first semiconductor chip and the adhesive layer in the center of the short side of the first semiconductor chip.

[0007] Based on the location and shape of the discovered voids, it is inferred that the voids were generated for the following reasons: The adhesive layer attached to the second semiconductor chip improves the shape retention of the adhesive layer. Furthermore, the protrusion length of the second semiconductor chip and the adhesive layer relative to the first semiconductor chip in the short-side direction of the first semiconductor chip is not particularly long. For this reason, it was previously believed that the second semiconductor chip and the adhesive layer would not sag toward the substrate on both sides of the short-side direction of the first semiconductor chip. However, in reality, the length of the first semiconductor chip in the long-side direction is longer than the length of the first semiconductor chip in the short-side direction, making the second semiconductor chip and the adhesive layer more likely to sag toward the substrate on both sides of the short-side direction of the first semiconductor chip. It is inferred that this sagging of the second semiconductor chip and the adhesive layer caused the adhesive layer to lift off the first semiconductor chip in the center of the short-side direction of the first semiconductor chip, resulting in the generation of a void extending in the long-side direction of the first semiconductor chip between the first semiconductor chip and the adhesive layer in the center of the short-side direction of the first semiconductor chip.

[0008] From these results, it was found that by arranging spacers on both sides of the short side of the first semiconductor chip, it is possible to prevent the second semiconductor chip and the adhesive layer on both sides of the short side of the first semiconductor chip from sagging toward the substrate, thereby preventing the occurrence of voids between the first semiconductor chip and the adhesive layer.

[0009] That is, the semiconductor device according to the present disclosure comprises a substrate, a rectangular first semiconductor chip arranged on the substrate, a plurality of spacers arranged around the first semiconductor chip on the substrate, a second semiconductor chip facing the substrate so as to cover the first semiconductor chip, and an adhesive layer provided on the surface of the second semiconductor chip facing the first semiconductor chip and adhered to the first semiconductor chip and the plurality of spacers, wherein the plurality of spacers include a first main spacer and a second main spacer arranged on both sides of the first semiconductor chip in the direction of the long side of the first semiconductor chip, and a first additional spacer and a second additional spacer arranged on both sides of the first semiconductor chip in the direction of the short side of the first semiconductor chip.

[0010] In this semiconductor device, not only are first main spacers and second main spacers disposed on both sides of the first semiconductor chip in the long-side direction of the first semiconductor chip, but first additional spacers and second additional spacers are also disposed on both sides of the first semiconductor chip in the short-side direction of the first semiconductor chip. Therefore, when manufacturing the semiconductor device, not only can the second semiconductor chip and adhesive layer on both sides of the first semiconductor chip in the long-side direction be prevented from sagging toward the substrate, but also the second semiconductor chip and adhesive layer on both sides of the first semiconductor chip in the short-side direction be prevented from sagging toward the substrate. This can prevent voids from occurring between the first semiconductor chip and the adhesive layer.

[0011] In the semiconductor device described above, the height of the first additional spacer and the second additional spacer relative to the substrate may be equal to or greater than the height of the first semiconductor chip relative to the substrate. In this semiconductor device, the height of the first additional spacer and the second additional spacer relative to the substrate is equal to or greater than the height of the first semiconductor chip relative to the substrate, thereby further suppressing the generation of voids between the first semiconductor chip and the adhesive layer.

[0012] In the semiconductor device described above, the height of the first additional spacer and the second additional spacer relative to the substrate may be greater than the height of the first semiconductor chip relative to the substrate. In this semiconductor device, the height of the first additional spacer and the second additional spacer relative to the substrate is greater than the height of the first semiconductor chip relative to the substrate, which further suppresses the generation of voids between the first semiconductor chip and the adhesive layer.

[0013] In the semiconductor device described above, the lengths of the first and second additional spacers in the long side direction may be 80% to 120% of the length of the first semiconductor chip in the long side direction. In this semiconductor device, the lengths of the first and second additional spacers in the long side direction are 80% to 120% of the length of the first semiconductor chip in the long side direction, so that sagging of the second semiconductor chip and adhesive layer on both sides of the first semiconductor chip in the short side direction toward the substrate can be appropriately suppressed during manufacturing of the semiconductor device. This further suppresses the occurrence of voids between the first semiconductor chip and the adhesive layer.

[0014] In the semiconductor device described above, the distance between the first semiconductor chip and the first additional spacer and the second additional spacer may be shorter than the distance between the first semiconductor chip and the first main spacer and the second main spacer. In this semiconductor device, the distance between the first semiconductor chip and the first additional spacer and the second additional spacer is shorter than the distance between the first semiconductor chip and the first main spacer and the second main spacer, making it easier to arrange the first additional spacer and the second additional spacer between the substrate and the second semiconductor chip even if the second semiconductor chip is short in the short side direction.

[0015] In the semiconductor device described above, the first additional spacer and the second additional spacer may protrude in a short-side direction from the second semiconductor chip in a plan view. In this semiconductor chip, since the first additional spacer and the second additional spacer protrude in a short-side direction from the second semiconductor chip in a plan view, it becomes easier to arrange the first additional spacer and the second additional spacer between the substrate and the second semiconductor chip even if the second semiconductor chip is short in the short-side direction.

[0016] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: adhering, onto a substrate, a rectangular first semiconductor chip; a first main spacer and a second main spacer arranged on both sides of the first semiconductor chip in the direction of the long side of the first semiconductor chip; and a first additional spacer and a second additional spacer arranged on both sides of the first semiconductor chip in the direction of the short side of the first semiconductor chip; attaching an uncured adhesive layer to one side of the second semiconductor chip; adhering the second semiconductor chip to the surfaces of the first semiconductor chip, the first main spacer, the second main spacer, the first additional spacer, and the second additional spacer using the adhesive layer so that the first semiconductor chip is covered by the second semiconductor chip; and curing the adhesive layer.

[0017] In this method for manufacturing a semiconductor device, a semiconductor device is manufactured in which not only first main spacers and second main spacers are disposed on both sides of the first semiconductor chip in the direction of the long side of the first semiconductor chip, but also first additional spacers and second additional spacers are disposed on both sides of the first semiconductor chip in the direction of the short side of the first semiconductor chip. This not only prevents the second semiconductor chip and adhesive layer on both sides of the first semiconductor chip in the direction of the long side from sagging toward the substrate, but also prevents the second semiconductor chip and adhesive layer on both sides of the first semiconductor chip in the direction of the short side from sagging toward the substrate. This prevents the occurrence of voids between the first semiconductor chip and the adhesive layer.

[0018] According to the present disclosure, it is possible to suppress the occurrence of voids between the first semiconductor chip and the adhesive layer.

[0019] FIG. 1 is a schematic plan view showing a semiconductor device according to the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a schematic plan view showing a method for manufacturing a semiconductor device according to the present disclosure. FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 4. FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a schematic plan view showing a method for manufacturing a semiconductor device according to the present disclosure. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a schematic cross-sectional view taken along line IX-IX in FIG. 7. FIG. 10 is a schematic plan view showing a semiconductor device of a comparative example. FIG. 11 is a schematic cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 is a schematic plan view showing a semiconductor device of an example. FIG. 13 is a schematic plan view showing a semiconductor device of a comparative example. 14 is a SAM photograph of the semiconductor devices of Examples 1 to 6 and Comparative Examples 1 to 6. FIG. 15 is a SAM photograph of the semiconductor devices of Examples 7 to 15.

[0020] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In the drawings, identical or corresponding parts are denoted by the same reference numerals, and redundant explanations will be omitted. In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. Furthermore, in this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. Furthermore, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0021] FIG. 1 is a schematic plan view showing a semiconductor device according to the present disclosure. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1 . The semiconductor device 1 shown in FIGS. 1 to 3 is configured as a semiconductor package for a memory such as a NAND flash memory. As shown in FIGS. 1 to 3 , the semiconductor device 1 includes a substrate 2, a rectangular (oblong) controller chip (first semiconductor chip) 3 disposed on the substrate 2, a plurality of spacers 4 disposed around the controller chip 3 on the substrate 2, a memory chip (second semiconductor chip) 5 facing the substrate 2 so as to cover the controller chip 3, and an adhesive layer 6 provided on a surface 5 a of the memory chip 5 facing the controller chip 3 and adhered to the controller chip 3 and the plurality of spacers 4. In addition to these components, the semiconductor device 1 also includes conductive members (not shown) that electrically connect electrodes (not shown) of the substrate 2 to the controller chip 3 and the memory chip 5, respectively. The controller chip 3 and the memory chip 5 are sealed by a sealing material 7 provided on the substrate 2. The sealing material 7 is made of, for example, epoxy resin. The constituent materials of the sealing material 7 may contain fillers, hardeners, hardening accelerators, etc. Furthermore, if necessary, colorants, release agents, modifiers, flame retardants, etc.

[0022] The substrate 2 is, for example, an organic substrate, but may also be a metal substrate such as a lead frame.

[0023] The controller chip 3 is adhered to the substrate 2 by an adhesive layer 8. The controller chip 3 is electrically connected to the electrodes of the substrate 2 by a conductive member. The adhesive layer 8 is made of, for example, a cured product of a thermosetting resin composition and is formed using a die attach film (DAF). The thickness of the adhesive layer 8 is, for example, approximately 5 to 25 μm. The controller chip 3 is formed in a rectangular shape in a plan view. That is, the controller chip 3 has long sides and short sides. The length L1 of the controller chip 3 in the long side direction D1 is, for example, approximately 2.0 to 10.0 mm. The length L2 of the controller chip 3 in the short side direction D2 is, for example, approximately 1.0 to 8.0 mm. The height H1 of the controller chip 3 relative to the substrate 2 is, for example, approximately 30 to 90 μm. The height H1 of the controller chip 3 relative to the substrate 2 is also the total thickness of the adhesive layer 8 and the controller chip 3. The total thickness of adhesive layer 8 and controller chip 3 is the dimension in direction D3 in which substrate 2 faces memory chip 5. The thickness of controller chip 3 is, for example, about 5 to 85 μm.

[0024] The plurality of spacers 4 are members for supporting the memory chip 5 and forming a space around the memory chip 5. The plurality of spacers 4 are arranged at a distance from the memory chip 5. Each of the plurality of spacers 4 is made of, for example, a cured thermosetting resin composition. The plurality of spacers 4 are adhered to the substrate 2 by an adhesive layer 9. The adhesive layer 9 is made of, for example, a cured thermosetting resin composition, and is formed using a die attach film (DAF). The thickness of the adhesive layer 9 is, for example, approximately the same as the thickness of the adhesive layer 8.

[0025] The multiple spacers 4 are composed of a first main spacer 41 and a second main spacer 42 arranged on both sides of the controller chip 3 in the long side direction D1 of the controller chip 3, and a first additional spacer 43 and a second additional spacer 44 arranged on both sides of the controller chip 3 in the short side direction D2 of the controller chip 3.

[0026] The first main spacer 41 is a spacer 4 arranged on one side of the controller chip 3 in the long side direction D1. The second main spacer 42 is a spacer 4 arranged on the other side of the controller chip 3 in the long side direction D1. The first additional spacer 43 is a spacer 4 arranged on one side of the controller chip 3 in the short side direction D2. The second additional spacer 44 is a spacer 4 arranged on the other side of the controller chip 3 in the short side direction D2.

[0027] The first main spacer 41 and the second main spacer 42 have, for example, the same shape. The arrangement of the first main spacer 41 and the second main spacer 42 relative to the controller chip 3 is the same, except that, for example, they are on the opposite side of the controller chip 3 in the long side direction D1. The separation distance G1 between the controller chip 3 and the first main spacer 41 and the second main spacer 42 in the long side direction D1 is, for example, approximately 0.2 to 2.0 mm. For example, when viewed from the long side direction D1, the first main spacer 41 and the second main spacer 42 protrude from both sides of the controller chip 3 in the short side direction D2. The length L3 of the first main spacer 41 and the second main spacer 42 in the short side direction D2 is, for example, approximately 180 to 360% of the length L2 of the controller chip 3 in the short side direction D2. The height H2 of the first main spacer 41 and the second main spacer 42 relative to the substrate 2 is, for example, approximately 30 to 90 μm. The height H2 of the first main spacers 41 and the second main spacers 42 relative to the substrate 2 is also the total thickness of the adhesive layer 9 and each of the first main spacers 41 and the second main spacers 42. The total thickness of the adhesive layer 9 and each of the first main spacers 41 and the second main spacers 42 is the dimension in the opposing direction D3. The thickness of each of the first main spacers 41 and the second main spacers 42 is, for example, about 5 to 85 μm.

[0028] The first additional spacer 43 and the second additional spacer 44 have, for example, the same shape. The arrangement of the first additional spacer 43 and the second additional spacer 44 relative to the controller chip 3 is the same, except that, for example, they are on the opposite side of the controller chip 3 in the short side direction D2. The separation distance G2 between the controller chip 3 and the first additional spacer 43 and the second additional spacer 44 in the short side direction D2 is, for example, about 0.2 to 1.0 mm. The separation distance G2 between the controller chip 3 and the first additional spacer 43 and the second additional spacer 44 in the short side direction D2 is, for example, shorter than the separation distance G1 between the controller chip 3 and the first main spacer 41 and the second main spacer 42 in the long side direction D1. The length L4 of the first additional spacer 43 and the second additional spacer 44 in the long side direction D1 is, for example, about 80 to 120% of the length L1 of the controller chip 3 in the long side direction D1. The length L4 of the first additional spacer 43 and the second additional spacer 44 in the long side direction D1 may be the same as the length L1 of the controller chip 3 in the long side direction D1, for example. Furthermore, the positions of the first additional spacer 43 and the second additional spacer 44 in the long side direction D1 may be the same as the position of the controller chip 3 in the long side direction D1, for example. The height H3 of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 is, for example, approximately 30 to 90 μm. The height H3 of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 is also the total thickness of the adhesive layer 9 and each of the first additional spacer 43 and the second additional spacer 44. The total thickness of the adhesive layer 9 and each of the first additional spacer 43 and the second additional spacer 44 is the dimension in the opposing direction D3. The thickness of each of the first additional spacer 43 and the second additional spacer 44 is, for example, approximately 5 to 85 μm.

[0029] The memory chip 5 is electrically connected to the electrodes of the substrate 2 via conductive members. The memory chip 5 is formed in a rectangular (oblong) shape in a plan view. That is, the memory chip 5 has long sides and short sides, similar to the controller chip 3. The long side direction of the memory chip 5 is the same as the long side direction D1 of the controller chip 3, and the short side direction of the memory chip 5 is the same as the short side direction D2 of the controller chip 3. In a plan view, the memory chip 5 is formed so as to cover the entire controller chip 3 and at least a portion of each of the multiple spacers 4. In a plan view, the first additional spacer 43 and the second additional spacer 44 may or may not protrude from the memory chip 5 in the short side direction D2. When the memory chip 5 is short in the short side direction D2, it is preferable that the first additional spacer 43 and the second additional spacer 44 protrude from the memory chip 5 in the short side direction D2 in a plan view, from the viewpoint of facilitating the arrangement of the first additional spacer 43 and the second additional spacer 44.

[0030] The adhesive layer 6 is made of, for example, a cured product of a thermosetting resin composition and is formed using a die attach film (DAF). The thickness of the adhesive layer 6 is, for example, about 10 to 80 μm.

[0031] In the semiconductor device 1 configured in this manner, the controller chip 3, the plurality of spacers 4, the memory chip 5, and the adhesive layer 6 form a dolmen structure on the substrate 2.

[0032] FIG. 4 is a schematic plan view showing a method for manufacturing a semiconductor device according to the present disclosure. FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 4. FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 4. As shown in FIGS. 4 to 6, in manufacturing the semiconductor device 1, first, a process of bonding a rectangular controller chip 3, a first main spacer 41 and a second main spacer 42 disposed on both sides of the controller chip 3 in the long-side direction D1 of the controller chip 3, and a first additional spacer 43 and a second additional spacer 44 disposed on both sides of the controller chip 3 in the short-side direction D2 of the controller chip 3, onto a substrate 2 is performed. Also, a process of attaching an uncured adhesive layer 6 to one surface of a memory chip 5 is performed. These processes may be performed in any order, or may be performed simultaneously.

[0033] The controller chip 3 is bonded to the substrate 2 via the adhesive layer 8. That is, the controller chip 3 is placed on the substrate 2 via the adhesive layer 8 before hardening, and heat is applied to the adhesive layer 8 to harden the adhesive layer 8. In this way, the controller chip 3 is bonded to the substrate 2 by the adhesive layer 8. Note that the placement of the controller chip 3 on the substrate 2 via the adhesive layer 8 before hardening and the application of heat to the adhesive layer 8 can be performed by well-known methods, and therefore detailed explanations thereof will be omitted.

[0034] The first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 are bonded to the substrate 2 via an adhesive layer 9. That is, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 are arranged on the substrate 2 via the adhesive layer 9 before hardening, and heat is applied to the adhesive layer 9 to harden the adhesive layer 9. As a result, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 are bonded to the substrate 2 by the adhesive layer 9. Note that the arrangement of the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 on the substrate 2 via the adhesive layer 9 before hardening, and the application of heat to the adhesive layer 9 can be performed by well-known methods, and therefore detailed description thereof will be omitted.

[0035] Fig. 7 is a schematic plan view showing a method for manufacturing a semiconductor device according to the present disclosure. Fig. 8 is a schematic cross-sectional view taken along line VIII-VIII in Fig. 7. Fig. 9 is a schematic cross-sectional view taken along line IX-IX in Fig. 7. As shown in Figs. 5 to 9, the next step in the manufacture of semiconductor device 1 is to bond memory chip 5 to surfaces of controller chip 3, first main spacer 41, second main spacer 42, first additional spacer 43, and second additional spacer 44 with adhesive layer 6 so that controller chip 3 is covered with memory chip 5.

[0036] To adhere the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 using the adhesive layer 6, first, the memory chip 5 to which the adhesive layer 6 has been attached is picked up. Then, while applying heat to the adhesive layer 6, the memory chip 5 is pressed from the adhesive layer 6 side against the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44. Note that picking up the controller chip 3, applying heat to the adhesive layer 6, and pressing the memory chip 5 against the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 can be performed by well-known methods, and therefore detailed explanations thereof will be omitted.

[0037] The next step in the manufacture of the semiconductor device 1 is to harden the adhesive layer 6. The adhesive layer 6 can be hardened by a well-known method, and therefore a detailed description thereof will be omitted.

[0038] The next step in the manufacture of the semiconductor device 1 is to seal the controller chip 3, the spacers 4, and the memory chip 5 on the substrate 2 with a sealing material 7. Note that sealing with the sealing material 7 can be performed by a well-known method, and therefore a detailed description thereof will be omitted. In this way, the semiconductor device 1 is obtained.

[0039] Here, a semiconductor device 1 of a comparative example will be described. Fig. 10 is a schematic plan view showing the semiconductor device of the comparative example. Fig. 11 is a schematic cross-sectional view taken along line XI-XI shown in Fig. 10. The semiconductor device 101 of the comparative example shown in Figs. 10 and 11 is basically the same as the semiconductor device 1 described above, but differs from the semiconductor device 1 described above only in that it does not include the first additional spacer 43 and the second additional spacer 44.

[0040] The semiconductor device 101 of the comparative example does not have the first additional spacer 43 and the second additional spacer 44 of the semiconductor device 1 described above, and therefore, when manufacturing the semiconductor device 101, the memory chip 5 and the adhesive layer 6 tend to sag toward the substrate 2 on both sides in the short side direction D2 of the controller chip 3. When the memory chip 5 and the adhesive layer 6 sag in this way, the adhesive layer 6 tends to lift up from the controller chip 3 in the central portion in the short side direction D2 of the controller chip 3. As a result, a void V extending in the long side direction D1 of the controller chip 3 tends to occur between the memory chip 5 and the adhesive layer 6 in the central portion in the short side direction D2 of the controller chip 3.

[0041] In contrast, in the semiconductor device 1 of the present disclosure, not only are first main spacers 41 and second main spacers 42 arranged on both sides of the controller chip 3 in the long side direction D1 of the controller chip 3, but first additional spacers and second additional spacers are also arranged on both sides of the first semiconductor chip in the short side direction D2 of the controller chip 3. Therefore, when manufacturing the semiconductor device 1, not only can the memory chip 5 and adhesive layer 6 on both sides of the controller chip 3 in the long side direction D1 be prevented from sagging toward the substrate 2, but also the memory chip 5 and adhesive layer 6 on both sides of the controller chip 3 in the short side direction D2 can be prevented from sagging toward the substrate 2. This makes it possible to suppress the occurrence of voids between the controller chip 3 and the adhesive layer 6.

[0042] Similarly, in the manufacturing method of the semiconductor device 1 disclosed herein, not only are the first main spacers 41 and the second main spacers 42 arranged on both sides of the controller chip 3 in the long side direction D1 of the controller chip 3, but also the first additional spacers 43 and the second additional spacers 44 are arranged on both sides of the controller chip 3 in the short side direction D2 of the controller chip 3. Therefore, not only can the memory chips 5 and the adhesive layers 6 on both sides of the controller chip 3 in the long side direction D1 be prevented from sagging toward the substrate 2, but also the memory chips 5 and the adhesive layers 6 on both sides of the controller chip 3 in the short side direction D2 of the controller chip 3 can be prevented from sagging toward the substrate 2. This makes it possible to suppress the occurrence of voids between the controller chip 3 and the adhesive layer 6.

[0043] Furthermore, by making the length L4 of the first additional spacer 43 and the second additional spacer 44 in the long side direction D1 80% to 120% of the length L1 of the controller chip 3 in the long side direction D1, it is possible to appropriately prevent the memory chip 5 and the adhesive layer 6 on both sides of the controller chip 3 in the short side direction D2 from sagging toward the substrate 2 when manufacturing the semiconductor device 1. This makes it possible to further prevent voids from occurring between the controller chip 3 and the adhesive layer 6.

[0044] Furthermore, since the separation distance G2 between the controller chip 3 and the first additional spacer 43 and the second additional spacer 44 is shorter than the separation distance G1 between the controller chip 3 and the first main spacer 41 and the second main spacer 42, it becomes easier to arrange the first additional spacer 43 and the second additional spacer 44 between the substrate 2 and the memory chip 5 even if the memory chip 5 is short in the short side direction D2.

[0045] Furthermore, since the first additional spacer 43 and the second additional spacer 44 protrude from the memory chip 5 in the short side direction D2 when viewed in a plane, it becomes easier to arrange the first additional spacer 43 and the second additional spacer 44 between the substrate 2 and the memory chip 5 even if the memory chip 5 is short in the short side direction D2.

[0046] Here, the present inventors evaluated the occurrence of voids between the controller chip 3 and the adhesive layer 6 by changing the height of the controller chip 3 relative to the substrate 2, the heights of the first main spacers 41 and the second main spacers 42 relative to the substrate 2, and the heights of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2. As a result, it was found that when the height H3 of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 is equal to or greater than the height H1 of the controller chip 3 relative to the substrate 2, the occurrence of voids between the memory chip 5 and the adhesive layer 6 is further suppressed, and further, when the height H3 of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 is greater than the height H1 of the controller chip 3 relative to the substrate 2, the occurrence of voids between the memory chip 5 and the adhesive layer 6 is further suppressed.

[0047] From this finding, it is more preferable that the height H3 of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 is equal to or greater than the height H1 of the controller chip 3 relative to the substrate 2, and it is even more preferable that the height H3 of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 is greater than the height H1 of the controller chip 3 relative to the substrate 2. By making the height H3 of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 equal to or greater than the height H1 of the controller chip 3 relative to the substrate 2, it is possible to further suppress the occurrence of voids between the memory chip 5 and the adhesive layer 6. Furthermore, by making the height H3 of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 greater than the height H1 of the controller chip 3 relative to the substrate 2, it is possible to further suppress the occurrence of voids between the memory chip 5 and the adhesive layer 6.

[0048] The gist of the present disclosure is as described in the following [1] to [7]. [1] A semiconductor device comprising: a substrate; a rectangular first semiconductor chip disposed on the substrate; a plurality of spacers disposed around the first semiconductor chip on the substrate; a second semiconductor chip facing the substrate so as to cover the first semiconductor chip; and an adhesive layer provided on a surface of the second semiconductor chip facing the first semiconductor chip and adhered to the first semiconductor chip and the plurality of spacers, wherein the plurality of spacers include a first main spacer and a second main spacer disposed on both sides of the first semiconductor chip in the direction of a long side of the first semiconductor chip, and a first additional spacer and a second additional spacer disposed on both sides of the first semiconductor chip in the direction of a short side of the first semiconductor chip. [2] The semiconductor device described in [1], wherein the height of the first additional spacer and the second additional spacer relative to the substrate is equal to or greater than the height of the first semiconductor chip relative to the substrate. [3] The semiconductor device described in [1], wherein the height of the first additional spacer and the second additional spacer relative to the substrate is greater than the height of the first semiconductor chip relative to the substrate. [4] The semiconductor device according to any one of [1] to [3], wherein the lengths of the first additional spacer and the second additional spacer in the long side direction are 80% to 120% of the length of the first semiconductor chip in the long side direction. [5] The semiconductor device according to any one of [1] to [4], wherein the distance between the first semiconductor chip and the first additional spacer and the second additional spacer is shorter than the distance between the first semiconductor chip and the first main spacer and the second main spacer. [6] The semiconductor device according to any one of [1] to [5], wherein the first additional spacer and the second additional spacer protrude from the second semiconductor chip in the short side direction in a plan view.[7] A method for manufacturing a semiconductor device, comprising the steps of: adhering a rectangular first semiconductor chip onto a substrate; a first main spacer and a second main spacer arranged on both sides of the first semiconductor chip in the long side direction of the first semiconductor chip; and a first additional spacer and a second additional spacer arranged on both sides of the first semiconductor chip in the short side direction of the first semiconductor chip; attaching an uncured adhesive layer to one side of the second semiconductor chip; adhering the second semiconductor chip to the surfaces of the first semiconductor chip, the first main spacer, the second main spacer, the first additional spacer, and the second additional spacer using the adhesive layer so that the first semiconductor chip is covered by the second semiconductor chip; and curing the adhesive layer.

[0049] Next, examples of the present disclosure will be described, but the present disclosure is not limited to the following examples.

[0050] Example A semiconductor device 1A shown in FIG. 12 was fabricated as a semiconductor device of the example. FIG. 12 is a schematic plan view showing the semiconductor device of the example. As shown in FIG. 12, first, a rectangular controller chip 3, a first main spacer 41 and a second main spacer 42 arranged on both sides of the controller chip 3 in the long side direction D1 of the controller chip 3, and a first additional spacer 43 and a second additional spacer 44 arranged on both sides of the controller chip 3 in the short side direction D2 of the controller chip 3 were bonded onto a substrate 2. In addition, an adhesive layer 6 before hardening was attached to one surface of a memory chip 5.

[0051] The length of the controller chip 3 in the long side direction D1 was 4.5 mm, and the length of the controller chip 3 in the short side direction D2 was 1.6 mm. The length of the first main spacer 41 and the second main spacer 42 in the long side direction D1 was 2.5 mm, and the length of the first main spacer 41 and the second main spacer 42 in the short side direction D2 was 3.6 mm. The length of the first additional spacer 43 and the second additional spacer 44 in the long side direction D1 was 4.5 mm, and the length of the first additional spacer 43 and the second additional spacer 44 in the short side direction D2 was 1.6 mm.

[0052] The distance between the controller chip 3 and the first main spacer 41 and the second main spacer 42 in the long side direction D1 was 1.0 mm. The distance between the controller chip 3 and the first additional spacer 43 and the second additional spacer 44 in the short side direction D2 was 0.6 mm.

[0053] When viewed from the long side direction D1, both end portions of the first main spacer 41 and the second main spacer 42 in the short side direction D2 protruded in the short side direction D2 from the controller chip 3. The positions of the first additional spacer 43 and the second additional spacer 44 in the long side direction D1 were the same as the positions of the controller chip 3 in the long side direction D1.

[0054] Next, the memory chip 5 was bonded to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 with the adhesive layer 6 so that the controller chip 3 was covered with the memory chip 5 and the first additional spacer 43 and the second additional spacer 44 protruded from the memory chip 5 in the short side direction D2 in a plan view. This bonding was performed by picking up the controller chip 3 with the adhesive layer 6 attached, and pressing the controller chip 3 from the adhesive layer 6 side against the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 while heating the adhesive layer 6. In this way, the semiconductor device of the example was obtained. Note that the semiconductor device of the example was obtained before the adhesive layer 6 was hardened.

[0055] In the semiconductor device of the above example, the height of the controller chip 3 relative to the substrate 2 was set to 85 μm, the height of the first main spacer 41 and the second main spacer 42 relative to the substrate 2 was set to 75 μm, and the height of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 was set to 75 μm. Then, the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 by the adhesive layer 6 were set to a temperature of 140° C., a load of 1.47 MPa, and a time of 1.5 seconds, and four semiconductor devices of example 1 were fabricated.

[0056] (Example 2) Four semiconductor devices of Example 2 were fabricated under the same conditions as Example 1, except that the adhesive layer 6 was used to bond the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 at a temperature of 120°C, a load of 0.49 MPa, and for a time of 1.5 seconds.

[0057] Example 3 Four semiconductor devices of Example 3 were fabricated under the same conditions as Example 1, except that the height of the controller chip 3 relative to the substrate 2 was set to 75 μm.

[0058] (Example 4) Four semiconductor devices of Example 4 were fabricated under the same conditions as Example 3, except that the adhesive layer 6 was used to bond the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 at a temperature of 120°C, a load of 0.49 MPa, and for a time of 1.5 seconds.

[0059] Example 5 Four semiconductor devices of Example 5 were fabricated under the same conditions as Example 1, except that the height of the controller chip 3 relative to the substrate 2 was set to 65 μm.

[0060] (Example 6) Four semiconductor devices of Example 6 were fabricated under the same conditions as Example 5, except that the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 using the adhesive layer 6 were a temperature of 120°C, a load of 0.49 MPa, and a time of 1.5 seconds.

[0061] (Comparative Example) A semiconductor device 101A shown in FIG. 13 was fabricated as a comparative example. FIG. 13 is a schematic plan view showing the semiconductor device of the comparative example. As shown in FIG. 13, the semiconductor device of the comparative example was the same as the semiconductor device of the example, except that it did not include the first additional spacer 43 and the second additional spacer 44. That is, first, a rectangular controller chip 3 and a first main spacer 41 and a second main spacer 42 arranged on both sides of the controller chip 3 in the long side direction D1 of the controller chip 3 were bonded to a substrate 2. In addition, an uncured adhesive layer 6 was attached to one surface of a memory chip 5. Next, the memory chip 5 was bonded to the surfaces of the controller chip 3, the first main spacer 41, and the second main spacer 42 using the adhesive layer 6 so that the controller chip 3 was covered by the memory chip 5. This resulted in the semiconductor device of the comparative example. Note that the semiconductor device of the comparative example was obtained before the adhesive layer 6 was cured.

[0062] (Comparative Example 1) In the semiconductor device of the above comparative example, the height of the controller chip 3 relative to the substrate 2 was set to 85 μm, and the heights of the first main spacer 41 and the second main spacer 42 relative to the substrate 2 were set to 75 μm. Then, the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, and the second main spacer 42 by the adhesive layer 6 were set to a temperature of 140° C., a load of 1.79 MPa, and a time of 1.5 seconds, and four semiconductor devices of Comparative Example 1 were fabricated.

[0063] (Comparative Example 2) Four semiconductor devices of Comparative Example 2 were fabricated under the same conditions as Comparative Example 1, except that the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, and the second main spacer 42 using the adhesive layer 6 were a temperature of 120°C, a load of 0.60 MPa, and a time of 1.5 seconds.

[0064] Comparative Example 3 Two semiconductor devices of Comparative Example 3 were fabricated under the same conditions as Comparative Example 1, except that the height of the controller chip 3 relative to the substrate 2 was set to 75 μm.

[0065] (Comparative Example 4) Two semiconductor devices of Comparative Example 4 were fabricated under the same conditions as Comparative Example 3, except that the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, and the second main spacer 42 using the adhesive layer 6 were a temperature of 120°C, a load of 0.60 MPa, and a time of 1.5 seconds.

[0066] Comparative Example 5 Four semiconductor devices of Comparative Example 5 were fabricated under the same conditions as Comparative Example 1, except that the height of the controller chip 3 relative to the substrate 2 was set to 65 μm.

[0067] (Comparative Example 6) Four semiconductor devices of Comparative Example 6 were fabricated under the same conditions as Comparative Example 5, except that the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, and the second main spacer 42 using the adhesive layer 6 were a temperature of 120°C, a load of 0.60 MPa, and a time of 1.5 seconds.

[0068] (Evaluation) The semiconductor devices of Examples 1 to 6 and Comparative Examples 1 to 6 were analyzed using an ultrasonic microscope (SAM: IS-450 Ultrasound Digital Imaging Diagnostic System, manufactured by Insight Corporation) to evaluate the occurrence of voids. In the evaluation, cases where no voids occurred were evaluated as OK, and cases where voids occurred were evaluated as NG, and the OK rate (number of OK semiconductor devices / total number of semiconductor devices x 100) was calculated. In addition, cases where no voids occurred in any of the semiconductor devices were evaluated as A, cases where no voids occurred in some of the semiconductor devices were evaluated as B, cases where voids occurred in all of the semiconductor devices but none of the voids were large were evaluated as C, and cases where voids occurred in all of the semiconductor devices and large voids were present were evaluated as D. SAM photographs of the semiconductor devices of Examples 1 to 6 and Comparative Examples 1 to 6 are shown in FIG. 14, and the results are shown in Table 1. In FIG. 14, Comparative Example 3 and Comparative Example 4 are shown in the same column, but the SAM photographs of Comparative Example 3 are the bottom two of the four SAM photographs in that column, and the SAM photographs of Comparative Example 4 are the top two of the four SAM photographs in that column.

[0069]

[0070] As shown in Table 1, Comparative Examples 1 to 6 were all rated D, whereas Examples 1 to 6 received no D rating and were rated A to C. Furthermore, Comparative Examples 1 to 6 all had an OK rate of 0%, whereas Example 4 had an OK rate of 50%, and Examples 5 and 6 had an OK rate of 100%. These results demonstrate that providing the first additional spacer and the second additional spacer can suppress the occurrence of voids between the first semiconductor chip and the adhesive layer. Furthermore, it was found that even if voids occur between the first semiconductor chip and the adhesive layer, the occurrence of large voids is suppressed.

[0071] In the semiconductor device of the above example, the height of the controller chip 3 relative to the substrate 2 was set to 65 μm, the height of the first main spacer 41 and the second main spacer 42 relative to the substrate 2 was set to 75 μm, and the height of the first additional spacer 43 and the second additional spacer 44 relative to the substrate 2 was set to 65 μm. Then, the conditions for bonding the memory chip 5 to the surfaces of the controller chip 3, the first main spacer 41, the second main spacer 42, the first additional spacer 43, and the second additional spacer 44 by the adhesive layer 6 were set to a temperature of 120° C., a load of 0.49 MPa, and a time of 1.5 seconds, and four semiconductor devices of example 7 were fabricated.

[0072] Example 8 Four semiconductor devices of Example 8 were fabricated under the same conditions as Example 7, except that the height of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 was set to 75 μm.

[0073] Example 9 Four semiconductor devices of Example 9 were fabricated under the same conditions as Example 7, except that the height of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 was set to 85 μm.

[0074] Example 10 Four semiconductor devices of Example 10 were fabricated under the same conditions as Example 7, except that the height of the controller chip 3 relative to the substrate 2 was set to 75 μm.

[0075] Example 11 Four semiconductor devices of Example 11 were fabricated under the same conditions as Example 10, except that the height of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 was set to 75 μm.

[0076] Example 12 Four semiconductor devices of Example 12 were fabricated under the same conditions as Example 10, except that the height of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 was set to 85 μm.

[0077] Example 13 Four semiconductor devices of Example 13 were fabricated under the same conditions as in Example 7, except that the height of the controller chip 3 relative to the substrate 2 was set to 85 μm.

[0078] Example 14 Four semiconductor devices of Example 14 were fabricated under the same conditions as in Example 13, except that the height of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 was set to 75 μm.

[0079] Example 15 Four semiconductor devices of Example 15 were fabricated under the same conditions as Example 13, except that the height of the first additional spacers 43 and the second additional spacers 44 relative to the substrate 2 was set to 85 μm.

[0080] (Evaluation) The semiconductor devices of Examples 7 to 15 were analyzed using an ultrasonic microscope (SAM: IS-450 Ultrasound Digital Imaging Diagnostic System, manufactured by Insight Corporation) to evaluate the occurrence of voids. In the evaluation, cases where no voids occurred were evaluated as OK, and cases where voids occurred were evaluated as NG, and the OK rate (number of OK semiconductor devices / total number of semiconductor devices x 100) was calculated. In addition, cases where no voids occurred in any of the semiconductor devices were evaluated as A, cases where no voids occurred in some of the semiconductor devices were evaluated as B, cases where voids occurred in all of the semiconductor devices but none of the voids were large were evaluated as C, and cases where voids occurred in all of the semiconductor devices but large voids were present were evaluated as D. SAM photographs of the semiconductor devices of Examples 7 to 15 are shown in FIG. 15, and the evaluation results are shown in Table 2.

[0081]

[0082] As shown in Table 2, none of Examples 7 to 15 received a rating of D, and all received ratings of A to C. Examples 10, 13, and 14, in which the height of the additional spacer relative to the substrate was less than the height of the controller chip relative to the substrate, were all rated C. On the other hand, of Examples 7 to 9, 11, 12, and 15, in which the height of the additional spacer relative to the substrate was equal to or greater than the height of the controller chip relative to the substrate, Examples 7 to 9, 11, and 12 were all rated A or B, and none received a rating of C. Furthermore, Examples 8, 9, and 12, in which the height of the additional spacer relative to the substrate was greater than the height of the controller chip relative to the substrate, were all rated A.

[0083] These results show that the occurrence of voids between the chip and the adhesive layer can be further suppressed by making the height of the additional spacers relative to the substrate equal to or greater than the height of the controller chip relative to the substrate.Furthermore, it was found that the occurrence of voids between the controller chip and the adhesive layer can be further suppressed by making the height of the additional spacers relative to the substrate greater than the height of the controller chip relative to the substrate.

[0084] 1...semiconductor device, 2...substrate, 3...controller chip (first semiconductor chip), 4...spacer, 5...memory chip (second semiconductor chip), 6...adhesive layer, 7...sealing material, 8...adhesive layer, 9...adhesive layer, 41...first main spacer, 42...second main spacer, 43...first additional spacer, 44...second additional spacer, 101...semiconductor device, D1...long side direction, D2...short side direction, D3...opposing direction, G1...separation distance, G2...separation distance, V...void.

Claims

1. A semiconductor device comprising: a substrate; a rectangular first semiconductor chip arranged on the substrate; a plurality of spacers arranged around the first semiconductor chip on the substrate; a second semiconductor chip facing the substrate so as to cover the first semiconductor chip; and an adhesive layer provided on a surface of the second semiconductor chip facing the first semiconductor chip and adhered to the first semiconductor chip and the plurality of spacers, wherein the plurality of spacers include a first main spacer and a second main spacer arranged on both sides of the first semiconductor chip in the direction of a long side of the first semiconductor chip, and a first additional spacer and a second additional spacer arranged on both sides of the first semiconductor chip in the direction of a short side of the first semiconductor chip.

2. The semiconductor device according to claim 1, wherein the height of said first additional spacer and said second additional spacer relative to said substrate is equal to or greater than the height of said first semiconductor chip relative to said substrate.

3. The semiconductor device according to claim 1, wherein the height of the first additional spacer and the second additional spacer relative to the substrate is greater than the height of the first semiconductor chip relative to the substrate.

4. The semiconductor device according to any one of claims 1 to 3, wherein the length of the first additional spacer and the second additional spacer in the long side direction is 80% or more and 120% or less of the length of the first semiconductor chip in the long side direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein a distance between the first semiconductor chip and the first additional spacer and the second additional spacer is shorter than a distance between the first semiconductor chip and the first main spacer and the second main spacer.

6. The semiconductor device according to claim 1, wherein, in a plan view, the first additional spacer and the second additional spacer protrude from the second semiconductor chip in the direction of the short side.

7. A method for manufacturing a semiconductor device, comprising the steps of: adhering a rectangular first semiconductor chip onto a substrate; a first main spacer and a second main spacer arranged on both sides of the first semiconductor chip in the direction of a long side of the first semiconductor chip; and a first additional spacer and a second additional spacer arranged on both sides of the first semiconductor chip in the direction of a short side of the first semiconductor chip; attaching an uncured adhesive layer onto one side of the second semiconductor chip; adhering the second semiconductor chip to surfaces of the first semiconductor chip, the first main spacer, the second main spacer, the first additional spacer, and the second additional spacer using the adhesive layer so that the first semiconductor chip is covered by the second semiconductor chip; and curing the adhesive layer.

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