Method for observing junction profile of sic semiconductor device

Abstract

A method for observing a junction profile of a SiC semiconductor includes providing a SiC semiconductor device within a chamber, providing an etching gas atmosphere within the chamber, etching a cross-sectional area of the SiC semiconductor device with the etching gas, and observing the cross-sectional area of the etched SiC semiconductor device.

Description

METHOD FOR OBSERVING JUNCTION PROFILE OF SIC SEMICONDUCTOR DEVICE

[0001] The present disclosure relates to a method for observing a junction profile of a silicon carbide (SiC) semiconductor device.

[0002] Power semiconductors are one of the key factors that determine efficiency, speed, durability and reliability of power electronic systems.

[0003] With the recent development of the power electronics industry, silicon (Si) power semiconductors reach their physical limits. Therefore, research on wide bandgap (WBG) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) have been actively conducted to replace the Si power semiconductors.

[0004] WBG power semiconductor devices have a bandgap energy about 3 times of Si power semiconductor devices, resulting in a low intrinsic carrier concentration, a high dielectric breakdown field (about 4 to 20 times), and a high thermal conductivity (about 3 to 13 times) and a large electron saturation rate (about 2 to 2.5 times).

[0005] Due to such characteristics, WBG power semiconductor devices may be operated in a high-temperature, a high-voltage environment and have a high switching speed and a low switching loss. Among them, a gallium nitride (GaN) power semiconductor device may be used for a low voltage system, and a silicon carbide (SiC) power semiconductor device may be used for a high voltage system.

[0006] On the other hand, the junction profile including the shape, length, distribution, etc. of a PN junction region, a channel, a gate, etc. among cross sections in a semiconductor device is a region closely related to the characteristics of the semiconductor device, but it is difficult to distinguish, especially, due to the material characteristics of SiC, deviations in observing the power semiconductor devices may occur depending on observation conditions, which make difficult to observe a cross-section of the power semiconductor devices. Therefore, it is difficult to observe characteristics through the cross-section of the power semiconductor devices during the device manufacturing process.

[0007] Accordingly, additional analysis may be required to identify a defect issue. Since analysis through a junction profile is difficult, analysis cost and difficulty in identifying device characteristics are inevitably increased.

[0008] The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form prior art that is already known to a person of ordinary skill in the art.

[0009] Accordingly, the present disclosure is directed to a method for observing a junction profile of a silicon carbide (SiC) semiconductor device that substantially obviates one or more of problems due to limitations and disadvantages described above.

[0010] Additional features and advantages of the disclosure will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0011] More specifically, the present disclosure is to provide a method for observing a junction profile of a SiC semiconductor device.

[0012] In addition, the present disclosure is to provide a method for easily identifying a specific region such as a channel in a SiC semiconductor device.

[0013] Further, the present disclosure is to provide is to a method for easily identifying the cause of a defect in device characteristics.

[0014] The present disclosure is not limited to those described in this section, but include those that may be understood through the description of the present disclosure.

[0015] To achieve these and other advantages and in accordance with the present disclosure, as embodied and broadly described, a method for observing a junction profile of a SiC semiconductor device includes providing the SiC semiconductor device within a chamber, forming an etching gas atmosphere within the chamber, etching a cross-sectional area of the SiC semiconductor device with the etching gas; observing the cross-sectional area of the etched SiC semiconductor device.

[0016] In addition, in the aspect, the cross-sectional area of the SiC semiconductor device may be formed by cutting the SiC semiconductor device with FIB equipment.

[0017] In addition, in an aspect, the etching gas may include insulator enhancement etch gas (IEE gas).

[0018] In addition, in an aspect, the etching gas may increase a surface roughness of un-doped region and a doped region of the semiconductor layer of the SiC semiconductor device.

[0019] In addition, in an aspect, the etching gas may separate the un-doped region and the doped region of the semiconductor layer.

[0020] In addition, the doped region may include a first doped region and a second doped region, and the etching gas may distinguish the first doped region and the second doped region from each other.

[0021] In addition, in observing the cross-sectional area of the etched SiC semiconductor device in the aspect, a junction profile of the SiC semiconductor device may be observed using a scanning electron microscope (SEM).

[0022] In addition, in an aspect, observing a cross-sectional area of the etched SiC semiconductor device may include measuring a channel length of the SiC semiconductor device.

[0023] In addition, in an aspect, observing the cross-sectional area of the etched SiC semiconductor device may include measuring a junction depth of the SiC semiconductor device.

[0024] In addition, a method for observing a junction profile of a SiC semiconductor device according to an aspect may include providing the SiC semiconductor device within a chamber, providing an etching gas atmosphere in the chamber and observing a cross-sectional area of the SiC semiconductor device at the same time.

[0025] The method for observing the SiC semiconductor device according to the aspect has a technical effect of improving the visibility of a junction profile.

[0026] The present disclosure may provide clearly observing a specific region of a device and analyzing a junction profile in a SiC semiconductor device.

[0027] In addition, the present disclosure may reduce analysis time and cost because it is possible to accurately determine the junction depth without an additional analysis method.

[0028] For example, device characteristics such as a channel length and a junction depth may be observed without additional analysis.

[0029] The present disclosure may also provide no deviation according to the state of the sample and the shooting conditions in observing the junction profile of the SiC semiconductor device.

[0030] Further, through the junction profile analysis of the SiC semiconductor device through the aspect, there is a technical effect of identifying the cause of the defect of the device.

[0031] The present disclosure is not limited to those described in this section, but include those that may be understood through the description of the disclosure.

[0032] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

[0033] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the disclosure, illustrate aspects of the disclosure and together with the description serve to explain the principle of the disclosure.

[0034] In the drawings:

[0035] FIG. 1 is an exemplary view of a power converter 1000 according to an aspect of the present disclosure;

[0036] FIG. 2 is a cross-sectional view of a power semiconductor device 100 according to an aspect of the present disclosure.

[0037] FIG. 3 is a scanning electron microscope (SEM) picture of a SiC semiconductor device;

[0038] FIG. 4 is a schematic view of a junction profile observation method of a SiC semiconductor device according to an aspect of the present disclosure; and

[0039] FIG. 5 is a conceptual diagram of a GIS (gas injection system) used in the embodiment.

[0040] FIG. 6 is a SEM picture of a SiC semiconductor device to according to the aspect of the present disclosure.

[0041] Hereinafter, the disclosure according to an aspect for solving the above problems will be described in more detail with reference to the drawings.

[0042] The suffixes "module" and "unit" for the elements used in the following description are simply given in consideration of ease of writing this specification, and do not themselves give a particularly important meaning or role. Accordingly, the "module" and "unit" may be used interchangeably.

[0043] Terms including ordinal numbers, such as first and second, may be used to describe various elements, but the elements are not limited by the terms. These terms are only used for the purpose of distinguishing one element from another.

[0044] Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0045] In this application, terms such as "comprise", "have" or "include" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and it is not precluded from being excluded one or other features, numbers, steps, operations, components, parts, or combinations thereof, or any combination thereof.

[0046] FIG. 1 is an exemplary view of a power converter 1000 according to the present disclosure.

[0047] The power converter 1000 according to the present disclosure may receive DC power from a battery or fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power converter 1000 may include an inverter, which receive DC power from a battery, convert the DC power into 3-phase AC power, and supply the 3-phase AC power to a motor M. The motor M may provide power to electric vehicles or fuel cell vehicles.

[0048] The power converter 1000 according to the present disclosure may include a plurality of power semiconductor devices. The power semiconductor devices may be a metal oxide semiconductor field effect transistor (MOSFET), but is not limited thereto, and may include an insulated gate bipolar transistor (IGBT).

[0049] For example, the power converter 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be internally incorporated in each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and may be disposed separately.

[0050] In the present disclosure, the DC power may be converted into the AC power through on-off control of the plurality of power semiconductor devices 100a to 100f.

[0051] For example, in the power converter 1000, the first power semiconductor device 100a may be turned on and the second power semiconductor device 100b may be turned off in a first time period of one cycle to supply positive polarity power to the motor M.

[0052] In the second time period of one cycle, the first power semiconductor device 100a may be turned off and the second power semiconductor device 100b may be turned on to supply negative polarity power to the motor M.

[0053] In the aspect of the present disclosure, a group of power semiconductor devices disposed in series in a high voltage line and a low voltage line of an input side may be referred to as an arm.

[0054] For example, the first power semiconductor device 100a and the second power semiconductor device 100b may constitute a first arm 12a, and the third power semiconductor device 100c and the fourth power semiconductor device 100d may constitute a second arm 12b. The fifth power semiconductor device 100e and the sixth power semiconductor device 100f may constitute a third arm 12c.

[0055] Among the arms, an upper side power semiconductor device and a lower side power semiconductor device may be controlled not to turn on at the same time. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b do not simultaneously turn on, but may turn on and off alternately.

[0056] Each of the power semiconductor devices 100a to 100f may receive high power in an off state. For example, when the second power semiconductor device 100b is turned off while the first power semiconductor device 100a is turned on, the input voltage may be applied to the second power semiconductor device 100b as it is. The voltage input to the second power semiconductor device 100b may be a relatively high voltage, and a withstand voltage of each power semiconductor device 100a to 100f may be designed to have a high level to withstand such a high voltage.

[0057] Each of the power semiconductor devices 100a to 100f may conduct a high current in a turn on state. The motor M may be driven with a relatively high current, and this high current may be supplied to the motor M through a power semiconductor that is turned on.

[0058] A high voltage applied to each of the power semiconductor devices 100a to 100f may cause a high switching loss. A high current conducting the power semiconductor devices 100a to 100f may cause a high conduction loss. To dissipate heat generated by such switching loss or conduction loss, the power semiconductor devices 100a to 100f may be packaged as a power semiconductor module including a heat dissipation means.

[0059] The power semiconductor device 100 of the aspect may be a silicon carbide (SiC) power semiconductor device, may operate in high-temperature and high-voltage environment, and may have a high switching speed and a low switching loss.

[0060] Meanwhile, the power converter 1000 according to the aspect of the present disclosure may include a plurality of power semiconductor modules.

[0061] For example, the plurality of power semiconductor devices 100a to 100f shown in FIG. 1 may be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0062] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f shown in FIG. 1 may be packaged into one power semiconductor module.

[0063] In addition, there may be additional power semiconductor devices disposed in parallel with each of the power semiconductor devices 100a to 100f to increase a current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module may be greater than six.

[0064] The power converter 1000 according to the aspect may include a diode-type power semiconductor device also to the transistor-type power semiconductor devices 100a to 100f. For example, a first diode (not shown) may be disposed in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be disposed in parallel with the second power semiconductor device 100b. In addition, these diodes may be packaged together in one power semiconductor module. In addition, the diode may be disposed in the form of an internal diode in each power semiconductor device.

[0065] Next, the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0066] For example, the first power semiconductor device 100a and the second power semiconductor device 100b constituting the first arm may be packaged as a first power semiconductor module. The third power semiconductor device 100c and the fourth power semiconductor device 100d constituting the second arm may be packaged into a second power semiconductor module. And the fifth power semiconductor device 100e and the sixth power semiconductor device 100f constituting the third arm may be packaged into a third power semiconductor module.

[0067] In addition, there may be additional power semiconductor devices arranged in parallel with each power semiconductor device 100a to 100f to increase a current capacity. In this case, the number of power semiconductor devices included in each power semiconductor module may be more than two. In addition, each arm may include a diode-type power semiconductor device (not shown) also to the transistor-type power semiconductor devices 100a to 100f, and these diodes may also be packaged together in one power semiconductor module. In addition, the diode may be disposed in a form of an internal diode in each power semiconductor device.

[0068] Next, FIG. 2 is a cross-sectional view of the power semiconductor device 100 according to the aspect.

[0069] The power semiconductor device 100 according to the aspect of the present disclosure may include a source electrode 190, a gate electrode 175 disposed on a semiconductor epitaxial layer 120, and a drain electrode 105 disposed below the semiconductor epitaxial layer 120.

[0070] In a MOSFET according to the aspect of the present disclosure, the source electrode 190 or the gate electrode 175 may include Al-based metal, and the drain electrode 105 may include Ti / Ni / Ag metal including a Ti layer, a Ni layer, or an Ag layer, or NiV / Ag, V (vanadium) / Ni / Ag, or the like, but is not limited thereto.

[0071] FIG. 3 is a SEM photograph of a junction of a SiC semiconductor device being studied. In FIG. 3, the SiC semiconductor device may be a SiC MOSFET, and a portion near the source or drain may be observed.

[0072] The SiC material may have a transparent property, and accordingly, the junction of the SiC semiconductor device may be identified.

[0073] However, there is a problem in that the reliability of the junction profile analysis is low due to deviations depending on the state of the SiC semiconductor device and the photographing conditions.

[0074] In addition, it is difficult to observe a shallow junction formed by implanting a dopant material because it is not clearly distinguished from surrounding materials. In addition, it is not easy to distinguish fine regions such as channels even if the resolution of the observation unit is increased. In addition, even if a semiconductor device outside the design specification is manufactured, it is difficult to identify the cause of the defect through junction profile analysis.

[0075] Referring to FIG. 3, it is difficult to analyze a junction profile because it is difficult to distinguish the semiconductor layer 140, the first doped region 150 and the second doped region 160 from each other. In particular, it is difficult to visually confirm the shape and depth of each doped region, the shape and length of the channel region 155, and the like.

[0076] So, there is a problem in that the junction could not be used for characterization and defect analysis. For example, even if a threshold voltage (Vth) of the manufactured SiC semiconductor device is different from the designed specification, it is very difficult to determine whether an issue has occurred in the channel region 155 or a junction.

[0077] A method for observing a junction profile of a SiC semiconductor device capable of solving the above problems will be described.

[0078] FIG. 4 is a schematic view of a method for observing a junction profile of a SiC semiconductor device according to an aspect of the present disclosure. Referring to FIG. 4, a sample 115 to be observed may be placed in a vacuum chamber 110. The sample 115 may be a SiC semiconductor device, for example, a SiC MOSFET, but is not limited thereto.

[0079] A cross section of the sample 115 may be exposed by the sample processing unit 170. The sample processing unit 170 may be focused ion beam (FIB), Broken, Spreading resistance profiling (SRP) equipment, etc., but is not limited thereto. The sample processing unit 170 may be used to observe the surface or process the sample surface by detecting electrons or ions generated by scanning the focused ion beam on the surface of the sample. In the aspect, the sample 115 may be processed by scanning ions with a constant intensity in a selective area of the sample 115 through FIB milling, and the cross-sectional area A to be observed may be exposed. At this time, the FIB milling may be scanned at an angle of 35°to 70°with the sample 115, but is not limited thereto. In addition, FIB milling may be scanned to have an intensity of about 20 to 30 KeV and 1.5 nA to 12 nA, but is not limited thereto.

[0080] In addition, the sample 115 may be FIB-milled by the sample processing unit 170 and then inserted into the chamber after the cross-sectional area A to be observed is exposed. Alternatively, FIB milling may be performed in the chamber 110.

[0081] After FIB milling, an etching gas 185 may be injected into the chamber 110 through a gas injection system (GIS) 180. Referring momentarily to FIG. 5, FIG. 5 is a conceptual diagram of a gas injection system (GIS) used in the embodiment. The GIS 180 may include at least one of a raw material storage unit 181, a vaporizer 182, a gas control device 183, and an inlet 184. The inlet 184 of the GIS 180 may be connected to the chamber or placed in the chamber so as to be close to the sample. Although only one GIS 180 is shown in FIG. 5, when two or more types of etching gases are used, a plurality of GIS 180 may be connected to the chamber.

[0082] Referring again to FIG. 4, the etching gas 185 may be sprayed from the GIS 180 to the cross-sectional area A of the sample 115 or may be injected for a predetermined time to form an atmosphere in the chamber 110. The etching gas 185 may be, for example, an insulator enhancement etch (IEE) gas or XeF2 gas, but is not limited thereto. In addition, the etching gas 185 may include one or more types of etching gas.

[0083] The etching gas 185 may form roughness in the cross-sectional area A to be observed. In addition, the rate of forming the roughness may be different depending on regions of the insulating layer, the polymer layer, the semiconductor layer, etc. appearing in the cross-sectional region A. A flow amount of the etching gas 185 may be about 2% to about 4.5%. Accordingly, the aspect has a technical effect in that the division between regions becomes clear and cross-sectional observation may be improved.

[0084] In addition, the cross-sectional area A of the sample may be observed through the observation unit 175. The observation unit 175 may be a scanning electron microscope SEM, but is not limited thereto. SEM can be observed by adjusting the accelerating voltage, and can be performed in a low voltage region of 0.5 kV to 5 kV. In the aspect, after the cross-sectional area A of the sample 115 is partially etched by the etching gas 185, the junction of the SiC semiconductor device may be observed through the observation unit 175.

[0085] In addition, the junction profile of the sample 115 may be observed while forming the etching gas 185 atmosphere in the GIS 180. While the cross-sectional area A of the sample 115 is being etched by the etching gas 185, the junction of the SiC semiconductor device may be observed through the observation unit 175.

[0086] Therefore, the aspect has a technical effect of improving the visibility of the junction of the SiC semiconductor device as the cross-sectional area A of the sample 115 is etched by the etching gas 185. In addition, the aspect has a technical effect of analyzing the junction profile of the sample 115 while spraying the etching gas 185.

[0087] FIG. 6 is a view showing a part of the cross-section of the SiC semiconductor device to according to the aspect of the present disclosure. FIG. 5 is a view obtained according to the aspect of the present disclosure through SEM of the same region of the SiC semiconductor device as in FIG. 3.

[0088] FIG. 6 shows a gate and a channel connected to one region of the source / drain of the SiC MOSFET, but is not limited to. In addition, the SiC MOSFET may be an NMOSFET or a PMOSFET.

[0089] Referring to FIG 6, the SiC semiconductor device may include at least one of the semiconductor layer 140, the first doped region 150, the second doped region 160, the gate oxide 145, the polysilicon 130, and the insulating layer 135. The semiconductor layer 140 may include SiC. In addition, the first doped region 150 may be doped with a p-type dopant material and may be a P-Well region. For example, the first doped region 150 may be doped with a p-type dopant material such as Al, B, Ga, or In, but is not limited thereto.

[0090] The second doped region 160 may be doped with an n-type dopant material and may be an N+ region. For example, the n-type dopant material may be N, P, As, etc., but is not limited thereto. It is also possible that the first doped region 150 is an N-well region and the second doped region 160 is a P+ region.

[0091] Meanwhile, in the aspect, the etching gas injected into the chamber may increase surface roughness of the SiC semiconductor device. The etching gas may selectively etch the semiconductor material in the cross section of the sample.

[0092] The polysilicon 130, the insulating layer 135, and the gate oxide 145 may not be etched, but at least one of semiconductor regions including the semiconductor layer 140, the first doped region 150, and the second doped region 160 may be etched.

[0093] An etching rate may vary according to a flow rate of the etching gas and an atmosphere formation time, and surface roughness of at least one of the semiconductor regions may increase.

[0094] As the surface roughness of the semiconductor regions increases, the regions may become distinctly distinct. In detail, surface roughness of the semiconductor regions may be increased to diffusely reflect light or electron beams so that more light or electron beams may be recognized when observed in an observation unit. Accordingly, the distinction between junctions where different doping regions adjacent each other may be distinguished and clarified each other, and there is a technical effect of visually defining the implanted region.

[0095] In addition, the aspect has a technical effect that there is no deviation according to the state of the sample and the photographing conditions in the observation of the junction of the SiC semiconductor device. Accordingly, the aspect may improve reliability of junction profile analysis.

[0096] On the other hand, in internal studies, the length of the channel region varied depending on the state of the sample and the photographing conditions, and the division of the implant region was ambiguous, so that it was difficult to determine the exact shape and length of the channel region at the junction, so it was difficult to use it as data to analyze device defects.

[0097] On the other hand, as the semiconductor regions such as the semiconductor layer 140, the first doped region 150, and the second doped region 160 may become clearer, a channel region 155 may become clearer. Accordingly, a length of the channel region 155 may be accurately observed in the present disclosure.

[0098] In addition, when the electrical characteristics such as Vth of the SiC semiconductor device are different from the design characteristics, it was difficult to confirm whether an issue occurred in the channel region in the internal technology, but through the method of observing the junction profile of the SiC semiconductor device through the aspect, there is a technical effect of identifying the cause of the electrical defect of the device.

[0099] On the other hand, the junction depth was analyzed through an additional analysis method such as secondary ion mass spectrometry (SIMS), so there was a problem in that the time and cost of the analysis process increased.

[0100] On the other hand, as the semiconductor region such as the semiconductor layer 140, the first doped region 150, and the second doped region 160 are clearly distinguished in the aspect, there is a technical effect of accurately observing the junction depth.

[0101] Accordingly, there is a technical effect of reducing the time and cost of the analysis process by accurately analyzing the depth of the junction without an additional analysis method.

[0102] Therefore, the aspect has a technical effect of visually analyzing specifications of a specific region, such as channel and junction depth, in a SiC semiconductor device.

[0103] The method for observing the SiC semiconductor device according to the aspect has a technical effect of improving the visibility of a junction profile.

[0104] In addition, the aspect has a technical effect of clearly observing a specific region of a device and analyzing a junction profile in a SiC semiconductor device.

[0105] In addition, the aspect has a technical effect of reducing analysis time and cost because it is possible to accurately determine the junction depth without an additional analysis method.

[0106] For example, in the aspect, device characteristics such as channel length and junction depth may be observed without additional analysis.

[0107] In addition, the aspect has a technical effect that there is no deviation according to the state of the sample and the photographing conditions in observing the junction profile of the SiC semiconductor device.

[0108] In addition, through the junction profile analysis of the SiC semiconductor device according to the aspect, there is a technical effect of identifying the cause of the electrical defect of the device.

[0109] A junction profile observation method of the SiC semiconductor device according to the aspect may be used in the field of SiC power semiconductors such as SiC MOSFET, IGBT, and Schottky diode.

[0110] It will be apparent to those skilled in the art that various modifications and variations can be made in the method for observing the junction profile of the SiC semiconductor device of the present disclosure without departing from the spirit or scope of the aspects. Thus, it is intended that the present disclosure covers the modifications and variations of the aspects provided they come within the scope of the appended claims and their equivalents.

[0111] The power converter 1000 according to the present disclosure may receive DC power from a battery or fuel cell, convert it into AC power, and supply the AC power to a predetermined load.

[0112] For example, the power converter 1000 may include an inverter, which receive DC power from a battery, convert the DC power into 3-phase AC power, and supply the 3-phase AC power to a motor M. The motor M may provide power to electric vehicles or fuel cell vehicles.

Claims

1.A method for observing a junction profile of a SiC semiconductor device, comprising:providing the SiC semiconductor device within a chamber;providing an etching gas atmosphere within the chamber;etching a cross-sectional area of the SiC semiconductor device with the etching gas, andobserving a junction profile from the cross-sectional area of an etched SiC semiconductor device.2.The method according to claim 1, wherein the cross-sectional area of the SiC semiconductor device is prepared by cutting the SiC semiconductor device with focused ion beam (FIB) equipment.3.The method according to claim 1, wherein the etching gas includes insulator enhancement etch gas.4.The method according to claim 3, wherein a surface roughness of an undoped region and a doped region of a semiconductor layer of the SiC semiconductor device is increased by the insulator enhancement etch gas.5.The method according to claim 4, wherein the insulator enhancement etch gas is configured to distinguish the undoped region and the doped region of the semiconductor layer from each other.6.The method according to claim 5, wherein the doped region comprises a first doped region and a second doped region, andwherein the first doped region and the second doped region are distinguishable from each other by using the etching gas.7.The method according to claim 1, wherein the observing the junction profile from the cross-sectional area of the etched SiC semiconductor device is carried out by a scanning electron microscope.8.The method according to claim 1, wherein the observing the junction profile from the cross-sectional area of the etched SiC semiconductor device includes measuring a channel length of the SiC semiconductor device.9.The method according to claim 1, wherein the observing the junction profile from the cross-sectional area of the etched SiC semiconductor device includes measuring a junction depth of the SiC semiconductor device.10.A method for observing a junction profile of a SiC semiconductor device, comprising:providing the SiC semiconductor device within a chamber; andproviding an etching gas atmosphere in the chamber and observing a junction profile from a cross-sectional area of the SiC semiconductor device at the same time.11.The method according to claim 10, wherein the cross-sectional area of the SiC semiconductor device is formed by cutting the SiC semiconductor device with FIB equipment.12.The method according to claim 10, wherein the etching gas comprises insulator enhancement etch gas.13.The method according to claim 12, wherein the etching gas is configured to increase a surface roughness of an un-doped region and a doped region of a semiconductor layer of the SiC semiconductor device.14.The method according to claim 13, wherein the etching gas is configured to distinguish the un-doped region and the doped region of the semiconductor layer from each other.15.The method according to claim 14, wherein the doped region comprises a first doped region and a second doped region, andwherein the etching gas is configured to distinguish the first doped region and the second doped region from each other.16.The method according to claim 10, wherein the observing a junction profile from a cross-sectional area of the SiC semiconductor device while forming the etching gas atmosphere in the chamber comprises a step of observing a junction profile of the SiC semiconductor device using a scanning electron microscope.17.The method according to claim 10, wherein the observing a junction profile from a cross-sectional area of the SiC semiconductor device while forming the etching gas atmosphere in the chamber comprises measuring a channel length of the SiC semiconductor device.18.The method according to claim 10, wherein the observing a junction profile from a cross-sectional area of the SiC semiconductor device while forming the etching gas atmosphere in the chamber comprises a step of measuring a junction depth of the SiC semiconductor device.19.A method for observing a junction profile of a SiC semiconductor device, comprising:providing the SiC semiconductor device within a vacuum chamber;exposing a cross-sectional area of a junction of the SiC semiconductor device with a focused ion beam system to observe the junction profile;providing etching gas through a gas injection system in the chamber to selectively etch Si on the cross-sectional area of the SiC semiconductor device with the etching gas, andobserving the cross-sectional area of an etched SiC semiconductor device.20.The method according to claim 19, wherein the etch gas increases a surface roughness of the junction of the semiconductor layer of the SiC semiconductor device.

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