Array substrate and display panel

Abstract

An array substrate and a display panel. The array substrate (100) comprises a base substrate (10), a first signal line (20), a first transistor (T1), and a second transistor (T2). The first signal line (20) is arranged on the base substrate (10), and is at least partially located in a display area (AA). The first transistor (T1) is located in the display area (AA) and is arranged on the side of the first signal line (20) away from the base substrate (10). The first transistor (T1) comprises a first semiconductor pattern (31) and a first gate electrode (32) provided on the side of the first semiconductor pattern (31) away from the base substrate (10). The second transistor (T2) is located in a peripheral area (BB), and the second transistor (T2) comprises a second semiconductor pattern (33) and a second gate electrode (34) provided on the side of the second semiconductor pattern (33) away from the base substrate (10), with the first gate electrode (32) and the second gate electrode (34) being arranged on the same layer.

Description

Array substrate and display panel

[0001] [Corrected on 09.08.2024 according to Rule 91] This application claims priority to Chinese patent application No. 202310954089.4 filed on July 31, 2023, and priority to Chinese patent application No. 202411047961.8 filed on July 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0003] Current LCD panels employ a variety of common electrode configurations. One approach involves placing both the common electrode and the pixel electrode on the array substrate, as exemplified by Advanced-Super Dimensional Switching (ADS) technology. ADS utilizes the electric field generated by the edges of slit electrodes within the same plane, as well as the electric field between the slit electrode layer and the planar electrode layer, to create a multi-dimensional electric field. This allows the rotation of all aligned liquid crystal molecules within the liquid crystal cell, between the slit electrodes and directly above them.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate includes a base substrate, a first signal line, a first transistor, and a second transistor. The first signal line is disposed on the base substrate and is at least partially located in the display area. The first transistor is located in the display area and is disposed on a side of the first signal line away from the base substrate. The first transistor includes a first semiconductor pattern and a first gate disposed on a side of the first semiconductor pattern away from the base substrate. The second transistor is located in the peripheral area and includes a second semiconductor pattern and a second gate disposed on a side of the second semiconductor pattern away from the base substrate, with the first gate and the second gate disposed on the same layer.

[0006] In some embodiments, the first semiconductor pattern includes a first channel region and a first region and a second region located on both sides of the first channel region. The array substrate further includes a first insulating layer, a second insulating layer, a first via, and a first connecting electrode. The first insulating layer is located between the first signal line and the first semiconductor pattern. The second insulating layer is located on a side of the first semiconductor pattern away from the base substrate. The first via penetrates at least the first insulating layer and the second insulating layer, exposing at least a portion of the first signal line and at least a portion of the first region. The first connecting electrode is disposed on a side of the second insulating layer away from the base substrate, and the first connecting electrode is electrically connected to the first signal line and the first region, respectively, within the first via.

[0007] In some embodiments, the first connecting electrode and the first gate are made of the same material and are disposed in the same layer; at least a portion of an edge of the first connecting electrode contacts the first region.

[0008] In some embodiments, the first region includes a first sub-portion and a second sub-portion located within the first via. The first sub-portion contacts the first connecting electrode, the second sub-portion abuts an edge of the first connecting electrode, and the orthographic projections of the second sub-portion and the first connecting electrode on the substrate do not overlap. The conductivity of the second sub-portion is greater than that of the first sub-portion.

[0009] In some embodiments, the thickness of the first subsection is greater than or equal to the thickness of the second subsection.

[0010] In some embodiments, a dimension of the second sub-portion along a first direction is greater than or equal to 0.3 μm. The first direction is perpendicular to a boundary where the first sub-portion and the second sub-portion are adjacent.

[0011] In some embodiments, the first via includes a first side wall and a second side wall; the first side wall is located in the first insulating layer, and the end of the first side wall away from the substrate is connected to the first semiconductor pattern, and at least a portion of the second side wall is located in the second insulating layer; the slope angle of the first side wall is greater than the slope angle of the second side wall.

[0012] In some embodiments, the slope angle of the first side wall is 60° to 90°; and / or the slope angle of the second side wall is 30° to 60°.

[0013] In some embodiments, the array substrate further includes a second via, a second connecting electrode, a third insulating layer, a third via, and a first electrode. The second via penetrates the second insulating layer and exposes at least a portion of the second region. The second connecting electrode is disposed on a side of the second insulating layer away from the base substrate and is at least partially located within the second via. The second connecting electrode is connected to the second region within the second via. The third insulating layer is disposed on a side of the second connecting electrode away from the base substrate. The third via penetrates the third insulating layer and exposes at least a portion of the second connecting electrode. The first electrode is at least partially located within the third via, and the first electrode is connected to the second connecting electrode within the third via.

[0014] In some embodiments, the second connecting electrode and the first gate are made of the same material and are disposed in the same layer; at least a portion of an edge of the second connecting electrode contacts the second region.

[0015] In some embodiments, the second region includes a third sub-portion and a fourth sub-portion located within the second via hole. The third sub-portion contacts the second connecting electrode, the fourth sub-portion abuts an edge of the second connecting electrode, and the orthographic projections of the fourth sub-portion and the second connecting electrode on the substrate do not overlap. The conductivity of the fourth sub-portion is greater than that of the third sub-portion.

[0016] In some embodiments, the thickness of the third subsection is greater than or equal to the thickness of the fourth subsection.

[0017] In some embodiments, a dimension of the fourth sub-portion along a second direction is greater than or equal to 0.3 μm; and the second direction is perpendicular to a boundary between the third sub-portion and the fourth sub-portion.

[0018] In some embodiments, the orthographic projections of the second via hole and the third via hole on the base substrate partially overlap.

[0019] In some embodiments, the third insulating layer includes a passivation layer and a planarization layer stacked in a direction away from the base substrate, and the third via hole includes a first sub-hole extending through the passivation layer and a second sub-hole extending through the planarization layer. In orthographic projections of the first sub-hole, the second sub-hole, and the second via hole on the base substrate, the first sub-hole is located within the range of the second sub-hole, and the overlapping area between the first sub-hole and the second via hole is smaller than the overlapping area between the second sub-hole and the second via hole.

[0020] In some embodiments, in the orthographic projection of the second sub-hole and the second via hole on the substrate, the second sub-hole includes a first boundary located within the second via hole, and a spacing between the first boundary and a boundary of the second via hole is greater than or equal to 0.5 μm.

[0021] In some embodiments, the second insulating layer is disposed between the first semiconductor pattern and the first gate, the second insulating layer including a first pattern in contact with the first gate. In an orthographic projection of the first pattern and the first gate on the substrate, the first pattern covers the first gate, and a boundary between the first pattern and a boundary of the first gate is spaced 0.3 μm to 1.5 μm.

[0022] In some embodiments, the angle between the sidewall of the first gate and the plane where the substrate is located is 30° to 80°.

[0023] In some embodiments, the second transistor further includes a source and a drain, and the source and the drain are made of the same material and are disposed in the same layer as the second gate.

[0024] In some embodiments, the second semiconductor pattern includes a second channel region and a third region and a fourth region located on both sides of the second channel region. The array substrate further includes a second insulating layer, a fourth via, and a fifth via. The second insulating layer is disposed between the second semiconductor pattern and the second gate. The fourth via penetrates the second insulating layer and exposes at least a portion of the third region. The fifth via penetrates the second insulating layer and exposes at least a portion of the fourth region. Wherein, at least a portion of the source electrode is located in the fourth via hole, connected to the third region through the fourth via hole, and at least a portion of the edge of the source electrode is in contact with the third region; at least a portion of the drain electrode is located in the fifth via hole, connected to the fourth region through the fifth via hole, and at least a portion of the edge of the drain electrode is in contact with the fourth region.

[0025] In some embodiments, at least portions of edges of the source and the drain are in contact with the second semiconductor pattern.

[0026] In some embodiments, the third region includes a fifth sub-portion and a sixth sub-portion located within the fourth via. The fifth sub-portion contacts the source, the sixth sub-portion abuts an edge of the source, and the orthographic projections of the sixth sub-portion and the source on the substrate do not overlap. The conductivity of the sixth sub-portion is greater than that of the fifth sub-portion. The fourth region includes a seventh sub-portion and an eighth sub-portion located within the fifth via. The seventh sub-portion contacts the drain, the eighth sub-portion abuts an edge of the drain, and the orthographic projections of the eighth sub-portion and the drain on the substrate do not overlap. The conductivity of the eighth sub-portion is greater than that of the seventh sub-portion.

[0027] In some embodiments, a dimension of the sixth sub-section along a third direction is greater than or equal to 0.3 μm; the third direction is perpendicular to a boundary between the fifth and sixth sub-sections. And / or a dimension of the eighth sub-section along a fourth direction is greater than or equal to 0.3 μm; the fourth direction is perpendicular to a boundary between the seventh and eighth sub-sections.

[0028] In some embodiments, the thickness of the fifth subsection is greater than or equal to the thickness of the sixth subsection, and / or the thickness of the seventh subsection is greater than or equal to the thickness of the eighth subsection.

[0029] In some embodiments, the thickness difference between the sixth sub-section and the fifth sub-section is And / or, the thickness difference between the eighth sub-section and the seventh sub-section is

[0030] In some embodiments, the second transistor further includes a third gate disposed on a side of the second semiconductor pattern close to the base substrate, an orthographic projection of the third gate on the base substrate covering an orthographic projection of the second gate on the base substrate, and the third gate being electrically connected to the second gate.

[0031] In some embodiments, the array substrate further includes a first insulating layer, a second insulating layer, and a passivation layer, a planarization layer, a first electrode, a fourth insulating layer, and a second electrode, sequentially arranged in a direction away from the base substrate. The first insulating layer is located between the first signal line and the first semiconductor pattern and includes a first material layer and a second material layer stacked in a direction away from the base substrate; the first material layer includes silicon nitride, and the second material layer includes silicon oxide. The second insulating layer is located between the first semiconductor pattern and the first gate electrode, and the second insulating layer includes silicon oxide. The passivation layer includes a third material layer and a fourth material layer stacked in a direction away from the base substrate; the third material layer includes silicon oxide, and the fourth material layer includes silicon nitride. The fourth insulating layer includes silicon nitride.

[0032] In some embodiments, the ratio of silicon atoms to nitrogen atoms in the silicon nitride of the first material layer is 1:1 to 1:0.5; the ratio of silicon atoms to oxygen atoms in the silicon oxide of the second material layer is 1:1 to 1:2; the ratio of silicon atoms to oxygen atoms in the silicon oxide of the second insulating layer is 1:1 to 1:2; the ratio of silicon atoms to oxygen atoms in the silicon oxide of the third material layer is 1:1.5 to 1:2; the ratio of silicon atoms to nitrogen atoms in the silicon nitride of the fourth material layer is 1:1 to 1:0.6; the ratio of silicon atoms to nitrogen atoms in the silicon nitride of the fourth insulating layer is 1:1 to 1:0.6.

[0033] In another aspect, a display panel is provided. The display device comprises: a display panel as described in any of the above embodiments, a color filter substrate, and a liquid crystal layer. The color filter substrate is disposed opposite the array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate.

[0034] In another aspect, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and do not limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, etc. involved in the embodiments of the present disclosure.

[0036] FIG1 is a structural block diagram of a display device according to some embodiments;

[0037] FIG2 is a structural diagram of a display panel according to some embodiments;

[0038] FIG3 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0039] FIG4 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0040] FIG5 is a partial plan view of the structure of a display area according to some embodiments;

[0041] FIG6 is a cross-sectional view along section line AA in FIG5 ;

[0042] FIG7 is another cross-sectional view along the section line AA in FIG5;

[0043] FIG8 is a partial planar structural diagram of a first connection electrode according to some embodiments;

[0044] FIG9 is a partial cross-sectional structural diagram of a first connection electrode according to some embodiments;

[0045] FIG10 is a partial planar structural diagram of a second connection electrode according to some embodiments;

[0046] FIG11 is a structural diagram of a first gate according to some embodiments;

[0047] FIG12 is a planar structural diagram of a first transistor according to some embodiments;

[0048] FIG. 13 illustrates another planar structure of a first transistor according to some embodiments. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0052] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0053] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0057] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0058] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0059] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0060] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0063] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0064] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0065] 1 , an embodiment of the present disclosure provides a display device 1000 , which is a product having an image display function. For example, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0066] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0067] In some embodiments, the display device 1000 may be a liquid crystal display (LCD) device, based on its light-emitting type. The display device 1000 may be a flat display device or a curved display device, for example. The display device 1000 may be rectangular or circular, for example. Some embodiments of the present disclosure are described below using a rectangular, flat liquid crystal display device as an example. However, the present disclosure is not limited thereto, and any other display device may also be considered, as long as the same technical concept is applied.

[0068] In some embodiments, the display device 1000 includes a display panel 1100 and a driver circuit board. The driver circuit board may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board may also include other circuit structures, which are not listed here one by one. The driver circuit board is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not specifically limited here.

[0069] In the case where the display device 1000 is a liquid crystal display device, referring to FIG2 , the display device 1000 may further include a backlight source 1200 disposed on the backlight side of the display panel 1100. For example, the backlight source 1200 may be a direct-lit backlight source or an edge-lit backlight source, etc. The backlight source 1200 is used to provide light for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display panel 1100, thereby enabling each sub-pixel to display the same or different grayscales to achieve the purpose of image display.

[0070] Continuing with FIG2 , in the case where the display panel 1100 is a liquid crystal display panel, the display panel 1100 may include an array substrate 100 and a color filter substrate 200 (also referred to as an opposing substrate or packaging substrate) disposed opposite each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may filter the light incident on the color filter substrate 200 so that each sub-pixel emits light of a color (e.g., red, green, and blue). Different sub-pixels may emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. Of course, the display panel 1100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may further include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the opposing substrate close to the liquid crystal layer 300.

[0071] Referring to Figure 3, the array substrate 100 may include a display area AA and a peripheral area BB arranged around the display area AA. The display area AA may include a plurality of pixel circuits, a plurality of signal lines (such as a first signal line 20, a scan signal line, etc.), a first electrode (such as a common electrode) 41, and a second electrode (such as a pixel electrode) 42. The peripheral area BB may include, for example, a gate driver circuit (Gate Driver On Array; GOA for short). The pixel circuit may include, for example, a first transistor T1. In an embodiment of the present disclosure, one of the first electrode 41 and the second electrode 42 is configured to form a pixel electrode, and the other is configured to form a common electrode. The pixel electrode is configured to be electrically connected to the first signal line, and the common electrode is configured to be electrically connected to the common voltage signal terminal (constant voltage signal terminal).

[0072] For example, as shown in FIG3 , the first electrode 41 is configured to form a common electrode, and the second electrode 42 is configured to form a pixel electrode. In this case, the pixel circuit (first transistor T1) can be connected to the first signal line 20 and the second electrode 42, respectively, and is configured to transmit a data signal to the second electrode 42 via the first signal line 20. Under the action of the data signal, the second electrode 42 generates an electric field with the first electrode 41, and the electric field drives the rotation of the liquid crystal molecules in the liquid crystal layer to achieve control of different grayscales.

[0073] In the related art, in the display area, the signal line (such as the data signal line) is usually arranged on the side of the transistor (the transistor included in the pixel circuit) away from the base substrate. The pixel electrode and the common electrode are closely spaced from the signal line, and parasitic capacitance is easily generated between the signal line and the pixel electrode and the common electrode, resulting in an increase in the load on the signal line, reducing the charging efficiency of the first electrode, and is not conducive to reducing the power consumption of the array substrate.

[0074] To address the above technical issues, referring to FIG3 , an array substrate 100 provided in an embodiment of the present disclosure includes a base substrate 10, a first signal line 20, a first transistor T1, a second transistor T2, a first electrode 41, and a second electrode 42. The first signal line 20 is disposed on the base substrate 10 and is at least partially located in the display area AA. The first transistor T1 is located in the display area AA and is disposed on a side of the first signal line 20 away from the base substrate 10.

[0075] In the embodiment of the present disclosure, the first transistor T1 is arranged on the side of the first signal line 20 away from the base substrate 10, that is, the first signal line 20 is arranged on the side of the first transistor T1 close to the base substrate 10. This is beneficial to increasing the spacing between the first signal line 20 and the first electrode 41 and the second electrode 42, thereby reducing the parasitic capacitance between the first signal line 20 and the first electrode 41 and the second electrode 42, which is beneficial to reducing the load of the first signal line 20, improving the charging efficiency of the first electrode 41, and improving the pixel density and refresh rate of the array substrate 100, as well as reducing the power consumption of the first signal line 20 and reducing the overall power consumption of the array substrate 100.

[0076] For example, the base substrate 10 can be made of a rigid material such as glass to improve the base substrate 10's ability to support other film layers thereon. Of course, the base substrate 10 can also be made of a flexible material such as polyimide (PI) to improve the overall bending and stretching resistance of the metal oxide thin film transistor, thereby preventing the stress generated during bending, stretching, and twisting from causing the base substrate 10 to break and cause a short circuit. In practical applications, the material of the base substrate 10 can be selected according to actual needs to ensure that the metal oxide thin film transistor has good performance.

[0077] The first signal line 20 can be, for example, a data signal line. In this case, the first signal line 20 can be configured to transmit a data signal to the pixel electrode. Of course, in other embodiments, the first signal line 20 can also be used to transmit other signals, as long as the same technical concept is adopted.

[0078] Exemplarily, the material of the first signal line 20 may include a conductive material, which may include a metal material, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and alloys thereof, or the first signal line 20 may include a metal laminate structure. Exemplarily, the first signal line 20 may include one of a titanium-aluminum-titanium (Ti / Al / Ti) laminate structure, a molybdenum-aluminum (Mo / Al) laminate structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) laminate structure, a molybdenum-niobium-titanium (MoNb / Ti) laminate structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) laminate structure, a molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) laminate structure, a molybdenum-neodymium-copper laminate structure, a MoNb-copper-MoNb laminate structure, and an AlNb-molybdenum-AlNd laminate structure. Of course, the embodiments of the present disclosure are not limited thereto, and the first signal line 20 may also include any other suitable metal or metal laminate structure. In addition, the thickness of the first signal line 20 may be 1500 angstroms (1 angstrom = 10-10m) to 8000 angstroms. For example, the thickness of the first signal line 20 may be 1500 angstroms, 2000 angstroms, 5500 angstroms or 8000 angstroms, etc., which are not listed one by one in the embodiments of the present disclosure.

[0079] Continuing with FIG. 3 , the first transistor T1 refers to a transistor disposed within the display area AA. For example, the first transistor T1 is a transistor that constitutes a pixel circuit. The first transistor T1 includes a first semiconductor pattern 31 and a first gate 32 disposed on the side of the first semiconductor pattern 31 away from the base substrate 10. In other words, the first transistor T1 is a top-gate transistor. The second transistor T2 refers to a transistor disposed within the peripheral area BB. For example, the second transistor T2 may be a transistor that constitutes a gate drive circuit. The second transistor T2 includes a second semiconductor pattern 33 and a second gate 34 disposed on the side of the second semiconductor pattern 33 away from the base substrate 10. In other words, the second transistor T2 is also a top-gate transistor. The first gate 32 and the second gate 34 are disposed in the same layer. Thus, the first gate 32 and the second gate 34 can be formed using the same mask and / or the same material in the same patterning process, which helps simplify the array substrate manufacturing process and thereby reduce the manufacturing cost of the array substrate.

[0080] In some embodiments, the first semiconductor pattern 31 and the second semiconductor pattern 33 can be manufactured using various suitable semiconductor materials and various suitable manufacturing methods. In other words, the materials of the first semiconductor pattern 31 and the second semiconductor pattern 33 can include at least one of various suitable semiconductor materials. In some embodiments, the semiconductor material includes M1OaNb, where M1 is a single metal or a combination of multiple metals, a>0 and b≥0, O represents oxygen, and N represents nitrogen. In other words, the semiconductor material is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the semiconductor layer ACT includes indium gallium zinc oxide (IGZO). In addition, the material of the first semiconductor pattern 31 may be in an amorphous, partially crystalline, single-crystal or polycrystalline state, and may also be a single-layer or multi-layer structure.

[0081] In some embodiments, the first semiconductor pattern 31 can be made of a high-mobility metal oxide semiconductor (HMOS) material. This helps improve the electron mobility of the first semiconductor pattern 31 and thus the on-state current of the first transistor T1. Furthermore, the HMOS material exhibits good light stability, which helps improve the light stability of the first transistor T1. Examples of HMOS materials include, but are not limited to, rare-earth element-doped IZO and IGZO, with the concentration of the rare-earth element doping ranging from 0.1% to 2%.

[0082] Exemplarily, the first gate 32 and the second gate 34 may also include the same conductive material. For example, the first gate and the second gate 34 may be a metal stacked structure. The metal stacked structure may refer to the metal stacked structure of the first signal line 20 described above, and will not be described again here. The material of the first gate 32 and the second gate 34 may be the same as the material of the first signal line 20, or the material of the first gate 32 and the second gate 34 may be different from the material of the first signal line 20. In addition, the thickness of the first gate 32 and the second gate 34 may be For example, the thickness of the first gate 32 and the second gate 34 may be or Etc., the embodiments of the present disclosure will not list them one by one.

[0083] In some embodiments, referring to FIG. 3 and FIG. 4 , the array substrate 100 may further include a first insulating layer 51 , a second insulating layer 52 , a third insulating layer 53 , a fourth insulating layer 54 , a first electrode 41 , and a second electrode 42 .

[0084] The first insulating layer 51 is disposed between the first signal line 20 and the first semiconductor pattern 31. For example, the first insulating layer 51 may also be a buffer layer. The second insulating layer 52 is disposed on the side of the first semiconductor pattern 31 away from the base substrate 10. For example, the second insulating layer 52 may be located between the first semiconductor pattern 31 and the first gate 32. In this case, the second insulating layer 52 may also be a gate insulating layer GI. The third insulating layer 53 may include a passivation layer 531 and a flat layer 532 stacked in a direction away from the base substrate 10. The first electrode 41 is located between the third insulating layer 53 and the fourth insulating layer 54, and the second electrode 42 is located on the side of the fourth insulating layer 54 away from the base substrate 10.

[0085] Continuing with Figures 3 and 4, the first insulating layer 51 may include a first material layer 511 and a second material layer 512 stacked in a direction away from the base substrate 10. The first material layer 511 is made of silicon nitride (SixNy), and the second material layer 512 is made of silicon oxide (SixOy). The second insulating layer 52 is located between the first semiconductor pattern 31 and the first gate 32, and the second insulating layer 52 is made of silicon oxide (SixOy). The passivation layer 531 includes a third material layer 533 and a fourth material layer 534 stacked in a direction away from the base substrate 10. The third material layer 533 is made of silicon oxide (SixOy), and the fourth material layer 534 is made of silicon nitride (SixNy). The fourth insulating layer 54 is made of silicon nitride (SixNy). When the different film layers described above include the same material, the values ​​of "x" and "y" in the materials (e.g., SixOy and SixNy) can be the same or different.

[0086] In some embodiments, when the material of the first semiconductor pattern 31 is a high-mobility metal oxide semiconductor (HMOS), the ratio of silicon atoms to nitrogen atoms in the silicon nitride (SixNy) of the first material layer 511 is 1:1 to 1:0.5. The ratio of silicon atoms to oxygen atoms in the silicon oxide (SixOy) of the second material layer 512 is 1:1 to 1:2. The ratio of silicon atoms to oxygen atoms in the silicon oxide (SixOy) of the second insulating layer 52 is 1:1 to 1:2. The ratio of silicon atoms to oxygen atoms in the silicon oxide (SixOy) of the third material layer 533 is 1:1.5 to 1:2. The ratio of silicon atoms to nitrogen atoms in the silicon nitride (SixNy) of the fourth material layer 534 is 1:1 to 1:0.6. The ratio of silicon atoms to nitrogen atoms in the silicon nitride (SixNy) of the fourth insulating layer 54 is 1:1 to 1:0.6. In this way, the structural stability of the first semiconductor pattern 31 is improved. On this basis, the first semiconductor pattern 31 and the second semiconductor pattern 33 can be made of high-mobility metal oxide semiconductor (HMOS) material.

[0087] In some embodiments, referring to Figures 5, 6, and 7, the first semiconductor pattern 31 includes a first channel region 313 and a first region 311 and a second region 312 located on both sides of the first channel region 313. The first channel region 313 is configured to form a channel structure of the first transistor T1. One of the first region 311 and the second region 312 is configured to form the source (or source connection region) of the first transistor T1, and the other is configured to form the drain (or drain connection region) of the first transistor T1. Moreover, one of the first region 311 and the second region 312 is configured to be electrically connected to the first signal line 20, and the other is configured to be electrically connected to the first electrode (e.g., pixel electrode); for example, the first region 311 is configured to be electrically connected to the first signal line 20, and the second region 312 is configured to be electrically connected to the first electrode 41.

[0088] Continuing to refer to FIG. 5 , FIG. 6 and FIG. 7 , the array substrate 100 further includes a first insulating layer 51 , a second insulating layer 52 , a first via hole V1 and a first connecting electrode 43 .

[0089] The first via hole V1 penetrates at least the first insulating layer 51 and the second insulating layer 52, exposing at least a portion of the first signal line 20 and at least a portion of the first region 311. The first connecting electrode 43 is disposed on a side of the second insulating layer 52 away from the base substrate 10. The first connecting electrode 43 is electrically connected to the first signal line 20 and the first region 311 within the first via hole V1; that is, the first region 311 is electrically connected to the first signal line 20 through the first connecting electrode 43.

[0090] Compared with the first region 311 being directly electrically connected to the first signal line 20 through a via (at least part of the first region 311 is located in the via and is in direct contact with the first signal line 20), the first region 311 is electrically connected to the first signal line 20 through the first connecting electrode 43, which is beneficial to reducing the morphological fluctuations of the first region 311 in the direction perpendicular to the base substrate 10, thereby improving the thickness uniformity of the first region 311, reducing the risk of local fracture or excessive local thickness of the first region 311, and helping to improve the reliability of the first transistor T1.

[0091] In some embodiments, the first connecting electrode 43 can include the same material and be arranged in the same layer as the first gate 32, the first electrode 41, and the second electrode 42. Compared with using additional film layers and processes to prepare the first connecting electrode 43, the first connecting electrode 43 includes the same material and is arranged in the same layer as the first gate 32, the first electrode 41, and the second electrode 42, which is beneficial to simplifying the preparation process of the array substrate 100 and reducing the preparation cost of the array substrate 100.

[0092] In some embodiments, as shown in FIG6 , the first connection electrode 43 and the first gate 32 are made of the same material and are disposed in the same layer. Exemplarily, the first connection electrode 43 and the first gate 32 are formed using the same mask and / or the same material in the same patterning process. Exemplarily, the film layer where the first connection electrode 43 and the first gate 32 are located is a gate conductive layer.

[0093] 5 and 6 , when the first connection electrode 43 and the first gate 32 are disposed in the same layer, at least a portion of the edge of the first connection electrode 43 contacts the first region 311. This reduces the connection resistance between the first connection electrode 43 and the first region 311, thereby improving the connection reliability between the first connection electrode 43 and the first region 311. For example, as shown in FIG5 and 6 , the first connection electrode 43 contacts the first region 311 at an edge near one side of the first channel region 313.

[0094] The first transistor T1 is a top-gate transistor. The fabrication process of the array substrate shown in FIG6 includes: forming a first semiconductor pattern 31 on a base substrate 10; forming a second insulating layer 52; forming a gate conductive layer; and performing a conductorization process on the first semiconductor pattern 31 using the gate conductive layer as a mask. When the first connection electrode 43 and the first gate electrode 32 are disposed on the same layer, during the conductorization process of the first semiconductor pattern using the gate conductive layer as a mask, the portion of the first region 311 covered by the first connection electrode 43 is not subjected to the conductorization process, resulting in poor conductivity. The portion not blocked by the first connection electrode 43 is doped to form a conductor, reducing resistance. At least a portion of the edge of the first connection electrode 43 contacts the first region 311. The portion of the edge of the first connection electrode 43 that contacts the first region 311 can be in contact with the conductorized first region 311, thereby reducing the connection resistance (contact resistance) between the first connection electrode 43 and the first region 311.

[0095] In other embodiments, when the first connection electrode and the first electrode or the second electrode include the same material and are disposed in the same layer, the edge of the first connection electrode may contact the first region, or the edge of the first connection electrode may not contact the first region. For example, when the first connection electrode and the first electrode are disposed in the same layer, the edge of the first connection electrode may be located entirely on the third insulating layer, or a portion of the edge of the first connection electrode may be located in the third insulating layer, and a portion of the edge may contact the first region 311.

[0096] When the first connecting electrode and the first electrode or the second electrode include the same material and are arranged in the same layer, during the process of conducting the first semiconductor pattern using the gate conductive layer as a mask, the first connecting electrode has not yet been prepared and formed, so the first connecting electrode will not play a shielding role on the first semiconductor pattern. The entire first area can be conducted, and the first area can be considered to be entirely a conductor. At this time, as long as the first connecting electrode contacts the first area, electrical connection can be achieved, and the first connecting electrode and the first area have a small connection resistance.

[0097] In some embodiments, referring to Figures 8 and 9 , the first connection electrode 43 and the first gate 32 are made of the same material and are disposed on the same layer. The first region 311 includes a first sub-portion 314 and a second sub-portion 315 located within the first via hole V1. The first sub-portion 314 contacts the first connection electrode 43, and the second sub-portion 315 abuts the edge of the first connection electrode 43. The orthographic projections of the second sub-portion 315 and the first connection electrode 43 on the base substrate 10 do not overlap. The conductivity of the second sub-portion 315 is greater than that of the first sub-portion 314, which helps reduce the connection resistance between the edge of the first connection electrode 43 and the second sub-portion 315.

[0098] Exemplarily, the first sub-portion 314 and the second sub-portion 315 include the same semiconductor material, and the difference between the first sub-portion 314 and the second sub-portion 315 is that the second sub-portion 315 undergoes a process to make it conductive (e.g., a doping process). During the doping process, the first semiconductor pattern 31 is doped using the first gate 32 and the first connecting electrode 43 as a mask. The first sub-portion 314 contacts the first connecting electrode 43 and is located on the side of the first connecting electrode 43 close to the base substrate 10. The doping ions are blocked by the first connecting electrode 43 and are therefore not subjected to the doping process. The orthographic projection of the second sub-portion 315 on the base substrate 10 does not overlap with the orthographic projection of the first connecting electrode 43 on the base substrate 10. In other words, the first connecting electrode 43 does not block the second sub-portion 315. In this way, the second sub-portion 315 can undergo the doping process and become more conductive (compared to the first sub-portion 314).

[0099] In some embodiments, referring to Figures 8 and 9 , the thickness H1 of the first sub-portion 314 is greater than or equal to the thickness H2 of the second sub-portion 315. In other words, the area within the first via hole V1 not covered by the first connection electrode 43 (the second sub-portion 315) is thinner and is recessed toward the side closer to the base substrate 10 to form a groove. For example, the thickness of the first sub-portion 314 is greater than the thickness of the second sub-portion 315.

[0100] For example, the thickness difference ΔH (H1-H2) between the first sub-portion 314 and the second sub-portion 315 can be For example, the thickness difference ΔH between the first sub-portion 314 and the second sub-portion 315 may be Alternatively, the thickness difference ΔH between the first sub-portion 314 and the second sub-portion 315 may be For example, the thickness difference ΔH between the first sub-portion 314 and the second sub-portion 315 can be or Etc., the embodiments of the present disclosure will not list them one by one.

[0101] The array substrate preparation process may include: sequentially forming a first signal line, a first insulating layer, a first semiconductor pattern, and a second insulating layer on a base substrate, and then forming a first via hole penetrating the first and second insulating layers; the first via hole exposes a portion of the first signal line and a portion of the first region; in this case, the first via hole includes a portion located in the first insulating layer and a portion located in the second insulating layer. Then, a first gate electrode and a first connecting electrode (gate conductive layer) are formed on a side of the second insulating layer away from the base substrate; wherein at least a portion of the first connecting electrode is located within the first via hole, and the first connecting electrode only covers a portion of the first via hole, or in other words, the first connecting electrode also exposes a portion of the first via hole, so that at least a portion of the edge of the first connecting electrode can contact the first region through the first via hole. Then, the second insulating layer is patterned using the gate conductive layer as a mask; when the first connecting electrode exposes a portion of the first via hole, the portion of the first via hole located in the second insulating layer can only retain the portion covered by the first connecting electrode, while the portion not covered by the first connecting electrode is removed. Based on this, the first via hole can be a structure with one side open. In the embodiment of the present disclosure, the description of the “first via hole” is based on the range where the first via hole is located before the second insulating layer is patterned.

[0102] During the process of forming the first via hole, the first sub-portion 314 and the second sub-portion 315 are overetched to a certain extent compared to other areas of the first region 311, resulting in a reduction in thickness of the first sub-portion 314 and the second sub-portion 315. Furthermore, during the patterning process of the second insulating layer, the second sub-portion 315 and other areas of the first region 311 not covered by the first connection electrode 43 are overetched to a certain extent, resulting in a further reduction in thickness of the second sub-portion 315. Therefore, the thickness of the first sub-portion 314 is greater than or equal to the thickness of the second sub-portion 315, and the thickness of the second sub-portion 315 is less than the thickness of other portions of the first region 311. Based on this, the portion of the first via hole V1 not covered by the first connection electrode 43 can be defined by the region of the second sub-portion 315 (the region where the groove is located).

[0103] Continuing with FIG8 , the second sub-portion 315 has a dimension D1 along the first direction M1, which is greater than or equal to 0.3 μm. This significantly reduces the risk of the edge of the first connection electrode 43 failing to contact the second sub-portion 315 due to process errors, ensuring that at least a portion of the edge of the first connection electrode 43 can contact the second sub-portion 315, thereby improving the connection reliability between the first connection electrode 43 and the first region 311. The first direction M1 is the direction perpendicular to the boundary L1 between the first sub-portion 314 and the second sub-portion 315, as measured by the orthographic projection of the first region 311 on the base substrate 10.

[0104] In some embodiments, referring to FIG. 9 , the first via V1 includes a first sidewall 11 and a second sidewall 12. The first sidewall 11 is located in the first insulating layer 51, and the end of the first sidewall 11 away from the base substrate 10 is connected to the first semiconductor pattern 31. In other words, the first sidewall 11 refers to the portion of the sidewall of the first via V1 located on the side of the first semiconductor pattern 31 close to the base substrate 10. At least a portion of the second sidewall 12 is located within the second insulating layer 52. In other words, the second sidewall 12 comprises the sidewall of all areas of the first via V1 except the first sidewall 11. The slope angle α1 of the first sidewall 11 is greater than the slope angle α2 of the second sidewall.

[0105] During the process of preparing and forming the first via hole V1, the first via hole V1 penetrates the second insulating layer 52 to expose a portion of the first region 311 and a portion of the first insulating layer 51. During continued etching, a hard mask is formed in the first region 311 to prevent further etching of the first insulating layer 51 under the first region 311. However, the portion of the first insulating layer 51 exposed by the first via hole V1 can continue to be etched. Based on this, the first side wall 11 and the second side wall 12 with different slope angles are formed in the first via hole V1.

[0106] In some embodiments, the slope angle α1 of the first sidewall 11 is 60° to 90°. For example, the slope angle α1 of the first sidewall 11 may be 60° to 70°; or the slope angle α1 of the first sidewall 11 may be 70° to 80°; or the slope angle α1 of the first sidewall 11 may be 80° to 90°. For example, the slope angle α1 of the first sidewall 11 may be 60°, 65°, 70°, 75°, 80°, 85°, or 90°, etc., which are not listed in detail in the embodiments of the present disclosure.

[0107] In some embodiments, the slope angle α2 of the second sidewall 12 is 30° to 60°. For example, the slope angle α2 of the second sidewall 12 may be 30° to 40°; or the slope angle α2 of the second sidewall 12 may be 40° to 50°; or the slope angle α2 of the second sidewall 12 may be 50° to 60°. For example, the slope angle α2 of the second sidewall 12 may be 30°, 35°, 40°, 45°, 50°, 55°, or 60°, etc., which are not listed in detail in the embodiments of the present disclosure.

[0108] 6 and 7 , the array substrate 100 further includes a second via hole V2 , a second connection electrode 44 , a third insulating layer 53 and a third via hole V3 . The third insulating layer 53 is disposed on a side of the second connection electrode 44 away from the base substrate 10 .

[0109] The second via V2 penetrates the second insulating layer 52 and exposes at least a portion of the second region 312. Exemplarily, the orthographic projection of the second via V2 on the base substrate 10 is within the range of the orthographic projection of the second region 312 on the base substrate 10. The second connecting electrode 44 is disposed on a side of the second insulating layer 52 away from the base substrate 10. At least a portion of the second connecting electrode 44 is located within the second via V2, and the second connecting electrode 44 is connected to the second region 312 within the second via V2. The third via V3 penetrates the third insulating layer 53 and exposes at least a portion of the second connecting electrode 44. At least a portion of the first electrode 41 is located within the third via V3, and the first electrode 41 is connected to the second connecting electrode 44 within the third via. In other words, the first electrode 41 is electrically connected to the second region 312 via the third via V3, the second connecting electrode 44, and the second via V2, in sequence. Compared with the direct connection between the first electrode 41 and the second area 312 through the via, the first electrode 41 is connected to the second area 312 through the second connecting electrode 44, which is beneficial to reducing the depth of the via through which the first electrode 41 passes, improving the adhesion ability (climbing ability) of the first electrode 41 on the side wall of the via, and thereby reducing the risk of short circuit of the first electrode 41 on the side wall of the via.

[0110] In some embodiments, the second connection electrode 44 can be made of the same material and disposed in the same layer as the first gate electrode 32. Compared to using additional film layers and processes to prepare the second connection electrode 44, the second connection electrode 44 and the first gate electrode 32 are made of the same material and disposed in the same layer, which helps simplify the manufacturing process of the array substrate 100 and reduce the manufacturing cost of the array substrate 100. Exemplarily, the second connection electrode 44 and the first gate electrode 32 are formed using the same mask and / or the same material in the same patterning process. Exemplarily, the second connection electrode 44, the first gate electrode 32, and the first connection electrode 43 can be disposed in the same layer, and the film layer containing the second connection electrode 44, the first gate electrode 32, and the first connection electrode 43 is referred to as a gate conductive layer.

[0111] 6 , 7 , and 10 , when the second connecting electrode 44 is disposed in the same layer as the first gate electrode 32, at least a portion of the edge of the second connecting electrode 44 contacts the second region 312. Similar to the reason why the edge of the first connecting electrode 43 contacts the first region 311, at least a portion of the edge of the second connecting electrode 44 contacts the second region 312. This reduces the connection resistance between the second connecting electrode 44 and the second region 312, thereby improving the connection reliability between the second connecting electrode 44 and the second region 312.

[0112] 10 , the second connection electrode 44 contacts the second region 312 at one edge close to the first channel region 313 . However, the present disclosure is not limited thereto. For example, the second connection electrode 44 may also contact the second region 312 at two or three edges.

[0113] The first transistor T1 is a top-gate transistor. The manufacturing process of the array substrate includes: forming a first semiconductor pattern; forming a second insulating layer; forming a gate conductive layer (including a second connecting electrode); and performing a conductorization process on the first semiconductor pattern using the gate conductive layer as a mask. When the second connecting electrode and the first gate electrode are provided in the same layer, during the conductorization process on the first semiconductor pattern using the gate conductive layer as a mask, the portion of the second region covered by the second connecting electrode is not subjected to the conductorization process and has poor conductivity, while the portion not blocked by the second connecting electrode is doped to form a conductor and has low resistance. At least a portion of the edge of the second connecting electrode contacts the second region, so that the portion of the edge of the second connecting electrode in contact with the second region contacts the conductorized second region, thereby reducing the connection resistance between the second connecting electrode and the second region.

[0114] In some embodiments, as shown in Figures 6, 7, and 10, the second region 312 includes a third sub-portion 316 and a fourth sub-portion 317 located within the second via hole V2. The third sub-portion 316 contacts the second connection electrode 44, and the fourth sub-portion 317 abuts the edge of the second connection electrode 44. Furthermore, the orthographic projections of the fourth sub-portion 317 and the second connection electrode 44 on the base substrate 10 do not overlap. The conductivity of the fourth sub-portion 317 is greater than that of the third sub-portion 316, which helps reduce the connection resistance between the edge of the second connection electrode 44 and the second region 312 (the fourth sub-portion 317).

[0115] Exemplarily, the third sub-portion 316 and the fourth sub-portion 317 comprise the same semiconductor material, and the difference between the third sub-portion 316 and the fourth sub-portion 317 is that the fourth sub-portion 317 undergoes a process to render it conductive (e.g., a doping process). During the doping process, the first semiconductor pattern 31 is doped using the first gate electrode 32 and the second connecting electrode 44 as a mask. The third sub-portion 316 contacts the second connecting electrode 44 and is located on the side of the second connecting electrode 44 closer to the base substrate 10. The doping ions are blocked by the second connecting electrode 44, and therefore the third sub-portion 316 does not undergo the doping process. The orthographic projection of the fourth sub-portion 317 on the base substrate 10 does not overlap with the orthographic projection of the second connecting electrode 44 on the base substrate 10. In other words, the second connecting electrode 44 does not block the fourth sub-portion 317. As a result, the fourth sub-portion 317 can undergo the doping process and become more conductive (compared to the first sub-portion 314).

[0116] In some embodiments, the thickness of the third sub-portion 316 (perpendicular to the dimension of the base substrate 10) is greater than or equal to the thickness of the fourth sub-portion 317 (perpendicular to the dimension of the base substrate 10). In other words, the area within the second via hole V2 not covered by the second connection electrode 44 (the fourth sub-portion 317) is thinner and is concave toward the side closer to the base substrate 10 to form a groove. Exemplarily, the thickness of the third sub-portion 316 is greater than the thickness of the fourth sub-portion 317.

[0117] For example, the thickness difference between the third sub-section 316 and the fourth sub-section 317 can be For example, the thickness difference between the third sub-section 316 and the fourth sub-section 317 can be Alternatively, the thickness difference ΔH between the third sub-portion 316 and the fourth sub-portion 317 may be For example, the thickness difference ΔH between the third sub-section 316 and the fourth sub-section 317 can be or For example, the thickness difference between the third sub-section 316 and the fourth sub-section 317 may be equal to the thickness difference between the first sub-section 314 and the second sub-section 315 .

[0118] The preparation process of the array substrate may include: forming a first signal line, a first insulating layer, a first semiconductor pattern and a second insulating layer on the base substrate in sequence, and then forming a second via hole penetrating the second insulating layer; the second via hole exposes a portion of the second region. Then, a first gate and a second connecting electrode (gate conductive layer) are formed on the side of the second insulating layer away from the base substrate. At least part of the second connecting electrode is located in the second via hole, and the second connecting electrode exposes a portion of the first via hole so that at least part of the edge of the second connecting electrode can contact the second region in the second via hole. The second insulating layer is patterned using the gate conductive layer as a mask, and the second connecting electrode exposes a portion of the second via hole. The second via hole can only retain a portion of the area covered by the second connecting electrode. In the embodiment of the present disclosure, the description of the "second via hole" is based on the range where the second via hole is located before the second insulating layer is patterned.

[0119] Structurally, during the formation of the second via hole, the third and fourth sub-sections undergo a certain amount of overetching compared to other areas of the second region, resulting in a reduction in thickness. Furthermore, during the patterning of the second insulating layer, the fourth sub-section and other areas of the second region not covered by the second connection electrode undergo a certain amount of overetching, further reducing the thickness of the fourth sub-section. Therefore, the thickness of the third sub-section is greater than or equal to that of the fourth sub-section 317. Based on this, the portion of the second via hole V2 not covered by the second connection electrode 44 can be defined by the area of ​​the fourth sub-section 317 (the area where the groove is located).

[0120] Referring to FIG. 10 , the fourth sub-portion 317 has a dimension D2 along the second direction M2, which is greater than or equal to 0.3 μm. This significantly reduces the risk of the edge of the second connecting electrode 44 failing to contact the fourth sub-portion 317 due to process errors, ensuring that at least a portion of the edge of the second connecting electrode 44 can contact the fourth sub-portion 317, thereby improving the connection reliability between the second connecting electrode 44 and the second region 312. The second direction M2 is the direction perpendicular to the boundary L2 between the third sub-portion 316 and the fourth sub-portion 317, as viewed in the orthographic projection of the second region 312 on the substrate 10.

[0121] In some embodiments, referring to Figures 6, 7, and 10, the orthographic projections of the second via V2 and the third via V3 on the substrate 10 partially overlap. That is, in the orthographic projections of the second via V2 and the third via V3 on the substrate 10, at least a portion of the second via V2 is located outside the range of the third via V3, and at least a portion of the third via V3 is located outside the second via V2. It can also be considered that the second via V2 and the third via V3 are partially staggered. This prevents the third via V3 from completely covering the second via V2, or vice versa, and reduces the area of ​​overlap between the third via V3 and the second via V2. This prevents the third insulating layer 53 from forming a large-area (equal to the area of ​​the second via V2) and thick film layer at the location of the second via V2. This reduces photoresist residue formed within the third via V3 during patterning to form the third via V3.

[0122] 6 and 7 , the third insulating layer 53 may include a passivation layer 531 and a planarization layer 532 stacked in a direction away from the base substrate 10. The third via hole V3 includes a first sub-hole V31 penetrating the passivation layer 531 and a second sub-hole V32 penetrating the planarization layer.

[0123] The orthographic projection of the first sub-hole V31 on the base substrate 10 is within the range of the orthographic projection of the second sub-hole V32 on the base substrate 10, and the overlapping area of ​​the orthographic projection of the first sub-hole V31 on the base substrate and the orthographic projection of the second via hole V2 on the base substrate 10 is smaller than the overlapping area of ​​the orthographic projection of the second sub-hole V32 on the base substrate and the orthographic projection of the second via hole V2 on the base substrate 10. This greatly reduces the overlapping area of ​​the third via hole V3 and the second via hole V2, and greatly reduces the risk of photoresist residue forming in the third via hole V3.

[0124] The array substrate 100 shown in FIG7 differs from the array substrate 100 shown in FIG6 in that, in the array substrate 100 shown in FIG6 , the first electrode 41 is configured to form a common electrode, the second electrode 42 is configured to form a pixel electrode, and the second electrode 42 is electrically connected to the second connection electrode 44 via a third via hole V3. In the array substrate 100 shown in FIG7 , the second electrode 42 is configured to form a common electrode, the first electrode 41 is configured to form a pixel electrode, and the first electrode 41 is electrically connected to the second connection electrode 44 via a third via hole V3.

[0125] For example, when the array substrate is configured to form a display panel with a high pixel density, the first electrode 41 can be configured to form a pixel electrode; in this case, the array substrate can be used to manufacture a VR / AR display device, for example. When the array substrate is used to form a display panel with a lower pixel density, the first electrode 41 can be configured to form a common electrode. In this case, the first electrode can also shield the second electrode from the first signal line 20, thereby reducing the impact of voltage fluctuations on the first signal line 20 on the voltage on the second electrode 42; in this case, the array substrate can be used to manufacture display devices such as notebooks and televisions.

[0126] Referring to Figure 6, when the first electrode 41 is configured to form a common electrode and the second electrode 42 is configured to form a pixel electrode, the process of preparing the array substrate includes sequentially forming a passivation layer 531, a flat layer 532 and a fourth insulating layer 54, wherein the material of the flat layer 532 includes an organic material. During the process of forming the flat layer 532, the second sub-hole V32 can be directly exposed, the fourth insulating layer 54 and the passivation layer 531 can contact within the second sub-hole V32, and the fourth insulating layer 54 and the passivation layer 531 can be synchronously etched to form the first sub-hole V31. At this time, the first sub-hole V31 also penetrates the fourth insulating layer 54.

[0127] As shown in Figure 7 , when the second electrode 42 is configured to form a common electrode and the first electrode 41 is configured to form a pixel electrode, the process of preparing the array substrate includes sequentially forming a passivation layer 531 and a planarization layer 532. The planarization layer 532 is made of an organic material. During the formation of the planarization layer 532, the second sub-hole V32 can be directly exposed to form a second sub-hole V32, which exposes a portion of the passivation layer 531. The portion of the passivation layer 531 exposed by the second sub-hole V32 is then etched to form a first sub-hole V31, which exposes the second connecting electrode 44. The process of preparing the array substrate also includes forming a first electrode 41 on the planarization layer, which passes through the second sub-hole V32 and the first sub-hole V31 to connect to the connecting electrode. Furthermore, the process of preparing the array substrate also includes forming a fourth insulating layer 54 on the side of the first electrode 41 away from the base substrate 10, which covers the first sub-hole V31 and the second sub-hole V32.

[0128] In the following embodiments of the present disclosure, the present disclosure is exemplarily described by taking the example of the first electrode 41 being configured to form a common electrode and the second electrode 42 being configured to form a pixel electrode as shown in FIG. 6 .

[0129] In some embodiments, referring to FIG. 10 , in the orthographic projection of the second sub-hole V32 and the second via V2 on the base substrate 10 , the second sub-hole V32 includes a first boundary L3 located within the second via V2, and the spacing D3 between the first boundary L3 and the boundary of the second via V2 is greater than or equal to 0.5 μm. This minimizes the risk of overlap between the first boundary L3 and the boundary of the second via V2 due to process errors, helps reduce the overlap area between the second sub-hole V32 and the second via V2, and reduces the risk of photoresist residue. For example, the spacing D3 between the first boundary L3 and the boundary of the second via V2 can be 0.5 μm, 0.6 μm, 0.7 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0130] In some embodiments, referring to FIG. 11 , a second insulating layer 52 is disposed between the first semiconductor pattern 31 and the first gate 32. The second insulating layer 52 includes a first pattern 521 that contacts the first gate 32. In an orthographic projection of the first pattern 521 and the first gate 32 on the substrate 10, the first pattern 521 covers the first gate 32, and a distance D4 between the boundary of the first pattern 521 and the boundary of the first gate 32 is 0.3 μm to 1.5 μm. In other words, the area of ​​the first pattern 521 is larger than that of the first gate 32.

[0131] For example, the distance D4 between the boundary of the first pattern 521 and the boundary of the first gate 32 may be 0.3 μm to 0.7 μm; or the distance D4 between the boundary of the first pattern 521 and the boundary of the first gate 32 may be 0.7 μm to 1.1 μm; or the distance D4 between the boundary of the first pattern 521 and the boundary of the first gate 32 may be 1.1 μm to 1.5 μm. For example, the distance between the boundary of the first pattern 521 and the boundary of the first gate 32 may be 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.1 μm, or 1.5 μm.

[0132] For example, during patterning of the second insulating layer 52 using the gate conductive layer (first gate) as a mask, the portion of the second insulating layer 52 close to the first gate 32 is not etched away, which causes the edge of the first pattern 521 to extend beyond the boundary of the first gate 32 .

[0133] In some embodiments, referring to FIG11 , the angle α3 between the sidewall 321 of the first gate 32 and the plane of the substrate 10 is 30° to 80°. In other words, the slope angle α3 of the sidewall 321 of the first gate 32 is 30° to 80°. For example, the angle α3 between the sidewall 321 of the first gate 32 and the plane of the substrate 10 can be 30° to 55°; or the angle α3 between the sidewall 321 of the first gate 32 and the plane of the substrate 10 can be 55° to 80°. For example, the angle α3 between the sidewall 321 of the first gate 32 and the plane of the substrate 10 can be 30°, 40°, 50°, 55°, 65°, or 80°, etc., which are not listed one by one in the embodiments of the present disclosure.

[0134] In some embodiments, referring to Figures 3 and 12, the second transistor T2 further includes a source 35 and a drain 36. The source 35 and the drain 36 include the same material and are arranged in the same layer as the second gate 34. In this way, the second gate 34, the source 35 and the drain 36 of the second transistor T2 are arranged in the same layer. For example, the second gate 34, the source 35 and the drain 36 are formed using the same mask and / or the same material in the same patterning process, which is conducive to simplifying the preparation process of the array substrate and reducing the preparation cost of the array substrate.

[0135] Continuing with FIG. 12 , the second semiconductor pattern 33 includes a second channel region 333 and a third region 331 and a fourth region 332 located on either side of the second channel region 333. The second channel region 333 is configured to form the channel structure of the second transistor T2. One of the third region 331 and the fourth region 332 is configured to form the source (or source connection region) of the second transistor T2, and the other is configured to form the drain (or drain connection region) of the second transistor T2. For example, the third region 331 is configured to form the source connection region, and the fourth region 332 is configured to form the drain connection region.

[0136] The array substrate 100 further includes a second insulating layer 52, a fourth via hole V4, and a fifth via hole V5. The second insulating layer 52 is located between the second semiconductor pattern 33 and the second gate 34. The fourth via hole V4 penetrates the second insulating layer 52 and exposes at least a portion of the third region 331. The fifth via hole V5 penetrates the second insulating layer 52 and exposes at least a portion of the fourth region 332.

[0137] At least a portion of the source electrode 35 is located within the fourth via V4. The source electrode 35 is connected to the third region 331 through the fourth via V4, and at least a portion of the edge of the source electrode 35 is in contact with the third region 331. This reduces the connection resistance between the source electrode 35 and the third region 331, thereby improving the connection reliability between the source electrode 35 and the third region 331. At least a portion of the drain electrode 36 is located within the fifth via V5, connected to the fourth region 332 through the fifth via V5, and at least a portion of the edge of the drain electrode 36 is in contact with the fourth region 332. This helps reduce the connection resistance between the drain electrode 36 and the fourth region 332, thereby improving the connection reliability between the drain electrode 36 and the fourth region 332.

[0138] In some embodiments, the third region 331 includes a fifth sub-portion 334 and a sixth sub-portion 335 located within the fourth via V4. The fifth sub-portion 334 contacts the source electrode 35, the sixth sub-portion 335 abuts the edge of the source electrode 35, and the orthographic projections of the sixth sub-portion 335 and the source electrode 35 on the substrate 10 do not overlap. The conductivity of the sixth sub-portion 335 is greater than that of the fifth sub-portion 334. This helps reduce the connection resistance between the third region 331 and the source electrode 35. The fourth region 332 includes a seventh sub-portion 336 and an eighth sub-portion 337 located within the fifth via V5. The seventh sub-portion 336 contacts the drain electrode 36, and the eighth sub-portion 337 abuts the edge of the drain electrode 36. The orthographic projections of the eighth sub-portion 337 and the drain electrode 36 on the substrate 10 do not overlap. The conductivity of the eighth sub-portion 337 is greater than that of the seventh sub-portion 336. This helps reduce the connection resistance between the fourth region 332 and the drain electrode 36.

[0139] Exemplarily, the fifth sub-portion 334 and the sixth sub-portion 335 comprise the same semiconductor material, and the difference between the fifth sub-portion 334 and the sixth sub-portion 335 is that the sixth sub-portion 335 undergoes a process to render it conductive (e.g., a doping process). The seventh sub-portion 336 and the eighth sub-portion 337 comprise the same semiconductor material, and the difference between the seventh sub-portion 336 and the eighth sub-portion 337 is that the eighth sub-portion 337 undergoes a process to render it conductive (e.g., a doping process). For example, during the doping process, the second semiconductor pattern 33 is doped using the second gate 34, the source 35, and the drain 36 as masks. The fifth sub-portion 334 and the seventh sub-portion 336 are in contact with the source 35 and the drain 36, respectively, and are shielded by the source 35 and the drain 36, and therefore do not undergo the doping process. Conversely, the sixth sub-portion 335 and the eighth sub-portion 337 are not shielded by the second gate 34, the source 35, and the drain 36, and can undergo the doping process to become more conductive.

[0140] In some embodiments, the thickness of the sixth subsection 335 is greater than or equal to the thickness of the fifth subsection 334; and / or the thickness of the eighth subsection 337 is greater than or equal to the thickness of the seventh subsection 336. For example, the thickness of the sixth subsection 335 is greater than the thickness of the fifth subsection 334; and the thickness of the eighth subsection 337 is greater than the thickness of the seventh subsection 336.

[0141] The preparation process of the column substrate may include: forming a second semiconductor pattern and a second insulating layer on the base substrate in sequence. Then, forming a fourth via V4 and a fifth via V5 through the second insulating layer. Then, forming a second gate, source, and drain (gate conductive layer) on the side of the second insulating layer away from the base substrate. Then, patterning the second insulating layer using the gate conductive layer as a mask. In the embodiments of the present disclosure, the descriptions of "fourth via" and "fifth via" refer to the areas where the fourth and fifth vias are located before the second insulating layer is patterned. Structurally, during the formation of the fourth and fifth vias, the fifth sub-portion 334 and the sixth sub-portion 335 undergo a certain amount of overetching compared to other areas of the third region 331, resulting in a reduction in thickness of the fifth and sixth sub-portions 334 and 335. Furthermore, the seventh and eighth sub-portions 336 and 337 undergo a certain amount of overetching compared to other areas of the fourth region 332, resulting in a reduction in thickness of the seventh and eighth sub-portions 336 and 337. During the patterning process of the second insulating layer, portions of the eighth and sixth sub-portions 337 and 335, as well as the third and fourth regions 331 and 332 not covered by the gate conductive layer, are overetched to a certain extent. This results in a further reduction in the thickness of the eighth and sixth sub-portions 337 and 335. The thickness of the fifth sub-portion 334 is greater than that of the sixth sub-portion 335, and the thickness of the seventh sub-portion is greater than that of the eighth sub-portion 337. Based on this, the portion of the fourth via V4 not covered by the source electrode 35 can be defined by the region of the sixth sub-portion 335 (the region with a smaller thickness), and the portion of the fifth via V5 not covered by the drain electrode 36 can be defined by the region of the eighth sub-portion 337 (the region with a smaller thickness).

[0142] In some embodiments, the thickness difference between the sixth sub-section 335 and the fifth sub-section 334 is For example, the thickness difference between the sixth sub-portion 335 and the fifth sub-portion 334 may be Alternatively, the thickness difference between the sixth sub-portion 335 and the fifth sub-portion 334 may be For example, the thickness difference between the sixth sub-section 335 and the fifth sub-section 334 can be or Etc., the embodiments of the present disclosure will not list them one by one.

[0143] In some embodiments, the thickness difference between the eighth sub-portion 337 and the seventh sub-portion 336 is For example, the thickness difference between the eighth sub-portion 337 and the seventh sub-portion 336 may be Alternatively, the thickness difference between the eighth sub-portion 337 and the seventh sub-portion 336 may be For example, the thickness difference between the eighth sub-section 337 and the seventh sub-section 336 can be or Etc., the embodiments of the present disclosure will not list them one by one.

[0144] In some embodiments, referring to FIG. 12 , the dimension D5 of the sixth sub-portion 335 along the third direction M3 is greater than or equal to 0.3 μm. The third direction M3 is the direction perpendicular to the boundary L4 between the fifth sub-portion 334 and the sixth sub-portion 335 in the orthographic projection of the third region 331 on the base substrate 10. In this way, the risk of the edge of the source 35 failing to contact the sixth sub-portion 335 due to process errors can be greatly reduced, ensuring that at least part of the edge of the source 35 can contact the sixth sub-portion 335, thereby improving the connection reliability between the source 35 and the third region 331. For example, the dimension D5 of the sixth sub-portion 335 along the third direction M3 can be 0.3 μm, 0.4 μm, 0.5 μm, or 0.6 μm, etc., which are not listed one by one in the embodiments of the present disclosure.

[0145] Continuing to refer to FIG. 12 , the dimension D6 of the eighth sub-portion 337 along the fourth direction M4 is greater than or equal to 0.3 μm. The fourth direction M4 is the direction perpendicular to the boundary L5 between the seventh sub-portion 336 and the eighth sub-portion 337 in the orthographic projection of the fourth region 332 on the base substrate 10. In this way, the risk of the edge of the drain 36 failing to contact the eighth sub-portion 337 due to process errors can be greatly reduced, ensuring that at least part of the edge of the drain 36 can contact the eighth sub-portion 337, thereby improving the connection reliability between the drain 36 and the fourth region 332. For example, the dimension D5 of the sixth sub-portion 335 along the third direction M3 can be 0.3 μm, 0.4 μm, or 0.5 μm, etc., which are not listed one by one in the embodiments of the present disclosure.

[0146] 12 , when the source 35 and the drain 36 extend in the same direction and two parallel edges of the source 35 and the drain 36 contact the sixth sub-portion 335 and the eighth sub-portion 337 , respectively, the third direction M3 and the fourth direction M4 may be parallel to each other.

[0147] For example, as shown in Figures 12 and 13 , the number of fourth vias V4 can be multiple. The multiple fourth vias V4 can be spaced apart along the direction in which the source electrode 35 extends, and the source electrode 35 is connected to the third region 331 through the multiple fourth vias V4. The number of fifth vias V5 can also be multiple. The multiple fifth vias V5 can be spaced apart along the direction in which the drain electrode 36 extends, and the drain electrode 36 is connected to the fourth region 332 through the multiple fifth vias V5.

[0148] In some embodiments, as shown in FIG12 , one side edge of the source electrode 35 contacts the third region 331. It is contemplated that in other embodiments, referring to FIG13 , the source electrode 35 may also have two side edges that contact the third region 331. For example, both side edges of the source electrode 35 along the third direction M3 may contact the third region 331. Corresponding to the source electrode 35, the drain electrode 36 may also have two or more side edges that contact the fourth region 332.

[0149] Continuing with Figures 12 and 13 , the second transistor T2 of the array substrate 100 may further include a third gate 37. The third gate 37 is disposed on a side of the second semiconductor pattern 33 that is close to the base substrate 10 and is electrically connected to the second gate 34. Thus, the second transistor T2 may form a dual-gate structure comprising the second gate 34 and the third gate 37. The upper and lower sides of the second channel region 333 may form a conductive interface, which facilitates increasing the on-state current of the second transistor T2. The orthographic projection of the third gate 37 on the base substrate 10 overlaps the orthographic projection of the second gate 34 on the base substrate 10. Thus, the third gate 37 may shield the second channel region 333, thereby reducing the risk of light irradiating the second channel region 333. This, in turn, improves the light stability of the second channel region 333 and reduces the risk of voltage drift in the second transistor T2.

[0150] For example, the third gate 37 can be made of the same material and disposed in the same layer as the first signal line 20. For example, the third gate 37 and the first signal line 20 can be formed using the same mask and / or the same material in the same patterning process. This can help simplify the array substrate manufacturing process and reduce the manufacturing cost of the array substrate.

[0151] In some embodiments, as shown in FIG6 , the array substrate 100 may further include a shielding pattern 21. The shielding pattern 21 is disposed on a side of the first semiconductor pattern 31 that is close to the base substrate 10, and the orthographic projection of the shielding pattern 21 on the base substrate 10 covers the orthographic projection of the first channel region 313 on the base substrate 10. The shielding pattern 21 can reduce the amount of light directed toward the first channel region 313 of the first semiconductor pattern 31, thereby improving the light stability of the first transistor.

[0152] In some embodiments, the shielding pattern 21 can be made of the same material and disposed in the same layer as the first signal line 20. For example, the shielding pattern 21 and the first signal line 20 can be formed using the same mask and / or the same material in the same patterning process, which helps to simplify the manufacturing process of the array substrate and reduce the manufacturing cost of the array substrate.

[0153] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate having a display area and a peripheral area, the array substrate comprising: substrate substrate; A first signal line is disposed on the base substrate and at least partially located in the display area; a first transistor located in the display area and disposed on a side of the first signal line away from the base substrate, the first transistor comprising a first semiconductor pattern and a first gate disposed on a side of the first semiconductor pattern away from the base substrate; The second transistor is located in the peripheral area, and includes a second semiconductor pattern and a second gate arranged on a side of the second semiconductor pattern away from the base substrate, and the first gate and the second gate are arranged in the same layer.

2. The array substrate according to claim 1, wherein: The first semiconductor pattern includes a first channel region and a first region and a second region located on both sides of the first channel region; the array substrate further includes: a first insulating layer, located between the first signal line and the first semiconductor pattern; A second insulating layer is located on a side of the first semiconductor pattern away from the substrate; a first via hole, at least penetrating the first insulating layer and the second insulating layer, and exposing at least a portion of the first signal line and at least a portion of the first region; The first connecting electrode is disposed on a side of the second insulating layer away from the base substrate, and the first connecting electrode is electrically connected to the first signal line and the first region in the first via hole.

3. The array substrate according to claim 2, wherein: The first connecting electrode and the first gate electrode are made of the same material and are arranged in the same layer; At least a portion of an edge of the first connecting electrode contacts the first region.

4. The array substrate according to claim 3, wherein: The first region includes a first sub-portion and a second sub-portion located in the first via hole, the first sub-portion contacts the first connecting electrode, the second sub-portion is adjacent to an edge of the first connecting electrode, and the orthographic projections of the second sub-portion and the first connecting electrode on the substrate do not overlap; The conductivity of the second sub-portion is greater than the conductivity of the first sub-portion.

5. The array substrate according to claim 4, wherein: The thickness of the first sub-portion is greater than or equal to the thickness of the second sub-portion.

6. The array substrate according to claim 4 or 5, wherein: A size of the second sub-portion along a first direction is greater than or equal to 0.3 μm; and the first direction is perpendicular to a boundary where the first sub-portion and the second sub-portion are adjacent.

7. The array substrate according to any one of claims 2 to 6, wherein: The first via hole comprises a first side wall and a second side wall; the first side wall is located in the first insulating layer, and an end of the first side wall away from the substrate is connected to the first semiconductor pattern, and at least a portion of the second side wall is located in the second insulating layer; The slope angle of the first side wall is greater than the slope angle of the second side wall.

8. The array substrate according to claim 7, wherein: The slope angle of the first side wall is 60° to 90°; and / or the slope angle of the second side wall is 30° to 60°.

9. The array substrate according to any one of claims 2 to 8, further comprising: a second via hole, penetrating the second insulating layer and exposing at least a portion of the second region; A second connecting electrode is disposed on a side of the second insulating layer away from the base substrate, and at least partially located in the second via hole, wherein the second connecting electrode is connected to the second region in the second via hole; A third insulating layer is provided on a side of the second connecting electrode away from the substrate; a third via hole, penetrating the third insulating layer and exposing at least a portion of the second connecting electrode; The first electrode is at least partially located in the third via hole, and the first electrode is connected to the second connection electrode in the third via hole.

10. The array substrate according to claim 9, wherein: The second connecting electrode and the first gate electrode are made of the same material and are disposed in the same layer; At least a portion of an edge of the second connecting electrode contacts the second region.

11. The array substrate according to claim 10, wherein: The second region includes a third sub-portion and a fourth sub-portion located in the second via hole, the third sub-portion contacts the second connecting electrode, the fourth sub-portion is adjacent to an edge of the second connecting electrode, and the orthographic projections of the fourth sub-portion and the second connecting electrode on the substrate do not overlap; The conductivity of the fourth sub-portion is greater than the conductivity of the third sub-portion.

12. The array substrate according to claim 11, wherein: The thickness of the third sub-portion is greater than or equal to the thickness of the fourth sub-portion.

13. The array substrate according to claim 11 or 12, wherein: The size of the fourth sub-portion along the second direction is greater than or equal to 0.3 μm; the second direction is perpendicular to a boundary between the third sub-portion and the fourth sub-portion.

14. The array substrate according to any one of claims 9 to 13, wherein: The orthographic projections of the second via hole and the third via hole on the base substrate partially overlap.

15. The array substrate according to claim 14, wherein: The third insulating layer includes a passivation layer and a planarization layer stacked in a direction away from the substrate; The third via hole includes a first sub-hole penetrating the passivation layer, and a second sub-hole penetrating the planar layer; in the orthographic projections of the first sub-hole, the second sub-hole and the second via hole on the substrate, the first sub-hole is located within the range of the second sub-hole, and the overlapping area of ​​the first sub-hole and the second via hole is smaller than the overlapping area of ​​the second sub-hole and the second via hole.

16. The array substrate according to claim 15, wherein: In the orthographic projection of the second sub-hole and the second via hole on the substrate, the second sub-hole includes a first boundary located within the second via hole, and the interval between the first boundary and the boundary of the second via hole is greater than or equal to 0.5μm.

17. The array substrate according to any one of claims 2 to 16, wherein: The second insulating layer is disposed between the first semiconductor pattern and the first gate, and includes a first pattern in contact with the first gate; In the orthographic projection of the first pattern and the first gate on the base substrate, the first pattern covers the first gate, and a boundary between the first pattern and a boundary of the first gate is spaced 0.3 μm to 1.5 μm.

18. The array substrate according to any one of claims 1 to 17, wherein: The included angle between the side wall of the first gate and the plane where the substrate is located is 30° to 80°.

19. The array substrate according to any one of claims 1 to 18, wherein: The second transistor further includes a source and a drain, and the source and the drain are made of the same material and are arranged in the same layer as the second gate.

20. The array substrate according to claim 19, wherein: The second semiconductor pattern includes a second channel region and a third region and a fourth region located on both sides of the second channel region; the array substrate further includes: A second insulating layer is disposed between the second semiconductor pattern and the second gate; a fourth via hole penetrating through the second insulating layer and exposing at least a portion of the third region; a fifth via hole penetrating through the second insulating layer and exposing at least a portion of the fourth region; Among them, at least part of the source is located in the fourth via hole, connected to the third area through the fourth via hole, and at least part of the edge of the source is in contact with the third area; at least part of the drain is located in the fifth via hole, connected to the fourth area through the fifth via hole, and at least part of the edge of the drain is in contact with the fourth area.

21. The array substrate according to claim 19, wherein: The third region includes a fifth sub-portion and a sixth sub-portion located in the fourth via hole, the fifth sub-portion is in contact with the source electrode, the sixth sub-portion is adjacent to an edge of the source electrode, and the orthographic projections of the sixth sub-portion and the source electrode on the substrate do not overlap, and the conductivity of the sixth sub-portion is greater than that of the fifth sub-portion; The fourth region includes a seventh sub-portion and an eighth sub-portion located in the fifth via hole, the seventh sub-portion is in contact with the drain, the eighth sub-portion is adjacent to the edge of the drain, and the orthographic projections of the eighth sub-portion and the drain on the substrate do not overlap, and the conductivity of the eighth sub-portion is greater than that of the seventh sub-portion.

22. The array substrate according to claim 20, wherein: The dimension of the sixth sub-portion along the third direction is greater than or equal to 0.3 μm; the third direction is perpendicular to the boundary where the fifth sub-portion and the sixth sub-portion are adjacent; and / or, A dimension of the eighth sub-portion along a fourth direction is greater than or equal to 0.3 μm; and the fourth direction is perpendicular to a boundary between the seventh sub-portion and the eighth sub-portion.

23. The array substrate according to claim 22, wherein: The thickness of the fifth sub-section is greater than or equal to the thickness of the sixth sub-section; and / or, The thickness of the seventh sub-portion is greater than or equal to the thickness of the eighth sub-portion.

24. The array substrate according to claim 23, wherein: The thickness difference between the sixth sub-section and the fifth sub-section is and / or, The thickness difference between the eighth sub-section and the seventh sub-section is 25. The array substrate according to claim 1, wherein: The second transistor further includes: The third gate is arranged on a side of the second semiconductor pattern close to the base substrate, the orthographic projection of the third gate on the base substrate covers the orthographic projection of the second gate on the base substrate, and the third gate is electrically connected to the second gate.

26. The array substrate according to claim 1, further comprising: A first insulating layer, located between the first signal line and the first semiconductor pattern, includes a first material layer and a second material layer stacked in a direction away from the base substrate; The material of the first material layer includes silicon nitride, and the material of the second material layer includes silicon oxide; a second insulating layer, located between the first semiconductor pattern and the first gate, wherein the material of the second insulating layer comprises silicon oxide; and A passivation layer, a planarization layer, a first electrode, a fourth insulating layer and a second electrode are sequentially arranged in a direction away from a substrate; the passivation layer comprises a third material layer and a fourth material layer stacked in a direction away from the substrate, the material of the third material layer comprises silicon oxide, the material of the fourth material layer comprises silicon nitride; the material of the fourth insulating layer comprises silicon nitride.

27. The array substrate according to claim 26, wherein: The ratio of silicon atoms to nitrogen atoms in the silicon nitride of the first material layer is 1:1 to 1:0.5; The ratio of silicon atoms to oxygen atoms in the silicon oxide of the second material layer is 1:1 to 1:2; The ratio of silicon atoms to oxygen atoms in the silicon oxide of the second insulating layer is 1:1 to 1:2; The ratio of silicon atoms to oxygen atoms in the silicon oxide of the third material layer is 1:1.5 to 1:2; The ratio of silicon atoms to nitrogen atoms in the silicon nitride of the fourth material layer is 1:1 to 1:0.6; The ratio of silicon atoms to nitrogen atoms in the silicon nitride of the fourth insulating layer is 1:1 to 1:0.

6.

28. A display panel comprising: The array substrate according to any one of claims 1 to 27; A color filter substrate, arranged opposite to the array substrate; The liquid crystal layer is arranged between the array substrate and the color filter substrate.

Images