Semiconductor device, method for operating a semiconductor device and method for producing a semiconductor device

Abstract

According to an embodiment, the semiconductor device (100) comprises a semiconductor body (1) having a first-type contact region (11) of a first conductivity type, a second-type contact region (12) of a second conductivity type and a drift region (14) of the first conductivity type. The semiconductor device further comprises a main electrode (2) and a gate electrode (3). A second-type barrier region (42) is arranged vertically between the drift region and the second-type contact region. The second-type barrier region forms a barrier for second-type charge carriers. The first-type contact region and the second-type contact region are laterally spaced apart from each other by a portion of the drift region. The gate electrode is at least partially arranged laterally between the first-type and the second-type contact region. The second-type contact region is arranged vertically between a top side (10) of the semiconductor body and the second-type barrier region. The main electrode electrically contacts the first-type contact region and the second-type contact region. The area arranged vertically between the top side of the semiconductor body and the second-type barrier region only enables a current of second-type charge carriers to flow between the main electrode and the portion of the drift region laterally between the contact regions.

Description

[0001] P2023,0666 WO E / P220380WO01 July 31, 2023 - 1 - Description SEMICONDUCTOR DEVICE, METHOD FOR OPERATING A SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE The present disclosure relates to a semiconductor device, a method for operating a semiconductor device and a method for producing a semiconductor device. One object to be achieved is to provide a semiconductor device which contributes to an improved plasma profile and / or an improved injection enhancement effect, particularly while reducing the possibility of latch-up during turn-off and thus improving the RBSOA capability. First, the semiconductor device is specified. According to an embodiment, the semiconductor device comprises a semiconductor body having a first-type contact region of a first conductivity type, a second-type contact region of a second conductivity type and a drift region of the first conductivity type. The semiconductor device further comprises a main electrode and a gate electrode. A second- type barrier region is arranged vertically between the drift region and the second-type contact region. The second-type barrier region forms a barrier for second-type charge carriers. The first-type contact region and the second-type contact region are laterally spaced apart from each other by a portion of the drift region. The gate electrode is at least partially arranged laterally between the first-type and the second-type contact region. The second-type contact region is arranged vertically between a top side of the semiconductor body and the second-type barrier region. The main electrode P2023,0666 WO E / P220380WO01 July 31, 2023 - 2 - electrically contacts the first-type contact region and the second-type contact region. The area arranged vertically between the top side of the semiconductor body and the second-type barrier region only enables a current of second- type charge carriers to flow between the main electrode and the portion of the drift region which is arranged laterally between the contact regions. The present invention is, inter alia, based on the idea to provide an additional second-type charge carrier extraction unit. Since the second-type charge carriers could be holes, this unit is also called “hole extracting accumulation-mode FET”, HEAF for short or “hole extracting enhancement-mode FET”, HEEF for short. This extraction unit provides an alternative path for second-type charge carrier extraction and, since this alternative path is distant from the first- type contact region, the whole device is less prone to parasitic thyristor latch-up and therefore offers improved immunity against RBSOA failure. The semiconductor body may comprise or may consist of Si or SiC. The semiconductor body has a top side and a bottom side opposite to the top side. Furthermore, the semiconductor body has a main extension plane, wherein the top side and / or the bottom side may run at least partially parallel to the main extension plane. Herein, lateral directions are defined as directions parallel to the main extension plane and vertical direction is defined as a direction perpendicular to the main extension plane. The first-type contact region is of a first conductivity type which is, for example, n-type, i.e. n-doped. The second conductivity type is opposite to the first conductivity type, P2023,0666 WO E / P220380WO01 July 31, 2023 - 3 - i.e. it could be p-type or p-doped, respectively. The maximum or average doping concentrations in the first-type and / or the second-type contact region is, for example, at least 1018cm- 3or at least 1019cm-3or at least 1020cm-3. The contactregions may herein also be called “source regions”. The first-type and / or the second-type contact region may adjoin the top side of the semiconductor body, i.e. may form a part thereof. The drift region is of the same conductivity type as the first-type contact region. Its maximum and / or average doping concentration is, for example, lower than that of the first- type and / or the second-type contact region, e.g. by a factor of at least 10 or at least 100 or at least 1000. The main electrode, herein also called “first main electrode”, may be arranged on the top side of the semiconductor body. It contacts both the first-type and the second-type contact region. Particularly, the main electrode adjoins the first-type and the second-type contact regions. The main electrodes may be formed of metal. For example, the main electrode is an emitter electrode. A further main electrode, also called “second main electrode”, may be arranged on the bottom side of the semiconductor body and may contact the semiconductor body at the bottom side. The further main electrode may be a collector electrode. The second-type barrier region forms a barrier for second- type charge carriers. Thus, during normal operation of the semiconductor device, no second-type charge carriers can pass through the second-type barrier region. The second-type P2023,0666 WO E / P220380WO01 July 31, 2023 - 4 - barrier region may be formed of highly-doped semiconductor material of the first conductivity type or an electrically insulating material, e.g. an oxide, like SiO2. The second- type barrier region may adjoin the drift region on one side and / or the second-type contact region on another side. It is possible that the second-type barrier region runs in parallel with the top side. For example, a length and a width of the second-type barrier region, measured in lateral directions, exceeds a thickness of the second-type barrier region, measured in the vertical direction, by at least a factor of five or by at least a factor of ten and / or by at most a factor of 50. The first-type contact region and the second-type contact region are spaced apart in a lateral direction, herein also called “first lateral direction”. A portion of the drift region is arranged laterally, i.e. in the first lateral direction, between the contact regions. This portion of the drift region is herein also called “intermediate portion”. The intermediate portion may adjoin the top side of the semiconductor body. In the first lateral direction, at least a portion of the gate electrode is arranged between the contact regions. The gate electrode may be of metal or highly-doped polysilicon. For example, the gate electrode is electrically insulated from the semiconductor body. In this case, the semiconductor device may be a gate insulated device. In top view of the top side of the semiconductor body, the gate electrode may overlap with the portion of the drift region laterally between the contact regions. Moreover, in this top view, the gate electrode may at least partially overlap with the P2023,0666 WO E / P220380WO01 July 31, 2023 - 5 - second-type barrier region. The gate electrode may at least partially overlap with the first-type contact region and the second-type contact region in this top view. Moreover, the second-type contact region is arranged vertically, i.e. in vertical direction, between the top side and the second-type barrier region. In top view of the top side, the second-type contact region overlaps with the second-type barrier region. The (whole) area arranged vertically between the top side of the semiconductor body and the second-type barrier region enables only a current of second-type charge carriers, but not of first type charge carriers, to flow between the main electrode and the portion of the drift region laterally between the contact regions. Herein, the area is meant which overlaps with the second-type barrier region in top view of the top side. In other words, the (whole) area arranged vertically between the top side of the semiconductor body and the second-type barrier region is configured such that, during normal operation (i.e. in the on-state and during turn-off), no current of first-type charge carriers flows between the main electrode and the intermediate portion of the drift region and through the second-type contact region. For example, this area is free of contact regions of the first conductivity type being in electrical contact with the main electrode. For example, in this area, only semiconductor material of the second conductivity type is contacted by the main electrode. The second-type barrier region as well as the contact regions may have a main extension direction in a second lateral direction, which is perpendicular to the first lateral P2023,0666 WO E / P220380WO01 July 31, 2023 - 6 - direction. For example, the length of the second-type barrier region and the contact regions measured in this second lateral direction is greater, e.g. at least 2 times or at least 5 times or at least 10 times greater, than the widths and thicknesses of these regions measured in the first lateral direction and the vertical direction, respectively. The second-type contact region and the second-type barrier region may be formed continuously and without interruptions. For example, the length of the second-type contact region is essentially the same as the length of the second-type barrier region, e.g. with a deviation of at most 10%. According to a further embodiment, the semiconductor device is designed such that a current of second-type charge carriers from the drift region to the main electrode via the second-type contact region is enabled in normal / intended operation, e.g. during the turn-off state. Particularly, a current of second-type charge carriers from the intermediate portion of the drift region to the main electrode via the second-type contact region is enabled in normal operation. According to a further embodiment, every path of second-type charge carriers from the drift region to the main electrode via the second-type contact region has at least a section which is arranged vertically between the top side and the second-type barrier region and which extends in lateral direction, particularly in the first lateral direction. In other words, the current paths of second-type charge carriers from the (intermediate portion of the) drift region through the second-type contact region extend at least partially, preferably mainly, laterally. Particularly, in the area arranged vertically between the top side and the second-type barrier region, which overlaps with the gate electrode when P2023,0666 WO E / P220380WO01 July 31, 2023 - 7 - viewed in top view of the top side of the semiconductor body, the current paths run essentially in (the first) lateral direction. This can be achieved, for example, by having the electrical contact between the main electrode and the second-type contact region being offset from the edges of the second-type barrier region in the first lateral direction. In particular, the second-type contact region is further spaced from the first contact region in the first lateral direction than the edge of the second-type barrier region facing the first contact region. The offset or difference in the spacing, respectively, may be, for example, at least 1 µm or at least 2 µm. Particularly, the width of the second-type barrier region may be greater than the width of the second-type contact region, wherein widths are herein measured in the first lateral direction. According to a further embodiment, the semiconductor body further comprises a second-type base region which is either of the first or of the second conductivity type. The second- type base region is arranged vertically between the second- type barrier region and the top side, for example. In top view of the top side, the second-type base region may overlap with the gate electrode and / or the second-type barrier region. For instance, the second-type barrier region adjoins the top side and / or the second-type barrier region. According to a further embodiment, the second-type contact region is separated from the drift region, particularly from the intermediate portion of the drift region, at least in lateral direction, particularly at least in the first lateral direction, by the second-type base region. The second-type P2023,0666 WO E / P220380WO01 July 31, 2023 - 8 - contact region may adjoin the second-type base region. For instance, the second-type base region is only arranged laterally adjacent to the second-type contact region but neither vertically above nor vertically below the second-type contact region. According to a further embodiment, the doping concentration, e.g. the maximum and / or average doping concentration, in the second-type base region is lower than in the second-type contact region, e.g. by a factor of at least 10 or at least 100 or at least 1000. According to a further embodiment, in top view of the top side of the semiconductor body, the gate electrode overlaps with the second-type base region. For example, the gate electrode completely overlaps the second-type base region in this top view. According to a further embodiment, the semiconductor device is configured such that, in an on-state (e.g. Vge ≥ 0) of the semiconductor device, the second-type base region is blocking for the second-type charge carriers so that a current of second-type charge carriers from the drift region, particularly the intermediate portion thereof, to the main electrode via the second-type contact region is disabled. For example, by appropriately designing the second-type base region and by appropriately setting the electrical potentials of the gate electrode, the main electrode and the further main electrode, first-type charge carriers may be accumulated in the second-type base region which prevents a current flow of second-type charge carriers through the base region. For example, the second-type base region remains fully depleted during the on-state. With this feature during the on-state, P2023,0666 WO E / P220380WO01 July 31, 2023 - 9 - no deterioration of the on-state (Vce-sat) appears. Particularly, the second-type base region is designed such that it remains fully depleted during normal on-state operation. So, it will not allow any second-type charge carrier current to flow. This can be achieved, for example, when thickness of the second-type base region is small (e.g. < 1µm) and / or when its doping concentration is small (e.g. <1015cm-3) or both.According to a further embodiment, the semiconductor device is configured such that, in a turn-off state (e.g. Vge < 0 V) of the semiconductor device, the second-type base region is permeable for the second-type charge carriers so that a current of second-type charge carriers from the drift region, particularly from the intermediate portion thereof, to the main electrode via the second-type contact region is enabled. Also for this, the electrical potentials of the electrodes have to be set appropriately. For example, the above- mentioned thickness and / or doping concentration of the second-type base region enables a current flow in the turn- off state. Particularly, the semiconductor device is designed such that every current path of second-type charge carriers from the intermediate portion of the drift region to the second-type contact region has to pass the second-type base region. For instance, by appropriately setting the electrical potential of the gate electrode, second-type charge carriers can be accumulated in a portion of the second-type base region facing the gate electrode so that this portion enables the formation of the current path. According to a further embodiment, the semiconductor body comprises a first-type base region which is of the second conductivity type. This first-type base region is also called P2023,0666 WO E / P220380WO01 July 31, 2023 - 10 - “well region”. The average and / or maximum doping concentration in the first-type base region is, for example, lower than in the first-type contact region, e.g. by a factor of at least 10 or at least 100 or at least 1000. According to a further embodiment, the first-type contact region is separated from the drift region by the first-type base region. For example, the first-type contact region adjoins the first-type base region. The first-type contact region may be embedded in the first-type base region. According to a further embodiment, the gate electrode overlaps with the first-type base region in top view of the top side of the semiconductor body. Particularly, a portion of the first-type base region which is arranged laterally between the intermediate portion of the drift region and the first-type contact region is overlapped by the gate electrode in this top view. The first-type base region, particularly the portion thereof overlapping with the gate electrode, is depleted followed by inversion in an on-state of the semiconductor device. This enables a current flow of first- type charge carriers from the main electrode to the drift region via the first-type contact region and the inverted first-type base region in an on-state of the semiconductor device. Also for this, the electrical potentials of the electrodes have to be set appropriately. The semiconductor device is, in particular, a so-called planar device with the gate electrode on the top side of the semiconductor body. According to a further embodiment, the semiconductor device further comprises a first-type barrier region which is P2023,0666 WO E / P220380WO01 July 31, 2023 - 11 - arranged vertically between the drift region and the first- type contact region. The first-type barrier region forms a barrier for second-type charge carriers. Particularly, in top view of the top side, the first-type contact region and, optionally, the first-type base region overlap with the first-type barrier region. Concerning the properties and the dimensions of the first-type barrier region, all features disclosed herein for the second-type barrier region are also disclosed for the first-type barrier region and vice versa. For example, the first-type contact region and / or the first- type base region adjoin the first-type barrier region. The first-type barrier region may also adjoin the drift region. The first-type contact region may be laterally offset from the edges of the first-type barrier region. Particularly, the width of the first-type contact region is smaller than the width of the first-type barrier region. According to a further embodiment, the first-type contact region is arranged vertically between the top side and the first-type barrier region and overlaps with the first-type barrier region in top view of the top side. Recently, trench devices, like trench IGBTs, have largely been considered as the preferred design choice over planar- devices due to their superior on-state performance and improved technology curve (Eoff-Vcesat trade-off). Trench design benefits, inter alia, from its superior plasma profile which originates from closely spaced vertical flow of electrons and holes near the emitter contact leading to a well-known injection enhancement effect. The plasma profile, and thereby its on-state performance in a trench structure can be further improved by scaling down the length of the P2023,0666 WO E / P220380WO01 July 31, 2023 - 12 - emitter contact (Lpcont) or, in other words, by reducing the distance between the trenches. In contrast, in conventional planar devices, injected electrons from planar channels also force holes to enter the emitter contact laterally near its edge. As a result, plasma profile and thereby Vce-sat cannot be simply improved in conventional planar design by scaling down the emitter contact length, as in a trench device. However, planar devices offer other benefits such as better long-term reliability (lifetime) and robust (SOAs) performance as compared to the trench design, along with a less complex (therefore cheaper) fabrication process. With the first-type barrier region and the first-type contact region, which is herein also called Trench-Like-Planar (TLP) design, it is possible to engineer the electron and hole flow in the planar design to achieve the same or even an improved on-state performance with respect to the trench design, while retaining the original benefits of the planar design. In short, a design that comprises the best of both worlds (trench and planar) is achieved. According to a further embodiment, the first-type barrier region and the second-type barrier region are laterally spaced apart from each other, particularly spaced apart from each other in the first lateral direction. The first-type barrier region and the second-type barrier region may be arranged on the same height in vertical direction. Such a semiconductor device with a barrier region below the first-type contact region is herein also called “trench-like- semiconductor device”. It uses a barrier region to block the vertical path of second-type charge carriers, e.g. holes, and instead reroutes the holes to flow parallel to the first-type P2023,0666 WO E / P220380WO01 July 31, 2023 - 13 - charge carriers. This feature allows the injection enhancement effect to be further improved by reducing a side emitter contact dimension, like Lpcont, and enhanced on-state performance and technology curve to be achieved just like in a device according to the trench design. Further, unlike in devices according to the trench design, the design described herein makes it possible to realize a true point contact emitter device without any lithography limitation by scaling down the vertical dimension Lpcont. In short, the introduction of the above feature leads to significantly improved on-state losses and technology curve as compared to, e.g., planar design, making it a potential candidate for next generation novel planar technology suitable for both low- voltage and high-voltage platforms. According to a further embodiment, the semiconductor device comprises a further second-type barrier region arranged vertically between the second-type barrier region and the second-type contact region. The further second-type barrier region may overlap with the second-type contact region and / or the second-type barrier region and / or the gate electrode in top view of the top side of the semiconductor body. Particularly, the second-type barrier region and the further second-type barrier region may have the same width and / or length within the limits of manufacturing tolerance. According to a further embodiment, a further second-type contact region of the second conductivity type is arranged vertically between the second-type barrier region and the further second-type barrier region. In top view of the top side, the further second type-contact region may overlap with the second-type contact region and / or the further second-type barrier region. The main electrode may electrically contact P2023,0666 WO E / P220380WO01 July 31, 2023 - 14 - the further second-type contact region, e.g. at a lateral side thereof. The second-type contact region may be separated and spaced apart from the drift region via a further second- type base region. The features disclosed above for the second-type contact region and the second-type base region are also disclosed for the further second-type contact region and the further second-type base region. According to a further embodiment, the main electrode electrically contacts the further second-type contact region, e.g. at a lateral side thereof. A lateral side is herein a side facing in lateral direction, i.e. extending obliquely or perpendicularly to the main extension plane or to the top side, respectively. The semiconductor device may comprise a plurality, i.e. two or more further second-type barrier regions arranged vertically between the second-type barrier region and the second-type contact region. A further second-type contact region and, optionally, a further second-type base region may be formed vertically between each two second-type barrier regions. All features disclosed for one further second-type barrier region and one further second-type contact region are also disclosed for the other further second-type barrier regions and the other further second-type contact regions. The vertical stacking of multiple (HEAF) units further enhances the beneficial effect of the HEAF unit. Likewise, the semiconductor device may comprise one or more further first-type barrier regions arranged vertically between the first-type barrier region and the first-type contact region. In this case, one or more further first-type P2023,0666 WO E / P220380WO01 July 31, 2023 - 15 - contact regions and, optionally, one or more further first- type base regions may be arranged vertically between the first-type barrier region and the further first-type barrier region or between each two further first-type barrier regions. Like the first-type contact region, the further first-type contact region(s) may be in electrical contact with the main electrode. According to a further embodiment, a portion of the main electrode extends in vertical direction, thereby passes the plurality of second-type barrier regions and electrically contacts the further second-type contact region, particularly at a lateral side of the further second-type contact regions. According to a further embodiment, the second-type barrier region is of, or comprises, an electrically insulating material, like SiO2. Additionally or alternatively, the second-type barrier region is of, or comprises, a semiconductor material of the first conductivity type. In this case, the maximum and / or average doping concentration of the semiconductor material of the second-type barrier regionmay be at least 1016cm-3or at least 1018cm-3or at least1020cm-3. The same is true for the first-type barrier region. According to a further embodiment, the further second-type barrier region comprises an electrically conductive layer which is electrically insulated from the semiconductor body by means of a dielectric layer. According to a further embodiment, the electrically conductive layer is in electrical contact either with the P2023,0666 WO E / P220380WO01 July 31, 2023 - 16 - gate electrode or with the main electrode. It is also possible that the electrically conductive layer is floating. According to a further embodiment, the semiconductor device comprises a plug region of the second conductivity type laterally adjacent to the first-type contact region. For example, the plug region adjoins the first-type contact region. Moreover, the plug region may adjoin the first-type base region. For example, the plug region is, like the first- type contact region, embedded in the first-type base region. The maximum and / or average doping concentration of the plug region may be greater than that of the first-type base region, e.g. by a factor of at least 10 or at least 100 or at least 1000. The plug region enables the formation of a further path for extracting second-type charge carriers in a turn-off state. According to a further embodiment, the main electrode electrically contacts the plug region, e.g. adjoins the plug region. According to a further embodiment, the gate electrode comprises at least two portions, namely a first and a second portion, which are at least partially laterally spaced apart from each other. Particularly, the two portions may be spaced apart, at least partially, in the first lateral direction. The gate capacity can be reduced with such a gate electrode. According to a further embodiment, the first portion of the gate electrode is assigned to the first-type contact region and the second portion of the gate electrode is assigned to the second-type contact region. For example, the second portion of the gate electrode overlaps with the second-type P2023,0666 WO E / P220380WO01 July 31, 2023 - 17 - barrier region in top view of the top side of the semiconductor body and the first portion of the gate electrode overlaps with the first-type barrier region in this top view. Furthermore, in this top view, the space between the two portions of the gate electrode may overlap with the intermediate portion of the drift region. According to a further embodiment, the main electrode electrically contacts the first-type contact region at a lateral side thereof and contacts the second-type contact region at the top side of the semiconductor body. This way of contacting, particularly the contact at the lateral side of the first-type contact region, enables the emitter contact length to be reduced at the first-type contact region. In this way, plasma profile and Vce-sat can be improved. According to a further embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured for a maximum voltage between the main electrodes of at least 0.2 kV or of at least 0.6 kV or of at least 1.2 kV. Alternatively or additionally, the semiconductor device is configured for a current between the main electrodes of at least 0.01 kA or of at least 0.1 kA or of at least 1 kA and / or of at most 100 kA or of at most 10 kA. That is, by means of the gate electrode and by having the respective voltages between the main electrodes, a flow of current through the semiconductor device can be controlled, in particular it can be switched on and off by turning on and off a voltage at the gate electrode. The semiconductor device may be a transistor, e.g. a gate insulated transistor. Particularly, the semiconductor device is an insulated gate bipolar transistor, IGBT for short, or P2023,0666 WO E / P220380WO01 July 31, 2023 - 18 - an Reverse Conducting IGBT, RC-IGBT for short. The IGBT may be of planar design. Next, the method for operating a semiconductor device is specified. According to an embodiment, the method for operating a semiconductor device is for operating a semiconductor device according to any of the embodiments described herein. The method comprises a step of operating the semiconductor device in an on-state in which first-type charge carriers are injected from the main electrode into the first-type contact region. In another step, e.g. after operating the semiconductor device in the on-state, the semiconductor device is operated in a turn-off state, i.e. is turned off, in which second-type charge carriers are made to exit out of the semiconductor body into the first main electrode via the second-type contact region. For example, during device operation, the first main electrode is on negative potential with respect to the second main electrode. In the on-state, the gate electrode may be on positive potential with respect to the first main electrode. In the turn-off state, the gate electrode may then be on negative potential with respect to the first main electrode. Next, the method for producing a semiconductor device is specified. The method is, in particular, suited for producing a semiconductor device according to any of the embodiments described herein. Therefore, all features disclosed in connection with the semiconductor device are also disclosed for the method and vice versa. P2023,0666 WO E / P220380WO01 July 31, 2023 - 19 - According to an embodiment, the method comprises a step of providing a base semiconductor body with a drift region of a first conductivity type and a step of forming a second-type barrier region. The method comprises a further step of producing a semiconductor body out of the base semiconductor body by forming semiconductor regions, namely a first-type contact region of the first conductivity type and a second- type contact region of a second conductivity type. The semiconductor regions are formed such that the second-type barrier region is arranged vertically between the drift region and the second-type contact region and forms a barrier for second-type charge carriers. The first-type contact region and the second-type contact region are laterally spaced apart from each other by a portion of the drift region and the second-type contact region is arranged vertically between the top side of the semiconductor body and the second-type barrier region. The method further comprises steps of applying a gate electrode so that the gate electrode is at least partially arranged laterally between the contact regions, and of applying a main electrode so that the main electrode electrically contacts the first-type contact region and the second-type contact region. The second-type contact region may be formed at or on a top side of the base semiconductor body. For example, the second- type barrier region is formed by ion implantation in the base semiconductor body or by applying an electrically insulating material on the base semiconductor body. According to a further embodiment, the method comprises a step of growing semiconductor material on top of the second- type barrier region. For example, by growing the P2023,0666 WO E / P220380WO01 July 31, 2023 - 20 - semiconductor material, the second-type barrier region is completely embedded in semiconductor material. According to a further embodiment, the second-type contact region is formed in the grown semiconductor material. For example, the second-type contact region is formed by ion implantation in the grown semiconductor material. According to a further embodiment, the method comprises a step in which a sacrificial layer and a mask layer are applied onto the second-type barrier region in this order, i.e. the sacrificial layer is applied onto the second-type barrier region before the mask layer. For example, the sacrificial layer adjoins the second-type barrier region and / or the mask layer adjoins the sacrificial layer. According to a further embodiment, the sacrificial layer is then at least partially removed between the mask layer and the second-type barrier region. This may be done by etching. For example, the sacrificial layer is removed such that the (intermediate) portion of the drift region arranged laterally between the first-type and the second-type contact region is exposed. By way of example, the mask layer and the second- type barrier region are less etched by the etchant than the sacrificial layer so that the sacrificial layer and the second-type barrier region remain intact when applying the etching process. According to a further embodiment, semiconductor material is then grown between the mask layer and the second-type barrier region with a growing direction being at least partially in lateral direction. For example, the growing process starts at the exposed (intermediate) portion of the drift region. The P2023,0666 WO E / P220380WO01 July 31, 2023 - 21 - semiconductor material may then grow in the first lateral direction until it projects beyond the mask layer. With this method, a subsequent polishing step for providing an even top side of the semiconductor body can be omitted. Hereinafter, the semiconductor device, the method for operating a semiconductor device and the method for producing a semiconductor device will be explained in more detail with reference to the drawings on the basis of exemplary embodiments. The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and / or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Insofar as elements or components correspond to one another in terms of their function in different figures, the description thereof is not repeated for each of the following figures. For the sake of clarity, elements might not appear with corresponding reference symbols in all figures. Figures 1 to 12, 22 and 23 show different exemplary embodiments of the semiconductor device in a cross-sectional view, Figure 13 shows a flowchart of an exemplary embodiment of the method for operating a semiconductor device, Figures 14 to 21 show different positions in a first exemplary embodiment of the method for producing a semiconductor device, P2023,0666 WO E / P220380WO01 July 31, 2023 - 22 - Figures 24 to 34 show different positions in a second exemplary embodiment of the method for producing a semiconductor device, Figures 35 to 40 show different positions in a third exemplary embodiment of the method for producing a semiconductor device, Figures 41 to 46 show different positions in a fourth exemplary embodiment of the method for producing a semiconductor device. Figure 1 shows a first exemplary embodiment of the semiconductor device 100 in a cross-sectional view. The semiconductor device 100 is an IGBT in planar design. A vertical direction V and a first lateral direction L1 are indicated in figure 1. These directions are the same in the following figures, but are not indicated again in the following figures. The semiconductor device 100 comprises a semiconductor body 1 having a top side 10 and a bottom side 19. The semiconductor body 1 comprises a drift region 14 which is of a first conductivity type which, by way of example, is n-type in the following. The bottom side 19 of the semiconductor body 1 is formed by a contact layer 13 of a second conductivity type which, accordingly, is p-type in the following. At the top side 10, the semiconductor body 1 comprises a first-type contact region 11 and a second-type contact region 12. The first-type contact region 11 is of the first conductivity type and the second-type contact region 12 is of the second conductivity type. The contact regions 11, 12 are P2023,0666 WO E / P220380WO01 July 31, 2023 - 23 - spaced apart from each other in the first lateral direction L1. A second-type barrier region 42 is vertically, i.e. in vertical direction V, arranged between the second-type contact region 12 and the drift region 14. During normal operation of the semiconductor device 100 the second-type barrier region 42 is impermeable for second-type charge carriers (holes). For example, the second-type barrier region 42 is of highly n-doped semiconductor material or of an oxide, like SiO2. The semiconductor device 100 further comprises a first-type base region 15, which is p-doped, and a second-type base region 16. In the exemplary embodiment of figure 1, the second-type base region 16 is p-doped as well, i.e. of the same conductivity type as the second-type contact region 12. The doping concentration of the first-type base region 15, also called “well region 15”, is lower than in the first-type contact region 11, e.g. at least by a factor of 100. The first-type contact region 11 is embedded in the first-type base region 15 and separated from the drift region 14 by the first-type base region 15. The doping concentration in the second-type base region 16 is lower than in the second-type contact region 12, e.g. at least by a factor of 100. The second-type base region 16 separates the second-type contact region 12 from the drift region 14. A gate electrode 3 and a first main electrode 2 are arranged on the top side 10 of the semiconductor body 1. A second main P2023,0666 WO E / P220380WO01 July 31, 2023 - 24 - electrode 4 is arranged on the bottom side 19 of the semiconductor body 1. The first main electrode 2 electrically contacts the first-type contact region 11 and the second-type contact region 12. The second main electrode 4 electrically contacts the contact layer 13. The gate electrode 3 is electrically isolated from the semiconductor body 1 and the first main electrode 2 by means of an insulating material 23. The gate electrode 3 overlaps with the base regions 15, 16 in top view of the top side 10 so that the base regions 15, 16 can be depleted / inverted by appropriately setting the electrical potential of the gate electrode 3. The operation of the semiconductor device 100 of figure 1 may be as follows: In an on-state, the first main electrode 2 is on a negative electrical potential with respect to the second main electrode 4. The gate electrode 3 is on a positive electrical potential with respect to the first main electrode 2. Accordingly, the portion of the base regions 15, 16 underneath the gate electrode 3 is depleted from holes which is followed by inversion and formation of n-type channel region underneath gate-electrode. Electrons can therefore be injected from the main electrode 2 into the first-type contact region 11 and can flow through the inverted portion or channel region of the first-type base region 15 into the drift region 14. In the drift region 14, the electrons may then recombine with holes injected from the second main electrode 4 through the p-type contact layer 13. Note that, during on-state operation (Vge>0V), the base region 16 remains fully depleted and therefore no portion of hole current flows out via second contact region 12. When turning off the semiconductor device 100, i.e. in a turn-off state, the electrical potential of the gate P2023,0666 WO E / P220380WO01 July 31, 2023 - 25 - electrode 3 may be negative with respect to the electrical potential of the first main electrode 2. Accordingly, holes are accumulated in a portion of the second base region 16 facing the gate electrode 3. Holes from the drift region 14 can travel through the accumulation portion of the second- type base region 16 into the second-type contact region 12 and from there can be injected into the main electrode 2. This is indicated by the arrow of figure 1. The holes thereby travel through the second-type base region 16 in a direction parallel to the first lateral direction L1. Thus, the second- type contact region 12 together with the second-type base region 16 form an alternative path for holes in order to reduce the electron hole-plasma in the drift region 14. A part of the holes, however, is also extracted via the first- type base region 15, as indicated by the vertical arrow in figure 1. Figures 2 and 3 show a second exemplary embodiment of the semiconductor device 100. Also here, the semiconductor device 100 is an IGBT of planar design. In contrast to the exemplary embodiment of figure 1, a first-type barrier region 41 is arranged below the first-type contact region 11 and the first-type base region 15. This first-type barrier region 41 is impermeable for holes during normal operation of the semiconductor device 100. Thus, during turn-off (Vge< 0V) operation (as shown in figure 2), holes which are extracted via the first-type base region 15 have to travel in lateral direction underneath the first-type contact region 11. The flow direction of the holes is therefore essentially parallel to the flow direction of the electrons in the on-state. In other words, during turn-off (Vge< 0V), there is p-type channel formation( via accumulation or inversion) in the second base region 16 which provide an alternative path to P2023,0666 WO E / P220380WO01 July 31, 2023 - 26 - hole-extraction in addition to the path via the first base region 15 as indicated by arrows in Figure 2. The flow direction of electrons is shown by the arrow in figure 3, illustrating the semiconductor device 100 in the on-state. Figure 4 illustrates an exemplary embodiment of the semiconductor device 100 in which the structure shown in figure 3 is mirrored at the right side. There are now two first-type contact regions 11 with associated first-type base regions 15 and first-type barrier regions 41. The second-type contact region 12 is arranged laterally between the two first-type contact regions 11 and is laterally sandwiched between two second-type base regions 16. As can be seen in figure 4, the width of the second-type barrier region 42 is larger than the width of the second-type contact region 12, i.e. the second-type barrier region 42 projects beyond the second-type contact region 12 in the first lateral direction L1 and in the direction opposite to the first lateral direction L1. In the previous exemplary embodiments, the barrier regions 41, 42 are formed, for example, of electrically insulating material, like SiO2. The exemplary embodiment of figure 5 shows the case in which the barrier regions 41, 42 are formed of a highly-doped n- type semiconductor material. Also this forms a barrier for holes. Figure 6 shows an exemplary embodiment of the semiconductor device 100 in which a plurality of further second-type barrier regions 42’ is arranged vertically between the second-type contact region 12 and the second-type barrier P2023,0666 WO E / P220380WO01 July 31, 2023 - 27 - region 42. The second-type barrier region 42 thereby projects beyond the further second-type barrier regions 42’ in the first lateral direction L1. A further second-type contact region 12’ is arranged between each two of the second-type barrier regions 42’. Each further second-type contact region 12’ is separated from the drift region 14 in the first lateral direction by a further second-type base region 16’. Furthermore, a further second-type contact region 12’ and a further second-type base region 16’ are arranged between the second-type barrier region 42’ closest to the second-type barrier region 42 and the second-type barrier region 42.The further second-type contact regions 12’ and the associated further second-type base regions 16’ may be formed identically to the second-type contact region 12 and the second-type base region 16, for example in terms of doping concentrations and relative spatial arrangement. The first main electrode 2 extends vertically across the second-type contact regions 12, 12’ and contacts the second-type contact regions 12, 12’ at lateral sides thereof. Each of the units comprising a second-type contact region 12, 12’ and a second- type base region 16, 16’ provides another path for hole extraction during the turn-off state. A similar structure is formed on the side of the first-type regions 11, 41, 16. Also here, a plurality of further first- type barrier regions 41’ is arranged vertically between the first-type barrier region 41 and the first-type contact region 11. At least one corresponding first-type contact region 11’ and a corresponding first-type base region 15’ are arranged between each two further first-type barrier regions 41’. The first main electrode 2 extends in vertical direction V across the first-type contact region 11 and the further first-type contact regions 11’ and electrically contacts them P2023,0666 WO E / P220380WO01 July 31, 2023 - 28 - at lateral sides thereof. Each of the units comprising a further first-type base region 15’ and the further first-type contact region 11’ provides a current path for electrons during the on-state of the semiconductor device 100. The semiconductor device 100 of figure 6 can be considered as a multi-trench-like planar device with the barrier regions 41, 41’, 42, 42’ forming trench-like structures extending in lateral directions instead of in the vertical direction. In figure 6, the further barrier regions 41’ and 42’ each comprise an electrically conductive layer 47 which is electrically insulated from the semiconductor body 1 by means of a dielectric layer 48. The electrically conductive layer 47 may be on the same potential as the gate electrode 3 or the first main electrode 2 or may be floating. Figure 7 shows a further exemplary embodiment of the semiconductor device 100. Here, a plug region 17 is provided vertically between the first-type barrier region 41 and the top side 10 of the semiconductor body 1. The plug region 17 is of the second conductivity type, i.e. p-doped and has a higher doping concentration than the first-type base region 15. The first main electrode 2 electrically contacts the plug region 17. By means of this plug region 17, an improved coverage of an emitter metal of the first main electrode 2 over the base region 15 / plug region 17 can be achieved leading to a decreased contact resistance as compared to only side- contacted designs, especially during a turn-off transient. In the latter case, Lpcont is still determined by a thickness of base region 15 and, therefore, injection enhancement can P2023,0666 WO E / P220380WO01 July 31, 2023 - 29 - still be achieved by scaling down Lpcont. It should be noted that, in difference to what is shown in figure 7, the plug region 17 could also extend underneath the first-type contact region 11, i.e. vertically between the first-type contact region 11 and the first-type barrier region 1. In the previous exemplary embodiments, the gate electrode 3 has been formed such that it extends in the first lateral direction L1 from the area of the first-type contact region 11 to the area of the second-type contact region 12 without interruptions. In these exemplary embodiments, the gate electrode was formed with a bridge-like structure so that a portion of the gate electrode 3 laterally between the base regions 15, 16 is further apart from the semiconductor body 1 than the portions overlapping with the base regions 15, 16. Thereby, the gate capacity is reduced. In the exemplary embodiment of figure 8, the gate electrode 3 has a hole in the region laterally between the base regions 15, 16 instead. Therefore, the gate electrode 3 comprises two portions 31, 32, which are at least partially spaced from each other in the first lateral direction L1. Each of the portions 31, 32 is either assigned to their first-type contact region 11 and the first-type base region 15 or to the second-type contact region 12 and the second-type base region 16. Such a so-called split gate electrode allows the gate capacity to be further reduced. Figure 9 shows an exemplary embodiment of the semiconductor device 100, in which an electrically conductive element 33 is arranged laterally between the two portions 31, 32. The electrically conductive element 33 is floating or electrically connected to the first main electrode 2. P2023,0666 WO E / P220380WO01 July 31, 2023 - 30 - Furthermore, the electrically conductive element 33 is at a greater or the same distance to the semiconductor body 1 than the portions 31, 32 of the gate electrode 3. In the previous exemplary embodiments, the second-type base region 16 was always formed of semiconductor material of the second conductivity type, i.e. p-type. In the exemplary embodiment of figure 10, the second-type base region 16 is formed of semiconductor material of the first conductivity type, i.e. n-type. The doping concentration may be lower than in the second-type contact region 12. In the off-state of the semiconductor device 100, the portion of the second-type base region 16 facing the gate electrode 3 is depleted followed by inversion so that a channel for second-type charge carriers is formed. In this way, during the turn-off state, holes can be extracted from the drift region 14 via the inverted portion of the second-type base region 16 and via the second- type contact region 12 and can be injected from there into the first main electrode 2. In contrast to the previous exemplary embodiments wherein the first main electrode 2 has always been formed such that it projects beyond the first-type contact region 11 in the direction opposite to the vertical direction V and has electrically contacted the first-type contact region 11 at a lateral side thereof, figure 12 shows an exemplary embodiment of the semiconductor device 100 where the first main electrode 2 electrically contacts the first-type contact region 11 at the top side 10 of the semiconductor body 1. The first-type barrier region 41 adjoins the lateral side of the first-type contact region 11 and covers this lateral side. Particularly, the first-type contact region 11 and the first- P2023,0666 WO E / P220380WO01 July 31, 2023 - 31 - type barrier region 41 are at least partially arranged on the same height in vertical direction. Figure 12 shows an exemplary embodiment of the semiconductor device 100, wherein the first main electrode 2 is guided vertically across the second-type contact region 12, electrically contacts the second-type contact region 12 at a lateral side thereof and reaches up to the second-type barrier region 42. Figure 13 shows a flowchart of an exemplary embodiment of the method for operating a semiconductor device, e.g. any of the semiconductor devices described in connection with figures 1 to 12. In a step S1, the semiconductor device is operated in its on-state in which first-type charge carriers, e.g. electrons, are injected from the main electrode 2 into the first-type contact region 11 (see, e.g. figure 3). In a step S2, the semiconductor device is then turned off, i.e. operated in its turn-off state, in which second-type charge carriers are made to exit the semiconductor body via the second-type contact region 12 into the first main electrode 2 (see for example figures 1 and 2). Figure 14 shows a first position in a first exemplary embodiment of the method for producing a semiconductor device. A base semiconductor body 1’ is provided, which comprises a drift region 14 and a contact layer 13. The drift region 14 is of a first conductivity type and the contact layer 13 is of a second conductivity type. Figure 15 shows a position in which a barrier layer 40 is applied onto the top side of the base semiconductor body 1’. P2023,0666 WO E / P220380WO01 July 31, 2023 - 32 - In figure 16, a position is shown in which a portion of the barrier layer 40 has been removed so that two barrier regions, namely a first-type barrier region 41 and a second- type barrier region 42, which are spaced apart from each other in the first lateral direction L1, remain. In the position of figure 17, semiconductor material 18 has been grown over the first-type 41 and the second-type 42 barrier region 18 and in the region laterally in between them. In the position of figure 18, a first-type contact region 11 of a first conductivity type and a first-type base region 15 of a second conductivity type have been formed in the area of the first-type barrier region 41. Furthermore, a second-type contact region 12 and a second-type base region 16 have been formed above the second-type barrier region 42. Both regions 12, 16 are of the second conductivity type. In this way, a semiconductor body 1 has been formed out of the base semiconductor body 1’. Figure 19 shows a position in which a layer of electrically insulating material 23, e.g. SiO2, has been applied onto the top side of the semiconductor body 1. In the position of figure 20, a portion of the semiconductor body 1 has been removed, e.g. etched away, such that a lateral side of the first-type contact region 11 and a lateral side of the first-type base region 15 are exposed and such that a top side of the first-type barrier region 41 is exposed. P2023,0666 WO E / P220380WO01 July 31, 2023 - 33 - Figure 21 shows a position after a gate electrode 3 has been applied on top of the electrically insulating material 23. The gate electrode 3 overlaps, in top view of the top side of the semiconductor body 1, with the portion of the first-type base region 15 arranged laterally between the first-type contact region 11 and the second-type contact region 12, and, in the same top view, overlaps with the second-type base region 16. In the position of figure 22, the gate electrode 3 is covered by additional electrically insulating material 23. In figure 23, a first main electrode 2 has been deposited onto the top side of the semiconductor body 1 so that it electrically contacts the first-type contact region 11 and the first-type base region 15 at the lateral sides thereof as well as the second-type contact region 12 at its top side. The first main electrode 2 thereby extends over the gate electrode 3 in lateral direction. Moreover, a second main electrode 4 has been applied such that it contacts the contact layer 30 at the bottom side of the semiconductor body 1. At the same time, figure 23 shows a finalized semiconductor device 100 in the form of a planar IGBT. Figure 24 shows a first position in a second exemplary embodiment of the method, which is the same position as shown in figure 14. In figure 25, a further position of the second exemplary embodiment of the method is shown, which is the same position as shown in figure 15. P2023,0666 WO E / P220380WO01 July 31, 2023 - 34 - In the position of figure 26, a portion of the barrier layer 40 has been removed, as explained in connection with figure 16. Furthermore, a sacrificial layer 5 has been applied onto the barrier regions 41, 42 and the exposed portion of the base semiconductor body 1’ laterally in between them. The sacrificial layer 5 is, for example, of carbon. In the position of figure 27, a mask layer 6 has been applied onto the sacrificial layer 5. The mask layer 6 may be a photoresist layer or a hard mask layer, like a metal layer. In the position of figure 28, a part of the mask layer 6 has been removed so that a top side of the sacrificial layer 5 is exposed. This may have been done with an additional mask. In figure 29, a portion of the sacrificial layer 5 underneath the mask layer 6 has been removed, e.g. by means of etching, and a portion of the drift region 14 as well as the first- type barrier region 41 have thereby been exposed. Figure 30 shows a position after semiconductor material 18 has been grown on the exposed drift region 14 and the exposed first-type barrier region 41 so that the semiconductor material 18 has grown in lateral direction between the first- type barrier region 41 and the mask layer 6. In figure 31, the remaining sacrificial layer 5 between the mask layer 6 and the second-type contact region 42 has been removed, e.g. again by means of etching, and again a portion of the drift region 14 as well as the second-type barrier region 42 have been exposed thereby. P2023,0666 WO E / P220380WO01 July 31, 2023 - 35 - In figure 32, another growing process has been executed so that semiconductor material 18 has been grown between the mask layer 6 and the second-type barrier region 42 with a growing direction in the first lateral direction. In figure 33, the mask layer has been removed so that a top side of the grown semiconductor material 18 is exposed. In figure 34, the first-type contact region 11, the first- type base region 15, the second-type contact region 12 and the second-type base region 16 have been formed in the grown part of the semiconductor material, e.g. by means of ion implantation. In this way, a semiconductor body 1 is produced which can be used to produce the semiconductor device 100 of figure 23, for example. Figure 35 shows a position in third exemplary embodiment of the method for producing a semiconductor device. It is the same position as shown in figure 27. However, the mask layer 6 is now left symmetric and the sacrificial layer below the mask layer 6 is completely removed, e.g. by means of etching (see position of figure 36). In the position of figure 37, semiconductor material 18 has been grown on the exposed drift region 14 so that the semiconductor material has grown in lateral direction between the first-type barrier region 41 and the mask layer 6 as well as between the second-type barrier region 42 and the mask layer 6. In the position of figure 38, portions of the mask layer 6 and the grown semiconductor material 18 are removed, e.g. by means of etching. The etching of the semiconductor material P2023,0666 WO E / P220380WO01 July 31, 2023 - 36 - 18 may be performed before or after removing the mask layer 6 (see position of figure 39). Figure 40 shows a position after the first-type contact region 11, the first-type base region 15, the second-type contact region 12 and the second-type base region 16 have been formed in the grown part of the semiconductor material, e.g. by means of ion implantation. In this way, a semiconductor body 1 is produced which can be used to produce the semiconductor device 100 of figure 23, for example. In contrast to the second exemplary embodiment, the third exemplary embodiment of the method only uses one overgrowth step for producing the semiconductor body 1 out of the base semiconductor body 1’. Figure 41 shows a position in a fourth exemplary embodiment of the method for producing a semiconductor device. The position is the same as shown in figure 28. In the position of figure 42 a portion of the sacrificial layer 5 underneath the mask layer 6 has been removed, e.g. by means of etching, and a portion of the drift region 14 as well as the first-type barrier region 41 have thereby been exposed. In the position of figure 43, semiconductor material 18 has been grown on the exposed drift region 14 and the exposed first-type barrier region 41 so that the semiconductor material 18 has grown in lateral direction between the first- type barrier region 41 and the mask layer 6. The semiconductor material has been doped in-situ, i.e. during P2023,0666 WO E / P220380WO01 July 31, 2023 - 37 - the growth so that the first-type base region 15 has been formed. Figure 44 shows a position in which the remaining sacrificial layer 5 between the mask layer 6 and the second-type contact region 42 has been removed, e.g. again by means of etching, and again a portion of the drift region 14 as well as the second-type barrier region 42 have been exposed thereby. In the position of figure 45 another growing process has been executed so that semiconductor material 18 has been grown between the mask layer 6 and the second-type barrier region 42 with a growing direction in the first lateral direction. Also here, in-situ doping has been performed so that the second-type base region 16 and the second-type contact region 12 have been formed during growing. Figure 46 shows a position after removing the mask layer 6 and after forming the first-type contact region 11 by means of implantation. Thus, in the fourth exemplary embodiment, only one implantation step is needed. From the position of figure 46, a semiconductor device 100 as shown in figure 23 can be produced, for example. The embodiments shown in the Figures 1 to 46 as stated represent exemplary embodiments of the semiconductor device, the method for operating a semiconductor device and the method for producing a semiconductor device; therefore, they do not constitute a complete list of all embodiments according to the semiconductor device, the method for operating a semiconductor device and the method for producing a semiconductor device. Actual semiconductor devices, methods for operating a semiconductor device and methods for P2023,0666 WO E / P220380WO01 July 31, 2023 - 38 - producing a semiconductor device may vary from the embodiments shown in terms of arrangements, elements and order of method steps, for example.

[0002] P2023,0666 WO E / P220380WO01 July 31, 2023 - 39 - Reference Signs 1 semiconductor body 1’ base semiconductor body 2 (first) main electrode 3 gate electrode 4 further / second main electrode 5 sacrificial layer 6 mask layer 10 top side 11 first-type contact region 11’ further first-type contact region 12 second-type contact region 12’ further second-type contact region 13 contact layer 14 drift region 15 first-type base region 15’ further first-type base region 16 second-type base region 16’ further second-type base region 17 plug region 18 semiconductor material 19 bottom side 23 electrically insulating material 31 first portion of gate electrode 32 second portion of gate electrode 33 electrically conductive element 40 barrier layer 41 first-type barrier region 41’ further first-type barrier region 42 second-type barrier region 42’ further second-type barrier region 47 electrically conductive layer P2023,0666 WO E / P220380WO01 July 31, 2023 - 40 - 48 dielectric layer 100 semiconductor device L1 first lateral direction V vertical direction S1 method step S2 method step

Claims

P2023,0666 WO E / P220380WO01 July 31, 2023 - 41 - Claims 1. A semiconductor device (100) comprising - a semiconductor body (1) having a first-type contact region (11) of a first conductivity type, a second-type contact region (12) of a second conductivity type and a drift region (14) of the first conductivity type, - a main electrode (2) and a gate electrode (3), wherein - a second-type barrier region (42) is arranged vertically between the drift region (14) and the second-type contact region (12), said second-type barrier region (42) forms a barrier for second-type charge carriers, - the first-type contact region (11) and the second-type contact region (12) are laterally spaced apart from each other by a portion of the drift region (14), - the gate electrode (3) is at least partially arranged laterally between the contact regions (11, 12), - the second-type contact region (12) is arranged vertically between a top side (10) of the semiconductor body (1) and the second-type barrier region (42), - the main electrode (2) electrically contacts the first-type contact region (11) and the second-type contact region (12), - the area arranged vertically between the top side (10) of the semiconductor body (1) and the second-type barrier region (42) enables only a current of second-type charge carriers to flow between the main electrode (2) and the portion of the drift region (14) which is arranged laterally between the contact regions (11, 12).

2. The semiconductor device (100) according to claim 1, wherein - the semiconductor device (100) is designed such thatP2023,0666 WO E / P220380WO01 July 31, 2023 - 42 - - a current of second-type charge carriers from the drift region (14) to the main electrode (2) via the second-type contact region (12) is enabled in normal operation, - every path of second-type charge carriers from the drift region (14) to the first main electrode (2) via the second-type contact region (12) has a section which is arranged vertically between the top side (10) and the second-type barrier region (42) and which extends in lateral direction.

3. The semiconductor device (100) according to claim 2, wherein - the semiconductor body (1) further comprises a second-type base region (16) which is either of the first or the second conductivity type, - the second-type contact region (12) is separated from the drift region (14), at least in lateral direction (L1), by the second-type base region (16), - the doping concentration in the second-type base region (16) is lower than in the second-type contact region (12), - the gate electrode (3) overlaps with the second-type base region (16) in top view of the top side (10) of the semiconductor body (1) such that - in an on-state of the semiconductor device (100), the second-type base region (16) is blocking for second-type charge carriers so that a current of second-type charge carriers from the drift region (14) to the main electrode (2) via the second-type contact region (12) is disabled, - in a turn-off state of the semiconductor device (100), the second-type base region (16) is permeable for the second-type charge carriers so that a current of second-P2023,0666 WO E / P220380WO01 July 31, 2023 - 43 - type charge carriers from the drift region (14) to the first main electrode (2) via the second-type contact region (12) is enabled.

4. The semiconductor device (100) according to any one of the preceding claims, wherein - the semiconductor body (1) comprises a first-type base region (15) which is of the second conductivity type, - the first-type contact region (11) is separated from the drift region (14) by the first-type base region (15), - the gate electrode (3) overlaps with the first-type base region (15) in top view of the top side (10) of the semiconductor body (1) such that the first-type base region (15) is depleted followed by inversion by appropriately setting the electrical potential of the gate electrode (3) in order to enable a current flow of first-type charge carriers from the main electrode (2) to the drift region (14) via the first-type contact region (11) and the inverted first-type base region (15) in an on-state of the semiconductor device (100).

5. The semiconductor device (100) according to any one of the preceding claims, further comprising - a first-type barrier region (41) which is arranged vertically between the drift region (14) and the first-type contact region (11) and which forms a barrier for second-type charge carriers, wherein - the first-type contact region (11) is arranged vertically between the top side (10) and the first-type barrier region (41) and overlaps with the first-type barrier region (41) in top view of the top side (10),P2023,0666 WO E / P220380WO01 July 31, 2023 - 44 - - the first-type barrier region (41) and the second-type barrier region (42) are laterally spaced apart from each other.

6. The semiconductor device (100) according to any one of the preceding claims, comprising - a further second-type barrier region (42’) arranged vertically between the second-type barrier region (42) and the second-type contact region (12), wherein - the at least one further second-type barrier region (42’) overlaps with the second-type contact region (12) in top view of the top side (10), - a further second-type contact region (12’) of the second conductivity type is arranged vertically between the second- type barrier region (42) and the further second-type barrier region (42’), - the main electrode (2) electrically contacts the further second-type contact region (12’).

7. The semiconductor device (100) according to claim 6, wherein - a portion of the main electrode (2) extends in vertical direction (V), thereby passes the plurality of second-type barrier regions (42, 42’) and electrically contacts the further second-type contact region (12’).

8. Semiconductor device (100) according to any one of the preceding claims, wherein - the second-type barrier region (42) is of an electrically insulating material and / or - the second-type (42) barrier region is of semiconductor material of the first conductivity type.P2023,0666 WO E / P220380WO01 July 31, 2023 - 45 - 9. Semiconductor device (100) according to claim 6 or any one of claims 7 and 8 in their dependency on claim 6, wherein - the further second-type barrier region (42’) comprises an electrically conductive layer (47) which is electrically insulated from the semiconductor body (1) by means of a dielectric layer (48), - the electrically conductive layer (47) is in electrical contact either with the gate electrode (3) or with the main electrode (2).

10. Semiconductor device (100) according to any one of the preceding claims, further comprising - a plug region (17) of the second conductivity type laterally adjacent to the first-type contact region (11), wherein - the main electrode (2) electrically contacts the plug region (17).

11. Semiconductor device (100) according to any one of the preceding claims, wherein - the gate electrode (3) comprises at least two portions (31, 32) which are at least partially laterally spaced apart from each other, - a first portion (31) of the gate electrode (3)is assigned to the first-type contact region (11), - a second portion (32) of the gate electrode (3) is assigned to the second-type contact region (12).

12. Semiconductor device (100) according to any one of the preceding claims, wherein - the main electrode (2) electrically contacts the first-type contact region (11) at a lateral side thereof and contactsP2023,0666 WO E / P220380WO01 July 31, 2023 - 46 - the second-type contact region (12) at the top side (10) of the semiconductor body (1).

13. Semiconductor device (100) according to any one of the preceding claims, wherein - the semiconductor device (100) is an IGBT.

14. Method for operating a semiconductor device (100) according to any one of the preceding claims, comprising the steps of - operating the semiconductor device (100) in an on-state in which first-type charge carriers are injected from the main electrode (2) into the first-type contact region (11), - operating the semiconductor device (100) in a turn-off state in which second-type charge carriers are made to exit the semiconductor body (1) via the second-type contact region (12) into the main electrode (2).

15. Method for producing a semiconductor device (100), comprising the steps of - providing a base semiconductor body (1’) with a drift region (14) of a first conductivity type, - forming a second-type barrier region (42), - producing a semiconductor body (1) out of the base semiconductor body (1’) by forming semiconductor regions, namely a first-type contact region (11) of the first conductivity type and a second-type contact region (12) of a second conductivity type so that - the second-type barrier region (42) is arranged vertically between the drift region (14) and the second- type contact region (12) and forms a barrier for second- type charge carriers,P2023,0666 WO E / P220380WO01 July 31, 2023 - 47 - - the first-type contact region (11) and the second-type contact region (12) are laterally spaced apart from each other by a portion of the drift region (14), - the second-type contact region (12) is arranged vertically between a top side (10) of the semiconductor body (1) and the second-type barrier region (42), - applying a gate electrode (3) so that the gate electrode (3) is arranged at least partially laterally between the contact regions (11, 12), - applying a main electrode (2) so that the main electrode (2) electrically contacts the first-type contact region (11) and the second-type contact region (12).

16. Method according to claim 15, further comprising - growing semiconductor material (18) on top of the second- type barrier region (42), wherein - the second-type contact region (12) is formed in the grown semiconductor material (18).

17. Method according to claim 16, wherein - a sacrificial layer (5) and a mask layer (6) are applied onto the second-type barrier region (42) in this order, - the sacrificial layer (5) is then at least partially removed between the mask layer (6) and the second-type barrier region (42), - semiconductor material (18) is then grown between the mask layer (6) and the second-type barrier region (42) with a growing direction being at least partially in lateral direction.

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