Electric power conversion apparatus

Abstract

First and second semiconductor switching elements (Q1, Q2) are connected in series between first positive-electrode wiring (112) and an output node (Nb) via second positive-electrode wiring (114). Third and fourth semiconductor switching elements (Q3, Q4) are connected in series between the output node (Nb) and first negative-electrode wiring (113) via second negative-electrode wiring (114). A flying capacitor (111) is connected between the second positive-electrode wiring (114) and the second negative-electrode wiring (115). Speed adjustment circuits (130, 140) are provided to the first and fourth semiconductor switching elements (Q1, Q4) and are configured such that the turn-off speed of the first and fourth semiconductor switching elements (Q1, Q4) is reduced so as to be lower than the turn-off speed of the second and third semiconductor switching elements (Q2, Q3), to which the speed adjustment circuits (130, 140) are not provided, in accordance with a drop in the voltage of the flying capacitor (111).

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] In recent years, there has been much discussion about the construction of power transmission and distribution networks that utilize diverse energy sources, including renewable energy. Among these, attention has been focused on the benefits of replacing conventional power transmission and distribution networks with higher-voltage direct current (DC) transmission and distribution.

[0003] DC power transmission and distribution is well suited to semiconductor power converters, and by reducing the number of converter stages, it is possible to reduce power conversion losses when repeatedly transmitting and receiving power over various paths. Furthermore, it also leads to a reduction in transmission losses when transmitting power over long distances, allowing for more efficient energy utilization.

[0004] To achieve higher voltages, semiconductor switching elements must be made to withstand higher voltages, but due to physical limitations, the increased voltage leads to an exponential degradation in performance. To solve this problem, a series connection of semiconductor switching elements and other configurations in which multiple semiconductor switching elements are connected in series are being considered.

[0005] For example, Japanese Patent Laid-Open Publication No. 2000-36731 (Patent Document 1) describes a control method for suppressing imbalances in the shared voltages between semiconductor elements in a semiconductor power converter in which semiconductor elements are connected in series and which are caused by variations in the characteristics of the elements and gate drivers and in snubber capacitors. Specifically, the shared voltages of each element when it is turned off are detected, and the delay times of the gate signals are adjusted between the elements, thereby automatically correcting the imbalances in the shared voltages.

[0006] Japanese Patent Application Laid-Open No. 2000-36731

[0007] However, in the control of Patent Document 1, the voltage shared by each element at the time of turn-off is detected, and the delay time of the gate signal of each element is adjusted so that the delay time of the gate signal of the other elements is increased based on the element with the lowest voltage.

[0008] For this reason, for semiconductor switching elements that are driven at high speed, it becomes necessary to speed up the calculation process that determines the delay time of each element using the detected value of the shared voltage described above, which raises concerns that it may become difficult to perform feedback at high speed and with high accuracy. For example, such a problem is a concern when using semiconductor switching elements made of wide bandgap semiconductors such as GaN (gallium nitride).

[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to suppress imbalances in the shared voltages between semiconductor switching elements in a power conversion device having multiple semiconductor switching elements connected in series, without requiring high-speed arithmetic processing.

[0010] In one aspect of the present invention, a power conversion device includes two first semiconductor elements (first and second), two second semiconductor elements (first and second), a first capacitor, and a first speed regulator circuit. The first and second first semiconductor elements are connected in series between a first positive wiring on the high-voltage side and an output node, arranged in order from the first positive wiring toward the output node. The first and second second semiconductor elements are connected in series between a first negative wiring on the low-voltage side and the output node, arranged in order from the first negative wiring toward the output node. The first capacitor is electrically connected between a second positive wiring connecting the negative terminal of the first first semiconductor element and the positive terminal of the second first semiconductor element, and a second negative wiring connecting the positive terminal of the first second semiconductor element and the negative terminal of the second second semiconductor element. The first speed regulator circuit is arranged for at least one of the first first semiconductor element and the first second semiconductor element in correspondence with the first capacitor, and each first speed regulator circuit is configured to reduce the turn-off speed of the first first semiconductor element or the first second semiconductor element in response to a voltage drop across the first capacitor to be slower than the turn-off speed of the second first semiconductor element or the second second semiconductor element in which the first speed regulator circuit is not arranged.

[0011] In another aspect of the present invention, a power conversion device includes N first semiconductor elements from a first to an Nth (N: an integer of 3 or greater) first semiconductor elements, N first to Nth second semiconductor elements, a first capacitor, and a first speed regulator circuit. The N first semiconductor elements from the first to the Nth first semiconductor elements are arranged in series between a first positive wiring on the high-voltage side and an output node, in order from the first positive wiring toward the output node. The N second semiconductor elements from the first to the Nth second semiconductor elements are arranged in series between a first negative wiring on the low-voltage side and the output node, in order from the first negative wiring toward the output node. The first capacitor is connected between an (i+1)th positive wiring connecting the negative terminal of an i-th (i: integer greater than or equal to 1 and less than or equal to (N-1)) first semiconductor element among the N first semiconductor elements and the positive terminal of the (i+1)th first semiconductor element, and an (i+1)th negative wiring connecting the positive terminal of an i-th second semiconductor element among the N second semiconductor elements and the negative terminal of the (i+1)th second semiconductor element, for a total of (N-1) first capacitors. A first speed regulator circuit is arranged for at least one of the i-th first semiconductor element and the i-th second semiconductor element in correspondence with each first capacitor, and each first speed regulator circuit is configured to reduce the turn-off speed of the i-th first semiconductor element or the i-th second semiconductor element to be lower than the turn-off speed of an N-th first semiconductor element or an N-th second semiconductor element in response to a voltage drop across the corresponding first capacitor.

[0012] According to the present disclosure, in a power conversion device having a plurality of semiconductor switching elements connected in series, the voltage of a first capacitor connected as a flying capacitor is maintained by adjusting the switching speed of the semiconductor elements using a first speed regulator circuit, thereby suppressing imbalances in the shared voltage between the semiconductor switching elements without requiring high-speed calculation processing.

[0013] 1 is a schematic configuration diagram of a power conversion device according to a first embodiment. FIG. 2 is a circuit diagram showing a main circuit configuration of the power conversion device shown in FIG. 1. FIG. 3 is a circuit diagram explaining a switching pattern of the power conversion device shown in FIG. 1. FIG. 4 is a conceptual first circuit diagram for explaining the operation of a speed regulator circuit when a semiconductor switching element is turned off. FIG. 5 is a conceptual first circuit diagram for explaining the operation of the speed regulator circuit during an on-period of a semiconductor switching element. FIG. 6 is a conceptual first waveform diagram for explaining the operation of the speed regulator circuit when a semiconductor switching element is turned off. FIG. 7 is a conceptual second circuit diagram for explaining the operation of the speed regulator circuit when a semiconductor switching element is turned off. FIG. 8 is a conceptual second circuit diagram for explaining the operation of the speed regulator circuit during an on-period of a semiconductor switching element. FIG. 9 is a conceptual second waveform diagram for explaining the operation of the speed regulator circuit when a semiconductor switching element is turned off. FIG. 10 is a first circuit diagram for explaining a modified example of the speed regulator circuit. FIG. 11 is a second circuit diagram for explaining a modified example of the speed regulator circuit. FIG. 12 is a schematic configuration diagram of a power conversion device according to a second embodiment. FIG. 13 is a schematic configuration diagram of a main part of a power conversion device according to a third embodiment. 10 is a conceptual waveform diagram for explaining the operation of a speed regulator circuit when a semiconductor switching element is turned on in a power conversion device according to embodiment 3. FIG. 11 is a schematic configuration diagram of a main part of a power conversion device according to a modified example of embodiment 3. FIG. 12 is a schematic configuration diagram of a main part of a power conversion device according to embodiment 4.

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, identical or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0015] First Embodiment (Schematic Configuration of Power Conversion Device) Fig. 1 is a schematic configuration diagram of a power conversion device 100A according to a first embodiment.

[0016] 1, the power conversion device 100A includes semiconductor switching elements Q1 to Q4, and performs power transmission between DC power sources 1 and 2. Specifically, the power conversion device 100A includes a bridge circuit 110, a capacitor 101, a filter reactor 102, a filter capacitor 103, and a controller 210. In FIG. 1, the power conversion device 100A is exemplified as a chopper circuit that is connected between the DC power sources 1 and 2 and performs DC / DC power conversion between the DC power sources 1 and 2.

[0017] The bridge circuit 110 is configured by connecting semiconductor switching elements Q1 to Q4 in series between a first positive wiring 112 and a first negative wiring 113. The semiconductor switching element Q1 is electrically connected between the first positive wiring 112 and a second positive wiring 114, and the semiconductor switching element Q2 is electrically connected between the second positive wiring 114 and an output node Nb of the bridge circuit 110.

[0018] The semiconductor switching element Q3 is electrically connected between the output node Nb and the second negative wiring 115, and the semiconductor switching element Q4 is electrically connected between the first negative wiring 113 and the second negative wiring 115.

[0019] Each of the semiconductor switching elements Q1 to Q4 can be configured by any self-extinguishing element such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a HEMT (High Electron Mobility Transistor).

[0020] Each of the semiconductor switching elements Q1 to Q4 is connected in anti-parallel to a diode 21. The diode may be an external element for each semiconductor switching element, or may be configured as a body diode built into each semiconductor switching element such as a MOSFET.

[0021] The capacitor 101 is electrically connected between the first positive wiring 112 and the first negative wiring 113. That is, the capacitor 101 is connected in parallel with the DC power supply 1. A capacitor 111 corresponding to a "flying capacitor" is connected between the second positive wiring 114 and the second negative wiring 115.

[0022] The filter reactor 102 is connected between the output node Nb of the bridge circuit 110 and the positive electrode of the DC power supply 2. The filter capacitor 103 is connected in parallel with the DC power supply 2.

[0023] The DC voltage Vd1 of the capacitor 101, the DC voltage Vd2 of the filter capacitor 103, and the voltage Vfc1 of the capacitor 111 are detected by voltage sensors and input to the controller 210. The current Io of the filter reactor 102 is detected by a current sensor and input to the controller 210.

[0024] The controller 210 generates gate signals Sd1 to Sd4 for the semiconductor switching elements Q1 to Q4 using Vd1, Vd2, and Vfc1 detected by the voltage sensor and Io detected by the current sensor. For example, the controller 210 can perform on / off control (switching control) of the semiconductor switching elements Q1 to Q4 so that the DC voltages Vd1 and Vd2, the voltage Vfc1 of the capacitor 111, the integrated value of the current Io, and the like become appropriate values.

[0025] The controller 210 may be configured with a digital electronic circuit that performs arithmetic processing using an FPGA (Field Programmable Gate Array) or the like via an A / D conversion device, or may be configured with analog electronic circuits such as a comparator, an operational amplifier, and a differential amplifier circuit, or may be configured with both a digital electronic circuit and an analog electronic circuit.

[0026] The bridge circuit 110 further includes driver circuits 151 to 154. The driver circuits 151 to 154 respond to gate signals Sd1 to Sd4 from the controller 210 to turn on and off the semiconductor switching elements Q1 to Q4.

[0027] Each of the semiconductor switching elements Q1 to Q4 has its gate (control electrode) driven by driver circuits 151 to 154 to turn on and off, thereby changing the output voltage between the positive terminal (drain or collector) and the negative terminal (source or emitter) and the output current generated between the positive terminal and the negative terminal.

[0028] When turning off the semiconductor switching elements Q1 to Q4, the driver circuits 151 to 154 output an off voltage Voff (GND or negative voltage) to the gates (control electrodes). Conversely, when turning on the semiconductor switching elements Q1 to Q4, the driver circuits 151 to 154 output an on voltage Von (a positive voltage higher than the threshold voltage Vth of the semiconductor switching elements Q1 to Q4) to the gates (control electrodes). Note that a gate resistor Rg is generally connected between the driver circuits 151 to 154 and each gate (control electrode) of the semiconductor switching elements Q1 to Q4.

[0029] The bridge circuit 110 also includes a speed regulating circuit 130 for adjusting the switching speed (turn-off speed) of the semiconductor switching element Q1, a speed regulating rectifying element 133, and a speed regulating resistive element 134. The speed regulating circuit 130 includes a speed regulating capacitor 131 and a speed regulating rectifying element 132 connected in series between the positive terminal and gate of the semiconductor switching element Q1. The speed regulating capacitor 131 is connected between the positive terminal of the semiconductor switching element Q1 and a node N1. The speed regulating rectifying element 132 is arranged so that the forward direction is from the node N1 to the gate (control electrode) of the semiconductor switching element Q1. The speed regulating rectifying element 133 and the speed regulating resistive element 134 are connected in series between the second negative wiring 115 (i.e., the negative side of the capacitor 111) and the node N1. The speed regulating rectifying element 133 is connected so that the forward direction is from the second negative wiring 115 to the node N1. 1, the connection order of the speed regulating element 133 and the speed regulating resistance element 134 may be reversed. That is, it is also possible to configure the speed regulating element 133 so that the anode is connected to the second negative wiring 115, and the speed regulating resistance element 134 is connected between the cathode of the speed regulating element 133 and the node N1.

[0030] The bridge circuit 110 further includes a speed regulating circuit 140 for adjusting the switching speed (turn-off speed) of the semiconductor switching element Q4, a speed regulating rectifying element 143, and a speed regulating resistive element 144. The speed regulating circuit 140 includes a speed regulating capacitor 141 and a speed regulating rectifying element 142 connected in series between the positive terminal and gate of the semiconductor switching element Q4. The speed regulating rectifying element 142 is connected between the positive terminal of the semiconductor switching element Q4 and node N2, with the direction from the positive terminal of the semiconductor switching element Q4 to node N2 being the forward direction. The speed regulating capacitor 141 is connected between node N2 and the gate (control electrode) of the semiconductor switching element Q4. The speed regulating rectifying element 143 and the speed regulating resistive element 144 are connected in series between the second positive wiring 114 (i.e., the positive side of the capacitor 111) and node N2. The speed control rectifier element 143 is connected with the direction from the node N2 to the second positive wiring 114 as the forward direction. Note that, in accordance with the configuration example of Fig. 1, the connection order of the speed control rectifier element 143 and the speed control resistance element 144 can also be reversed. That is, it is also possible to configure the speed control rectifier element 143 so that the cathode is connected to the second positive wiring 114 and the speed control resistance element 144 is connected between the anode of the speed control rectifier element 143 and the node N2.

[0031] (Switching Control in Power Converter) Next, the on / off control (switching control) of the semiconductor switching elements Q1 to Q4 in the power converter 100A will be described with reference to FIGS.

[0032] Fig. 2 is a circuit diagram showing the main circuit configuration of the power conversion device 100A. Fig. 2 shows a basic configuration for power conversion, in which the speed control circuits 130 and 140, the speed control rectifier elements 133 and 143, and the speed control resistor elements 134 and 144 are omitted from the configuration example of Fig. 1.

[0033] 2 , semiconductor switching elements Q1 and Q2 are connected in series between the first positive wiring 112 and the output node Nb via the second positive wiring 114. Similarly, semiconductor switching elements Q1 and Q2 are connected in series between the output node Nb and the first negative wiring 113 via the second negative wiring 115.

[0034] Capacitor 111 is connected between a second positive wiring 114 that connects the negative terminal of semiconductor switching element Q1 and the positive terminal of semiconductor switching element Q2, and a second negative wiring 115 that connects the negative terminal of semiconductor switching element Q3 and the positive terminal of semiconductor switching element Q4. As a result, capacitor 111 has the function of maintaining the sum of the output voltages of semiconductor switching elements Q2 and Q3.

[0035] Capacitor 101, by being connected between first positive wiring 112 and first negative wiring 113, has the function of holding the sum of the output voltages of semiconductor switching elements Q1 to Q4, and in combination with the function of capacitor 111, has the secondary function of holding the sum of the output voltages of semiconductor switching elements Q1 and Q4.

[0036] By controlling the voltage Vfc1 of the capacitor 111 to be half the DC voltage Vd1 of the capacitor 101, the total output voltage of the semiconductor switching elements Q1 and Q4 and the total output voltage of the semiconductor switching elements Q3 are each set to (1 / 2)·Vd1, thereby equalizing the output voltages of the semiconductor switching elements Q1 to Q4. This reduces the risk of an overvoltage exceeding the breakdown voltage being applied to the semiconductor switching elements Q1 to Q4.

[0037] Thus, the power conversion device 100A has a circuit configuration including a plurality of (two) semiconductor switching elements connected in series between the first positive wiring 112 and the output node Nb, and between the first negative wiring 113 and the output node Nb, and a flying capacitor (capacitor 111).

[0038] FIG. 3 shows a circuit diagram illustrating the switching pattern of the power conversion device 100A.

[0039] The power conversion device 100A is basically controlled so that the semiconductor switching elements Q2 and Q3 are turned on and off in a complementary manner, and the semiconductor switching elements Q1 and Q4 are turned on and off in a complementary manner. Therefore, the power conversion device 100A is switched by appropriately combining the four switching patterns shown in Figures 3(a) to 3(d).

[0040] As shown in FIG. 3A, in a switching pattern in which the semiconductor switching elements Q1 and Q2 are turned on while the semiconductor switching elements Q3 and Q4 are turned off, the first positive electrode wiring 112 is connected to the output node Nb.

[0041] As shown in FIG. 3B, in a switching pattern in which the semiconductor switching elements Q3 and Q4 are turned on while the semiconductor switching elements Q1 and Q2 are turned off, the first negative wiring 113 is connected to the output node Nb.

[0042] As shown in FIG. 3C, in a switching pattern in which the semiconductor switching elements Q1 and Q3 are turned on while the semiconductor switching elements Q2 and Q4 are turned off, the second negative wiring 115 is connected to the output node Nb.

[0043] As shown in FIG. 3D, in a switching pattern in which the semiconductor switching elements Q2 and Q4 are turned on while the semiconductor switching elements Q1 and Q3 are turned off, the second positive electrode wiring 114 is connected to the output node Nb.

[0044] As described above, the power conversion device 100A operates as a chopper circuit between the DC power source 1 and the DC power source 2. Therefore, basically, power is transmitted between the DC power source 1 (Vd1) and the DC power source 2 (Vd2) by alternately repeating the switching patterns of Fig. 3(a) and Fig. 3(b). As is well known, the voltage ratio (Vd1 / Vd2) can be controlled by controlling the ratio between the period length of the switching pattern of Fig. 3(a) and the period length of the switching pattern of Fig. 3(b).

[0045] In the power conversion device 100A according to the first embodiment, the semiconductor switching elements Q1 to Q4 are controlled to alternately repeat the switching patterns of Figures 3(a) and 3(b) in accordance with the basic pattern described above in order to control the voltage ratio (Vd1 / Vd2), and voltage adjustment control is automatically performed to maintain the voltage Vfc1 of the capacitor 111 (flying capacitor) at (1 / 2) Vd1 by controlling the switching speed (turn-off speed) of the semiconductor switching elements Q1 and Q4 using the speed regulation circuits 130 and 140.

[0046] In the power conversion device 100A, the switching pattern of FIG. 3(c) can form a current path from the first positive wiring 112 to the output node Nb, accompanied by charging of the capacitor 111. On the other hand, the switching pattern of FIG. 3(d) can form a current path from the first negative wiring 113 to the output node Nb, accompanied by discharging of the capacitor 111. Therefore, by providing periods of the switching patterns of FIG. 3(c) and FIG. 3(d) to a basic pattern in which the switching patterns of FIG. 3(a) and FIG. 3(b) are alternately repeated, it is also possible to execute control to bring the voltage Vfc1 of the capacitor 111 closer to (½)·Vd1. Therefore, under the above-described voltage adjustment control, it is also possible to control the switching of the semiconductor switching elements Q1 to Q4 so that periods of the switching pattern of FIG. 3(c) or FIG. 3(d) are provided when the voltage difference between the voltages Vfc1 and (½)·Vd1 becomes large.

[0047] (Voltage Adjustment Control of Flying Capacitor by Speed ​​Regulator Circuit) First, adjustment of the switching speed (turn-off speed) of the semiconductor switching element Q1 by the speed regulator circuit 130 or the like will be described with reference to FIG. 1 and FIGS. 4 to 6. FIG.

[0048] Referring again to FIG. 1, when the semiconductor switching element Q1 is turned off, the speed regulating rectifying element 132 becomes conductive while the speed regulating rectifying element 133 becomes non-conductive in response to an increase in the output voltage (Vds) of the semiconductor switching element Q1, and the speed regulating circuit 130 operates as shown in FIG.

[0049] As shown by the dotted line in Figure 4, when Vds rises after the semiconductor switching element Q1 starts to turn off, if the output voltage Vds of the semiconductor switching element Q1 becomes higher than the sum of the voltage (V131) of the speed control capacitor 131, the threshold voltage Vth of the semiconductor switching element Q1, and the voltage drop Vclmp of the diode 21, that is, if the following equation (1) is established, a charging path for the speed control capacitor 131 is formed.

[0050] Vds>V131+Vth+Vclmp (1) The charging path of the speed control capacitor 131 is formed via the speed control capacitor 131, the speed control rectifying element 132 (conductive), the gate resistor Rg, the driver circuit 151, and the diode 21 (conductive).

[0051] 4 is formed, the gate (control electrode) of the semiconductor switching element Q1 connected to the cathode of the speed control rectifier element 132 is also charged, along with the speed control capacitor 131. As a result, the decrease in gate voltage (from on voltage Von to off voltage Voff) caused by the driver circuit 151 at turn-off becomes gradual, and the turn-off speed of the semiconductor switching element Q1 is reduced.

[0052] Referring again to FIG. 1, during the on period of the semiconductor switching element Q1, the output voltage (Vds) of the semiconductor switching element Q1 is approximately zero, so that the speed regulating rectifying element 132 is non-conductive, while the speed regulating rectifying element 133 is conductive, causing the speed regulating circuit 130 to operate as shown in FIG. 5.

[0053] As shown by the dotted line in Figure 5, during the on period of the semiconductor switching element Q1, when the voltage V131 of the speed control capacitor 131 is higher than the voltage Vfc1 of the capacitor 111 (V131 > Vfc1), a discharge path for the speed control capacitor 131 is formed.

[0054] The discharge path of the speed control capacitor 131 is formed via the speed control capacitor 131, the semiconductor switching element Q1 (on), the capacitor 111, the speed control resistance element 134, and the speed control rectifying element 133 (conducting). By forming the discharge path shown in Figure 5, the voltage of the speed control capacitor 131 becomes equal to the voltage Vfc1 of the capacitor 111.

[0055] 4 every time the semiconductor switching element Q1 is turned off, and is discharged to a voltage (approximately Vfc1) equivalent to that of the capacitor 111 during each on period of the semiconductor switching element Q1 via the path shown in Fig. 5. As a result, the voltage of the speed controlling capacitor 131 is equivalent to the voltage Vfc1 of the capacitor 111 (V131 = Vfc1) at the timing when the semiconductor switching element Q1 starts to turn off.

[0056] As described above, the timing at which the discharge path in FIG. 4 is formed is the timing at which the output voltage Vds of semiconductor switching element Q1, which rises after turn-off begins, exceeds (V131+Vth+Vclmp. Because threshold voltage Vth and voltage drop amount Vclmp are circuit constants, it can be understood that the lower the voltage V131 of speed control capacitor 131, the earlier the timing at which the discharge path in FIG. 4 is formed, and the shorter the time that elapses from the start of turn-off until the turn-off speed starts to decrease. As a result, the timing at which the turn-off speed of semiconductor switching element Q1 starts to decrease is automatically adjusted depending on voltage Vfc1 of capacitor 111.

[0057] On the other hand, the semiconductor switching element Q2 connected in series with the semiconductor switching element Q1 does not have a speed regulator circuit 130 for adjusting the turn-off speed. Therefore, the conceptual operating waveform diagram when the semiconductor switching elements Q1 and Q2 are turned off at the same timing is as shown in Figure 6 as a result of the operation of the speed regulator circuit 130.

[0058] In Figure 6, the waveforms of the output voltage Vds (Q2) and output current Ids (Q2) of the semiconductor switching element Q2, which does not have a speed regulator circuit 130, are shown by dotted lines, while the waveforms of the output voltage Vds (Q1) and output current Ids (Q2) of the semiconductor switching element Q1, which has a speed regulator circuit 130, are shown by solid lines.

[0059] In FIG. 6, in the initial state, the semiconductor switching elements Q1 and Q2 are in the ON state, the output voltage Vds(Q1)=Vds(Q2)=0, and the output currents Ids(Q1)>0, Ids(Q2)>0.

[0060] When the gate signals Sd1 and Sd2 change from H level to L level, the driver circuits 151 and 152 start to turn off the semiconductor switching elements Q1 and Q2. As the driver circuits 151 and 152 reduce the gate voltages of the semiconductor switching elements Q1 and Q2, Vds(Q1) and Vds(Q2) start to increase from time t0.

[0061] Furthermore, the output current Ids(Q2) of the semiconductor switching element Q2 starts to decrease from time t2, and at time t3, Ids(Q2) becomes 0, and the semiconductor switching element Q2 is completely turned off.

[0062] Meanwhile, in semiconductor switching element Q1, from time t0, output voltage Vds(Q1) rises at the same rate as output voltage Vds(Q2), but at time t1, output voltage Vds(Q1) satisfies the above formula (1), turning on speed controlling rectifier element 132 and forming the charging path shown in Fig. 4. In formula (1), V131 >> Vth + Vclmp, so at the timing when Vds(Q1) > V131 (≈ Vfc1), speed controlling rectifier element 132 turns on.

[0063] As a result, the gate (control electrode) of the semiconductor switching element Q1 is charged, and the gate voltage decreases more slowly, so the rate at which the output voltage Vds (Q1) increases decreases.

[0064] As a result, the output current Ids(Q1) of the semiconductor switching element Q1 begins to decrease from time t4, which is later than time t2, and is completely turned off at time t5 when Ids(Q1) = 0. In response to the formation of the gate charging path described above, a charging current Ichg1 is generated for the speed control capacitor 131 between times t1 and t5.

[0065] In this way, while semiconductor switching elements Q1 and Q2 start to turn off at the same time, in semiconductor switching element Q1, output current Ids(Q1) starts to decrease at a later timing than output current Ids(Q2) due to the operation of speed governing circuit 130. As a result, it can be understood that the turn-off speed of semiconductor switching element Q1 is slower than that of semiconductor switching element Q2 due to the operation of speed governing circuit 130.

[0066] As a result, during the period from time t2 to t4, the semiconductor switching element Q2 is turned off while the semiconductor switching element Q1 is maintained on, thereby providing a charging period for the capacitor 111.

[0067] As described above, the greater the degree of decrease in voltage Vfc1 of capacitor 111, the lower the voltage of speed control capacitor 131 at the start of turn-off, and therefore the later the timing (time t1) at which speed control circuit 130 forms a charging path (FIG. 4). As a result, the period over which the turn-off speed is reduced becomes relatively longer, and the timing (time t4) at which output current Ids (Q1) begins to decrease and the timing (time t5) at which it becomes zero are automatically adjusted so that the lower the voltage of capacitor 111, the later they become.

[0068] On the other hand, the timing (time t2) when semiconductor switching element Q2 is completely turned off is constant and does not depend on the voltage Vfc1 of capacitor 111. For this reason, it can be understood that the length of the period from time t2 to t5, i.e., the charging period of capacitor 111 during which semiconductor switching element Q2 is turned off and semiconductor switching element Q1 is turned on, is automatically adjusted so that the lower the voltage Vfc1 of capacitor 111, the longer the charging period becomes. As a result, speed governor circuit 130 performs voltage adjustment control so that the greater the degree of decrease in voltage Vfc1 of capacitor 111, the greater the degree of decrease in the turn-off speed of semiconductor switching element Q1.

[0069] Next, the operation of the speed regulation circuit 140 provided in the semiconductor switching element Q4 will be similarly described with reference to FIG. 1 and FIGS.

[0070] 1, when semiconductor switching element Q4 is turned off, driver circuit 154 outputs off voltage Voff (GND or negative voltage), and therefore speed-regulating rectifier element 142 becomes conductive in response to an increase in output voltage (Vds) of semiconductor switching element Q1. As a result, speed-regulating circuit 140 operates as shown in FIG.

[0071] As shown by the dotted line in Figure 7, when Vds rises when the semiconductor switching element Q4 is turned off, if the output voltage Vds of the semiconductor switching element Q4 becomes higher than the sum of the voltage (V141) of the speed control capacitor 141, the threshold voltage Vth of the semiconductor switching element Q4, and the voltage drop Vclmp of the diode 21, that is, if the following equation (2) is established, a charging path for the speed control capacitor 141 is formed.

[0072] Vds>V141+Voff+Vth+Vclmp (2) The charging path of the speed control capacitor 141 is formed via the speed control capacitor 141, the speed control rectifying element 142 (conductive), the gate resistor Rg, the driver circuit 154, and the diode 21 (conductive).

[0073] 7 is formed, the gate (control electrode) of semiconductor switching element Q4 is charged as well as speed control capacitor 141. This reduces the rate at which the gate voltage is reduced by driver circuit 154 during turn-off, thereby slowing down the turn-off speed of semiconductor switching element Q4.

[0074] 1, during the on-period of semiconductor switching element Q4, driver circuit 154 outputs on-voltage Von (positive voltage), and the output voltage (Vds) of semiconductor switching element Q4 becomes approximately 0. As a result, speed controlling rectifying element 142 becomes non-conductive, while speed controlling rectifying element 143 becomes conductive, so that speed controlling circuit 140 operates as shown in FIG.

[0075] As shown by the dotted line in Figure 8, during the on period of semiconductor switching element Q4, when the sum of the voltage V141 of speed control capacitor 141 and the on voltage Von is higher than the voltage Vfc1 of capacitor 111 (V141 + Von > Vfc1), a discharge path for speed control capacitor 141 is formed.

[0076] The discharge path of the speed control capacitor 141 is formed via the speed control capacitor 141, the speed control rectifying element 143 (conducting), the speed control resistive element 144, the capacitor 111, the semiconductor switching element Q4 (on), the driver circuit 154, and the gate resistor Rg. By forming the discharge path of FIG. 8, the voltage of the speed control capacitor 141 becomes equal to the voltage Vfc1 of the capacitor 111.

[0077] 7 every time semiconductor switching element Q4 is turned off, and is discharged to a voltage (approximately Vfc1) equivalent to that of capacitor 111 during each on period of semiconductor switching element Q4 via the path shown in Fig. 8. As a result, the voltage of speed controlling capacitor 141 is also equivalent to the voltage Vfc1 of capacitor 111 (V141 = Vfc1) at the timing when semiconductor switching element Q4 starts to turn off.

[0078] As described above, the timing at which the discharge path in FIG. 8 is formed is the timing at which the output voltage Vds of semiconductor switching element Q4, which rises after turn-off begins, exceeds (V141+Voff+Vth+Vclmp. The off-voltage Voff, threshold voltage Vth, and voltage drop amount Vclmp are circuit constants. Therefore, it can be understood that the lower the voltage V141 of speed control capacitor 141, the earlier the timing at which the discharge path in FIG. 7 is formed, and the shorter the time that elapses from the start of turn-off until the turn-off speed starts to decrease. As a result, the timing at which the turn-off speed of semiconductor switching element Q4 starts to decrease is automatically adjusted depending on the voltage Vfc1 of capacitor 111.

[0079] On the other hand, the semiconductor switching element Q3 connected in series with the semiconductor switching element Q4 is not provided with a speed regulator circuit 140 for adjusting the turn-off speed. Therefore, the conceptual operating waveform diagram when the semiconductor switching elements Q3 and Q4 are turned off at the same timing is as shown in FIG. 9 as a result of the operation of the speed regulator circuit 140.

[0080] In Figure 9, the waveforms of the output voltage Vds (Q3) and output current Ids (Q3) of the semiconductor switching element Q3, which does not have a speed regulator circuit 140, are shown by dotted lines, while the waveforms of the output voltage Vds (Q4) and output current Ids (Q4) of the semiconductor switching element Q4, which has a speed regulator circuit 140, are shown by solid lines.

[0081] In FIG. 9, in the initial state, the semiconductor switching elements Q3 and Q4 are in the ON state, the output voltage Vds(Q3)=Vds(Q3)=0, and the output currents Ids(Q1)>0, Ids(Q2)>0.

[0082] When the gate signals Sd3 and Sd4 change from H level to L level, the driver circuits 153 and 154 start to turn off the semiconductor switching elements Q3 and Q4. As the driver circuits 153 and 154 reduce the gate voltages of the semiconductor switching elements Q1 and Q2, Vds(Q3) and Vds(Q4) start to increase from time t0x.

[0083] Furthermore, the output current Ids(Q3) of the semiconductor switching element Q3 starts to decrease from time t2x, and at time t3x, Ids(Q3) becomes 0, and the semiconductor switching element Q3 is completely turned off.

[0084] In semiconductor switching element Q4, from time t0x, output voltage Vds(Q4) rises at the same rate as output voltage Vds(Q3), but at time t1x, output voltage Vds(Q4) satisfies the above formula (2), turning on speed controlling rectifier element 142 and forming the charging path shown in Fig. 7. In formula (2), V141 >> Voff + Vth + Vclmp, so at the timing when Vds(Q4) > V141 (≈ Vfc1), speed controlling rectifier element 142 turns on.

[0085] As a result, the gate (control electrode) of the semiconductor switching element Q4 is charged, and the gate voltage decreases more slowly, so the rate at which the output voltage Vds (Q4) increases decreases.

[0086] As a result, the output current Ids(Q4) of the semiconductor switching element Q4 starts to decrease from time t4x, which is later than time t2x, and is completely turned off at time t5x when Ids(Q4) = 0. In response to the formation of the charging path described above, a charging current Ichg2 for the speed control capacitor 141 is generated between times t1x and t5x.

[0087] In this way, while semiconductor switching elements Q3 and Q4 start to turn off at the same time, the output current Ids(Q4) of semiconductor switching element Q4 starts to decrease at a later timing than the output current Ids(Q3) due to the operation of speed regulator circuit 140. As a result, it can be seen that the turn-off speed of semiconductor switching element Q4 is slower than that of semiconductor switching element Q3 due to the operation of speed regulator circuit 140.

[0088] As a result, during the period from time t2x to time t4x, the semiconductor switching element Q3 is turned off while the semiconductor switching element Q4 is maintained on, thereby providing a charging period for the capacitor 111.

[0089] As described above, the greater the degree of decrease in voltage Vfc1 of capacitor 111, the lower the voltage of speed control capacitor 141 at the start of turn-off, and therefore the later the timing (time t1x) at which speed control circuit 140 forms a charging path (FIG. 7). As a result, the period over which the turn-off speed is reduced becomes relatively longer, and the timing (time t4x) at which output current Ids (Q4) begins to decrease and the timing (time t5x) at which it becomes zero are automatically adjusted so that the lower the voltage of capacitor 111, the later they become.

[0090] On the other hand, the timing (time t2x) when semiconductor switching element Q3 is completely turned off is constant and does not depend on the voltage Vfc1 of capacitor 111. Therefore, it can be understood that the length of the period from time t2x to time t5x, i.e., the charging period of capacitor 111 during which semiconductor switching element Q3 is turned off and semiconductor switching element Q4 is turned on, is automatically adjusted so that the lower the voltage Vfc1 of capacitor 111, the longer the charging period becomes. As a result, the speed governor circuit 140 also performs voltage adjustment control so that the greater the degree of decrease in voltage Vfc1 of capacitor 111, the greater the degree of decrease in the turn-off speed of semiconductor switching element Q4.

[0091] In power conversion device 100A, when voltage Vfc1 of capacitor 111 is greater than half the DC voltage Vd1 of capacitor 101 (Vfc1>(Vd1 / 2)), the effect of capacitor 111 is such that output voltage Vds of semiconductor switching element Q1 or Q4 is maintained at the voltage difference (Vd1-Vfc1) / 2 between capacitors 101 and 111. Therefore, when semiconductor switching elements Q1 and Q4 are turned off, speed governing rectifier elements 132 and 142 are maintained non-conductive in speed governing circuits 130 and 140. Therefore, speed governing circuits 130 and 140 do not perform the above-described automatic adjustment to reduce the turn-off speed of semiconductor switching elements Q1 and Q4 in order to charge capacitor 111.

[0092] On the other hand, if the voltage Vfc1 of capacitor 111 is smaller than half the DC voltage Vd1 of capacitor 101 (Vfc1<(Vd1 / 2)), when semiconductor switching elements Q1, Q4 are turned off, speed control rectifier elements 132, 142 in speed control circuits 130 and / or 140 are made conductive, and a charging path (FIGS. 4 and 7) is formed for speed control capacitors 131, 141. As a result, automatic adjustment is performed to reduce the turn-off speed of semiconductor switching elements Q1, Q4, and a charging period for capacitor 111 is provided, thereby suppressing a voltage drop across capacitor 111.

[0093] Therefore, according to power conversion device 100A of embodiment 1, by providing speed governing circuits 130, 140, when voltage Vfc1 of capacitor 111 (flying capacitor) drops, a charging period for capacitor 111 can be automatically set when semiconductor switching elements Q1, Q4 are turned off. By maintaining voltage Vfc1 of capacitor 111 (flying capacitor) at Vd1·(½) through voltage adjustment control by speed governing circuits 130, 140, it is possible to suppress imbalance in the distribution of output voltage Vds among semiconductor switching elements Q1 to Q4 without requiring high-speed calculation processing.

[0094] The speed regulator circuits 130 and 140 may have modified configurations shown in FIGS.

[0095] FIG. 10 shows a modified example of the speed regulator circuit 130 provided in the semiconductor switching element Q1.

[0096] The speed regulating circuit 130 can be configured to further connect an impedance element 135 between the speed regulating capacitor 131 and the node N1, as shown in Fig. 10(a). Alternatively, as shown in Fig. 10(b), the impedance element 135 may be connected between the node N1 and the speed regulating rectifying element 132 (anode).

[0097] The modified speed regulator circuit 130 shown in Figures 10(a) and 10(b) can suppress the oscillation phenomenon due to resonance in the charging path shown in Figure 4. This can stabilize the circuit operation of the speed regulator circuit 130 for the voltage regulation control described above. The impedance element 135 can be configured with a resistive element to reduce the sharpness of the resonance. Alternatively, the impedance element 135 can be configured with an inductor to move the resonance frequency away from the switching frequency of the semiconductor switching elements Q1 to Q4.

[0098] FIG. 11 shows a modified example of the speed regulator circuit 140 provided in the semiconductor switching element Q4.

[0099] 11(a), the speed regulating circuit 140 can be configured to further connect an impedance element 145 between the speed regulating rectifying element 142 (cathode) and the node N2. Alternatively, as shown in FIG. 11(b), the impedance element 145 may be connected between the node N2 and the speed regulating capacitor 141. Like the impedance element 135, the impedance element 145 can be configured by a resistive element or an inductor.

[0100] The modified speed regulator circuit 140 shown in Figures 11(a) and 11(b) can suppress the oscillation phenomenon caused by resonance in the charging path shown in Figure 7. This makes it possible to stabilize the circuit operation of the speed regulator circuit 140 for the voltage regulation control described above.

[0101] Second Embodiment The power conversion device 100A according to the first embodiment can automatically compensate for a voltage drop in the capacitor 101 by using the speed regulation circuits 130 and 140, but needs to introduce the switching pattern shown in Fig. 3(d) to cope with a voltage rise in the capacitor 111. In the second embodiment, a configuration for coping with a voltage rise in the capacitor 111 will be described.

[0102] FIG. 12 is a schematic configuration diagram of a power conversion device 100B according to the second embodiment. As shown in FIG. 12, the power conversion device 100B further includes a discharge element 120 connected in parallel with the capacitor 111, in addition to the configuration of the power conversion device 100A according to the first embodiment ( FIG. 1 ). The discharge element 120 can typically be configured as a resistive element. Except for this, the configuration of the power conversion device 100B is similar to that of the power conversion device 100A, and therefore detailed description will not be repeated. The speed control circuits 130 and 140 can also be configured in the same manner as those shown in FIGS. 10 and 11 (the modified example of the first embodiment) according to the modified example of the first embodiment.

[0103] Therefore, in power conversion device 100B, when voltage Vfc1 of capacitor 111 (flying capacitor) drops, voltage adjustment control to provide a charging period for capacitor 111 by speed regulation circuits 130, 140 is executed in the same manner as in embodiment 1. Furthermore, in power conversion device 100B, when voltage Vfc1 of capacitor 111 rises, a charging period for capacitor 111 by speed regulation circuits 130, 140 is not provided, and capacitor 111 is discharged by discharge element 120, thereby making it possible to lower voltage Vfc1 of capacitor 111.

[0104] As a result, the power conversion device according to the second embodiment makes it easier to maintain the voltage Vfc1 of capacitor 111 (flying capacitor) at (½)·Vd1 by combining the voltage adjustment control in the voltage increasing direction by speed regulator circuits 130, 140, as in the first embodiment, and the voltage adjustment in the voltage decreasing direction by discharge element 120. This makes it possible to more reliably suppress imbalances in the distribution of output voltage Vds among semiconductor switching elements Q1 to Q4.

[0105] Third Embodiment In a third embodiment, a description will be given of voltage regulation control in the voltage increasing direction of the capacitor 111 by adjusting the turn-on speed of the semiconductor switching elements Q1 and Q4.

[0106] Fig. 13 is a schematic configuration diagram of a main part of a power conversion device 100C according to embodiment 3. As shown in Fig. 13, in addition to the configuration of power conversion device 100A (Fig. 1) according to embodiment 1, power conversion device 100C further includes a speed control circuit 180, a speed control resistance element 184, and a speed control capacitor 185 for adjusting the turn-on speed of semiconductor switching element Q1, and a speed control circuit 190, a speed control resistance element 194, and a speed control capacitor 195 for adjusting the turn-on speed of semiconductor switching element Q4.

[0107] The speed control circuit 180 is connected in parallel with the speed control circuit 130, which adjusts the turn-off speed, between the positive terminal and gate (control electrode) of the semiconductor switching element Q1. The speed control circuit 180 includes a speed control capacitor 181 and a speed control rectifier element 182 connected in series. The speed control capacitor 181 is connected between the positive terminal of the semiconductor switching element Q1 and a node N3. The speed control rectifier element 182 is arranged so that the forward direction is from the gate (control electrode) of the semiconductor switching element Q1 to the node N3. The speed control resistor element 184 and the speed control capacitor 185 are connected in series between the node N3 and the first negative wiring 113 via the second negative wiring 115. The speed control resistor element 184 is connected between the node N3 and the speed control capacitor 185, and the speed control capacitor 185 is connected between the speed control resistor element 184 and the first negative wiring 113.

[0108] The speed control circuit 190 is connected in parallel with the speed control circuit 140 for adjusting the turn-off speed between the positive terminal and gate (control electrode) of the semiconductor switching element Q4. The speed control circuit 190 has a speed control capacitor 191 and a speed control rectifier element 192 connected in series. The speed control rectifier element 192 is connected between the positive terminal of the semiconductor switching element Q4 and the node N4 so that the direction from the node N4 to the positive terminal of the semiconductor switching element Q4 is the forward direction. The speed control capacitor 191 is connected between the node N4 and the gate (control electrode) of the semiconductor switching element Q4. The speed control resistor element 194 and the speed control capacitor 195 are connected in series between the node N4 and the first positive wiring 112 via the second positive wiring 114. The speed control resistance element 194 is connected between the node N4 and the speed control capacitor 195, and the speed control capacitor 195 is connected between the speed control resistance element 194 and the first positive electrode wiring 112.

[0109] Other configurations of power conversion device 100C are similar to those of power conversion device 100A, and therefore detailed description thereof will not be repeated.

[0110] In the speed control circuit 180, during the off period of the semiconductor switching element Q1, the speed control capacitor 181 is charged to a voltage equivalent to that of the capacitor 111 through a charging path via the speed control resistance element 184 and the speed control capacitor 185, or if charging is not completed, is charged to a voltage below that of the capacitor 111.In either case, the speed control capacitor 181 is configured to be charged to a higher voltage as the voltage of the capacitor 111 increases.

[0111] On the other hand, when the semiconductor switching element Q1 is turned on, if the speed control rectifier element 182 becomes conductive in response to a decrease in the output voltage Vds, the turn-on speed of the semiconductor switching element Q1 decreases as the gate (control electrode) is discharged. At this time, the speed control rectifier element 182 becomes conductive at an earlier timing as the voltage of the speed control capacitor 181 is higher. At the start of turn-on, the speed control capacitor 181 is charged to a higher voltage within a range equal to or lower than the voltage of capacitor 111, and the higher the voltage of capacitor 111, so the conduction timing of the speed control rectifier element 182 is automatically adjusted depending on the voltage of capacitor 111.

[0112] When the semiconductor switching element Q1 is turned on, the speed control capacitor 185 is charged via the capacitor 111 and the speed control rectifying element 133, and is also charged and discharged by the action of the speed control circuit 130 and the speed control circuit 180. As a result, the voltage of the speed control capacitor 185 is maintained at a voltage equivalent to the voltage difference between the capacitor 101 (DC power supply 1) and the capacitor 111 (flying capacitor). Furthermore, if the action of charging the speed control capacitor 185 is large, a discharging resistance element may be further provided in parallel with the speed control capacitor 185, as necessary.

[0113] Similarly, in the speed control circuit 190, during the off period of the semiconductor switching element Q4, the speed control capacitor 191 is charged to a voltage equivalent to that of the capacitor 111 through a charging path via the speed control capacitor 195 and the speed control resistance element 194, or if charging is not completed, is charged to a voltage below that of the capacitor 111.In either case, the speed control capacitor 191 is configured to be charged to a higher voltage as the voltage of the capacitor 111 increases.

[0114] On the other hand, when the semiconductor switching element Q4 is turned on, if the speed control rectifier element 192 becomes conductive in response to a decrease in the output voltage Vds, the turn-on speed of the semiconductor switching element Q4 decreases as the gate (control electrode) is discharged. At this time, the speed control rectifier element 192 becomes conductive at an earlier timing as the voltage of the speed control capacitor 191 is higher. At the start of turn-on, the speed control capacitor 191 is charged to a higher voltage within a range equal to or lower than the voltage of capacitor 111, and the higher the voltage of capacitor 111, so the conduction timing of the speed control rectifier element 192 is automatically adjusted depending on the voltage of capacitor 111.

[0115] When semiconductor switching element Q4 is turned on, speed control capacitor 195 is charged via capacitor 111 and speed control rectifying element 143, and is also charged and discharged by the action of speed control circuit 140 and speed control circuit 190. As a result, the voltage of speed control capacitor 195 is maintained at a voltage equivalent to the voltage difference between capacitor 101 (DC power supply 1) and capacitor 111 (flying capacitor). Furthermore, if the action of charging speed control capacitor 195 is large, a discharging resistance element may be further provided in parallel with speed control capacitor 195, as necessary.

[0116] In this way, when speed control circuits 180, 190 for adjusting the turn-off speed are provided, speed control capacitors 181, 191 cannot be directly charged from capacitor 111 while semiconductor switching elements Q1, Q4 are off. Therefore, by providing capacitors 185, 195 that are charged to a voltage equivalent to the difference between capacitor 101 (DC power source 1) and capacitor 111, a configuration is realized in which speed control capacitors 181, 191 are charged to a voltage corresponding to the voltage of capacitor 111 when semiconductor switching elements Q1, Q4 are turned on.

[0117] FIG. 14 is a conceptual waveform diagram for explaining the operation of the speed regulator circuit when the semiconductor switching elements in the power conversion device 100C are turned on.

[0118] FIG. 14 shows an example of turn-on waveforms of the semiconductor switching elements Q1 and Q2 to explain the operation of the speed regulator circuit 180.

[0119] Also in Figure 14, the waveforms of the output voltage Vds(Q2) and output current Ids(Q2) of the semiconductor switching element Q2 in which the speed regulator circuit 180 is not arranged are shown by dotted lines, while the waveforms of the output voltage Vds(Q1) and output current Ids(Q1) of the semiconductor switching element Q1 in which the speed regulator circuit 180 is arranged are shown by solid lines.

[0120] In FIG. 14, in the initial state, the semiconductor switching elements Q1 and Q2 are in the off state, so the output currents Ids(Q1)=0 and Ids(Q2)=0, and the output voltages Vds(Q1)>0 and Vds(Q2)>0.

[0121] When the gate signals Sd1 and Sd2 change from L level to H level, the driver circuits 151 and 152 start to turn on the semiconductor switching elements Q1 and Q2. As the gate voltages of the semiconductor switching elements Q1 and Q2 increase by the driver circuits 151 and 152, Vds(Q1) and Vds(Q2) start to decrease from time t0y.

[0122] Furthermore, the output current Ids(Q2) of the semiconductor switching element Q2 starts to increase from time t2y, and at time t3y, Ids(Q2) reaches a steady value, and the semiconductor switching element Q2 is completely turned on.

[0123] On the other hand, in the semiconductor switching element Q1, from time t0y, the output voltage Vds(Q1) decreases at the same rate as the output voltage Vds(Q2), but at time t1y, the output voltage Vds(Q1) decreases to a level equivalent to the voltage of the speed control capacitor 181 (i.e., the voltage of the capacitor 111), turning on the speed control rectifier element 182. As a result, a discharge path is formed for the gate (control electrode) of the semiconductor switching element Q1, which results in a gradual increase in the gate voltage, and therefore the rate at which the output voltage Vds(Q1) decreases.

[0124] As a result, the output current Ids(Q1) of the semiconductor switching element Q1 starts to increase at time t4y, which is later than time t2y, and reaches a steady value at time t5y, at which time the semiconductor switching element Q1 is completely turned off. In response to the formation of the gate discharge path described above, a charging current Ichg3 for the speed control capacitor 131 is generated between times t1y and t5y.

[0125] In this way, while semiconductor switching elements Q1 and Q2 start to turn on at the same time, in semiconductor switching element Q1, output current Ids(Q1) starts to rise at a later timing than output current Ids(Q2) due to the operation of speed regulator circuit 180. As a result, it can be seen that the turn-on speed of semiconductor switching element Q1 is slower than that of semiconductor switching element Q2 due to the operation of speed regulator circuit 180.

[0126] As a result, during the period from time t2y to time t4y, the semiconductor switching element Q2 is turned on while the semiconductor switching element Q1 is maintained off, thereby providing a discharging period for the capacitor 111.

[0127] As described above, the greater the rate of increase in voltage Vfc1 of capacitor 111, the higher the voltage of speed control capacitor 181 at the start of turn-off, and therefore the earlier the timing (time t1y) at which speed control circuit 180 forms a gate discharge path. As a result, the period during which the turn-on speed is reduced becomes relatively longer, and the timing (time t4y) at which output current Ids (Q1) starts to increase and the timing (time t5y) at which it reaches a steady value are automatically adjusted so that they become later the higher the voltage of capacitor 111.

[0128] On the other hand, the timing (time t2y) when semiconductor switching element Q2 is completely turned off is constant and does not depend on the voltage Vfc1 of capacitor 111. Therefore, the length of the period from time t2y to time t5y, i.e., the discharge period of capacitor 111 caused by semiconductor switching element Q2 being turned on while semiconductor switching element Q1 is turned off, is automatically adjusted so that the higher the voltage Vfc1 of capacitor 111, the longer this discharge period becomes. As a result, speed regulator circuit 180 performs voltage adjustment control so that the greater the rate of increase in voltage Vfc1 of capacitor 111, the greater the rate of decrease in the turn-on speed of semiconductor switching element Q1.

[0129] Although waveforms are not shown, speed regulator circuit 190 adjusts the turn-on speed of semiconductor switching element Q4 in the same way that speed regulator circuit 180 adjusts the turn-on speed of semiconductor switching element Q1. That is, the turn-on speed is automatically adjusted so that the timing at which output current Ids rises becomes slower (i.e., the turn-on speed becomes slower) as the voltage of speed regulator capacitor 191 at the start of turn-on, i.e., the voltage of capacitor 111, becomes higher.

[0130] On the other hand, semiconductor switching element Q3, which is not provided with speed regulating circuit 190, is similar to semiconductor switching element Q2 and is quickly turned on at a fixed timing without depending on the voltage of capacitor 111. As a result, speed regulating circuit 190 reduces the turn-off speed, so that semiconductor switching element Q3 is turned off while semiconductor switching element Q4 is maintained on, thereby providing a discharge period for capacitor 111.

[0131] Therefore, by adjusting the turn-on speed of semiconductor switching element Q4, speed regulator circuit 190 can perform voltage adjustment control, similar to speed regulator circuit 180, so that the greater the increase in voltage Vfc1 of capacitor 111, the greater the decrease in the turn-on speed of semiconductor switching element Q4.

[0132] In the power conversion device 100C, the speed control circuits 130 and 140 operate as described in the first embodiment each time the semiconductor switching elements Q1 to Q4 are turned off, thereby automatically compensating for the voltage drop in the capacitor 111.

[0133] Therefore, according to the power conversion device of the third embodiment, by arranging both speed regulator circuits 130, 140 that adjust the turn-off speed and speed regulator circuits 180, 190 that adjust the turn-on speed, the above-described voltage regulation control can be executed in response to both a decrease and an increase in voltage Vfc1 of capacitor 111 (flying capacitor). This enhances the effect of maintaining voltage Vfc1 of capacitor 111 (flying capacitor) at (½)·Vd1, thereby more reliably suppressing imbalances in output voltages Vds (shared voltages) of semiconductor switching elements Q1 to Q4.

[0134] In the configuration of FIG. 15, it is also possible to combine the third embodiment with the second embodiment by connecting the discharge element 120 shown in FIG. 12 in parallel with the capacitor 111.

[0135] In the third embodiment, the speed regulating circuits 130 and 140 can also be configured in the same manner as in Figures 10 and 11 (a modified example of the first embodiment). Similarly, the speed regulating circuits 180 and 190 may also be configured in the same manner as the modified example of the first embodiment. Specifically, in the speed regulating circuit 180, an impedance element (resistance element or inductor) may be connected between the speed regulating capacitor 181 and the node N3, or between the speed regulating rectifying element 182 and the node N3. Similarly, in the speed regulating circuit 190, an impedance element (resistance element or inductor) may be connected between the node N4 and the speed regulating rectifying element 192, or between the speed regulating capacitor 191 and the node N4.

[0136] FIG. 15 shows a schematic configuration diagram of a main part of a power conversion device 100D according to a modification of the third embodiment.

[0137] 15, the power conversion device 100D includes, in addition to the configuration of the power conversion device 100C (FIG. 13) according to the third embodiment, Zener diodes 186 and 196. Each of the Zener diodes 186 and 196 may be formed by connecting a plurality of Zener diodes in series, or may be formed by a single Zener diode.

[0138] The Zener diode 186 is connected between the speed controlling resistance element 184 and the speed controlling capacitor 185 (second negative wiring 115), with the direction from the second negative wiring 115 toward the speed controlling resistance element 184 as the forward direction. The arrangement of the Zener diode 186 makes it possible to generate a voltage difference according to the breakdown voltage Vz1 of the Zener diode 186 between the voltage of the speed controlling capacitor 181 and the voltage of the capacitor 111.

[0139] Similarly, the Zener diode 196 is connected between the speed controlling resistance element 194 and the speed controlling capacitor 195 (second positive wiring 114), with the direction from the speed controlling resistance element 194 to the second positive wiring 114 being the forward direction. The arrangement of the Zener diode 196 makes it possible to generate a voltage difference between the voltage of the speed controlling capacitor 191 and the voltage of the capacitor 111 according to the breakdown voltage Vz2 of the Zener diode 196. The breakdown voltages Vz1 and Vz2 can be freely adjusted by the specifications of the Zener diode or the number of connected diodes.

[0140] 14, when semiconductor switching elements Q1, Q4 are turned on, the turn-on speed is reduced by speed control circuits 180, 190 from the timing when output voltage Vds has decreased to approximately the voltage of speed control capacitors 181, 191. Therefore, by intentionally providing a voltage difference between the voltage of speed control capacitors 181, 191 and the voltage of capacitor 111 using Zener diodes 186, 196, it becomes possible to adjust the timing at which adjustment (reduction) of the turn-on speed relative to voltage Vfc1 of capacitor 111 begins.

[0141] As a result, according to the power conversion device of the modified example of embodiment 3, fine adjustment is possible to activate voltage adjustment control by the speed regulator circuits 180 and 190 to lower the voltage of capacitor 111, for example, when the voltage of capacitor 111 becomes higher than (1 / 2) the voltage of capacitor 101 (Vfc1≧(1 / 2)·Vd1).

[0142] Fourth Embodiment In the first to third embodiments, the power conversion device has been described in which two semiconductor switching elements are connected in series, but the number of semiconductor switching elements connected in series can be any number equal to or greater than three.

[0143] Fig. 16 is a schematic configuration diagram of a main part of a power conversion device 100X according to embodiment 4. As shown in Fig. 16, the power conversion device 100X according to embodiment 4 differs from Fig. 1 (power conversion device 100A) in that three semiconductor switching elements Q1 to Q3 are connected in series between a first positive wiring 112 and an output node Nb, and three semiconductor switching elements Q4 to Q6 are connected in series between the output node Nb and a first negative wiring 113.

[0144] The driver circuits 151 to 156 are arranged corresponding to the semiconductor switching elements Q1 to Q6, respectively, and turn on and off the semiconductor switching elements Q1 to Q6 in response to gate signals Sd1 to Sd6 from the controller 210.

[0145] 1, capacitor 111 is connected as a flying capacitor between a second positive wiring 114 connecting semiconductor switching elements Q1 (negative terminal) and Q2 (positive terminal) and a second negative wiring 115 connecting semiconductor switching elements Q5 (negative terminal) and Q6 (positive terminal). Capacitor 111 is connected in parallel with four semiconductor switching elements Q2 to Q5.

[0146] In the power conversion device 100X, a capacitor 121 is further arranged as a flying capacitor. The capacitor 121 is connected between a third positive wiring 116 connecting semiconductor switching elements Q2 (negative terminal) and Q3 (positive terminal) and a third negative wiring 117 connecting semiconductor switching elements Q4 (negative terminal) and Q5 (positive terminal). In addition to the voltage Vfc1 of the capacitor 111, a voltage Vfc2 of the capacitor 121 is input to the controller 210 from the respective voltage sensors. The capacitor 121 is connected in parallel with the two semiconductor switching elements Q3 and Q4.

[0147] As with the power conversion device 100A of Figure 1, for the semiconductor switching element Q1 connected between the positive side of the capacitor 111 (flying capacitor) and the first positive wiring 112, a speed control circuit 130 is connected between the positive terminal and gate (control electrode) of the semiconductor switching element Q1, and a speed control rectifier element 133 and a speed control resistor element 134 are connected between the speed control circuit 130 and the capacitor 111 (negative side).

[0148] Furthermore, in the power conversion device 100X, a speed regulation circuit 130, a speed regulation rectifier element 133, and a speed regulation resistance element 134 are also arranged for the semiconductor switching element Q2 connected between the positive electrode side of the capacitor 121 (flying capacitor) and the second positive electrode wiring 114. The speed regulation circuit 130 is connected between the positive electrode terminal and gate (control electrode) of the semiconductor switching element Q2, and the speed regulation rectifier element 133 and the speed regulation resistance element 134 are connected between the speed regulation circuit 130 and the capacitor 121 (negative electrode side).

[0149] As with the power conversion device 100A of Figure 1, for the semiconductor switching element Q6 connected between the negative side of the capacitor 111 (flying capacitor) and the first negative wiring 113, a speed control circuit 140 is connected between the positive terminal and gate (control electrode) of the semiconductor switching element Q6, and a speed control rectifier element 143 and a speed control resistor element 144 are connected between the speed control circuit 140 and the capacitor 111 (positive side).

[0150] Furthermore, in the power conversion device 100X, a speed regulation circuit 140, a speed regulation rectifier element 143, and a speed regulation resistance element 144 are also arranged for the semiconductor switching element Q5 connected between the negative side of the capacitor 121 (flying capacitor) and the second negative wiring 115. The speed regulation circuit 140 is connected between the positive terminal and gate (control electrode) of the semiconductor switching element Q5, and the speed regulation rectifier element 143 and the speed regulation resistance element 144 are connected between the speed regulation circuit 140 and the capacitor 121 (positive side).

[0151] As a result, in response to a voltage drop across capacitor 111, voltage regulation control can be performed to provide a charging period for capacitor 111 when the voltage drops by adjusting the turn-off speed of semiconductor switching elements Q1 and Q6 using speed regulation circuits 130 and 140, as in the first embodiment. Through this voltage regulation control, voltage Vf1 across capacitor 111, which is connected in parallel with four semiconductor switching elements Q2 to Q5, is maintained at a reference voltage (2 / 3)·Vd1, which is (4 / 6) times the DC voltage Vd1.

[0152] Furthermore, in response to a voltage drop across capacitor 121, voltage regulation control can be performed to provide a charging period for capacitor 111 when the voltage drops by adjusting the turn-off speed of semiconductor switching elements Q2 and Q5 using speed regulation circuits 130 and 140. This voltage regulation control maintains voltage Vf2 across capacitor 111, which is connected in parallel with two semiconductor switching elements Q3 and Q4, at a reference voltage (1 / 3)·Vd1, which is (2 / 6) times the DC voltage Vd1.

[0153] Furthermore, in correspondence with the speed control circuit 130 provided in the semiconductor switching element Q1 on the outermost side (the side closest to the first positive wiring 112), a resistance element 136 is additionally arranged between the node at which the speed control rectifier element 133 and the speed control resistance element 134 are connected and the first positive wiring 112. This allows the speed control capacitor 131 to be charged by the voltage (between the first positive wiring 112 and the negative side of the capacitor 111) resistively divided by the speed control resistance element 134 and the resistance element 136.

[0154] Furthermore, in correspondence with the speed control circuit 130 provided in the semiconductor switching element Q4 on the outermost side (the side closest to the first negative wiring 113), a resistance element 146 is additionally arranged between the node at which the speed control rectifier element 143 and the speed control resistance element 144 are connected and the first negative wiring 113. This allows the speed control capacitor 141 to be charged by the voltage (between the positive side of the capacitor 111 and the first negative wiring 113) resistively divided by the speed control resistance element 144 and the resistance element 146.

[0155] 16, DC voltage Vd1 is shared by three semiconductor switching elements Q1 to Q3 or semiconductor switching elements Q4 to Q6, so that output voltage Vds of semiconductor switching elements Q1, Q6 at turn-off is (1 / 3)·Vds. Correspondingly, during the on-period of semiconductor switching elements Q1, Q6, the voltage of capacitor 111, whose reference voltage is (2 / 3)·Vd1, is divided to charge speed control capacitors 131, 141, thereby optimizing the voltage of speed control capacitors 131, 141 at the start of turn-off, and speed control circuits 130, 140 can be operated in the same manner as in embodiment 1.

[0156] Furthermore, for the semiconductor switching elements Q1 and Q2, it is also possible to further arrange a speed regulator circuit 180 for adjusting the turn-on speed, as shown in Figure 14, in parallel with the speed regulator circuit 130, and to further connect a speed regulator resistance element 184 and a speed regulator capacitor 185 similar to those in Figure 14 to the speed regulator circuit 180.

[0157] Similarly, for semiconductor switching elements Q5 and Q6, a speed regulator circuit 190 for adjusting the turn-on speed, as shown in Figure 14, can be further arranged in parallel with speed regulator circuit 140, and a speed regulator resistance element 194 and a speed regulator capacitor 195 similar to those in Figure 14 can be further connected to speed regulator circuit 190.

[0158] As described above, the power conversion device according to this embodiment has a circuit configuration in which any N (N: an integer of 2 or greater) semiconductor switching elements are connected in series and (N-1) flying capacitors are provided, and by providing speed regulator circuits 130, 140 for each flying capacitor, it is possible to achieve the same effects as those of embodiment 1 or 3. This makes it possible to maintain the voltage of each flying capacitor at a reference voltage that is determined depending on the number of semiconductor switching elements connected in parallel.

[0159] The reference voltage of each flying capacitor can be expressed as (N-i) / N·Vd1 for a flying capacitor connected between the (i+1)th positive wiring and the (i+1)th negative wiring. For example, when N=3, the reference voltage of capacitor 111 (FIG. 16) connected between second positive wiring 114 and second negative wiring 115 (i=1) is expressed as (2 / 3)·Vd1. Similarly, the reference voltage of capacitor 121 (FIG. 16) connected between third positive wiring 116 and third negative wiring 117 (i=2) is expressed as (1 / 3)·Vd1.

[0160] Furthermore, even in a circuit configuration in which any N (N: an integer of 2 or greater) semiconductor switching elements are connected in series and (N-1) flying capacitors are provided, at least one of the speed control circuits 130, 140, 180, and 190 can be configured to further include an impedance element (resistance element or inductor) for suppressing oscillation, as in the modified example of embodiment 1. Also, it is possible to connect a discharge element 120, similar to embodiment 2, in parallel to each flying capacitor.

[0161] In the configuration example (power conversion device 100A) of FIG. 1 , with respect to the semiconductor switching elements Q1 and Q2 corresponding to the “two first semiconductor switching elements,” in order from the outside (the first positive wiring 112 side), the semiconductor switching element Q2 corresponds to an example of the “first first semiconductor switching element,” and the semiconductor switching element Q1 corresponds to an example of the “second first semiconductor switching element.”

[0162] Similarly, with regard to the semiconductor switching elements Q3 and Q4 corresponding to the "two second semiconductor switching elements," from the outside (the first negative wiring 113 side), the semiconductor switching element Q4 corresponds to an example of the "first second semiconductor switching element," and the semiconductor switching element Q3 corresponds to an example of the "second second semiconductor switching element."

[0163] Furthermore, capacitor 111 arranged as a flying capacitor corresponds to the "first capacitor." Speed ​​regulator circuits 130, 140 (FIG. 1, etc.) for adjusting the turn-off speed correspond to an embodiment of the "first speed regulator circuit," speed regulator capacitors 131, 141 in speed regulator circuits 130, 140 correspond to an implementation of the "second capacitor," and speed regulator rectifier elements 132, 142 correspond to an implementation of the "first rectifier element."

[0164] Similarly, the speed regulating circuits 180, 190 (Figure 13) for adjusting the turn-on speed correspond to one embodiment of the "second speed regulating circuit," the speed regulating capacitors 181, 191 in the speed regulating circuits 180, 190 correspond to one implementation of the "third capacitor," and the speed regulating rectifying elements 182, 192 correspond to one implementation of the "second rectifying element."

[0165] In the configuration example of FIG. 16 (power conversion device 100X), N=3, and the semiconductor switching elements Q1 to Q3 corresponding to the "three first semiconductor switching elements" are, in order from the outside (the first positive wiring 112 side), semiconductor switching element Q1 corresponds to an example of the "first first semiconductor switching element," semiconductor switching element Q2 corresponds to an example of the "second first semiconductor switching element," and semiconductor switching element Q3 corresponds to an example of the "third first semiconductor switching element."

[0166] Similarly, with regard to the semiconductor switching elements Q4 to Q6 corresponding to the "three second semiconductor switching elements," in order from the outside (the first negative wiring 113 side), semiconductor switching element Q6 corresponds to an example of the "first second semiconductor switching element," semiconductor switching element Q5 corresponds to an example of the "second second semiconductor switching element," and semiconductor switching element Q4 corresponds to an example of the "third second semiconductor switching element."

[0167] 1 (N=2), the present embodiment has been described with reference to an example configuration in which speed regulator circuits 130, 140 for adjusting the turn-off speed, or speed regulator circuits 130, 140 for adjusting the turn-off speed and speed regulator circuits 180, 190 for adjusting the turn-on speed, are provided for each of the positive-side semiconductor switching element Q1 and the negative-side semiconductor switching element Q4, but a configuration in which only one of speed regulator circuits 130 and 140, or only one of speed regulator circuits 130, 180 and speed regulator circuits 140, 190, is provided for only one of semiconductor switching element Q1 and semiconductor switching element Q4 may also be used. In other words, the power conversion device according to this embodiment can be configured by providing at least one of speed regulator circuit 130 or speed regulator circuits 130, 180, and speed regulator circuit 130 or speed regulator circuits 140, 190 corresponding to capacitor 111. For example, when the power conversion device 100 operates as a chopper circuit with only one current direction, there is no need to provide a speed regulator circuit for adjusting the turn-off speed, or a speed regulator circuit for adjusting the turn-off speed and a speed regulator circuit for adjusting the turn-on speed, for one of the semiconductor switching elements Q1, Q4 that always operates as a diode.

[0168] Similarly, in the configuration example of N≧3, typified by the configuration example of FIG. 16 (power conversion device 100X), in a circuit configuration provided with (N−1) flying capacitors, both speed regulator circuit 130 for the positive-side semiconductor switching element and speed regulator circuit 140 for the positive-side semiconductor switching element are provided for each flying capacitor. However, a configuration in which only one of speed regulator circuit 130 and speed regulator circuit 140 is provided for each flying capacitor may also be used. Alternatively, a configuration in which only one of speed regulator circuits 130 and 180, or speed regulator circuits 140 and 190 is provided for each flying capacitor is also possible. In other words, the power conversion device according to this embodiment can be configured by providing at least one of speed regulator circuit 130 or speed regulator circuits 130, 180, and speed regulator circuit 130 or speed regulator circuits 140, 190 for each flying capacitor.

[0169] Regarding the multiple embodiments described above, we would like to confirm that it was intended from the beginning of the application to appropriately combine the configurations described in each embodiment, including combinations not mentioned in the specification, within the scope that does not result in inconsistencies or contradictions.

[0170] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0171] 1, 2 DC power supply, 21 Diodes, 100A to 100D, 100X Power conversion device, 101 Capacitor, 111, 121 Capacitor (flying capacitor), 102 Filter reactor, 103 Filter capacitor, 110 Bridge circuit, 112 First positive wiring, 113 First negative wiring, 114 Second positive wiring, 115 Second negative wiring, 116 Third positive wiring, 117 Third negative wiring, 120 Discharge element, 130, 140 Speed ​​control circuit (turn-off speed), 131, 141, 181, 185, 191, 195 Speed ​​control capacitor, 132, 133, 142, 143, 182, 192 Speed ​​control rectifier element, 134, 144, 184, 194 Speed ​​control resistance element, 135, 145 Impedance elements, 136, 146 resistance elements, 151 to 156 driver circuits, 180, 190 speed regulating circuit (turn-on speed), 186, 196 Zener diodes, 210 controller, Ichg1, Ichg2, Ichg3 charging current (speed regulating circuit), Ids output current (semiconductor switching element), N1 to N4 nodes, Nb output node, Q1 to Q6 semiconductor switching elements, Rg gate resistance, Sd1 to Sd6 gate signal, Vclmp voltage drop amount, Vd1, Vd2 DC voltage, Vds output voltage (semiconductor switching element), Vfc1, Vfc2 voltage (flying capacitor), Voff off voltage, Von on voltage, Vz1, Vz2 breakdown voltage (Zener diode).

Claims

1. A power supply comprising: two first and second first semiconductor elements connected in series between a first positive wiring on a high voltage side and an output node, the first and second first semiconductor elements being arranged in series from the first positive wiring toward the output node; two second semiconductor elements connected in series between a first negative wiring on a low voltage side and the output node, the first and second second semiconductor elements being arranged in series from the first negative wiring toward the output node; a first capacitor electrically connected between a second positive wiring connecting the negative terminal of the first first semiconductor element and the positive terminal of the second first semiconductor element, and a second negative wiring connecting the positive terminal of the first second semiconductor element and the negative terminal of the second second semiconductor element; and a first speed regulator circuit arranged for at least one of the first first semiconductor element and the first second semiconductor element in correspondence with the first capacitor; A power conversion device, wherein each of the first speed regulating circuits is configured to reduce the turn-off speed of the first first semiconductor element or the first second semiconductor element in response to a voltage drop in the first capacitor, below the turn-off speed of the second first semiconductor element or the second second semiconductor element in which the first speed regulating circuit is not arranged.

2. A power conversion device as described in claim 1, wherein each of the first speed regulating circuits is configured to slow down the turn-off speed of the first first semiconductor element or the first second semiconductor element to be slower than the turn-off speed of the second first semiconductor element or the second second semiconductor element when the voltage of the first capacitor drops to less than (1 / 2) times the DC voltage between the first positive wiring and the first negative wiring, such that the greater the amount of voltage drop of the first capacitor, the greater the degree of reduction in the turn-off speed.

3. The power conversion device according to claim 1 or 2, further comprising a discharge element connected in parallel with the first capacitor between the second positive wiring and the second negative wiring.

4. A power conversion device as described in any one of claims 1 to 3, further comprising a second speed regulating circuit arranged in parallel with the first speed regulating circuit for at least one of the first first semiconductor element and the first second semiconductor element corresponding to the first capacitor, each of the second speed regulating circuits being configured to reduce the turn-on speed of the first first semiconductor element or the first second semiconductor element in response to a voltage rise of the first capacitor below the turn-on speed of the second first semiconductor element or the second second semiconductor element in which the second speed regulating circuit is not arranged.

5. A power conversion device as described in claim 4, wherein each of the second speed regulating circuits is configured to slow down the turn-on speed of the first first semiconductor element or the first second semiconductor element to be slower than the turn-on speed of the second first semiconductor element or the second second semiconductor element when the voltage of the first capacitor rises to more than (1 / 2) times the DC voltage between the first positive wiring and the first negative wiring, such that the greater the amount of voltage rise of the first capacitor, the greater the degree of reduction in the turn-on speed.

6. The power conversion device according to claim 4 or 5, wherein each of the first speed adjusting circuits has a second capacitor and a first rectifying element connected between the control electrode of the first first semiconductor element or the first second semiconductor element and the positive terminal, the voltage of the second capacitor is set to a voltage equivalent to that of the first capacitor during an on-period of the first first semiconductor element or the first second semiconductor element, and the first rectifying element becomes conductive to charge the control electrode when the voltage between the positive terminal and the negative terminal becomes higher than the voltage of the second capacitor after the first first semiconductor element or the first second semiconductor element starts to turn off.

7. A power conversion device as described in claim 6, wherein each of the first speed regulating circuits further has an impedance element connected in series with the second capacitor and the first rectifying element between the control electrode of the first first semiconductor element or the first second semiconductor element and the positive terminal.

8. The power conversion device according to claim 4 or 5, wherein each of the second speed regulating circuits has a third capacitor and a second rectifying element connected between the control electrode of the first first semiconductor element or the first second semiconductor element and the positive terminal, the voltage of the third capacitor is set to a voltage equivalent to that of the first capacitor during an off period of the first first semiconductor element or the first second semiconductor element, and the second rectifying element becomes conductive to discharge the control electrode when the voltage between the positive terminal and the negative terminal becomes lower than the voltage of the third capacitor after the first first semiconductor element or the first second semiconductor element starts to turn on.

9. A power conversion device as described in claim 8, wherein each of the second speed regulating circuits further has an impedance element connected in series with the third capacitor and the second rectifying element between the control electrode of the first first semiconductor element or the first second semiconductor element and the positive terminal.

10. N first semiconductor elements, numbered from 1st to Nth (N: an integer of 3 or more), arranged in series in order from the first positive wiring toward the output node between a first positive wiring on a high voltage side and an output node; N second semiconductor elements, numbered from 1st to Nth (N: an integer of 3 or more) arranged in series in order from the first negative wiring toward the output node between a first negative wiring on a low voltage side and the output node; and (N-1) first capacitors in total, connected between an (i+1)th positive wiring connecting the negative terminal of an i-th (i: an integer of 1 or more and (N-1) or less) first semiconductor element among the N first semiconductor elements and a positive terminal of the (i+1)th first semiconductor element, and an (i+1)th negative wiring connecting the positive terminal of the i-th second semiconductor element among the N second semiconductor elements and a negative terminal of the (i+1)th second semiconductor element; a first speed regulating circuit arranged for at least one of the i-th first semiconductor element and the i-th second semiconductor element corresponding to each of the first capacitors, wherein each of the first speed regulating circuits is configured to reduce the turn-off speed of the i-th first semiconductor element or the i-th second semiconductor element in response to a voltage drop of the corresponding first capacitor below the turn-off speed of the N-th first semiconductor element or the N-th second semiconductor element in which the first speed regulating circuit is not arranged.

11. A power conversion device as claimed in claim 10, wherein each of the first speed regulating circuits is configured to slow down the turn-off speed of the i-th first semiconductor element or the i-th second semiconductor element to be slower than the turn-off speed of the N-th first semiconductor element or the N-th second semiconductor element when the voltage of the first capacitor drops below a reference voltage such that the greater the amount of voltage drop of the first capacitor, the greater the degree of reduction in the turn-off speed; and wherein the reference voltage is represented by ((N-i) / N) times the DC voltage between the first positive wiring and the first negative wiring in the first capacitor connected between the (i+1) positive wiring and the (i+1) negative wiring.

12. The power conversion device according to claim 10 or 11, further comprising a discharge element connected in parallel with each of the first capacitors between the (i+1) positive wiring and the (i+1) negative wiring.

13. A power conversion device as described in any one of claims 10 to 12, further comprising a second speed regulating circuit arranged in parallel with the first speed regulating circuit for at least one of the i-th first semiconductor element and the i-th second semiconductor element corresponding to each of the first capacitors, each of the second speed regulating circuits being configured to reduce the turn-on speed of the i-th first semiconductor element or the i-th second semiconductor element in response to a voltage rise of the first capacitor below the turn-on speed of the N-th first semiconductor element or the N-th second semiconductor element in which the second speed regulating circuit is not arranged.

14. A power conversion device as claimed in claim 13, wherein each of the second speed regulating circuits is configured to slow down the turn-on speed of the i-th first semiconductor element or the i-th second semiconductor element to be slower than the turn-on speed of the N-th first semiconductor element or the N-th second semiconductor element when the voltage of the first capacitor rises above a reference voltage such that the greater the amount of voltage rise of the first capacitor, the greater the degree of reduction in the turn-on speed; and wherein the reference voltage is represented by ((N-i) / N) times the DC voltage between the first positive wiring and the first negative wiring for the first capacitor connected between the (i+1) positive wiring and the (i+1) negative wiring.

15. The power conversion device according to claim 13 or 14, wherein each of the first speed adjusting circuits has a second capacitor and a first rectifying element connected between a control electrode of the i-th first semiconductor element or the i-th second semiconductor element and the positive terminal, the second capacitor is set to a voltage equivalent to that of the first capacitor during an on-period of the i-th first semiconductor element or the i-th second semiconductor element, and the first rectifying element becomes conductive to charge the control electrode when the voltage between the positive terminal and the negative terminal becomes higher than the voltage of the second capacitor after the i-th first semiconductor element or the i-th second semiconductor element starts to turn off.

16. A power conversion device as described in claim 15, wherein the second capacitor of the first speed regulator circuit arranged corresponding to each of the i-th first semiconductor element and the i-th second semiconductor element is charged by a resistive voltage division of the voltage between the first positive wiring and the second negative wiring, or the voltage between the second positive wiring and the first negative wiring.

17. A power conversion device as claimed in claim 13 or 14, wherein each of the second speed regulating circuits has a third capacitor and a second rectifying element connected between a control electrode of the i-th first semiconductor element or the i-th second semiconductor element and the positive terminal, the third capacitor is set to a voltage equivalent to that of the first capacitor during an off period of the i-th first semiconductor element or the i-th second semiconductor element, and the second rectifying element becomes conductive to discharge the control electrode when the voltage between the positive terminal and the negative terminal becomes lower than the voltage of the third capacitor after the i-th first semiconductor element or the i-th second semiconductor element starts to turn on.

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