Method for manufacturing semiconductor device

Abstract

Provided is a method for manufacturing a semiconductor device by which characteristics can be improved. According to one embodiment, a method for manufacturing a semiconductor device involves forming a first metal layer containing a first metal element on a first surface of a structure including a substrate including SiC and including a first surface. The manufacturing method includes injecting a first element containing at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, and Si to the first surface through the first metal layer. The manufacturing method involves irradiating the first surface with a laser through the first metal layer after the injection.

Description

Semiconductor device manufacturing method

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device.

[0002] It is desirable to improve the characteristics of semiconductor devices.

[0003] JP 2023-40706 A

[0004] The embodiments provide a method for manufacturing a semiconductor device that can improve characteristics.

[0005] According to an embodiment, a method for manufacturing a semiconductor device includes forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and including the first surface. The manufacturing method includes implanting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer. After the implantation, the manufacturing method includes irradiating the first surface with a laser through the first metal layer.

[0006] FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 8 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a flowchart illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIG. 10 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 11 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 12 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 13 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 14 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 15 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment.

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions will be omitted as appropriate.

[0008] First Embodiment FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIGS. 2 to 8 are schematic cross-sectional views illustrating the method for manufacturing a semiconductor device according to the first embodiment. As shown in FIGS. 1 and 2, for example, a structure 18 is prepared (step S105). As shown in FIG. 2, the structure 18 includes a substrate 15. The substrate 15 may be, for example, a semiconductor substrate. The substrate 15 includes SiC. The substrate 15 includes a first surface 15a. The substrate 15 may be, for example, at least a portion of a SiC wafer.

[0009] 1 and 2, a first metal layer 61 is formed on the first surface 15a of the structure 18 (step S110). The first metal layer 61 includes a first metal element.

[0010] 1 and 3, a first element 81 is implanted into the first surface 15a through the first metal layer 61 (step S120). The first element 81 includes, for example, at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga. The first element 81 may include, for example, at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, and Si. The implantation is, for example, ion implantation. For example, ions of the first element 81 are implanted.

[0011] 1 and 5, after the implantation, a laser 80L is irradiated onto the first surface 15a through the first metal layer 61 (step S130). For example, laser annealing is performed. As a result, a silicide layer 61S is formed from at least a portion of the first metal layer 61, as shown in FIG.

[0012] In the embodiment, after the first metal layer 61 is formed, the first element 81 is implanted through the first metal layer 61. This allows a stable low-resistance ohmic contact to be obtained. This is thought to be because the implantation of the first element 81 causes a portion of the first metal element contained in the first metal layer 61 to be introduced into the substrate 15. For example, it is thought that a knock-on phenomenon occurs.

[0013] For example, the first metal element is introduced relatively uniformly and stably near the first surface 15a of the substrate 15. As a result, a mixed layer (a mixed region 15M described later) having a high reaction rate of silicide reaction is uniformly formed. The highly reactive mixed layer is efficiently silicided by subsequent annealing using laser irradiation. As a result, a uniform silicide layer 61S is stably formed. As a result, low electrical resistance is obtained. High flatness is obtained. For example, high flatness and low electrical resistance are obtained. According to the embodiment, a method for manufacturing a semiconductor device capable of improving characteristics is provided. For example, a highly flat silicide layer 61S is obtained. The surface morphology can be improved.

[0014] In the embodiment, laser annealing is performed after the injection of the first element 81 through the first metal layer 61. This allows a stable silicide layer 61S to be obtained even with low-power laser irradiation. For example, a low-energy density laser 80L can be applied. This allows the efficiency of the laser irradiation process to be improved. For example, a high throughput can be obtained. For example, energy consumption can be reduced.

[0015] 2, the substrate 15 may include a second surface 15b. In addition to the substrate 15, the structure 18 may include a semiconductor layer 10. The structure 18 may include a conductive layer 50 and an insulating member 40.

[0016] For example, the semiconductor layer 10 is provided between the substrate 15 and the insulating member 40. The conductive layer 50 is provided between the semiconductor layer 10 and the insulating member 40. The conductive layer 50 may be, for example, an electrode layer. The insulating member 40 may be, for example, a passivation layer. The second surface 15b is between the semiconductor layer 10 and the first surface 15a. The first surface 15a corresponds to, for example, a surface on which an ohmic electrode is provided. For example, the semiconductor layer 10 includes SiC.

[0017] For example, at least a portion of the semiconductor layer 10 may be epitaxially grown on a base (SiC wafer) that will become the substrate 15. A conductive layer 50 and an insulating member 40 may be formed on the semiconductor layer 10. After this, the base may be thinned. For example, a process such as grinding may be performed. In this way, the preparation of the structure 18 (step S105) may include thinning the thickness of the base that will become the substrate 15.

[0018] 2 and 3, the structure 18 may be fixed to a support member 60 during the implantation of the first element 81. This increases the mechanical strength and allows for stable processing.

[0019] 3 and 4 , the mixed region 15M is formed by the implantation of the first element 81. The mixed region 15M includes, for example, Si, C, and the first metal element. For example, the implantation of the first element 81 may include migrating a portion of the first metal element to a region including the first surface 15 a of the substrate 15. For example, the implantation of the first element 81 forms the mixed region 15M in the region including the first surface 15 a of the substrate 15. As described above, the formation of the mixed region 15M is due to the knock-on phenomenon.

[0020] The first metal element includes, for example, at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt. A mixed region 15M including such a first metal element, Si, and carbon is formed. For example, the first metal element is uniformly introduced near the first surface 15a. The mixed region 15M may further include a first element 81. Ti, Co, Ni, Mo, Ta, W, and Pt can react with Si to form silicide.

[0021] As shown in FIG. 5, the first metal layer 61 and the mixed region 15M are irradiated with a laser 80L. As a result, a silicide layer 61S is formed as shown in FIG. 6. In this manner, the irradiation includes forming the silicide layer 61S from the first metal layer 61. After the silicide layer 61S is formed, the mixed region 15M may remain. At least a portion of the mixed region 15M may be amorphous. At least a portion of the mixed region 15M may include a crystal (including a polycrystal).

[0022] In the embodiment, the thickness of the first metal layer 61 is preferably 10 nm or more and 100 nm or less. If the thickness of the first metal layer 61 is excessively thin, for example, it becomes difficult to obtain a uniform silicide layer 61S. If the thickness of the first metal layer 61 is excessively thick, for example, the energy required for implanting the first element 81 and / or for laser irradiation becomes excessively large.

[0023] In the embodiment, the first element 81 may include at least one selected from the group consisting of Ar, B, P, and As. This makes it easier to form the mixed region 15M with an appropriate thickness. This provides good compatibility with other processes. For example, an ion implantation apparatus used for imparting conductivity may be used.

[0024] The implantation of the first element 81 may include implantation of a first metal element.

[0025] In the embodiment, the first element 81 may include Si. For example, a Si-rich mixed region 15M is obtained. For example, silicon can be easily introduced into the first metal layer 61. This allows a uniform silicide layer 61S to be efficiently formed. For example, a portion of silicon is introduced into the first metal layer 61. This forms a region in which the substrate 15, the region formed by knock-on, and the region where silicon is implanted into the first metal layer 61 are continuous.

[0026] 1 and 7 , after irradiation with the laser 80L, a first conductive layer 51 may be formed on the silicide layer 61S (step S140). The first conductive layer 51 functions as, for example, an electrode. The first conductive layer 51 may include, for example, a metal such as aluminum, copper, or gold. The first conductive layer 51 makes ohmic contact with the substrate 15 with low resistance via the silicide layer 61S.

[0027] As shown in Figure 1, between the implantation (step S120) and the irradiation (step S130), a second metal layer 62 (see Figure 8) may be formed (step S125). As shown in Figure 8, the second metal layer 62 is formed on the first metal layer 61. The second metal layer 62 includes a second metal element. The second metal element may include, for example, at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt. The second metal element may be the same as or different from the first metal element.

[0028] For example, a thin first metal layer 61 is formed, and then the first element 81 is implanted. This efficiently forms the desired mixed region 15M. Thereafter, the second metal layer 62 is formed. By laser irradiation, the silicide layer 61S can be efficiently formed from the first metal layer 61 and the second metal layer 62. The silicide layer 61S of the desired thickness can be stably formed.

[0029] The second metal element may be the same as the first metal element, or may be different from the first metal element.

[0030] As already described, the structure 18 may further include a semiconductor layer 10 containing SiC. Providing the semiconductor layer 10 results in higher quality. The semiconductor layer 10 is an epitaxially grown layer. In this embodiment, laser irradiation is performed to form the silicide layer 61S. This allows the target region (the region including the first metal layer 61 and the mixed region 15M) to be locally and effectively heated. Damage to the surface device structure (the semiconductor layer 10 and the conductive layer 50) is suppressed. The temperature of the surface device structure (the semiconductor layer 10 and the conductive layer 50) increased by laser irradiation is, for example, 50°C or higher and 1000°C or lower. The temperature may be, for example, 100°C or lower.

[0031] In an embodiment, the power of the laser 80L is, for example, 1.0 J / cm ２ 3.0J / cm or more ２ The following is true: A good ohmic contact can be obtained while suppressing damage to the surface device structure (semiconductor layer 10 and conductive layer 50).

[0032] Second Embodiment FIG. 9 is a flowchart illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIGS. 10 to 14 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. As shown in FIG. 9, in the second embodiment, after implantation (step S210), formation of a first metal layer 61 (step S220) is performed. Then, irradiation with a laser 80L (step S230) is performed. Except for the order of these steps, the configuration described with respect to the first embodiment may be applied to the second embodiment.

[0033] For example, as shown in Fig. 10, for example, a structure 18 is prepared (step S105). As shown in Fig. 10, the structure 18 includes a substrate 15. The substrate 15 includes SiC. The substrate 15 includes a first surface 15a.

[0034] 10, a metal element 85 for implantation is implanted into the first surface 15a of the structure 18 (step S210). The metal element 85 for implantation includes at least one element selected from the group consisting of, for example, Ti, Co, Ni, Mo, Ta, W, and Pt.

[0035] 11 , a mixed region 15M is formed in the vicinity of the first surface 15a by implanting the metal element 85. The mixed region 15M is a region that includes the first surface 15a. The mixed region 15M includes Si, C, and the metal element 85 to be implanted.

[0036] 12, after the implantation, a first metal layer 61 containing the first metal element is formed on the first surface 15a (step S220). As shown in FIG. 13, a laser 80L is irradiated onto the first surface 15a through the first metal layer 61 (step S230).

[0037] In the second embodiment, the mixed region 15M is formed by implanting the metal element 85 before the formation of the first metal layer 61. The mixed region 15M can be efficiently formed by implanting the metal element 85 with low energy. The silicide layer 61S can be efficiently formed by irradiating the mixed region 15M containing the metal element 85 and the first metal layer 61 containing the first metal element with a laser 80L. At least a portion of the silicide layer 61S may be formed from at least a portion of the first metal layer 61. A portion of the silicide layer 61S may be formed from at least a portion of the mixed region 15M. In this way, the irradiation of the laser 80L (step S230) may include forming at least a portion of the silicide layer 61S from the first metal layer 61.

[0038] For example, a first reference example can be considered in which a first metal layer 61 is formed after implanting Ar ions or the like, and then laser irradiation is performed. In the first reference example, an amorphous region is formed by implanting Ar ions or the like. This makes it possible to form silicide using a low-power laser 80L. However, in the first reference example, a mixed region 15M is not formed. In the first reference example, in the silicide reaction, metal elements are supplied only from the first metal layer 61 formed on the surface. The reaction region is limited to the vicinity of the first metal layer 61. Therefore, for example, there is a limit to the reduction in electrical resistance.

[0039] In contrast, in the embodiment, a mixed region 15M is formed by injecting a metal element 85. Thereafter, a first metal layer 61 is formed, and then a laser 80L is irradiated. The laser 80L is irradiated onto the mixed region 15M and the first metal layer 61, and a silicide layer 61S is formed. The mixed region 15M functions, for example, as a transition region. During the formation of the silicide layer 61S, stress and the like are alleviated. For example, the silicide layer 61S can be efficiently formed while maintaining good film quality. For example, good morphology can be obtained. For example, a surface with good flatness can be obtained.

[0040] As shown in FIGS. 9 and 14, after the irradiation with the laser 80L (step S230), the first conductive layer 51 may be formed on the silicide layer 61S.

[0041] In the second embodiment, the first metal element also includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt. In the second embodiment, the thickness of the first metal layer 61 may be 10 nm or more and 500 nm or less. In the second embodiment, the structure 18 may also further include a semiconductor layer 10 containing SiC. In the second embodiment, the structure 18 may include a conductive layer 50 and an insulating member 40.

[0042] In the first and second embodiments, the structure 18 may be separated from the support member 60 after the laser irradiation or after the formation of the first conductive layer 51. This completes the semiconductor device.

[0043] Third Embodiment The third embodiment relates to a semiconductor device. FIG. 15 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. As shown in FIG. 15 , a semiconductor device 110 according to the embodiment includes a first conductive layer 51, a semiconductor layer 10, a substrate 15, a silicide layer 61S, and a mixed region 15M. The semiconductor layer 10 includes SiC. The substrate 15 includes SiC. The substrate 15 is provided between the first conductive layer 51 and the semiconductor layer 10. The silicide layer 61S is provided between the first conductive layer 51 and the substrate 15. The silicide layer 61S includes a first metal element and silicon. The mixed region 15M is provided between the silicide layer 61S and the substrate 15. The mixed region 15M includes the first metal element, silicon, and carbon.

[0044] The first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt. A good ohmic contact is obtained between the first conductive layer 51 and the substrate 15. A low electrical resistance is obtained. For example, a low on-resistance is obtained.

[0045] 15 , in this example, the semiconductor device 110 includes a second conductive layer 52 and a third conductive layer 53. The semiconductor layer 10 includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, and a fourth semiconductor region 14. A first direction D1 from the first conductive layer 51 to the second conductive layer 52 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0046] The first semiconductor region 11 has a first conductivity type (e.g., n-type). The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, and a third partial region 11c. A second direction D2 from the first partial region 11a to the second partial region 11b intersects with the first direction D1. The second direction D2 may be the X-axis direction. The third partial region 11c is provided between the first partial region 11a and the third conductive layer 53 in the first direction D1.

[0047] The second semiconductor region 12 is of a second conductivity type (e.g., p-type). The third semiconductor region 13 is of a first conductivity type. The fourth semiconductor region 14 is of a second conductivity type. The impurity concentration of the first conductivity type in the third semiconductor region 13 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 11. The impurity concentration of the second conductivity type in the fourth semiconductor region 14 is higher than the impurity concentration of the second conductivity type in the second semiconductor region 12.

[0048] A part 12p of the second semiconductor region 12 is located between the second partial region 11b and the third semiconductor region 13 in the first direction D1. Another part 12q of the second semiconductor region 12 is located between the third partial region 11c and the fourth semiconductor region 14 in the second direction D2. The third semiconductor region 13 is located between the other part 12q of the second semiconductor region 12 and the fourth semiconductor region 14 in the second direction D2.

[0049] The second conductive layer 52 is electrically connected to the third semiconductor region 13 and the fourth semiconductor region 14. The insulating member 40 may include a first insulating region 41 and a second insulating region 42. At least a portion of the first insulating region 41 is provided between the third partial region 11c and the third conductive layer 53. The second conductive layer 52 is provided between the semiconductor layer 10 and the second insulating region 42. The third conductive layer 53 may extend along a third direction D3 that intersects with a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0050] The current flowing between the first conductive layer 51 and the second conductive layer 52 can be controlled by the potential of the third conductive layer 53. The semiconductor device 110 is, for example, a transistor. The first conductive layer 51 may be, for example, a drain electrode. The second conductive layer 52 may be, for example, a source electrode. The third conductive layer 53 may be, for example, a gate electrode.

[0051] The semiconductor device 110 according to the embodiment may be, for example, a diode. The first conductive layer 51 may be any electrode layer. In the semiconductor device 110 according to the embodiment, good ohmic contact is obtained. A semiconductor device with improved characteristics can be provided. For example, low electrical resistance can be obtained. For example, high flatness can be obtained. For example, high flatness and low electrical resistance can be obtained.

[0052] In embodiments, for example, substrate 15 may include at least one selected from the group consisting of 4H—SiC, 6H—SiC, and 3C—SiC.

[0053] For example, the impurities of the first conductivity type include at least one selected from the group consisting of N, P, and As. For example, the impurities of the second conductivity type include at least one selected from the group consisting of B, Al, and Ga.

[0054] In an embodiment, information about the length and thickness can be obtained by electron microscopy, etc. Information about the composition of the material can be obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy Dispersive X-ray spectroscopy), etc.

[0055] The embodiments may include the following technical proposals: (Technical proposal 1) A method for manufacturing a semiconductor device, comprising: forming a first metal layer containing a first metal element on a first surface of a structure including a substrate including SiC and including the first surface; injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface via the first metal layer; and irradiating the first surface with a laser via the first metal layer after the injection.

[0056] (Technical Solution 2) The method for manufacturing a semiconductor device according to Technical Solution 1, wherein the implantation includes moving a portion of the first metal element to a region of the substrate that includes the first surface.

[0057] (Technical Solution 3) The method for manufacturing a semiconductor device according to Technical Solution 1, wherein the implantation forms a mixed region in a region of the substrate that includes the first surface, and the mixed region includes Si, C, and the first metal element.

[0058] (Technical Solution 4) The method for manufacturing a semiconductor device according to Technical Solution 2 or 3, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, W, Ta, and Pt.

[0059] (Technical Solution 5) The method for manufacturing a semiconductor device according to any one of Technical Solutions 2 to 4, wherein the first element includes at least one selected from the group consisting of Ar, B, P, and As.

[0060] (Technical Solution 6) The method for manufacturing a semiconductor device according to any one of Technical Solutions 2 to 4, wherein the first element includes Si.

[0061] (Technical Solution 7) The method for manufacturing a semiconductor device according to any one of Technical Solutions 2 to 6, wherein the irradiation includes forming a silicide layer from the first metal layer.

[0062] (Technical Solution 8) The method for manufacturing a semiconductor device according to Technical Solution 7, wherein after the irradiation, a first conductive layer is formed on the silicide layer.

[0063] (Technical Solution 9) The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 8, wherein the thickness of the first metal layer is 10 nm or more and 100 nm or less.

[0064] (Technical Solution 10) A method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 9, wherein a second metal layer containing a second metal element is formed on the first metal layer between the implantation and the irradiation.

[0065] (Technical Solution 11) The method for manufacturing a semiconductor device according to Technical Solution 10, wherein the second metal element is the same as the first metal element.

[0066] (Technical proposal 12) A method for manufacturing a semiconductor device according to any one of Technical proposals 1 to 11, wherein the structure further includes a semiconductor layer containing SiC, the substrate further includes a second surface, and the second surface is located between the first surface and the semiconductor layer.

[0067] (Technical Solution 13) The method for manufacturing a semiconductor device according to Technical Solution 12, wherein the temperature of the semiconductor layer increased by the irradiation is 100° C. or less.

[0068] (Technical proposal 14) A method for manufacturing a semiconductor device, comprising: injecting a metal element for injection into a first surface of a structure including a substrate including SiC and including a first surface; after the injection, forming a first metal layer including the first metal element on the first surface; and irradiating a laser onto the first surface via the first metal layer.

[0069] (Technical proposal 15) A method for manufacturing a semiconductor device according to Technical proposal 14, wherein the implantation includes forming a mixed region in a portion of the substrate, the mixed region includes the first surface, and the mixed region includes Si, C, and the metal element for implantation.

[0070] (Technical Solution 16) The method for manufacturing a semiconductor device according to Technical Solution 14 or 15, wherein the metal element for injection includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

[0071] (Technical Solution 17) The method for manufacturing a semiconductor device according to any one of Technical Solutions 14 to 16, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

[0072] (Technical Solution 18) The method for manufacturing a semiconductor device according to any one of Technical Solutions 14 to 17, wherein the irradiation includes forming a silicide layer from the first metal layer.

[0073] (Technical Solution 19) The method for manufacturing a semiconductor device according to any one of Technical Solutions 1 to 18, further comprising preparing the structure, wherein the preparation of the structure includes thinning the thickness of a base body that will become the substrate.

[0074] (Technical Solution 20) A semiconductor device comprising: a first conductive layer; a semiconductor layer containing SiC; a substrate containing SiC provided between the first conductive layer and the semiconductor layer; a silicide layer provided between the first conductive layer and the substrate and containing a first metal element and silicon; and a mixed region provided between the silicide layer and the substrate and containing the first metal element, silicon, and carbon.

[0075] According to the embodiment, a method for manufacturing a semiconductor device that can improve characteristics can be provided.

[0076] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in a semiconductor device or structure, such as a substrate, a semiconductor layer, and a silicide layer, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0077] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0078] In addition, all semiconductor device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the semiconductor device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0079] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0080] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0081] 10: Semiconductor layer, 11 to 14: First to fourth semiconductor regions, 11a to 11c: First to third partial regions, 12p: Part, 12q: Other part, 15: Substrate, 15M: Mixed region, 15a, 15b: First and second surfaces, 18: Structure, 40: Insulating member, 41, 42: First and second insulating regions, 50: Conductive layer, 51 to 53: First to third conductive layers, 60: Support member, 61, 62: First and second metal layers, 61S: Silicide layer, 80L: Laser, 81: First element, 85: Metal element, 110: Semiconductor device, D1 to D3: First to third directions

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first metal layer including a first metal element on a first surface of a structure including a substrate including SiC and including a first surface; injecting a first element including at least one selected from the group consisting of He, Ne, Ar, Kr, Xe, Rn, Si, N, P, As, B, Al, and Ga into the first surface through the first metal layer; and, after the injection, irradiating the first surface with a laser through the first metal layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the implantation includes migrating a portion of the first metal element to a region of the substrate that includes the first surface.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the implantation forms a mixed region in a region including the first surface of the substrate, the mixed region containing Si, C and the first metallic element.

4. The method for manufacturing a semiconductor device according to claim 2, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

5. The method for manufacturing a semiconductor device according to claim 2, wherein the first element includes at least one selected from the group consisting of Ar, B, P, and As.

6. The method for manufacturing a semiconductor device according to claim 2, wherein the first element includes Si.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising forming a second metal layer containing a second metal element on the first metal layer between the implantation and the irradiation.

8. A method for manufacturing a semiconductor device, comprising: injecting a metal element for injection into a first surface of a structure including a substrate including SiC and including a first surface; forming a first metal layer including the first metal element on the first surface after the injection; and irradiating a laser onto the first surface through the first metal layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the implantation includes forming a mixed region in a portion of the substrate, the mixed region including the first surface, and the mixed region including Si, C and the metal element for implantation.

10. The method of manufacturing a semiconductor device according to claim 8, wherein the metallic element for implantation includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

11. The method for manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the first metal element includes at least one selected from the group consisting of Ti, Co, Ni, Mo, Ta, W, and Pt.

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